Message notification method and apparatus

Abstract

The application provides a message notification method and device, which can solve the problem that a plurality of query commands need to be sent by software of a main chip to know the command execution state of a flash memory, reduces the additional software overhead, and is suitable for the case that the logic circuit of the main chip initiatively sends a sleep request to the flash memory. The message notification method comprises that the flash memory receives a first sleep request from the main chip. The flash memory detects the execution state of a work command initiated by the flash memory. The work command is used to initiate a read / write operation between the flash memory and the main chip. The flash memory sends a first notification to the main chip, and the first notification is used to indicate the execution state of the work command.

Description

Technical Field

[0001] This application relates to the field of chips, and more particularly to a message notification method and apparatus. Background Technology

[0002] With the development of technology, electronic devices are becoming increasingly multifunctional, leading to a corresponding increase in power consumption. Therefore, when an electronic device has no business to process, both the main chip and flash memory can enter a sleep state to reduce power consumption. Specifically, the main chip can send a sleep request to the flash memory, receive a sleep-ready indication from the flash memory, and close the first transmission channel for data transmission from the main chip to the flash memory to enter a sleep state. Correspondingly, after sending a sleep-ready indication to the main chip, the flash memory can also close the second transmission channel for data transmission from the flash memory to the main chip after performing necessary internal operations, and then enter a sleep state. However, the above sleep process does not consider scenarios where the flash memory needs to send work commands to the main chip. Therefore, if the flash memory needs to send work commands to the main chip, the above sleep process may cause the work commands to fail to execute, resulting in data loss due to flash memory read / write errors, leading to low reliability.

[0003] To address the issue of flash memory-side work commands failing to execute, a solution can be introduced before executing the aforementioned hibernation process. This involves the main chip's software querying the execution status of work commands on the flash memory side before actively initiating a hibernation request. Specifically, the main chip's software can periodically and proactively send query commands to the flash memory to check if there are any work commands currently being executed or pending execution. The hibernation process will only be executed by the main chip and flash memory when the main chip's software determines that there are no more work commands to be executed on the flash memory side.

[0004] However, the above query steps may need to be executed many times, incurring additional signaling overhead and making the sleep process time-consuming and inefficient. Furthermore, the multiple query commands sent by the main chip to the flash memory are initiated proactively by the main chip's software. The main chip's logic circuits can only perform command scheduling and transmission; they cannot proactively initiate query commands. In other words, in scenarios where the main chip's logic circuits initiate a sleep request to the flash memory, the flash memory may enter a sleep state before its working commands have been completed, leading to flash memory read / write errors and data loss, resulting in poor reliability. Summary of the Invention

[0005] This application provides a message notification method and apparatus that can solve the problem that the main chip may need to query multiple times to know the execution status of the flash memory's working commands, which leads to a long sleep process. It can effectively reduce the signaling overhead between the main chip and the flash memory, thereby improving sleep efficiency and reducing power consumption. It is also applicable to scenarios where the logic circuit of the main chip actively initiates a sleep request to the flash memory, so as to improve the reliability of sleep.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] Firstly, a message notification method is provided, applied to the flash memory of a terminal device, the terminal device further including a main chip. The method includes: the flash memory receiving a first sleep request from the main chip; the flash memory detecting the execution status of a work command initiated locally; wherein the work command is used to initiate a read / write operation between the flash memory and the main chip; and the flash memory sending a first notification to the main chip. The first notification indicates the execution status of the work command and whether a conflict exists between the first sleep request and the execution of the work command.

[0008] Based on the message notification method provided in the first aspect, after receiving the first sleep request from the main chip, the flash memory can independently detect the execution status of the working commands initiated locally and proactively send the detection results to the main chip. Therefore, the main chip does not need to send multiple query commands to the flash memory to obtain the execution status of the flash memory's working commands, effectively reducing signaling overhead between the main chip and the flash memory, thereby improving sleep efficiency and reducing power consumption. Furthermore, since the execution status of the working commands is proactively sent from the flash memory to the main chip, rather than being queried by the main chip through query commands, the main chip can obtain the execution status of the flash memory's working commands regardless of whether the sleep request is initiated by the main chip's software or its logic circuitry. This ensures that the flash memory's working commands are not lost, the integrity of data read / write operations is maintained, and the reliability of the flash memory entering sleep mode is guaranteed.

[0009] In one possible design, the first notification can be used to indicate the existence of a work command in an executing or pending state, and to indicate a conflict between a first sleep request and the execution of a work command. When the main chip receives the first notification indicating the existence of a work command in an executing or pending state, it can determine that the first sleep request initiated by the main chip conflicts with the work command initiated by the flash memory. The main chip and flash memory fail to enter sleep mode, allowing the flash memory to continue executing the work command, thus ensuring that the flash memory's work command is not lost.

[0010] Furthermore, after the flash memory sends the first notification to the main chip, the method provided in the first aspect may also include: the flash memory continuing to execute the working command. This ensures that the working command is not affected by the first sleep request issued by the main chip, and that the original process continues to execute.

[0011] Alternatively, after the flash memory sends the first notification to the main chip, the method provided in the first aspect may further include: the flash memory receiving a second sleep request from the main chip. After sending the first notification to the main chip, the flash memory continues to execute working commands. Upon receiving the second sleep request, if the flash memory has completed executing its working commands, it can enter a sleep state, thereby reducing power consumption.

[0012] In another possible design, the first notification can be used to indicate that there are no work commands in an executing or pending state, and that the first sleep request does not conflict with the execution of a work command. After the main chip receives the first notification indicating that there are no work commands in an executing or pending state, the flash memory and the main chip each enter a sleep state according to an agreed-upon process to reduce power consumption.

[0013] Furthermore, after the flash memory sends the first notification to the main chip, the method provided in the first aspect may further include: the flash memory disabling its command sending function and entering a sleep state. After disabling the command sending function, even if a working command is generated again, the flash memory will no longer send the working command to the main chip, thus preventing the loss of working commands.

[0014] In one possible design, the flash memory's protocol stack may include a physical layer and firmware. The flash memory's detection of the execution status of working commands may include: after receiving a first sleep request, the physical layer sends an interrupt handling request to the firmware. Accordingly, in response to the interrupt handling request, the firmware detects the execution status of the working commands and sends the detection result to the physical layer.

[0015] Secondly, a message notification device is provided, applied to the flash memory of a terminal device. The terminal device also includes a main chip. The device includes a transceiver unit and a processing unit. The transceiver unit is used to receive a first sleep request from the main chip. The processing unit is used to detect the execution status of a work command initiated by the local device. The work command is used to initiate read / write operations between the device and the main chip. The transceiver unit is also used to send a first notification to the main chip. The first notification is used to indicate the execution status of the work command and whether a conflict exists between the first sleep request and the execution of the work command.

[0016] In one possible design, the first notification can be used to indicate that there is a work command in an executing state or a pending state, and that a first hibernation request conflicts with the execution work command.

[0017] Furthermore, the processing unit can also be used to continue executing working commands after sending the first notification to the main chip.

[0018] Alternatively, the transceiver unit can also be used to receive a second sleep request from the main chip after the flash memory sends a first notification to the main chip.

[0019] In another possible design, the first notification can also be used to indicate that there are no work commands in an executing or pending state, and that the first hibernation request does not conflict with the execution of the work command.

[0020] Furthermore, the processing unit can also be used to disable the command sending function and enter a sleep state after the flash memory sends the first notification to the main chip.

[0021] In one possible design, the flash memory protocol stack may include a physical layer and firmware. Specifically, the processing unit is used for the physical layer to send an interrupt handling request to the firmware after receiving a first sleep request; the firmware responds to the interrupt handling request by detecting the execution status of the working command; and the firmware sends the detection result to the physical layer.

[0022] Optionally, the transceiver unit provided in the second aspect may include a receiving unit and a sending unit. The sending unit is used to perform the sending function of the message notification device implementing the second aspect, and the receiving unit is used to perform the receiving function of the message notification device implementing the second aspect.

[0023] Optionally, the apparatus provided in the second aspect may further include a storage unit. The storage unit stores programs or instructions. When the processing module executes the program or instructions, the apparatus can perform the message notification method of the first aspect.

[0024] It should be noted that the message notification device described in the second aspect can be a terminal device or a network device, or it can be a chip (system) or other component or assembly that can be set in a terminal device or a network device, or it can be a device that includes a terminal device or a network device. This application does not limit it in this regard.

[0025] Thirdly, a message notification method is provided, applied to the main chip of a terminal device, which also includes flash memory. The method includes: the main chip sending a first sleep request to the flash memory; and the main chip receiving a first notification from the flash memory. The first notification indicates the execution status of a working command and whether there is a conflict between the first sleep request and the execution of the working command. The working command is used by the flash memory to initiate read / write operations with the main chip.

[0026] In one possible design, the first notification can be used to indicate the existence of a work command in an executing or pending state, and a conflict between a first sleep request and the execution of a work command. After the main chip receives the first notification from the flash memory, the method described in the third aspect may further include: the main chip starting a timer. After the timer expires, the main chip sends a second sleep request to the flash memory.

[0027] In one possible design, the first notification can be used to indicate that there are no work commands in an executing or pending state, and that the first sleep request does not conflict with the execution of a work command. After the main chip receives the first notification from the flash memory, the method described in the third aspect may further include: the main chip entering a sleep state.

[0028] Fourthly, a message notification device is provided, applied to the main chip of a terminal device, the terminal device further including flash memory. The device includes a sending unit and a receiving unit. The sending unit is used to send a first sleep request to the flash memory. The receiving unit is used to receive a first notification from the flash memory. The first notification indicates the execution status of a working command and whether there is a conflict between the first sleep request and the execution of the working command. The working command is used for the flash memory to initiate read / write operations with the main chip.

[0029] In one possible design, the first notification can be used to indicate the existence of a work command in an executing or pending state, and that a first sleep request conflicts with the execution of a work command. The apparatus described in the fourth aspect may further include a processing unit. The processing unit is used to start a timer. The sending unit is further used to send a second sleep request to the flash memory after the timer expires.

[0030] In one possible design, the first notification can be used to indicate that there are no work commands in an executing or pending state, and that the first sleep request does not conflict with the execution work command. The apparatus described in the fourth aspect may further include a processing unit. The processing unit is used to enable the main chip to enter a sleep state.

[0031] Optionally, the receiving unit and the sending unit provided in the fourth aspect can be integrated into a transceiver unit, which is used to perform the sending and receiving functions of the message notification device implementing the fourth aspect.

[0032] Optionally, the apparatus provided in the fourth aspect may further include a storage unit. The storage unit stores programs or instructions. When the processing module executes the program or instructions, the apparatus can perform the message notification method of the third aspect.

[0033] It should be noted that the message notification device described in the fourth aspect may be a terminal device or a network device, or it may be a chip (system) or other component or assembly that can be set in a terminal device or a network device, or it may be a device that includes a terminal device or a network device. This application does not limit it in this regard.

[0034] Fifthly, this application also provides an electronic device. The electronic device includes: flash memory; read-only memory; and one or more computer programs. The one or more computer programs are stored on the read-only memory, and when executed by the flash memory, cause the electronic device to perform the message notification method described in the first or third aspect.

[0035] In a sixth aspect, embodiments of this application also provide a computer-readable storage medium, which includes a computer program or instructions that, when executed on a computer, cause the computer to perform the message notification method in the first or third aspect.

[0036] In a seventh aspect, this application also provides a computer program product, comprising: a computer program or instructions that, when executed on a computer, cause the computer to perform the message notification method of the first or third aspect.

[0037] Understandably, the apparatus provided in the second aspect, the method provided in the third aspect, the apparatus provided in the fourth aspect, the electronic device provided in the fifth aspect, the computer-readable storage medium provided in the sixth aspect, and the computer program product provided in the seventh aspect are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here. Attached Figure Description

[0038] Figure 1 A schematic diagram of the hardware structure of a mobile phone provided in an embodiment of this application;

[0039] Figure 2 Flowchart of the message notification method provided in the embodiments of this application Figure 1 ;

[0040] Figure 3 A schematic diagram illustrating the principle of flash memory detection of the execution status of work commands initiated by the local end, provided in an embodiment of this application.

[0041] Figure 4 Flowchart of the message notification method provided in the embodiments of this application Figure 2 ;

[0042] Figure 5 Schematic diagram of the message notification device provided in the embodiments of this application Figure 1 ;

[0043] Figure 6 Schematic diagram of the message notification device provided in the embodiments of this application Figure 2 ;

[0044] Figure 7 This is a schematic diagram of the structural composition of the electronic device provided in the embodiments of this application. Detailed Implementation

[0045] The technical terms used in the embodiments of this application are described below.

[0046] Universal Flash Storage (UFS): Universal Flash Storage (UFS) is a type of memory built on serial data transmission technology that allows for multiple erases and writes during operation. Although there are only two data channels between its internal storage units and the main chip, its actual data transmission speed is very high due to the use of serial data transmission. UFS supports full-duplex mode, meaning all data channels can perform read and write operations simultaneously, resulting in very high response speeds for data read and write operations.

[0047] Universal Flash Storage Host Controller Interface (UFSHCI): The external interface between the host chip and the flash memory is the UFS interface. The host chip controls and interacts with the UFS via the APB bus and the AXI bus. When the host chip accesses the UFSHCI via the APB bus, the UFS address space can be directly accessed by the host chip by allocating virtual address space in the kernel through ioremap. The host chip can also allocate virtual address space through the dma_alloc interface and access the UFS via the AXI bus.

[0048] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0049] The message notification method provided in this application can be applied to electronic devices, such as mobile phones, tablets, laptops, ultra-mobile personal computers (UMPCs), handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, etc. This application does not impose any limitations on this.

[0050] For example, such as Figure 1As shown, the electronic device in this embodiment can be a mobile phone 100. The following detailed description uses mobile phone 100 as an example. It should be understood that the illustrated mobile phone 100 is merely an example of the aforementioned electronic device, and mobile phone 100 may have more or fewer components than shown in the figure, may combine two or more components, or may have different component configurations.

[0051] like Figure 1 As shown, the mobile phone 100 includes a main chip 101, internal memory 121, external memory interface 122, antenna A, mobile communication module 131, antenna B, wireless communication module 132, audio module 140, speaker 140A, receiver 140B, microphone 140C, headphone jack 140D, display screen 151, subscriber identification module (SIM) card interface 152, camera 153, buttons 154, sensor module 160, universal serial bus (USB) interface 170, charging management module 180, power management module 181, and battery 182. In some embodiments, the mobile phone 100 may also include a motor, indicator, etc.

[0052] The main chip 101 may include one or more processing units. For example, the main chip 101 may include an application processor (AP), a modem, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). It should be noted that different processing units can be independent devices or integrated into one or more independent processors, and can be integrated with other modules in the mobile phone 100 within the same device.

[0053] The internal memory 121 can be used to store data and / or at least one computer program, which includes instructions. Specifically, the internal memory 121 may include a program storage area and a data storage area. The program storage area may store at least one computer program. The computer program may include applications (such as a gallery, contacts, etc.), operating systems (such as Android or iOS), or other programs. The data storage area may store at least one of the following: data created during the use of the mobile phone 100, data received from other devices (such as other mobile phones 100, network devices, servers, etc.), or data pre-stored before leaving the factory. For example, the data stored in the internal memory 121 may be at least one of the following: images, files, or identification information.

[0054] In some embodiments, internal memory 121 may include high-speed random access memory and / or non-volatile memory. For example, internal memory 121 may include one or more disk storage devices, flash memory, or universal flash storage (UFS), etc.

[0055] The main chip 101 can invoke one or more computer programs and / or data stored in the internal memory 121, thereby enabling the mobile phone 100 to perform one or more functions to meet the user's needs. For example, the main chip 101 can invoke instructions and data stored in the internal memory 121 to cause the electronic device to execute the message notification method provided in the embodiments of this application.

[0056] The external storage interface 122 can be used to connect an external storage card (e.g., a Micro SD card) to expand the storage capacity of the mobile phone 100. The external storage card communicates with the main chip 101 through the external storage interface 122 to perform data storage functions. For example, images, music, and video files can be saved on the external storage card.

[0057] In some embodiments, a cache area may also be provided in the main chip 101 to store instructions and / or data that the main chip 101 needs to use repeatedly. If the main chip 101 needs to use the instruction or data again, it can directly retrieve it from the cache area. This helps to avoid repeated accesses, reduce the waiting time of the main chip 101, and thus help improve the efficiency of the system. For example, the cache area can be implemented using a high-speed cache memory.

[0058] It should be understood that Figure 1The structure of the mobile phone 100 shown is merely an example. The mobile phone 100 of this application embodiment may have more or fewer components than those shown in the figures, may combine two or more components, or may have different component configurations. The various components shown in the figures can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0059] For example, Figure 2 Flowchart of the message notification method provided in the embodiments of this application Figure 1 Taking the aforementioned mobile phone 100 as an example of the aforementioned electronic device, this message notification method can be applied to the flash memory and main chip of the mobile phone 100. The method may include the following steps:

[0060] S201, the main chip 101 sends a first sleep request to the flash memory 102, and the flash memory 102 receives the first sleep request from the main chip 101.

[0061] The main chip 101 and the flash memory 102 can interact via a data transmission link, which may include a first transmission channel and a second transmission channel. The first and second transmission channels can be implemented based on the same set of buses connecting the main chip 101 and the flash memory 102; alternatively, the first transmission channel can be implemented using one set of buses connecting the main chip 101 and the flash memory 102, and the second transmission channel can be implemented using another set of buses connecting the main chip 101 and the flash memory 102. The first transmission channel is used by the main chip 101 to transmit data / signals to the flash memory 102, and the second transmission channel is used by the flash memory 102 to transmit data / signals to the main chip 101. To save power, when the main chip 101 does not need to access the flash memory, it can send a first sleep request to the flash memory 102 through the first transmission channel, so that both the main chip 101 and the flash memory 102 enter a sleep state, thereby saving power.

[0062] The protocol stack of the main chip 101 includes firmware and a physical layer. Specifically, the process by which the main chip 101 detects whether it needs to access the flash memory can be as follows: When the firmware of the main chip 101 needs to read data from the flash memory 102, the firmware reads the data from the flash memory 102 through the physical layer. Alternatively, when the firmware of the main chip 101 needs to write data, the firmware writes the data to the double data rate synchronous dynamic random access memory (DDR) and notifies the physical layer of the main chip 101 to send a data write request to the flash memory 102. After receiving the data write request, the flash memory 102 sends a data acquisition instruction packet to the main chip 101. After receiving the data acquisition instruction packet, the main chip 101 writes the data to the flash memory 102. Whether the firmware of the main chip 101 needs to read data, write data, or has other command transmissions, the main chip 101 determines that it needs to access the flash memory. Conversely, if the firmware of the main chip 101 neither needs to read data nor write data, and there are no other commands to be transmitted, the main chip 101 determines that there is no service to process.

[0063] Alternatively, the flash memory 102 may also include firmware and a physical layer, and the physical layer of the flash memory 102 receives a first sleep request from the main chip 101 and sends it to the firmware of the flash memory 102.

[0064] S202, Flash memory 102 detects the execution status of work commands initiated by the local end.

[0065] The working command is used to initiate data read / write operations with the main chip 101. The execution status of the working command includes at least a working command in execution, a working command to be executed, and a working command with no working command to be executed.

[0066] For example, such as Figure 3 As shown, after receiving the first sleep request, the physical layer of flash memory 102 does not immediately enter a sleep preparation state, nor does it send a confirmation instruction to the main chip 101 to enter a sleep state. Instead, it sends an interrupt handling request to the firmware of flash memory 102. In response to the interrupt handling request, the firmware of flash memory 102 checks the execution status of the working command. Finally, the firmware of flash memory 102 sends the detection result to the physical layer. For example, the firmware of flash memory 102 configures a register in the physical layer of flash memory 102, which is used to instruct flash memory 102 to send a first notification to the main chip 101. This first notification indicates the execution status of the working command and confirms that the first sleep request and the execution of the working command do not conflict.

[0067] Flash memory 102 will perform different operations depending on the execution state of the working command. Please continue to refer to [the relevant documentation / reference]. Figure 2 The message notification method may also include:

[0068] If in S202, the flash memory 102 detects a working command that is in an executing state or a pending state, then S203 is executed.

[0069] S203, flash memory 102 sends a first notification to main chip 101, and main chip 101 receives the first notification from flash memory 102.

[0070] The first notification indicates that there is a work command in an executing or pending state, and that the first sleep request conflicts with the work command. For example, the value of the PACP_PWR_cnf field included in the first notification can be conflict. Here, "conflict" can also be represented by a binary number, such as using the binary number 1 to represent a conflict; this embodiment of the application does not specifically limit this. Specifically, the flash memory 102 sends the first notification to the main chip 101 through the second transmission channel. When the main chip 101 receives the first notification indicating that there is a work command in an executing or pending state, it indicates that the first sleep request initiated by the main chip 101 conflicts with the work command of the flash memory 102, and the main chip 101 and flash memory 102 fail to enter the sleep state.

[0071] S204, Flash 102 continues to execute work commands.

[0072] After receiving the first notification, the physical layer of the main chip 101 sends the first notification to the firmware of the main chip 101. The firmware of the main chip 101 parses the first notification. If it finds that the value of the PACP_PWR_cnf field in the first notification is "conflict", then it executes S205.

[0073] S205, the main chip 101 starts the timer and begins timing.

[0074] If the first notification received by the main chip 101 is conflicting, in order to ensure that the flash memory 102 can continue to execute working commands, it can temporarily not enter a sleep state, nor can it control the flash memory 102 to enter a sleep state. Instead, a timer can be started, for example, by the firmware of the main chip 101 or by UFSHCI. During the timer's timing, the flash memory 102 continues to execute working commands.

[0075] The timer timeout value can be set to 50ms, 100ms, 200ms, etc., and no specific limit is set here.

[0076] S206, main chip 101 timeout.

[0077] For example, when the timer reaches its timeout value, it can be considered that the main chip 101 has timed out.

[0078] S207, the main chip 101 sends a second sleep request to the flash memory 102. The flash memory 102 receives the second sleep request from the main chip 101 and returns to execute S203.

[0079] Similar to the first sleep request, the main chip 101 also sends the second sleep request through the first transmission channel.

[0080] Similarly, when flash memory 102 receives a second hibernation request, flash memory 102 returns to execute S203. If flash memory 102 detects a working command that is in an executing state or a pending state, it continues to execute S204-S207.

[0081] If flash memory 102 detects that no work command is in an executing or pending state, it sends a second notification to main chip 101, which receives the second notification from flash memory 102. The second notification indicates that no work command is in an executing or pending state, and that the first sleep request does not conflict with the execution of the work command. For example, the value of the PACP_PWR_cnf field in the second notification can be either "ready" (ok) or the binary number "0". The firmware of main chip 101 parses the second notification to obtain its content: "ready" (ok) or "0". Then, main chip 101 enters a sleep state, and flash memory 102 also enters a sleep state. In this way, if the work command of flash memory 102 has not been completed, the execution of the work command by flash memory 102 will be prioritized; if the work command of flash memory 102 has been completed, main chip 101 and flash memory 102 will each enter a sleep state according to the agreed-upon process, saving power and preventing the loss of work commands from flash memory 102.

[0082] based on Figure 2 The message notification method shown allows flash memory 102 to detect the execution status of its locally initiated work commands after receiving a first sleep request from the main chip, and actively send the detection result to the main chip 101. Therefore, the main chip 101 can obtain the execution status of flash memory 102's work commands without issuing multiple query commands to flash memory 102, effectively reducing signaling overhead between the main chip 101 and flash memory 102, thereby improving sleep efficiency and reducing power consumption. Furthermore, since the execution status of the work commands is actively sent from flash memory 102 to the main chip 101, rather than queried by the main chip 101 through query commands, the main chip 101 can obtain the execution status of flash memory's work commands regardless of whether the sleep request is initiated by the main chip 101's software or its logic circuit. This ensures that the work commands of flash memory 102 are not lost, the integrity of data read / write operations is maintained, and the reliability of flash memory 102 entering sleep mode is guaranteed.

[0083] For example, Figure 4 Flowchart of the message notification method provided in the embodiments of this application Figure 2 Taking the aforementioned mobile phone 100 as an example of the aforementioned electronic device, this message notification method can be applied to the flash memory 102 and the main chip 101 of the mobile phone 100. The method may include the following steps:

[0084] S401, the main chip 101 sends a first sleep request to the flash memory 102, and the flash memory 102 receives the first sleep request from the main chip 101.

[0085] S402, Flash 102 detects the execution status of work commands initiated by the local end.

[0086] The specific implementations of S401-S402 can be referred to S201-S202 above, and will not be repeated here.

[0087] It should be noted that if in S402, the flash memory 102 detects that there is no working command in the execution state or the pending execution state, then S403 can be executed.

[0088] S403, flash memory 102 sends a second notification to main chip 101, and main chip 101 receives the second notification from flash memory 102.

[0089] The second notification indicates that there are no work commands in an executing or pending state, and that the first sleep request does not conflict with the execution of the work command. For example, the value of the PACP_PWR_cnf field in the second notification can be "ready" (ok). "Ready" can also be represented by a binary number, such as 0, which is not specifically limited in this embodiment. Specifically, the flash memory 102 can send the second notification to the main chip 101 through the second transmission channel. Correspondingly, the main chip 101 can receive the second notification from the flash memory 102 through the second transmission channel.

[0090] It should be noted that if flash memory 102 needs to execute new work commands after sending the second notification to main chip 101, it can continue to notify main chip 101 to perform read / write operations. However, after receiving the second notification from flash memory 102, main chip 101 may have already entered a sleep state, thus failing to receive notifications to execute read / write operations, which would still result in the loss of work commands. To solve this problem, the message notification method may further include:

[0091] S404, Flash 102 disables command sending function.

[0092] Specifically, the firmware and / or physical layer of flash memory 102 can disable the command sending function. After disabling the command sending function, flash memory 102 will no longer send working commands to the main chip even if working commands are generated, thus preventing the loss of working commands.

[0093] S405, main chip 101 enters sleep mode, flash memory 102 enters sleep mode.

[0094] For example, the specific implementation process of S403 may include: after receiving the second notification, the main chip 101 sends a first specific sequence to the flash memory 102, and the flash memory 102 receives the first specific sequence. The main chip 101 and the flash memory 102 close the first transmission channel based on the first sequence. Similarly, the flash memory 102 may also send a second specific sequence to the main chip 101, and the main chip 101 receives the second specific sequence. The main chip 101 and the flash memory 102 close the second transmission channel based on the second specific sequence. Finally, the main chip 101 enters a sleep state, and the flash memory 102 enters a sleep state. The first specific sequence and the second specific sequence can be transition signals composed of multiple level signals.

[0095] It should be noted that if the main chip 101 is woken up, and if the main chip receives a service that needs to be processed, the main chip 101 can wake up the flash memory 102. After being woken up, the flash memory 102 enables the command sending function so as to send previously unsent work commands to the main chip 101.

[0096] based on Figure 4 The message notification method shown allows flash memory 102 to detect the execution status of its locally initiated work commands after receiving a first sleep request from the main chip, and actively send the detection result to the main chip 101. Therefore, the main chip 101 can obtain the execution status of flash memory 102's work commands without issuing multiple query commands to flash memory 102, effectively reducing signaling overhead between the main chip 101 and flash memory 102, thereby improving sleep efficiency and reducing power consumption. Furthermore, since the execution status of the work commands is actively sent from flash memory 102 to the main chip 101, rather than queried by the main chip 101 through query commands, the main chip 101 can obtain the execution status of flash memory's work commands regardless of whether the sleep request is initiated by the main chip 101's software or its logic circuit. This ensures that the work commands of flash memory 102 are not lost, the integrity of data read / write operations is maintained, and the reliability of flash memory 102 entering sleep mode is guaranteed.

[0097] For example, Figure 5 This is one of the structural schematic diagrams of a message notification device 500 provided in an embodiment of this application. The message notification device 500 is applied to the flash memory 102 and can be used to perform... Figure 2 or Figure 4 The message notification method is executed in the flash memory 102. It should be noted that the message notification device 500 provided in this embodiment has the same basic principle and technical effects as the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. For example... Figure 5 As shown, the message notification device 500 includes a transceiver unit 501 and a processing unit 502. The transceiver unit 501 is used to execute S201, S203, S207, S401 and S403, and the processing unit 502 is used to execute S202, S204, S402, S404 and S405.

[0098] For example, Figure 6 This is a second schematic diagram of the message notification device 600 provided in an embodiment of this application. The message notification device 600 is applied to the main chip 101 and can be used to execute... Figure 2 or Figure 4 The message notification method is executed by the main chip 101. It should be noted that the message notification device 600 provided in this embodiment has the same basic principle and technical effects as the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0099] like Figure 6 As shown, the message notification device 600 includes a sending unit 601, a receiving unit 602, and a processing unit 603. The sending unit 601 executes steps S201, S203, and S207 as described above. The receiving unit 602 executes steps S401 and S403 as described above. The processing unit 603 executes steps S205, S206, and S405 as described above.

[0100] For example, Figure 7 This is a schematic diagram of the structure of the electronic device 700 provided in an embodiment of this application. The following is in conjunction with... Figure 7 A detailed introduction to each component of the electronic device 700 is provided below:

[0101] The main chip 701 is the control center of the electronic device 700, and may include one or more processors. For example, the main chip 701 may include one or more central processing units (CPUs), or may include application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of this application, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0102] Optionally, the main chip 701 can perform various functions of the electronic device 700 by running or executing software programs stored in the read-only memory 702 and calling data stored in the read-only memory 702. For example, the main chip 701 can execute S201, S203, S205, S207, S207, S401, S403, and S405 in the above embodiments of this application, which are not limited herein.

[0103] In a specific implementation, as one example, the main chip 701 may include one or more CPUs, for example... Figure 7 CPU0 and CPU1 are shown in the diagram.

[0104] The read-only memory 702 is used to store the software program that executes the solution of this application, and is controlled by the main chip 701. The specific implementation method can be referred to the above method embodiment, which will not be repeated here.

[0105] Optionally, the read-only memory 702 may be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The read-only memory 702 may be integrated with the main chip 701 or exist independently, and may be accessed through the interface circuit of the electronic device 700. Figure 7 (Not shown in the image) is coupled to the main chip 701, and this embodiment does not specifically limit this.

[0106] Transceiver 703 is used for communication with other electronic devices. For example, if electronic device 700 is an electronic device, transceiver 703 can be used to communicate with a network device or with another electronic device. As another example, if electronic device 700 is a network device, transceiver 703 can be used to communicate with an electronic device or with another network device.

[0107] Optionally, transceiver 703 may include a receiver and a transmitter. Figure 7 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the sending function.

[0108] Optionally, the transceiver 703 can be integrated with the main chip 701, or it can exist independently and be connected via the interface circuit of the electronic device 700. Figure 7 (Not shown in the image) is coupled to the main chip 701, and this embodiment does not specifically limit this.

[0109] Flash memory 704, built on serial data transmission technology, is a memory that allows for multiple erases and writes during operation. Although there are only two data channels between its internal storage units and the main chip, its actual data transmission speed is very high due to the use of serial data transmission. UFS supports full-duplex mode, where all data channels can perform read and write operations simultaneously, resulting in very high response speeds for data read and write operations. Flash memory 704 can execute S201, S202, S203, S204, S207, S401, S402, S403, S404, and S405 in the above embodiments of this application.

[0110] It should be noted that, Figure 7 The structure of the electronic device 700 shown does not constitute a limitation on the message notification device. The actual message notification device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0111] Furthermore, the technical effects of the electronic device 700 can be referred to the technical effects of the message notification method described in the above method embodiments, and will not be repeated here.

[0112] This application also provides a computer-readable storage medium storing computer program code. When a processor executes the computer program code, the electronic device performs the method described in the above embodiments.

[0113] This application also provides a computer program product that, when run on an electronic device, causes the electronic device to execute the methods described in the above embodiments.

[0114] This application also provides a chip system, including: a processor coupled to a memory, the memory being used to store programs or instructions, wherein when the program or instructions are executed by the processor, the chip system implements the methods in any of the above method embodiments.

[0115] Optionally, the chip system may contain one or more processors. These processors can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor, implemented by reading software code stored in memory.

[0116] Optionally, the chip system may contain one or more memories. The memory may be integrated with the processor or disposed separately from it; this application does not limit this. For example, the memory may be a non-transient processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip or disposed separately on different chips. This application does not specifically limit the type of memory or the arrangement of the memory and processor.

[0117] For example, the chip system may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0118] This application provides a message notification system. The message notification system includes one or more terminal devices and / or one or more network devices.

[0119] It should be understood that the processor in the embodiments of this application can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0120] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0121] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0122] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0123] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0124] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0125] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0127] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0128] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0130] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A message notification method characterized by, The application relates to a flash memory applied to a terminal device, wherein the terminal device further comprises a main chip, and the method comprises the following steps: The flash memory receives a first sleep request from the main chip; The flash memory detects an execution state of a work command initiated by the flash memory, wherein the work command is used for initiating a read / write operation between the flash memory and the main chip; The flash memory sends a first notification to the main chip, wherein the first notification is used for indicating the execution state of the work command and whether the first sleep request conflicts with the execution of the work command.

2. The method of claim 1, wherein, The first notification is used for indicating that there is a work command in an execution state or a standby execution state, and the first sleep request conflicts with the execution of the work command.

3. The method of claim 2, wherein, After the flash memory sends the first notification to the main chip, the method further comprises the following steps: The flash memory continues to execute the work command.

4. The method of claim 2, wherein, After the flash memory sends the first notification to the main chip, the method further comprises the following steps: The flash memory receives a second sleep request from the main chip.

5. The method of claim 1, wherein, The first notification is used for indicating that there is no work command in an execution state or a standby execution state, and the first sleep request does not conflict with the execution of the work command.

6. The method of claim 4, wherein, After the flash memory sends the first notification to the main chip, the method further comprises the following steps: The flash memory closes a command sending function; The flash memory enters a sleep state.

7. The method according to any one of claims 1 to 6, characterized in that, The protocol stack of the flash memory comprises a physical layer and a firmware, The flash memory detects the execution state of the work command, and the detection comprises the following steps: The physical layer sends an interrupt processing request to the firmware after receiving the first sleep request; The firmware detects the execution state of the work command in response to the interrupt processing request; The firmware sends a detection result to the physical layer.

8. A message notification apparatus characterized by comprising: The application relates to a flash memory applied to a terminal device, wherein the terminal device further comprises a main chip, and the device comprises a transceiving unit and a processing unit, wherein The transceiving unit is used for receiving a first sleep request from the main chip; The processing unit is used for detecting an execution state of a work command initiated by the flash memory, wherein the work command is used for initiating a read / write operation between the flash memory and the main chip; The transceiving unit is further used for sending a first notification to the main chip, wherein the first notification is used for indicating the execution state of the work command and whether the first sleep request conflicts with the execution of the work command.

9. The apparatus of claim 8, wherein, The first notification is used for indicating that there is a work command in an execution state or a standby execution state, and the first sleep request conflicts with the execution of the work command.

10. The apparatus of claim 9, wherein, The processing unit is further used for continuing to execute the work command after the transceiving unit sends the first notification to the main chip.

11. The apparatus of claim 9, wherein, The transceiving unit is further used for receiving a second sleep request from the main chip after the flash memory sends the first notification to the main chip.

12. The apparatus of claim 8, wherein, The first notification is used for indicating that there is no work command in an execution state or a standby execution state, and the first sleep request does not conflict with the execution of the work command.

13. The apparatus of claim 12, wherein, The processing unit is further used for closing a command sending function and entering a sleep state after the flash memory sends the first notification to the main chip.

14. The apparatus of any one of claims 8-13, wherein, The protocol stack of the flash memory includes a physical layer and a firmware, and the processing unit is specifically configured to send an interrupt processing request to the firmware after the physical layer receives the first sleep request; the firmware detects an execution state of the work command in response to the interrupt processing request; and the firmware sends the detection result to the physical layer.

15. A message notification method characterized by comprising: The method is applied to a main chip of a terminal device, and the terminal device further includes a flash memory. The main chip sends a first sleep request to the flash memory. The main chip receives a first notification from the flash memory, where the first notification is used to indicate an execution state of a work command and whether the first sleep request conflicts with execution of the work command, and the work command is used for the flash memory to initiate a read / write operation with the main chip.

16. The method of claim 15, wherein, The first notification is used to indicate that there is a work command in an execution state or a to-be-executed state, and the first sleep request conflicts with execution of the work command. After the main chip receives the first notification from the flash memory, the method further includes: The main chip starts a timer. After the timer times up, the main chip sends a second sleep request to the flash memory.

17. The method of claim 15, wherein, The first notification is used to indicate that there is no work command in an execution state or a to-be-executed state, and the first sleep request does not conflict with execution of the work command. After the main chip receives the first notification from the flash memory, the method further includes: The main chip enters a sleep state.

18. A message notification apparatus characterized by comprising: The method is applied to a main chip of a terminal device, and the terminal device further includes a flash memory. The sending unit is configured to send a first sleep request to the flash memory. The receiving unit is configured to receive a first notification from the flash memory, where the first notification is used to indicate an execution state of a work command and whether the first sleep request conflicts with execution of the work command, and the work command is used for the flash memory to initiate a read / write operation with the main chip.

19. The apparatus of claim 18, wherein, The first notification is used to indicate that there is a work command in an execution state or a to-be-executed state, and the first sleep request conflicts with execution of the work command. The processing unit is configured to start a timer. The sending unit is further configured to send a second sleep request to the flash memory after the timer times up.

20. The apparatus of claim 18, wherein, The first notification is used to indicate that there is no work command in an execution state or a to-be-executed state, and the first sleep request does not conflict with execution of the work command. The processing unit is configured to enable the main chip to enter a sleep state.

21. An electronic device, comprising: The method includes: a flash memory; a read-only memory; and one or more computer programs, where the one or more computer programs are stored on the read-only memory, and when the computer programs are executed by the flash memory, the electronic device performs the message notification method in any one of claims 1-7 or 15-17.

22. A computer-readable storage medium, characterized in that, The computer readable storage medium includes a computer program or instructions, which, when executed on a computer, cause the computer to perform the message notification method according to any one of claims 1-7 or 15-17.

23. A computer program product, characterised in that, The computer program product includes a computer program or instructions, which, when executed on a computer, cause the computer to perform the message notification method according to any one of claims 1-7 or 15-17.

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