Accelerated units, computing devices, systems on a chip, and related methods

Abstract

Embodiments of the present application provide an acceleration unit, a computing device, a system on chip and related methods. The acceleration unit comprises: a receiving subunit configured to receive a network packet through a network; a packet writing subunit configured to write the network packet into a plurality of memory buffers allocated by a host according to an allocation strategy, wherein at least part of the memory buffers have a data amount written into the memory buffers smaller than a data capacity of the memory buffers; and a queue writing subunit configured to write addresses and occupied lengths of the memory buffers into a completion queue, so that a packet receiving end on the host reads the network packet from the plurality of memory buffers according to the completion queue. The present scheme can improve the efficiency of writing network packets into memory.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and in particular to an acceleration unit, a computing device, a system on chip and related methods. BACKGROUND

[0002] In a cloud computing scenario, the network needs to be virtualized, a host constructs multiple virtual machines (VMs), and an infrastructure processing unit (IPU) writes a network packet into a memory buffer allocated by a virtual machine after receiving the network packet, and then the virtual machine can read the network packet from the memory buffer and perform corresponding processing.

[0003] Currently, when the infrastructure processing unit writes a network packet into a memory buffer, if the data volume of the network packet is greater than the data capacity of one memory buffer, the network packet is stored in multiple memory buffers, and after one memory buffer is written full, the subsequent memory buffer is written, and so on, until the network packet is completely written into the memory buffer.

[0004] However, the data capacity of the memory buffer for caching the network packet is not fixed, and when the network packet is written into the memory buffer until the memory buffer is written full, there may be fragmented operations, resulting in low efficiency of writing the network packet into the memory. SUMMARY

[0005] Therefore, embodiments of the present application provide an acceleration unit, a computing device, a system on chip and related methods to at least solve or alleviate the above problems.

[0006] According to a first aspect of embodiments of the present application, an acceleration unit is provided, comprising: a receiving subunit configured to receive a network packet through a network; a packet writing subunit configured to write the network packet into multiple memory buffers allocated by a host according to an allocation strategy, wherein at least part of the memory buffers has a data volume less than the data capacity of the memory buffer; and a queue writing subunit configured to write the address and the occupied length of the memory buffer into a completion queue, so that a packet receiving end on the host reads the network packet from the multiple memory buffers according to the completion queue.

[0007] According to a second aspect of embodiments of the present application, a computing device is provided, comprising: a processing unit configured to construct a host, the host being configured to allocate multiple memory buffers; and the acceleration unit according to the first aspect.

[0008] According to a third aspect of the embodiments of the present application, a system on chip is provided, comprising the acceleration unit according to the first aspect.

[0009] According to a fourth aspect of the embodiments of the present application, a data center is provided, comprising the computing device according to the second aspect.

[0010] According to a fifth aspect of the embodiments of the present application, a packet transmission method is provided, comprising: receiving a network packet through a network; writing the network packet into a plurality of memory buffers allocated by a host according to an allocation strategy, wherein the data amount written into at least part of the memory buffers is less than the data capacity of the memory buffers; and writing the address and the occupied length of the memory buffers into a completion queue, so that a packet receiving end on the host reads the network packet from the plurality of memory buffers according to the completion queue.

[0011] According to the scheme provided by the embodiments of the present application, after the receiving subunit receives the network packet, the packet writing subunit can write the network packet into the plurality of memory buffers according to the allocation strategy, so that the data amount written into at least part of the memory buffers is less than the data capacity of the memory buffers, and the queue writing subunit can write the address and the occupied length of the memory buffers into the completion queue, so that the packet receiving end on the host can read the network packet from the memory buffers according to the address and the occupied length in the completion queue. Since the packet writing subunit can write the network packet into the plurality of memory buffers according to the allocation strategy, the memory buffers can not be filled, so that the number of times of the occurrence of the fragmented operations in the process of writing the packet data into the memory can be reduced, and the efficiency of writing the network packet into the memory can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0013] Figure 1 is a schematic diagram of a data center of an embodiment of the present application;

[0014] Figure 2 is a schematic diagram of a server of an embodiment of the present application;

[0015] Figure 3 is a schematic diagram of an acceleration unit of an embodiment of the present application;

[0016] Figure 4 is a schematic diagram of a network packet writing process of an embodiment of the present application;

[0017] Figure 5 is a schematic diagram of a network message writing process according to another embodiment of the present application;

[0018] Figure 6 is a schematic diagram of a memory buffer according to an embodiment of the present application;

[0019] Figure 7 is a flow chart of a message transmission method according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The present application is described in the following based on embodiments, but the present application is not limited to these embodiments only. In the following detailed description of the present application, some specific details are described in detail. The present application can also be understood without the description of these details by those skilled in the art. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0021] First, some of the nouns or terms appearing in the description of the embodiments of the present application are applicable to the following explanations.

[0022] Infrastructure processor: Infrastructure Processing Units (IPU) is a special processor designed for cloud data center, which accesses physical computing, storage, network resources downward, fast cloud and hardware acceleration, accesses cloud operating system upward, and controls the server of cloud data center. Infrastructure processor can solve the problem of data migration bandwidth, and can also cloud and virtualize the control of data center.

[0023] Host: Host is a cloud server, physical server or virtual host deployed with virtualization environment. The host can create multiple virtual machines and provide software and hardware support for the operation of virtual machines. The host can also include a bare metal server (Bare Metal Server), which is a hardware device with the characteristics of a traditional physical server, and also has the virtualization function of cloud computing technology. It is a combination of hardware and software advantages.

[0024] Virtual machine: Virtual Machine (VM) is a complete computer system that is simulated by software and runs in an isolated environment.

[0025] Packet receiving end: The packet receiving end is the main body of the host for receiving and processing network packets. The packet receiving end can be a virtual machine or a bare-metal server. After the network packet is stored in the memory buffer, the virtual network card can notify the packet receiving end that the network packet has been written into the memory buffer through the write completion queue (CQ) mode, and then the packet receiving end can read the network packet from the memory buffer.

[0026] Memory buffer: The memory buffer is a specified size of storage space reserved in the memory for temporary storage of input / output (I / O) data. The memory buffer in the embodiment of the present application refers to the storage space reserved in the memory for storing network packets.

[0027] System on a chip: System on a chip (SoC) refers to a technology that integrates a complete system on a single chip, grouping all or part of necessary electronic circuits. A complete system generally includes a processor (CPU) or an acceleration unit, a memory, and peripheral circuits, etc. SoC is developed in parallel with other technologies, such as silicon on insulator (SOI), which can provide enhanced clock frequency, thereby reducing the power consumption of the microchip.

[0028] Data center

[0029] A data center is a globally collaborative network of specific devices used to deliver, accelerate, display, compute, and store data information on the Internet network infrastructure. In the future development, the data center will also become an asset for enterprise competition. With the wide application of data centers, virtualization technology is increasingly applied to data centers. As an important support for virtualization technology, infrastructure processors have been widely applied to input / output virtualization scenarios in data centers.

[0030] In a traditional large data center, the network structure is usually as shown in Figure 1 , that is, a hierarchical inter-networking model. This model includes the following parts:

[0031] Server 140: Each server 140 is a processing and storage entity of the data center, and the processing and storage of a large amount of data in the data center are completed by these servers 140.

[0032] Access switch 130: The access switch 130 is a switch used to access the server 140 in the data center. One access switch 130 accesses multiple servers 140. The access switch 130 is usually located at the top of the rack, so it is also called a Top of Rack switch, which is physically connected to the server.

[0033] Aggregation Switch 120: Each aggregation switch 120 connects multiple access switches 130 while providing other services such as firewall, intrusion detection, network analysis, etc.

[0034] Core Switch 110: Core switch 110 provides high speed forwarding for packets coming in and out of the data center and provides connectivity for aggregation switches 120. The network of the entire data center is divided into L3 routed network and L2 routed network, and core switch 110 usually provides a resilient L3 routed network for the entire data center.

[0035] Generally, aggregation switch 120 is the demarcation point between L2 and L3 routed network, and aggregation switch 120 below is L2 network and above is L3 network. Each group of aggregation switches manages a Point Of Delivery (POD), and the POD is an independent VLAN network. Migration of servers within a POD does not require modification of IP address and default gateway because a POD corresponds to one L2 broadcast domain.

[0036] Spanning Tree Protocol (STP) is usually used between aggregation switch 120 and access switch 130. STP makes only one aggregation switch 120 available for a VLAN network, and other aggregation switches 120 are used only when a failure occurs. That is, at the level of aggregation switch 120, horizontal expansion cannot be achieved because even if multiple aggregation switches 120 are added, only one is working.

[0037] Embodiments of the present application can be applied to an input / output virtualization scenario, a virtualization environment can be deployed on server 140, multiple virtual machines and / or bare metal servers can be created based on the virtualization environment, and network packets are sent between virtual machines, between a virtual machine and a bare metal server, between bare metal servers, between a virtual machine and a client, or between a bare metal server and a client through a network.

[0038] Server

[0039] The computing device in the embodiments of the present application can be a server 140 included in a data center, and the server 140 is a real processing device of the data center, Figure 2A structural block diagram inside a server 140 is shown. The server 140 includes a bus-connected memory 210, a processing unit cluster 270, and an acceleration unit cluster 280. The processing unit cluster 270 includes a plurality of processing units 220. The acceleration unit cluster 280 includes a plurality of acceleration units 230. The acceleration unit 230 is a specialized processor designed mainly for accelerating writing network packets into memory in embodiments of the present application, which can be embodied as a graphics processing unit (GPU) designed specially for input / output virtualization, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a cloud infrastructure processing unit (CIPU), an infrastructure processing unit (IPU), or a data processing unit (DPU), etc.

[0040] The architecture design of a conventional processing unit makes the control unit and the storage unit occupy a large part of the space in the architecture, while the computing unit occupies insufficient space. Therefore, it is very effective in logical control, but not efficient in large-scale parallel computing. Therefore, various specialized acceleration units have been developed to improve the operation speed more effectively for different functions and different fields of computing. In embodiments of the present application, the acceleration unit 230 is a hardware accelerator specially designed for accelerating the input / output speed of the packet receiving end. After receiving a network packet, the acceleration unit 230 can write the network packet into a plurality of memory buffers allocated by the host according to a pre-set allocation logic, so that the amount of data written into the memory buffer is less than or equal to the data capacity of the memory buffer, reducing the fragmented operations in the process of writing network packets into the memory buffer, and improving the efficiency of writing network packets into the memory buffer, which will be described in detail below.

[0041] The processing unit 220 is used to build a host, which can include a plurality of packet receiving ends. The packet receiving ends perform input / output through the acceleration unit 230, for example, the packet receiving ends receive network packets through the acceleration unit 230. The host can be built based on one or more processing units 220. The packet receiving ends can include a plurality of virtual machines. A plurality of virtual machines can be created based on one processing unit 220. The plurality of virtual machines created in the same host can perform input / output through one or more acceleration units 230. The plurality of virtual machines performing input / output through one acceleration unit 230 can be created based on the same processing unit 220 or different processing units 220. In embodiments of the present application, the host built by the processing unit 220 can allocate a memory buffer. After the acceleration unit 230 writes the network packet into the memory buffer, the packet receiving end on the host can read the network packet from the memory buffer.

[0042] This application focuses on the structure and configuration of the acceleration unit 230, which will be described in detail later.

[0043] Internal structure of the acceleration unit

[0044] The following is combined Figure 3 The diagram shows the internal structure of the acceleration unit 230, which explains in detail how the acceleration unit 230 works.

[0045] like Figure 3 As shown, the acceleration unit 230 includes a receiving subunit 231, a packet writing subunit 232, and a queue writing subunit 233. The receiving subunit 231 can receive network packets via the network. The packet writing subunit 232, according to an allocation strategy, writes the network packets received by the receiving subunit 231 into multiple memory buffers allocated by the host, ensuring that the amount of data written to at least some memory buffers is less than the data capacity of the memory buffers. The queue writing subunit 233 can write the address and length of the memory buffer used to write the network packets into a completion queue, so that the packet receiver on the host can read network packets from the memory buffers according to the completion queue.

[0046] The host has one or more message receivers running on it. After receiving a network message sent to a message receiver, the acceleration unit 230 needs to write the network message into a memory buffer on the host. Then, the corresponding message receiver can read the network message from the memory buffer and perform corresponding processing based on the read network message. The host pre-allocates multiple memory buffers for caching network messages. The memory buffers are located in the host's main memory (also known as RAM or internal memory).

[0047] The packet receiver running on the host can connect to multiple virtual network interface cards (NICs), which are virtualized by the acceleration unit 230. Before receiving packets in the virtual network, the NIC driver of the packet receiver can allocate one or more queues for packet reception, each queue including multiple memory buffers. When a virtual NIC receives a network packet, it can write the received network packet into its allocated queue, and then the packet receiver to which the virtual NIC belongs can read the network packet from the queue.

[0048] The queues of the virtual network card are allocated by the network card driver, and different types of network card drivers allocate queues according to different logics, so the number of queues allocated by different network drivers for the message receiving end, and the number and data capacity of the memory buffers in the queues are different. For example, the queues allocated by network card driver A for the message receiving end include 10 memory buffers, and the data capacity of the 10 memory buffers is 1024 bytes. The queues allocated by network card driver B for the message receiving end include 5 memory buffers, and the data capacity of the 5 memory buffers is 1024 bytes, 1025 bytes, 1026 bytes, 666 bytes, 1023 bytes and 4096 bytes. Since the network card driver is specified by the user of the message receiving end, the memory buffers of different message receiving ends may be allocated according to different logics, so the data capacity of the memory buffers allocated by the network card driver is not fixed for the acceleration unit 230.

[0049] When the network card driver allocates memory buffers for the message receiving end, the number of memory buffers, the available capacity of the main memory, the available space address of the main memory and the like affect the network card driver, and the plurality of memory buffers allocated by the network card driver can have different data capacities. For example, the network card driver allocates 5 memory buffers for a message receiving end, and the data capacity of the 5 memory buffers is 1024 bytes, 1025 bytes, 1026 bytes, 666 bytes, 1023 bytes and 4096 bytes.

[0050] After the network card driver on the host allocates memory buffers for the message receiving end, the host will store the address and length (data capacity) of the memory buffer into the submission queue (SQ). The submission queue includes a plurality of data, each data includes the address and length of a memory buffer, and the position of each data in the submission queue indicates the write order of the corresponding memory buffer. After receiving the network message, the acceleration unit 230 will determine the write order of each memory buffer according to the submission queue, and then write the network message into the memory buffer according to the write order of each memory buffer. When the data amount of the network message is greater than the data capacity of a memory buffer, the acceleration unit 230 can use a plurality of memory buffers to cache a network message.

[0051] After the receiving subunit 231 receives the network packet, the packet writing subunit 232 writes the network packet into the plurality of memory buffers according to the allocation strategy, so that the data amount of the data written into at least part of the memory buffers is less than the data capacity of the memory buffer, i.e., at least part of the memory buffers is not filled up. The queue writing subunit 233 can write the address and the occupied length of the memory buffer into which the network packet is written into the completion queue (CQ), and then after the network packet is written into the memory buffer, the packet receiving end can find the memory buffer in which the network packet is buffered according to the address recorded in the completion queue, and read the data of the network packet from the found memory buffer according to the occupied length recorded in the completion queue.

[0052] Since at least part of the memory buffers is not filled up, the part of the memory buffer in which the network packet is not written stores invalid data, so it is necessary to record the occupied length of the memory buffer in the completion queue, i.e., how many bytes of the memory buffer are used to store the network packet, so that the packet receiving end can accurately read out the data of the network packet according to the occupied length recorded in the completion queue when reading the network packet from the memory buffer, without reading the invalid data in the memory buffer, thereby ensuring the accuracy of the network packet read by the packet receiving end.

[0053] The queue writing subunit 233 can write the address and the occupied length of the memory buffer into the completion queue after the packet writing subunit 232 writes the network packet into the memory buffer, or can be performed synchronously with the process of writing the network packet into the memory buffer by the packet writing subunit 232, which is not limited in the present application. For example, after the packet writing subunit 232 completes writing the network packet data into one memory buffer, the queue writing subunit 233 writes the address and the occupied length of the memory buffer into the completion queue.

[0054] In the embodiment of the present application, after the receiving subunit 231 receives the network packet, the packet writing subunit 232 can write the network packet into the plurality of memory buffers according to the allocation strategy, so that the data amount of the data written into at least part of the memory buffers is less than the data capacity of the memory buffer, and the queue writing subunit 233 can write the address and the occupied length of the memory buffer into the completion queue, and then the packet receiving end on the host can read the network packet from the memory buffer according to the address and the occupied length in the completion queue. Since the packet writing subunit 232 can write the network packet into the plurality of memory buffers according to the allocation strategy, the memory buffer can not be filled up, thereby reducing the number of times of the occurrence of the fragmented operation in the process of writing the packet data into the memory, and thereby improving the efficiency of writing the network packet into the memory.

[0055] In a possible implementation, the packet writing subunit 232 can split the network packet into multiple packet segments according to the allocation strategy, and write the split multiple packet segments into different memory buffers, so that the data amount of at least part of the packet segments is less than the data capacity of the corresponding memory buffer, that is, the data amount of at least part of the packet segments is less than the data capacity of the memory buffer storing the packet segments.

[0056] After the receiving subunit 231 receives the network packet, the packet writing subunit 232 determines the starting memory buffer from which to write the network packet according to the writing order of the memory buffers, that is, determines the starting memory buffer to write the network packet. After the starting memory buffer is determined, the packet writing subunit 232 can split the network packet into multiple packet segments according to the data capacity of the starting memory buffer and the subsequent memory buffers according to the allocation strategy, and then write the split packet segments into the corresponding memory buffers, where the data amount of the packet segments is less than or equal to the data capacity of the memory buffer storing the packet segments, and there is at least one packet segment whose data amount is less than the data capacity of the memory buffer storing the packet segment.

[0057] When splitting the network packet, the packet writing subunit 232 can first split the network packet into multiple packet segments, and then write the packet segments into the corresponding memory buffers, or can split one packet segment and write the packet segment into the corresponding memory buffer, and then split the remaining part of the network packet until the network packet is completely written into the memory buffer, which is not limited by the embodiments of the present application.

[0058] The packet writing subunit 232 splits the network packet into multiple packet segments according to the allocation strategy, and the data amount of at least part of the packet segments is less than the data capacity of the corresponding memory buffer. Corresponding to the data amount of the network packet, the allocation strategy and the data capacity of the memory buffer, the data amount of part or all of the packet segments is less than the data capacity of the corresponding memory buffer, that is, there is at least one packet segment whose data amount is less than the data capacity of the corresponding memory buffer, while one or more packet segments can have a data amount equal to the data capacity of the corresponding memory buffer.

[0059] In one example, after the packet writing subunit 232 determines the start memory buffer for writing the network packet, it compares the data amount of the network packet with the data capacity of the start memory buffer. If the data amount of the network packet is less than or equal to the data capacity of the start memory buffer, the network packet is written into the start memory buffer, i.e., the network packet is buffered by one memory buffer. If the data amount of the network packet is greater than the data capacity of the start memory buffer, the network packet is split into multiple packet segments according to the allocation strategy, and the multiple packet segments are written into different memory buffers.

[0060] When the data amount of the network packet is less than or equal to the data capacity of the start memory buffer, the start memory buffer can buffer the network packet, i.e., the network packet can be buffered by one memory buffer. The packet writing subunit 232 writes the network packet into the start memory buffer, and the memory space of the memory buffer can be fully utilized, thereby improving the utilization of the memory space. When the data amount of the network packet is greater than the data capacity of the start memory buffer, the start memory buffer cannot buffer all the data of the network packet, and thus the network packet is split into multiple packet segments according to the allocation strategy, and the multiple packet segments are written into different memory buffers. In this way, the network packet can be written into the memory, and the fragmented operations in the process of writing the network packet into the memory are reduced, thereby improving the efficiency of writing the network packet into the memory.

[0061] It should be noted that, when the data amount of the network packet is greater than the data capacity of the start memory buffer, the network packet is split, which is only one possible implementation manner of the embodiments of the present application. In other embodiments, when the data amount of the network packet is less than or equal to the data capacity of the start memory buffer, the network packet can also be split into multiple packet segments according to the allocation strategy, which is not limited in the embodiments of the present application.

[0062] In the embodiments of the present application, the packet writing subunit 232 splits the network packet into multiple packet segments according to the allocation strategy, and writes the packet segments into corresponding memory buffers, so that the data amount of at least part of the packet segments is less than the data capacity of the memory buffer buffering the packet segment, thereby reducing the fragmented operations in the process of writing the network packet into the memory, and improving the efficiency of writing the network packet into the memory.

[0063] In a possible implementation, the allocation strategy defines rules for splitting the network packet, and the packet writing subunit 232 can split the network packet into multiple packet segments according to the allocation strategy, and write the multiple packet segments into corresponding multiple memory buffers, so as to reduce fragmented operations in the process of writing the network packet into the memory, and improve the efficiency and performance of writing the network packet into the memory. In order to reduce fragmented operations in the process of writing the network packet into the memory, and improve the efficiency and performance of writing the network packet, the allocation strategy can include at least one of the following:

[0064] (i) According to the data capacity of the memory buffer, the network packet is split into multiple packet segments, so that the data amount of the packet segment is less than or equal to the data capacity of the corresponding memory buffer, and the data amount of the packet segment is an integer multiple of the upper limit of the single writing data amount when writing data into the memory buffer;

[0065] (ii) According to the start address of the memory buffer, the network packet is split into multiple packet segments, so that the data amount of the packet segment is less than or equal to the data capacity of the corresponding memory buffer, and the end address of the packet segment in the corresponding memory buffer is the boundary address of the cache line;

[0066] (iii) According to the occupation state of the internal bus of the acceleration unit, the network packet is split into multiple packet segments, so that the data amount of the packet segment is less than or equal to the data capacity of the corresponding memory buffer, and the data amount of the packet segment is an integer multiple of the available bandwidth of the internal bus of the acceleration unit.

[0067] For the above (i), when the packet writing subunit 232 writes data into the memory buffer, there is an upper limit of the writing data amount for the single writing operation, and when the data amount of the data to be written is sufficient, the packet writing subunit 232 will write data into the memory buffer multiple times according to the upper limit of the writing data amount. The upper limit of the writing data amount for the single writing operation of the packet writing subunit 232 is usually an integer power of 2, such as 256 bytes, 512 bytes, etc. If the data capacity of the memory buffer is not equal to an integer multiple of the upper limit of the writing data amount for the single writing operation of the packet writing subunit 232, when the network packet is written into the memory buffer until the memory buffer is full, the data amount of the data written in the last writing operation is less than the upper limit of the writing data amount, which produces fragmented operations, resulting in low efficiency of writing the network packet into the memory buffer.

[0068] Figure 4 is a schematic diagram of the network packet writing process in the related art. The host allocates a memory buffer, and stores the address and length of the memory buffer into a submission queue (SQ), as shown in Figure 4As shown, the submission queue records the addresses and lengths of memory buffers 0 to 5. From the submission queue, it can be seen that when writing network packets to memory buffers, the write operations are performed on memory buffers in the order from memory buffer 0 to memory buffer 5. The address of memory buffer 0 is Desc0 and its length (len) is 1024 bytes, the address of memory buffer 1 is Desc1 and its length (len) is 1025 bytes, the address of memory buffer 2 is Desc2 and its length (len) is 1026 bytes, the address of memory buffer 3 is Desc3 and its length (len) is 666 bytes, the address of memory buffer 4 is Desc4 and its length (len) is 1023 bytes, and the address of memory buffer 5 is Desc5 and its length (len) is 4096 bytes.

[0069] like Figure 4 As shown, when writing an 8KB (8192 bytes) network packet to the memory buffer, the network packet is written to the memory buffer in the order from memory buffer 0 to memory buffer 5. 1024 bytes of the network packet are written to memory buffer 0, 1025 bytes are written to memory buffer 1, 1026 bytes are written to memory buffer 2, 666 bytes are written to memory buffer 3, 1023 bytes are written to memory buffer 4, and 3428 bytes are written to memory buffer 5. Memory buffers 0 to 4 are all filled.

[0070] If the maximum amount of data that can be written to the memory buffer in a single write operation is 256 bytes, since the data capacity of memory buffer 0 is an integer multiple of the maximum write capacity, memory buffer 0 can be filled in 4 write operations, and there are no fragmented operations during the write operation of memory buffer 0. The data capacities of memory buffers 1, 2, 3, and 4 are not integer multiples of the maximum write capacity. For memory buffer 1, the first 4 write operations each write 256 bytes of data, and the 5th write operation writes 1 byte of data; the 5th write operation is a fragmented operation. For memory buffer 2, the first 4 write operations each write 256 bytes of data, and the 5th write operation writes 2 bytes of data; the 5th write operation is a fragmented operation. For memory buffer 3, the first 2 write operations each write 256 bytes of data, and the 3rd write operation writes 154 bytes of data; the 3rd write operation is a fragmented operation. For memory buffer 4, the first 3 write operations each write 256 bytes of data, and the 4th write operation writes 255 bytes of data; the 4th write operation is a fragmented operation. The data capacity of memory buffer 5 is an integer multiple of the upper limit of the amount of data to be written, but memory buffer 5 is not filled. The first 13 write operations on memory buffer 5 each write 256 bytes of data, and the 14th write operation writes 100 bytes of data. The 14th write operation is a fragmented operation.

[0071] From the above analysis, after writing a memory buffer to the full, and then write the subsequent memory buffer, when writing memory buffer 1 to memory buffer 5, there will be fragmented operations, and 35 write operations are needed to write a network packet including 8192 bytes into a memory buffer, which results in a low efficiency of writing network packets into a memory.

[0072] Figure 5 is a schematic diagram of a network packet writing process according to an embodiment of the present application. The host-allocated memory buffer and the memory buffer writing subunit 232 are consistent with the embodiments shown in Figure 4 and will not be described here again.

[0073] As shown in Figure 5 , when a network packet including 8KB (8192 bytes) is written into a memory buffer, and the upper limit of the data amount written into the memory buffer in a single write operation is 256 bytes, the packet writing subunit 232 splits the network packet into 6 packet fragments, packet fragment 0 includes 1024 bytes, packet fragment 1 includes 1024 bytes, packet fragment 2 includes 1024 bytes, packet fragment 3 includes 512 bytes, packet fragment 4 includes 512 bytes, and packet fragment 5 includes 4096 bytes. The packet writing subunit 232 writes packet fragment 0 into memory buffer 0, writes packet fragment 1 into memory buffer 1, writes packet fragment 2 into memory buffer 2, writes packet fragment 3 into memory buffer 3, writes packet fragment 4 into memory buffer 4, and writes packet fragment 5 into memory buffer 5.

[0074] Packet fragment 0 is written into memory buffer 0 through 4 write operations, each write operation writes 256 bytes of data, and the process of writing memory buffer 0 does not have fragmented operations. Packet fragment 1 is written into memory buffer 1 through 4 write operations, each write operation writes 256 bytes of data, and the process of writing memory buffer 1 does not have fragmented operations. Packet fragment 2 is written into memory buffer 2 through 4 write operations, each write operation writes 256 bytes of data, and the process of writing memory buffer 2 does not have fragmented operations. Packet fragment 3 is written into memory buffer 3 through 2 write operations, each write operation writes 256 bytes of data, and the process of writing memory buffer 3 does not have fragmented operations. Packet fragment 4 is written into memory buffer 4 through 2 write operations, each write operation writes 256 bytes of data, and the process of writing memory buffer 4 does not have fragmented operations. Packet fragment 5 is written into memory buffer 5 through 16 write operations, each write operation writes 256 bytes of data, and the process of writing memory buffer 5 does not have fragmented operations.

[0075] It should be noted that, Figure 5The shown message segment 4 includes 512 bytes, and the length of the memory buffer 4 of the user cache message segment 4 is 1023 bytes. In another embodiment, when the network message is segmented, the message segment corresponding to the memory buffer 4 can include 768 bytes, the message segment corresponding to the memory buffer 5 can include 3840 bytes, the message segment corresponding to the memory buffer 4 can be written into the memory buffer 4 by 3 write operations, each write operation writes 256 bytes of data, the message segment corresponding to the memory buffer 5 can be written into the memory buffer 5 by 15 write operations, each write operation writes 256 bytes of data, and there is no fragmented operation in the process of writing into the memory buffer 4 and the memory buffer 5.

[0076] From the above analysis, it can be known that the network message including 8192 bytes is segmented into 6 message segments, the data amount of each message segment is equal to the upper limit of the write data amount of the single write memory buffer, the 6 message segments are written into the corresponding 6 memory buffers, and there is no fragmented operation. The network message including 8192 bytes is written into the memory buffer, and 32 write operations are required. Compared with the network message writing scheme shown in Figure 4 The writing method shown saves 4 write operations, and thus the efficiency of writing the network message into the memory can be improved.

[0077] It should be noted that the network message writing process shown in Figure 5 The data amount of the network message can not be equal to an integer multiple of the upper limit of the write data amount, which will cause the write data amount of a write operation not to be equal to the upper limit of the write data amount. Compared with the network message writing scheme shown in Figure 4 The number of fragmented operations can still be reduced, and thus the efficiency of writing the network message into the memory can be improved.

[0078] For the above (ii), the message receiving end on the host reads the network message cached in the memory buffer in the cache line unit when reading the network message from the memory buffer. However, the start address of the memory buffer allocated by the network card driver can not be the boundary address of the cache line. Therefore, when the memory buffer is full, the network message written into the memory buffer can cross the cache line, and the efficiency of reading the network message crossing the cache line by the message receiving end is low. Therefore, the network message can be segmented into multiple message segments, so that the end address of the message segment in the corresponding memory buffer is the boundary address of the cache line, the network message crossing the cache line is reduced, and thus the efficiency of reading the network message from the memory buffer by the message receiving end can be improved.

[0079] Figure 6 is a schematic diagram of the memory buffer of an embodiment of the present application. As Figure 6As shown, the packet receiving end reads the network packet from the memory buffer in the unit of cache line with a length of 64 bytes, that is, the address 64 is the demarcation address of the cache line. The length of the memory buffer is 64 bytes, the start address of the memory buffer is the address 10, and the end address of the memory buffer is the address 74.

[0080] If the memory buffer is filled when the network packet is written, the network packet cached in the memory buffer has 54 bytes of data before the demarcation address (address 64) of the cache line and 10 bytes of data before and after the demarcation address (address 64) of the cache line. When the packet receiving end reads the network packet from the memory buffer, two read operations need to be performed to read the network packet cached in the memory buffer, resulting in low efficiency of the packet receiving end in reading the network packet from the memory buffer.

[0081] The packet writing subunit 232 splits a network packet segment with a length of 54 bytes from the network packet for the memory buffer with the start address of the address 10 and the end address of the address 74, and writes the network packet segment with the length of 54 bytes into the memory buffer, so that there is no network packet across the cache line in the memory buffer. Compared with the network packet writing scheme that fills the memory buffer, the 10 bytes of data not written into the memory buffer will be written into another memory buffer together with other data included in the network packet, so that the number of times of network packet across the cache line in the memory buffer can be reduced, and the efficiency of the packet receiving end in reading the network packet from the memory buffer can be improved.

[0082] For the above (iii), the packet writing subunit 232 needs to cooperate with related modules in the acceleration unit 230 when writing the network packet into the memory buffer. The modules in the acceleration unit 230 interact through the bus inside the acceleration unit 230, such as that the receiving subunit 231 sends the network packet to the packet writing subunit 232 through the bus inside the acceleration unit 230, the packet writing subunit 232 transmits the network packet to the host bus through the bus inside the acceleration unit 230, and then writes the network packet into the memory buffer on the host. The bus inside the acceleration unit 230 can also transmit other data while transmitting the network packet. If the transmission of other data by the bus inside the acceleration unit 230 occupies a part of the bandwidth, only the remaining part of the bandwidth can be used to transmit the network packet. If the network packet is divided into multiple packet segments, so that the data amount of the packet segment is an integer multiple of the available bandwidth of the bus inside the acceleration unit 230, the bus inside the acceleration unit 230 can be fully utilized to transmit data in each clock cycle when the packet segment is written into the memory buffer, and the situation that the bus inside the acceleration unit 230 is not fully occupied in one or more clock cycles will not occur.

[0083] For example, if the bandwidth of the internal bus of the acceleration unit 230 is 32, the internal bus of the acceleration unit 230 can transmit 32 bits of data in each clock cycle. The internal bus of the acceleration unit 230 transmits network packets and other data at the same time. If the transmission of the other data occupies 8 bits of bandwidth, the internal bus of the acceleration unit 230 can transmit 24 bits of network packet data in each clock cycle, i.e., the available bandwidth of the internal bus of the acceleration unit 230 is 24 bits, and the internal bus of the acceleration unit 230 can transmit network packet data with a length of 3 bytes in each clock cycle. The length of a memory buffer is 1025 bytes. If the memory buffer is filled, 342 clock cycles are needed. In the first 341 clock cycles, 3 bytes of data are written in each clock cycle, and in the 342th clock cycle, 1 byte of data is written. In the 342th clock cycle, 16 bits of bandwidth are wasted. If the memory buffer is divided into 1024-byte-length packet segments, the packet segments can be written into the memory buffer through 341 clock cycles, and the bandwidth of the internal bus of the acceleration unit 230 is fully used in each clock cycle, and there is no waste of the bandwidth of the internal bus of the acceleration unit 230.

[0084] The occupation state of the internal bus of the acceleration unit 230 includes the available bandwidth of the interface between the internal bus of the acceleration unit 230 and the host bus. When the packet writing subunit 232 writes network packets into a memory buffer, the network packets need to be transmitted to the host bus through the interface between the internal bus of the acceleration unit 230 and the host bus, and then the network packets are written into the memory buffer through the host bus. The interface between the internal bus of the acceleration unit 230 and the host bus is used not only for transmitting network packets but also for transmitting other data. If the transmission of the other data occupies a part of the bandwidth of the interface between the internal bus of the acceleration unit 230 and the host bus, the network packets can only be transmitted through the remaining part of the bandwidth of the interface. If the network packets are divided into packet segments such that the data amount of the packet segments is an integer multiple of the available bandwidth of the interface between the internal bus of the acceleration unit 230 and the host bus, the bandwidth of the interface between the internal bus of the acceleration unit 230 and the host bus can be fully used in each clock cycle when the packet segments are written into the memory buffer, and there is no case that the bandwidth of the interface between the internal bus of the acceleration unit 230 and the host bus is not fully occupied in one or more clock cycles.

[0085] The packet writing subunit 232 can divide network packets into packet segments according to the occupation state of the internal bus of the acceleration unit 230, so that the data amount of the packet segments is an integer multiple of the available bandwidth of the internal bus of the acceleration unit 230. Thus, when the packet segments are written into corresponding memory buffers, the bandwidth of the internal bus of the acceleration unit 230 can be fully used, the number of times of waste of the bandwidth of the internal bus of the acceleration unit 230 in the process of writing network packets into memory buffers can be reduced, and thus the efficiency of writing network packets into memory buffers can be improved.

[0086] In the embodiments of the present application, the packet writing subunit 232 can split the network packet into packet segments according to the (i) point, the (ii) point or the (iii) point, or can split the network packet into packet segments in combination with any two or all of the (i) point, the (ii) point and the (iii) point, so as to improve the efficiency of writing the network packet into the memory and be suitable for different application scenarios.

[0087] In a possible implementation, if the receiving subunit 231 receives multiple network packets, the packet writing subunit 232 can split the multiple network packets into multiple packet groups according to the allocation strategy, and write the multiple packet groups into different memory buffers respectively. Among them, the data amount of at least part of the packet groups is less than the data capacity of the memory buffer for caching the packet group, and the packet group includes data of at least one network packet.

[0088] The receiving subunit 231 can receive network packets from multiple communication objects, which can be clients other than the host or packet receiving ends on the host. The receiving subunit 231 can simultaneously receive multiple network packets from multiple communication objects, and then the packet writing subunit 232 needs to write the multiple network packets into the memory buffer, so that the corresponding one or more packet receiving ends can read the network packets from the memory buffer.

[0089] If the multiple network packets are written into the memory buffer respectively, part of the memory buffer will have a large storage space wasted, and when the network packets are transmitted through the internal bus of the acceleration unit 230, multiple network packets can cause bandwidth waste. For example, the network packet 1 is written into the memory buffer 0 to the memory buffer 5, the length of the memory buffer 5 is 4096 bytes, but the network packet 1 only occupies 1025 bytes of the memory buffer 5, and 3071 bytes of the memory buffer 5 are wasted. For another example, the available bandwidth of the internal bus of the acceleration unit 230 is 32 bits, and 342 clock cycles are needed to write 1025 bytes of data included in the network packet 1 into the memory buffer 5, 3 bytes of data are written every clock cycle for the first 341 clock cycles, 1 byte of data is written in the 342th clock cycle, and 16 bits of bandwidth are wasted in the 342th clock cycle. The network packet 2 is written into the memory buffer 6 and the memory buffer 7, the length of the memory buffer 7 is 1024 bytes, and the network packet 2 occupies 1022 bytes of the memory buffer 7. 341 clock cycles are needed to write 1022 bytes of data included in the network packet 2 into the memory buffer 7, 3 bytes of data are written every clock cycle for the first 341 clock cycles, 2 bytes of data are written in the 341th clock cycle, and 8 bits of bandwidth are wasted in the 341th clock cycle.

[0090] If network message 1 and network message 2 are divided into multiple message groups as a whole, each message group can include data of one or more network messages, so that data of multiple network messages can be written into the same memory buffer, for example, 1022 bytes of data included in network message 2 and 1023 bytes of data included in network message 1 can be written into memory buffer 5, without occupying memory buffer 7 to cache network message 2, so as to fully utilize the storage space of the memory buffer and save the host memory occupied by the cached network messages, thereby improving the performance of the host. In addition, by dividing network message 1 and network message 2 into multiple message groups as a whole, 1 byte of data of network message 1 and 2 bytes of data of network message 2 can be written in the same clock cycle, fully utilizing the bandwidth of the internal bus of the acceleration unit 230.

[0091] It should be noted that when the message writing sub-unit 232 divides multiple network messages into multiple message groups, the multiple network messages can be regarded as a whole, and then the multiple network messages regarded as a whole can be divided into multiple message groups according to the distribution strategy in the above embodiment. For specific division rules, refer to the description of dividing a single network message in the foregoing embodiment, which will not be repeated here.

[0092] In the embodiment of the present application, when the receiving sub-unit 231 receives multiple network messages, the message writing sub-unit 232 can regard the multiple network messages as a whole, and divide the multiple network messages into multiple message groups according to the distribution strategy, so that the data amount of at least part of the message groups is less than the data capacity of the corresponding memory buffer, thereby reducing the waste of the storage space of the memory buffer and reducing the waste of the bandwidth of the internal bus of the acceleration unit 230 in the process of writing the network messages into the memory buffer, thereby improving the efficiency of writing the network messages into the memory buffer.

[0093] In a possible implementation, when the message writing sub-unit 232 divides multiple network messages into multiple message groups according to the distribution strategy, at least part of the message groups include data of at least two network messages.

[0094] In the embodiment of the present application, the message writing sub-unit 232 divides multiple network messages as a whole to obtain multiple message groups, some of which include data of one network message and some of which include data of two or more network messages, that is, data of multiple network messages is written into the same memory buffer, which can fully utilize the storage space of the memory buffer, reduce the host memory occupied by the cached network messages, and thereby improve the performance of the host.

[0095] In a possible implementation, when the packet group includes data of multiple network packets, the queue writing subunit 233 writes, on the basis of writing the address and the occupied length of the memory buffer corresponding to the packet group into the completion queue, the demarcation address information of the packet group, which can indicate the demarcation address of the multiple network packets included in the packet group in the memory buffer, and then writes the obtained demarcation address information into the completion queue.

[0096] In an example, the packet group includes 1024 bytes of data, the first 512 bytes of data are data of a network packet 1, and the last 512 bytes of data are data of a network packet 2. After the packet group is written into a memory buffer with a length of 1025 bytes, the address corresponding to the 513th byte in the memory buffer is the demarcation address, and the queue writing subunit 233 can obtain the demarcation address information indicating the demarcation address. The occupied length of the memory buffer is 1024 bytes, and the demarcation address is the address corresponding to the 513th byte, so that it can be determined that the memory buffer stores 1024 bytes of network packet data, and the first 512 bytes of data are data of one network packet and the last 512 bytes of data are data of another network packet.

[0097] In the embodiments of the present application, since the packet writing subunit 232 can write data of multiple network packets into the same memory buffer, in order to enable the packet receiving end to read the data of the required network packet from the memory buffer, the queue writing subunit 233 writes the demarcation address information into the completion queue, so that the packet receiving end can obtain the address of the memory buffer, the occupied length, and the demarcation address information from the completion queue, find the corresponding memory buffer according to the address of the memory buffer, find the data of the required network packet according to the occupied length and the demarcation address information, and ensure that the packet receiving end can accurately read the data of the required network packet from the memory buffer.

[0098] System on chip

[0099] The embodiments of the present application further provide an on-chip system, which includes the acceleration unit 230 in any of the above embodiments.

[0100] It should be noted that the application of the acceleration unit 230 in the embodiments of the present application is not limited to the on-chip system, and can also be applied in other various suitable ways, such as deploying the acceleration unit 230 and the interactive components such as the central processing unit (CPU) and the main memory on a printed circuit board, and enabling the acceleration unit 230 to interact with the central processing unit (CPU) and the main memory through the bus on the printed circuit board.

[0101] Packet transmission method

[0102] The acceleration unit 230 in the foregoing embodiment can be applied to a network virtualization scenario to implement transmission of a network packet to a packet receiving end. The acceleration unit 230 writes a received network packet into a memory buffer allocated by a host. The working process of the acceleration unit 230 in the network virtualization scenario is described below through a packet transmission method embodiment.

[0103] Figure 7 FIG. 7 is a flowchart of a packet transmission method according to an embodiment of the present application. As shown in FIG. 7, the packet transmission method comprises the following steps. Figure 7

[0104] Step 701: receiving a network packet through a network;

[0105] Step 702: writing the network packet into a plurality of memory buffers allocated by a host according to an allocation policy, wherein a data amount of data written into at least part of the memory buffers is less than a data capacity of the memory buffers;

[0106] Step 703: writing an address and an occupied length of the memory buffers into a completion queue, so that a packet receiving end on the host reads the network packet from the plurality of memory buffers according to the completion queue.

[0107] In the embodiment of the present application, after receiving the network packet, the network packet can be written into the plurality of memory buffers according to the allocation policy, so that the data amount of data written into at least part of the memory buffers is less than the data capacity of the memory buffers. Then, the address and the occupied length of the memory buffers can be written into the completion queue, and the packet receiving end on the host can read the network packet from the memory buffers according to the address and the occupied length in the completion queue. Since the network packet can be written into the plurality of memory buffers according to the allocation policy, the memory buffers can not be filled, so that the number of times of occurrence of fragmented operations in the process of writing the packet data into the memory can be reduced, and the efficiency of writing the network packet into the memory can be improved.

[0108] It should be noted that the packet transmission method in the embodiment of the present application is a specific application of the acceleration unit 230 in the foregoing embodiment in the network virtualization scenario. The specific packet transmission method can be referred to the description in the foregoing acceleration unit embodiment, and will not be described here again.

[0109] Commercial value of the embodiments of the present application

[0110] ​In the embodiment of the present application, the acceleration unit splits the network message into multiple message segments according to the allocation strategy, and writes the multiple message segments into different memory buffers, so that the data amount of at least part of the message segments is less than the data capacity of the memory buffer storing the message segments, which can reduce the fragmented operations in the process of writing the network message into the memory buffer, and improve the efficiency of writing the network message into the memory buffer. By configuring the allocation strategy, the occupation of the host memory by the cached network message can be reduced, and the performance of the host can be improved. The present scheme can be applied to network virtualization scenarios, such as data centers, and has good market prospects.

[0111] It should be noted that the information related to the user (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with the relevant laws, regulations and standards of the country and region, and provide corresponding operation portal for the user to choose authorization or refusal.

[0112] It should be understood that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the difference from other embodiments. Especially for the method embodiment, since it is basically similar to the method described in the device and system embodiment, the description is relatively simple, and the relevant parts can refer to the description of other embodiments.

[0113] It should be understood that the above describes specific embodiments of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0114] It should be understood that the elements described herein in singular form or only one shown in the drawings do not represent the number of the elements limited to one. In addition, the modules or elements described or shown herein as separate can be combined into a single module or element, and the modules or elements described or shown herein as single can be split into multiple modules or elements.

[0115] It is also to be understood that the terminology and phraseology employed herein is for the purpose of description and the specification one or more embodiments of the present application should not be limited to the terms used. The use of such terms and expressions should not be construed to impart a limitation on the description (or portions thereof) contained herein. It is recognized that various modifications are possible in light of the disclosure, and these are to be included within the intended scope of the claims. Other modifications, changes, and substitutions are also possible. Accordingly, the claims should be viewed in the only favorable light, as possibly encompassing all such equivalents.

Claims

1. An acceleration unit, comprising: The receiving subunit is used to receive network packets over the network. The message writing subunit is used to divide the network message into multiple message fragments according to the allocation strategy, and write the multiple message fragments into multiple different memory buffers allocated by the host, wherein at least some of the memory buffers have a data volume of less than the data capacity of the memory buffer. The queue writing subunit is used to write the address and occupied length of the memory buffer into the completion queue, so that the message receiving end on the host can read the network message from the plurality of memory buffers according to the completion queue.

2. The acceleration unit according to claim 1, wherein, The allocation strategy includes at least one of the following: Based on the data capacity of the memory buffer, the network packet is divided into multiple packet segments, such that the data size of the packet segment is less than or equal to the data capacity of the corresponding memory buffer, and the data size of the packet segment is equal to an integer multiple of the maximum amount of data written at one time when writing data to the memory buffer; Based on the starting address of the memory buffer, the network packet is divided into multiple packet fragments, such that the data volume of the packet fragment is less than or equal to the data capacity of the corresponding memory buffer, and the ending address of the packet fragment in the corresponding memory buffer is the boundary address of the cache line. Based on the occupancy status of the bus within the acceleration unit, network packets are divided into multiple packet segments, such that the data size of each packet segment is less than or equal to the data capacity of the corresponding memory buffer, and the data size of each packet segment is equal to an integer multiple of the available bandwidth of the bus.

3. The acceleration unit according to any one of claims 1-2, wherein, The message writing subunit is used to, when the receiving subunit receives multiple network messages, divide the multiple network messages into multiple message groups according to the allocation strategy, and write the multiple message groups into different memory buffers respectively. At least some of the message groups have a data volume smaller than the data capacity of the corresponding memory buffer. The message group includes the data of at least one network message.

4. The acceleration unit according to claim 3, wherein, At least a portion of the message group includes data from at least two network messages.

5. The acceleration unit according to claim 4, wherein, The queue writing subunit is used to obtain the boundary address information of the packet group when the packet group includes data of multiple network packets, and write the boundary address information into the completion queue. The boundary address information is used to indicate the boundary address of the multiple network packets included in the packet group in the memory buffer.

6. A computing device, comprising: A processing unit for constructing a host, the host being used to allocate multiple memory buffers; The acceleration unit according to any one of claims 1-5.

7. A system-on-a-chip, comprising: The acceleration unit according to any one of claims 1-5.

8. A data center, comprising: The computing device according to claim 6.

9. A message transmission method, comprising: Receive network messages over the network; According to the allocation strategy, the network packet is divided into multiple packet fragments, and the multiple packet fragments are written into multiple different memory buffers allocated by the host, wherein at least some of the data written into the memory buffers is less than the data capacity of the memory buffers; The address and length of the memory buffer are written into the completion queue so that the message receiver on the host can read the network message from the plurality of memory buffers according to the completion queue.

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