Tri-state content addressable memory and method of operation

Abstract

The application relates to a ternary content addressable memory, comprising a first nonvolatile reconfigurable transistor, a second nonvolatile reconfigurable transistor, a match line, a first write line, a second write line, a first search line and a second search line, wherein the match line is connected with the source of the first nonvolatile reconfigurable transistor and the drain of the second nonvolatile reconfigurable transistor; the first write line is connected with the drain of the first nonvolatile reconfigurable transistor; the second write line is connected with the source of the second nonvolatile reconfigurable transistor and the first write line; the first search line is connected with the gate of the first nonvolatile reconfigurable transistor; and the second search line is connected with the gate of the second nonvolatile reconfigurable transistor; the writing operation is realized by controlling the voltage of the first write line and the voltage of the second write line; and the addressing operation is realized by controlling the voltage of the first search line and the voltage of the second search line; the ternary content addressable memory has the advantages of small device quantity, low energy consumption and the like.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a three-state content-addressable memory and its operation method. Background Technology

[0002] Ternary Content Addressable Memory (TCAM) is a storage technology that differs from traditional address memory. It does not require searching for stored content using address pointers; instead, it directly searches based on whether the stored content matches. Furthermore, in addition to the data 0 and 1, it has a third state, hence the name "ternary content addressable memory." TCAM offers the advantage of fast lookup and is currently widely used in network communication and routing technologies.

[0003] However, traditional TCAM is based on static random access memory, and often a single cell requires more than a dozen complementary semiconductor transistors to build. In recent years, with the rapid development of artificial intelligence and big data, the amount of data available for searching has exploded. Traditional TCAM implementation methods will pose huge challenges to power consumption and circuit area. If transistor devices can be upgraded and replaced with lower power and more powerful transistors, the energy consumption of TCAM will be greatly reduced, the storage density of TCAM will be increased, and the cost will be reduced. Summary of the Invention

[0004] Therefore, it is necessary to provide a three-state content-addressable memory and its operation method to address the above-mentioned technical problems, thereby solving the problems of high power consumption and high cost of traditional three-state content-addressable memory.

[0005] This application provides a three-state content-addressable memory, characterized in that it includes a first non-volatile reconfigurable transistor, a second non-volatile reconfigurable transistor, a matching line, a first write line, a second write line, a first lookup line, and a second lookup line, wherein the matching line is connected to both the source of the first non-volatile reconfigurable transistor and the drain of the second non-volatile reconfigurable transistor; the first write line is connected to the drain of the first non-volatile reconfigurable transistor and is used to apply a preset voltage to the drain of the first non-volatile reconfigurable transistor to reconfigure its polarity; the second write line is connected to both the source of the second non-volatile reconfigurable transistor and the first write line and is used to apply the preset voltage to the drain of the second non-volatile reconfigurable transistor to reconfigure its polarity; The second non-volatile reconfigurable transistor polarity is reconfigured; wherein, by changing the polarity of the first non-volatile reconfigurable transistor and the second non-volatile reconfigurable transistor, preset data is written to the tri-state content-addressable memory; a first lookup line, connected to the gate of the first non-volatile reconfigurable transistor, is used to apply a first turn-on trigger voltage to the gate of the first non-volatile reconfigurable transistor to turn it on; a second lookup line, connected to the gate of the second non-volatile reconfigurable transistor, is used to apply a second turn-on trigger voltage to the gate of the second non-volatile reconfigurable transistor to turn it on; wherein, by applying a preset level to the first lookup line and the second lookup line, the preset data is addressed.

[0006] In the tri-state content-addressable memory described in the above embodiments, each memory cell is constructed using two non-volatile reconfigurable transistors as basic components. Each non-volatile reconfigurable transistor is an N-type transistor with an initial polarity and includes a tellurium source electrode and a tellurium drain electrode. By controlling the voltage between the source and drain, the polarity of the transistor can be easily changed. Therefore, in the tri-state content-addressable memory of this embodiment, by configuring the voltage between the first write line and the matching line and the voltage between the second write line and the matching line, the first non-volatile reconfigurable transistor and the second non-volatile reconfigurable transistor can be... Volatile reconfigurable transistors exhibit different polarity combinations, enabling the tri-state content-addressable memory to possess tri-state storage states. On the other hand, by applying a preset level to the first lookup line and the second lookup line, the first non-volatile reconfigurable transistor and the second non-volatile reconfigurable transistor are controlled to conduct. Based on the different conduction states of the two transistors, the corresponding storage state of the tri-state content-addressable memory can be obtained. The above-mentioned memory greatly reduces the number of transistors used, and both write and address operations only need to be implemented by controlling two non-volatile reconfigurable transistors, which greatly reduces energy consumption and manufacturing and usage costs.

[0007] In one embodiment, the preset voltage includes a preset negative voltage and a preset positive voltage; the preset negative voltage is applied between the source and drain of the first non-volatile reconfigurable transistor, and the gate of the first non-volatile reconfigurable transistor is grounded, and this is continued for a preset time to change the polarity of the first non-volatile reconfigurable transistor from N-type to P-type; the preset positive voltage is applied between the source and drain of the first non-volatile reconfigurable transistor, and the gate of the first non-volatile reconfigurable transistor is grounded, and this is continued for the preset time to change the polarity of the first non-volatile reconfigurable transistor from P-type to N-type; or

[0008] A preset negative voltage is applied between the source and drain of the second non-volatile reconfigurable transistor, and the gate of the second non-volatile reconfigurable transistor is grounded, and this is continued for the preset time, so that the polarity of the second non-volatile reconfigurable transistor changes from N-type to P-type; a preset positive voltage is applied between the source and drain of the second non-volatile reconfigurable transistor, and the gate of the second non-volatile reconfigurable transistor is grounded, and this is continued for the preset time, so that the polarity of the second non-volatile reconfigurable transistor changes from P-type to N-type;

[0009] Wherein, the electric field strength formed by the preset voltage between the source and drain of the first non-volatile reconfigurable transistor is greater than the minimum electric field strength required to cause tellurium atoms to migrate between the source and drain of the first non-volatile reconfigurable transistor, and the electric field strength formed by the preset voltage between the source and drain of the second non-volatile reconfigurable transistor is greater than the minimum electric field strength required to cause tellurium atoms to migrate between the source and drain of the second non-volatile reconfigurable transistor.

[0010] In one embodiment, the preset level includes a preset positive level and a preset negative level; if the polarity of the first non-volatile reconfigurable transistor is N-type, the first turn-on trigger voltage is controlled to be the preset positive level to turn on the first non-volatile reconfigurable transistor; if the polarity of the first non-volatile reconfigurable transistor is P-type, the first turn-on trigger voltage is controlled to be the preset negative level to turn on the first non-volatile reconfigurable transistor; or

[0011] If the polarity of the second non-volatile reconfigurable transistor is N-type, the second turn-on trigger voltage is controlled to the preset positive level to turn on the second non-volatile reconfigurable transistor; if the polarity of the second non-volatile reconfigurable transistor is P-type, the second turn-on trigger voltage is controlled to the preset negative level to turn on the second non-volatile reconfigurable transistor.

[0012] Wherein, the absolute values ​​of the preset positive level and the preset negative level are equal.

[0013] In one embodiment, if the polarity of the first non-volatile reconfigurable transistor is P-type and the polarity of the second non-volatile reconfigurable transistor is N-type, the tri-state content addressing memory stores 0.

[0014] In one embodiment, if the polarity of the first non-volatile reconfigurable transistor is N-type and the polarity of the second non-volatile reconfigurable transistor is P-type, the tri-state content addressing memory stores 1.

[0015] In one embodiment, if the polarity of both the first non-volatile reconfigurable transistor and the second non-volatile reconfigurable transistor is N-type, the tri-state content addressing memory stores preset address data.

[0016] In one embodiment, when the voltage of the matching line is a first high level...

[0017] Set the voltage of the first search line to the preset negative level and the voltage of the second search line to the preset positive level. If the voltage of the matching line changes to the second high level, it is determined that the address has been reached to 0.

[0018] Set the voltage of the first search line to the preset positive level and the voltage of the second search line to the preset negative level. If the voltage of the matching line changes to the second high level, it is determined that 1 has been addressed.

[0019] If the voltage of the first search line is set to the preset negative level and the voltage of the second search line is set to the preset positive level, or the voltage of the first search line is set to the preset positive level and the voltage of the second search line is set to the preset negative level, and the voltage of the matching line becomes the second high level, it is determined that the preset address data has been addressed.

[0020] Wherein, the first high level is greater than the second high level.

[0021] A second aspect of this application provides a method for operating a three-state content-addressable memory, implemented based on the three-state content-addressable memory described in any of the preceding claims, the method comprising:

[0022] The voltage between the source and drain of the non-volatile reconfigurable transistor is controlled to a preset voltage to change the polarity of the non-volatile reconfigurable transistor, so as to write preset data to the tri-state content addressing memory; the non-volatile reconfigurable transistor includes a first non-volatile reconfigurable transistor and a second non-volatile reconfigurable transistor.

[0023] The gate level of the non-volatile reconfigurable transistor is controlled to a preset level in order to address the preset data.

[0024] In one embodiment, the preset data includes 0, 1, and preset address data; the preset voltage includes a preset positive voltage and a preset negative voltage; and the method for writing the preset data includes:

[0025] The control matching line, the first search line, and the second search line are all grounded;

[0026] The voltage of the first write line is controlled to the preset positive voltage, and the voltage of the second write line is controlled to the preset positive voltage, so as to write 0 into the tri-state content addressing memory;

[0027] The voltage of the first write line is controlled to the preset negative voltage, and the voltage of the second write line is controlled to the preset negative voltage, so as to write 1 into the tri-state content addressing memory;

[0028] The voltage of the first write line is controlled to be the preset negative voltage, and the voltage of the second write line is controlled to be the preset positive voltage, so as to write the preset address data into the tri-state content addressing memory.

[0029] In one embodiment, the preset level further includes a preset positive level and a preset negative level, wherein the absolute values ​​of the preset positive level and the preset negative level are equal, and the method for addressing the preset data includes:

[0030] The voltage of the matching line is controlled to a first high level;

[0031] The voltage of the first search line is controlled to the preset negative level and the voltage of the second search line is controlled to the preset positive level. If the voltage of the matching line becomes the second high level, it is determined that the address has been reached to 0.

[0032] The voltage of the first search line is controlled to the preset positive level and the voltage of the second search line is controlled to the preset negative level. If the voltage of the matching line changes to the second high level, it is determined that 1 has been addressed.

[0033] If the voltage of the first search line is controlled to the preset negative level and the voltage of the second search line is controlled to the preset positive level, or the voltage of the first search line is controlled to the preset positive level and the voltage of the second search line is controlled to the preset negative level, and the voltage of the matching line becomes the second high level, it is determined that the preset address data has been addressed.

[0034] Wherein, the first high level is greater than the second high level. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of the structure of a tri-state content-addressable memory in one embodiment provided in this application;

[0037] Figure 2 A structural diagram of a non-volatile reconfigurable transistor is provided in one embodiment of this application;

[0038] Figure 3 A schematic diagram of the addressing principle of a tri-state content-addressable memory in one embodiment provided in this application;

[0039] Figure 4 A flowchart illustrating the operation of a tri-state content-addressable memory in one embodiment provided in this application;

[0040] Figure 5 A flowchart of a write operation of a tri-state content-addressable memory in one embodiment provided in this application;

[0041] Figure 6 A flowchart of the addressing operation of a tri-state content-addressable memory in one embodiment provided in this application;

[0042] Explanation of reference numerals in the attached figures: 1-Gate electrode; 2-Insulating layer; 3-Channel layer; 4-Drain electrode containing tellurium; 5-Source electrode containing tellurium. Detailed Implementation

[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0045] It should be understood that when an element or layer is referred to as "on" or "connected to" other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" or "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0049] The evolution of data networks has also witnessed the rapid expansion of mobile phone storage. From the earliest flip phones to today's smartphones, and from 3G to 5G, this is not only a major advancement in data transmission but also requires more storage capacity for computation. Compared to traditional RAM, ternary content addressable memory (TCAM) is a storage device that supports network devices. It is mainly used to shorten data search time, improve router search speed, classify data, and control access permissions, resulting in faster data processing.

[0050] However, traditional TCAM is based on static random access memory, which often requires more than a dozen complementary semiconductor transistors to build a single cell. This results in high energy consumption and high manufacturing and usage costs. If transistor devices can be upgraded to use transistors with lower power consumption and more powerful functions, the energy consumption and cost of TCAM can be greatly reduced, and the storage density of TCAM can be increased.

[0051] To address the above problems, this application provides a three-state content-addressable memory and its operation method, which will be described below through specific embodiments.

[0052] In one embodiment of this application, such as Figure 1As shown, a tri-state content-addressable memory is provided, including a first non-volatile reconfigurable transistor RT1, a second non-volatile reconfigurable transistor RT2, a matching line ML, a first write line W1, a second write line W2, a first lookup line S1, and a second lookup line S2. The matching line ML is connected to both the source of the first non-volatile reconfigurable transistor RT1 and the drain of the second non-volatile reconfigurable transistor RT2. The first write line W1 is connected to the drain of the first non-volatile reconfigurable transistor RT1 and is used to apply a preset voltage to the drain of the first non-volatile reconfigurable transistor RT1 to reconfigure its polarity. The second write line W2 is connected to both the source of the second non-volatile reconfigurable transistor RT2 and the first write line W1, and is used to apply a preset voltage to the drain of the second non-volatile reconfigurable transistor RT2. The polarity of the second non-volatile reconfigurable transistor is reconfigured; wherein, by changing the polarity of the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor RT2, preset data is written to the tri-state content-addressable memory; the first lookup line S1 is connected to the gate of the first non-volatile reconfigurable transistor RT1 and is used to apply a first turn-on trigger voltage to the gate of the first non-volatile reconfigurable transistor RT1 to turn on the first non-volatile reconfigurable transistor RT1; the second lookup line S2 is connected to the gate of the second non-volatile reconfigurable transistor RT2 and is used to apply a second turn-on trigger voltage to the gate of the second non-volatile reconfigurable transistor RT2 to turn on the second non-volatile reconfigurable transistor RT2; wherein, by applying a preset level to the first lookup line S1 and the second lookup line S2, the preset data is addressed.

[0053] Specifically, the preset voltage includes a preset negative voltage and a preset positive voltage; a preset negative voltage is applied between the source and drain of the first non-volatile reconfigurable transistor RT1, and the gate of the first non-volatile reconfigurable transistor RT1 is grounded, and this is maintained for a preset time, so that the polarity of the first non-volatile reconfigurable transistor RT1 changes from N-type to P-type; a preset positive voltage is applied between the source and drain of the first non-volatile reconfigurable transistor RT1, and the gate of the first non-volatile reconfigurable transistor RT1 is grounded, and this is maintained for a preset time, so that the polarity of the first non-volatile reconfigurable transistor RT1 changes from P-type to N-type; or a preset negative voltage is applied between the source and drain of the second non-volatile reconfigurable transistor RT2, and the gate of the second non-volatile reconfigurable transistor RT2 is grounded, and this is maintained for a preset time, so that the polarity of the second non-volatile reconfigurable transistor RT2 changes from N-type to P-type. The polarity of the second non-volatile reconfigurable transistor RT2 is changed from P-type to N-type. A preset positive voltage is applied between the source and drain of the second non-volatile reconfigurable transistor RT2, and the gate of the second non-volatile reconfigurable transistor RT2 is grounded. This is continued for a preset time to change the polarity of the second non-volatile reconfigurable transistor RT2 from P-type to N-type. The electric field strength formed by the preset voltage between the source and drain of the first non-volatile reconfigurable transistor RT1 is greater than the minimum electric field strength required for tellurium atoms to migrate between the source and drain of the first non-volatile reconfigurable transistor RT1, and the electric field strength formed by the preset voltage between the source and drain of the second non-volatile reconfigurable transistor RT2 is greater than the minimum electric field strength required for tellurium atoms to migrate between the source and drain of the second non-volatile reconfigurable transistor RT2.

[0054] Further, as an example, the preset level includes a preset positive level and a preset negative level; if the polarity of the first non-volatile reconfigurable transistor RT1 is N-type, the first turn-on trigger voltage is controlled to be a preset positive level to turn on the first non-volatile reconfigurable transistor RT1; if the polarity of the first non-volatile reconfigurable transistor RT1 is P-type, the first turn-on trigger voltage is controlled to be a preset negative level to turn on the first non-volatile reconfigurable transistor RT1; or if the polarity of the second non-volatile reconfigurable transistor RT2 is N-type, the second turn-on trigger voltage is controlled to be a preset positive level to turn on the second non-volatile reconfigurable transistor RT2; if the polarity of the second non-volatile reconfigurable transistor RT2 is P-type, the second turn-on trigger voltage is controlled to be a preset negative level to turn on the second non-volatile reconfigurable transistor RT2; wherein, the absolute values ​​of the preset positive level and the preset negative level are equal.

[0055] In one embodiment of this application, such as Figure 2 As shown, a non-volatile reconfigurable transistor is provided, including a gate electrode 1, the upper surface of which is covered with an insulating layer 2; a channel layer 3, a tellurium source electrode 5, and a tellurium drain electrode 4 are formed in the surface of the insulating layer 2 away from the gate electrode 1, the tellurium source electrode 5 and the tellurium drain electrode 4 are located on opposite sides of the channel layer 3 and are both electrically connected to the channel layer 3; wherein, by applying a preset excitation electrical signal for a preset time between the tellurium source electrode 5 and the tellurium drain electrode 4, the tellurium atoms in the tellurium source electrode 5 and the tellurium drain electrode 4 migrate under the action of an electric field, changing the polarity of the channel layer 3, so as to reconfigure the polarity of the transistor.

[0056] Specifically, elemental tellurium, as a natural P-type semiconductor material, not only possesses excellent conductivity but also exhibits more active electrochemical properties. Under the influence of an electric field, tellurium atoms migrate between the source and drain electrodes. When tellurium atoms pass through channel layer 3, they accumulate. When the tellurium atoms in channel layer 3 accumulate to a certain extent, the initial polarity of the N-type channel layer reverses, thereby realizing the polarity reconfiguration process of the transistor. Once the above process is completed, unless a reverse electric field is applied, tellurium atoms will not leave channel layer 3. Even if the excitation voltage is removed, the polarity of the transistor will not change again, and vice versa. By applying a reverse voltage between the tellurium source electrode 5 and the tellurium drain electrode 4, a reverse electric field is generated between them, causing the tellurium atoms originally deposited in the channel layer 3 to migrate back to the tellurium drain electrode 4. This allows the channel layer 3 to gradually return to its initial polarity. Therefore, as an example, both the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor RT2 adopt the non-volatile reconfigurable transistor described in this embodiment. Each transistor has two polarities and can be polarized according to usage requirements, thereby greatly reducing the number of transistors and lowering the power consumption of the three-state content addressing memory.

[0057] In the tri-state content-addressable memory described in the above embodiments, each memory cell is constructed using two non-volatile reconfigurable transistors as basic components. Each non-volatile reconfigurable transistor is an N-type transistor with an initial polarity and includes a tellurium source electrode and a tellurium drain electrode. By controlling the voltage between the source and drain, the transistor's polarity can be easily changed. Therefore, in the tri-state content-addressable memory of this embodiment, by configuring the voltage between the first write line W1 and the matching line ML and the voltage between the second write line W2 and the matching line ML, the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor ML can be... The non-volatile reconfigurable transistor RT2 presents different polarity combinations, enabling the tri-state content-addressable memory to have a tri-state storage state. On the other hand, by applying a preset level to the first lookup line S1 and the second lookup line S2, the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor RT2 are controlled to be turned on. According to the different conduction states of the two, the corresponding storage state of the tri-state content-addressable memory can be obtained. The above memory greatly saves the number of transistors used, and both writing and addressing operations only need to be implemented by controlling two non-volatile reconfigurable transistors, which greatly reduces energy consumption and manufacturing and usage costs.

[0058] In one embodiment of this application, if the polarity of the first non-volatile reconfigurable transistor RT1 is P-type and the polarity of the second non-volatile reconfigurable transistor RT2 is N-type, the tri-state content-addressable memory stores 0; if the polarity of the first non-volatile reconfigurable transistor RT1 is N-type and the polarity of the second non-volatile reconfigurable transistor RT2 is P-type, the tri-state content-addressable memory stores 1; if the polarities of both the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor RT2 are N-type, the tri-state content-addressable memory stores preset address data, where the preset address data is any value. It should be noted that the above write operation is not fixed, and those skilled in the art can arbitrarily specify the polarity combination of the non-volatile reconfigurable transistors corresponding to the tri-state storage content according to actual needs, as long as the above function can be achieved. This embodiment does not impose specific limitations.

[0059] In one embodiment of this application, when the voltage of the matching line ML is a first high level, the voltage of the first search line S1 is set to a preset negative level and the voltage of the second search line S2 is set to a preset positive level. If the voltage of the matching line ML changes to a second high level, it is determined that the address has been reached to 0, wherein the first high level is greater than the second high level.

[0060] Specifically, as an example, please refer to Figure 3In Figure (a), the voltage of the matching line ML is at the first high level, and the tri-state content addressing memory stores 0. At this time, a preset negative level with an amplitude range of -6V to -4V is applied to the first lookup line S1, and a preset positive level with an amplitude range of 4V to 6V is applied to the second lookup line S2. Since the first non-volatile reconfigurable transistor RT1 is a P-type transistor, it conducts when a negative voltage is applied to the gate, while the second non-volatile reconfigurable transistor RT2 is an N-type transistor, it conducts when a positive voltage is applied to the gate. That is, under this condition, both the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor RT2 are in the conducting state, and the voltage of the matching line ML will be pulled down from the first high level to the second high level, thereby determining that 0 has been addressed.

[0061] In one embodiment of this application, when the voltage of the matching line ML is at a first high level, the voltage of the first search line S1 is set to a preset positive level and the voltage of the second search line S2 is set to a preset negative level. If the voltage of the matching line ML changes to a second high level, it is determined that address 1 has been reached.

[0062] Specifically, as an example, please refer to Figure 3 In Figure (b), the voltage of the matching line ML is at the first high level, and the tri-state content addressing memory stores 1. At this time, a preset positive level with an amplitude range of 4V to 6V is applied to the first lookup line S1, and a preset negative level with an amplitude range of -6V to -4V is applied to the second lookup line S2. Since the first non-volatile reconfigurable transistor RT1 is an N-type transistor, it is turned on when a positive voltage is applied to the gate, while the second non-volatile reconfigurable transistor RT2 is a P-type transistor, it is turned on when a negative voltage is applied to the gate. That is, under this condition, both the first non-volatile reconfigurable transistor RT1 and the second non-volatile reconfigurable transistor RT2 are in the on state, and the voltage of the matching line ML will be pulled down from the first high level to the second high level, thereby determining that 1 has been addressed.

[0063] In one embodiment of this application, when the voltage of the matching line ML is at a first high level, the voltage of the first search line S1 is set to a preset negative level and the voltage of the second search line S2 is set to a preset positive level, or the voltage of the first search line S1 is set to a preset positive level and the voltage of the second search line S2 is set to a preset negative level. If the voltage of the matching line ML changes to a second high level, it is determined that the preset address data has been addressed.

[0064] Specifically, as an example, please refer to Figure 3In Figure (c), the voltage of the matching line ML is at the first high level, and the tri-state content addressing memory stores the preset address data. At this time, a preset negative level with an amplitude range of -6V to -4V is applied to the first lookup line S1, and a preset positive level with an amplitude range of 4V to 6V is applied to the second lookup line S2. Since the first non-volatile reconfigurable transistor RT1 is an N-type transistor, it is turned off when a negative voltage is applied to the gate, while the second non-volatile reconfigurable transistor RT2 is an N-type transistor, it is turned on when a positive voltage is applied to the gate. Under these circumstances, the voltage of the matching line ML will be pulled down from the first high level to the second high level through the second non-volatile reconfigurable transistor RT2, thereby determining that the preset address data has been addressed.

[0065] Furthermore, as an example, please refer to Figure 3 In Figure (d), the voltage of the matching line ML is at the first high level, and the tri-state content-addressable memory stores the preset address data. At this time, a preset positive level with an amplitude range of 4V to 6V is applied to the first lookup line S1, and a preset negative level with an amplitude range of -6V to -4V is applied to the second lookup line S2. Since the first non-volatile reconfigurable transistor RT1 is an N-type transistor, it is turned on when a positive voltage is applied to its gate, while the second non-volatile reconfigurable transistor RT2 is an N-type transistor, it is turned off when a negative voltage is applied to its gate. Under these circumstances, the voltage of the matching line ML will be pulled down from the first high level to the second high level through the first non-volatile reconfigurable transistor RT1, thereby determining that the preset address data has been addressed.

[0066] In one embodiment of this application, such as Figure 4 As shown, a method for operating a three-state content-addressable memory is provided, implemented based on the three-state content-addressable memory described in any of the foregoing embodiments. The method includes:

[0067] Step 22: Control the voltage between the source and drain of the non-volatile reconfigurable transistor to a preset voltage to change the polarity of the non-volatile reconfigurable transistor and write preset data to the tri-state content addressing memory.

[0068] The non-volatile reconfigurable transistor includes a first non-volatile reconfigurable transistor and a second non-volatile reconfigurable transistor.

[0069] Step 24: Control the gate level of the non-volatile reconfigurable transistor to a preset level in order to address the preset data.

[0070] As an example, such as Figure 5 As shown, the preset data includes 0, 1, and preset address data; the preset voltage includes a preset positive voltage and a preset negative voltage; and the method for writing the preset data in step 22 includes:

[0071] Step 222: Control the matching line, the first search line, and the second search line to be grounded;

[0072] Step 224: Control the voltage of the first write line to the preset positive voltage, and control the voltage of the second write line to the preset positive voltage, so as to write 0 into the tri-state content addressing memory;

[0073] Step 226: Control the voltage of the first write line to the preset negative voltage, and control the voltage of the second write line to the preset negative voltage, so as to write 1 into the tri-state content addressing memory;

[0074] Step 228: Control the voltage of the first write line to the preset negative voltage and control the voltage of the second write line to the preset positive voltage, so as to write the preset address data into the tri-state content addressing memory.

[0075] As an example, such as Figure 6 As shown, it also includes, the preset level includes a preset positive level and a preset negative level, the absolute values ​​of the preset positive level and the preset negative level are equal, and the method for addressing the preset data in step 24 includes:

[0076] Step 242: Control the voltage of the matching line to a first high level;

[0077] Step 244: Control the voltage of the first search line to the preset negative level and control the voltage of the second search line to the preset positive level. If the voltage of the matching line becomes the second high level, it is determined that the address has been reached to 0.

[0078] Step 246: Control the voltage of the first search line to the preset positive level and control the voltage of the second search line to the preset negative level. If the voltage of the matching line changes to the second high level, it is determined that 1 has been addressed.

[0079] Step 248: Control the voltage of the first search line to the preset negative level and control the voltage of the second search line to the preset positive level, or control the voltage of the first search line to the preset positive level and control the voltage of the second search line to the preset negative level. If the voltage of the matching line becomes the second high level, it is determined that the preset address data has been addressed.

[0080] Wherein, the first high level is greater than the second high level.

[0081] It should be understood that, although Figure 4 , Figure 5 , Figure 6The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 , Figure 5 , Figure 6 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0082] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A tri-state content-addressable memory, characterized in that, include: The first non-volatile reconfigurable transistor; The second non-volatile reconfigurable transistor; The matching line is connected to both the source of the first non-volatile reconfigurable transistor and the drain of the second non-volatile reconfigurable transistor. The first write line is connected to the drain of the first non-volatile reconfigurable transistor and is used to apply a preset voltage to the drain of the first non-volatile reconfigurable transistor to reconfigure the polarity of the first non-volatile reconfigurable transistor. The second write line is connected to both the source of the second non-volatile reconfigurable transistor and the first write line, and is used to apply the preset voltage to the drain of the second non-volatile reconfigurable transistor to reconfigure the polarity of the second non-volatile reconfigurable transistor; wherein, by changing the polarity of the first non-volatile reconfigurable transistor and the polarity of the second non-volatile reconfigurable transistor, preset data is written to the tri-state content addressing memory. The first lookup line is connected to the gate of the first non-volatile reconfigurable transistor and is used to apply a first turn-on trigger voltage to the gate of the first non-volatile reconfigurable transistor to turn on the first non-volatile reconfigurable transistor. The second lookup line is connected to the gate of the second non-volatile reconfigurable transistor and is used to apply a second turn-on trigger voltage to the gate of the second non-volatile reconfigurable transistor to turn on the second non-volatile reconfigurable transistor; wherein, the preset data is addressed by applying a preset level to the first lookup line and the second lookup line. The non-volatile reconfigurable transistor includes: a gate electrode, the upper surface of which is covered with an insulating layer; a channel layer formed in the surface of the insulating layer away from the gate electrode; a tellurium source electrode; a tellurium drain electrode; the tellurium source electrode and the tellurium drain electrode are located on opposite sides of the channel layer and are both electrically connected to the channel layer; wherein, when a preset voltage for a preset time is applied between the tellurium source electrode and the tellurium drain electrode, tellurium atoms in the tellurium source electrode and the tellurium drain electrode migrate under the action of the electric field, changing the polarity of the channel layer, so that the transistor polarity changes from N-type to P-type, or from P-type to N-type; the electric field strength formed by the preset voltage between the source of the non-volatile reconfigurable transistor and the drain of the first non-volatile reconfigurable transistor is greater than the minimum electric field strength required to cause tellurium atoms to migrate between the source of the non-volatile reconfigurable transistor and the drain of the non-volatile reconfigurable transistor.

2. The tri-state content-addressable memory according to claim 1, characterized in that, The preset voltage includes a preset negative voltage and a preset positive voltage; the preset negative voltage is applied between the source and the drain of the first non-volatile reconfigurable transistor and the gate of the first non-volatile reconfigurable transistor is grounded, and this is continued for a preset time so that the polarity of the first non-volatile reconfigurable transistor is changed from N-type to P-type. The preset positive voltage is applied between the source and the drain of the first non-volatile reconfigurable transistor and the gate of the first non-volatile reconfigurable transistor is grounded, and the preset time is maintained to change the polarity of the first non-volatile reconfigurable transistor from P-type to N-type. or The preset negative voltage is applied between the source and the drain of the second non-volatile reconfigurable transistor, and the gate of the second non-volatile reconfigurable transistor is grounded, and the preset time is maintained, so that the polarity of the second non-volatile reconfigurable transistor is changed from N-type to P-type. The preset positive voltage is applied between the source and the drain of the second non-volatile reconfigurable transistor, and the gate of the second non-volatile reconfigurable transistor is grounded, and the preset time is maintained, so that the polarity of the second non-volatile reconfigurable transistor is changed from P-type to N-type. Wherein, the electric field strength formed by the preset voltage between the source and drain of the first non-volatile reconfigurable transistor is greater than the minimum electric field strength required to cause tellurium atoms to migrate between the source and drain of the first non-volatile reconfigurable transistor, and the electric field strength formed by the preset voltage between the source and drain of the second non-volatile reconfigurable transistor is greater than the minimum electric field strength required to cause tellurium atoms to migrate between the source and drain of the second non-volatile reconfigurable transistor.

3. The tri-state content-addressable memory according to claim 2, characterized in that, The preset level includes a preset positive level and a preset negative level; if the polarity of the first non-volatile reconfigurable transistor is N-type, the first turn-on trigger voltage is controlled to be the preset positive level so that the first non-volatile reconfigurable transistor is turned on; if the polarity of the first non-volatile reconfigurable transistor is P-type, the first turn-on trigger voltage is controlled to be the preset negative level so that the first non-volatile reconfigurable transistor is turned on. or If the polarity of the second non-volatile reconfigurable transistor is N-type, the second turn-on trigger voltage is controlled to the preset positive level so that the second non-volatile reconfigurable transistor is turned on; If the polarity of the second non-volatile reconfigurable transistor is P-type, the second turn-on trigger voltage is controlled to the preset negative level so that the second non-volatile reconfigurable transistor is turned on; Wherein, the absolute values ​​of the preset positive level and the preset negative level are equal.

4. The tri-state content-addressable memory according to claim 2 or 3, characterized in that, If the polarity of the first non-volatile reconfigurable transistor is P-type and the polarity of the second non-volatile reconfigurable transistor is N-type, the tri-state content addressing memory stores 0.

5. The tri-state content-addressable memory according to claim 2 or 3, characterized in that, If the polarity of the first non-volatile reconfigurable transistor is N-type and the polarity of the second non-volatile reconfigurable transistor is P-type, the tri-state content addressing memory stores 1.

6. The tri-state content-addressable memory according to claim 5, characterized in that, If both the first non-volatile reconfigurable transistor and the second non-volatile reconfigurable transistor are N-type, the tri-state content addressing memory stores preset address data.

7. The tri-state content-addressable memory according to claim 6, characterized in that, When the voltage on the matching line is at a first high level. Set the voltage of the first search line to the preset negative level and the voltage of the second search line to the preset positive level. If the voltage of the matching line changes to the second high level, it is determined that the address has been reached to 0. Set the voltage of the first search line to the preset positive level and the voltage of the second search line to the preset negative level. If the voltage of the matching line changes to the second high level, it is determined that 1 has been addressed. If the voltage of the first search line is set to the preset negative level and the voltage of the second search line is set to the preset positive level, or the voltage of the first search line is set to the preset positive level and the voltage of the second search line is set to the preset negative level, and the voltage of the matching line becomes the second high level, it is determined that the preset address data has been addressed. Wherein, the first high level is greater than the second high level.

8. A method for operating a three-state content-addressable memory, characterized in that, Based on the tri-state content-addressable memory described in claims 1-7, the method includes: The voltage between the source and drain of the non-volatile reconfigurable transistor is controlled to a preset voltage to change the polarity of the non-volatile reconfigurable transistor, so as to write preset data to the tri-state content addressing memory; the non-volatile reconfigurable transistor includes a first non-volatile reconfigurable transistor and a second non-volatile reconfigurable transistor. The gate level of the non-volatile reconfigurable transistor is controlled to a preset level in order to address the preset data.

9. The method according to claim 8, characterized in that, The preset data includes 0, 1, and preset address data; the preset voltage includes a preset positive voltage and a preset negative voltage; and the method for writing the preset data includes: The control matching line, the first search line, and the second search line are all grounded; The voltage of the first write line is controlled to the preset positive voltage, and the voltage of the second write line is controlled to the preset positive voltage, so as to write 0 into the tri-state content addressing memory; The voltage of the first write line is controlled to the preset negative voltage, and the voltage of the second write line is controlled to the preset negative voltage, so as to write 1 into the tri-state content addressing memory; The voltage of the first write line is controlled to be the preset negative voltage, and the voltage of the second write line is controlled to be the preset positive voltage, so as to write the preset address data into the tri-state content addressing memory.

10. The method according to claim 9, characterized in that, It also includes, wherein the preset level comprises a preset positive level and a preset negative level, the absolute values ​​of the preset positive level and the preset negative level are equal, and the method for addressing the preset data includes: The voltage of the matching line is controlled to a first high level; The voltage of the first search line is controlled to the preset negative level and the voltage of the second search line is controlled to the preset positive level. If the voltage of the matching line becomes the second high level, it is determined that the address has been reached to 0. The voltage of the first search line is controlled to the preset positive level and the voltage of the second search line is controlled to the preset negative level. If the voltage of the matching line changes to the second high level, it is determined that 1 has been addressed. If the voltage of the first search line is controlled to the preset negative level and the voltage of the second search line is controlled to the preset positive level, or the voltage of the first search line is controlled to the preset positive level and the voltage of the second search line is controlled to the preset negative level, and the voltage of the matching line becomes the second high level, it is determined that the preset address data has been addressed. Wherein, the first high level is greater than the second high level.

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