An ethernet burner
By using an Ethernet programmer with an FPGA+MCU architecture, combining a network module, a main control module, and a level conversion module, the performance limitations of existing Ethernet programmers are solved, achieving high-speed programming and system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG GOWIN SEMICON TECH CO LTD
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
Existing Ethernet programmers have limited performance, especially with the use of USB and the fact that LPT ports are no longer standard on newer PCs, making it difficult to achieve high-efficiency programming speeds.
The Ethernet programmer, which adopts an FPGA+MCU architecture, receives and converts network signals through a network module. The main control module extracts valid data and implements a JTAG module internally. It uses the Advanced Peripheral Bus (APB) to communicate with the JTAG module. Combined with a level conversion module, it ensures signal compatibility and improves the programming speed.
It enables the receiving instruction data or bin file to be sent to the target device at a higher rate, which improves the burning speed, simplifies the system architecture, reduces dependence on external components, and improves the stability and maintainability of the system.
Smart Images
Figure CN122240144A_ABST
Abstract
Description
Technical Field
[0001] This application relates to, but is not limited to, embedded system design techniques, and in particular to an Ethernet programmer. Background Technology
[0002] Field Programmable Gate Array (FPGA) programmers mainly include offline programmers such as those using USB cables (which convert USB signals to Joint Test Action Group (JTAG) protocol via a USB chip) or parallel port programming kits (LPT ProgKits, which convert parallel port signals to JTAG signals). For some development applications, USB is not permitted, and LPT ports are no longer standard on newer PCs. Therefore, Ethernet programmers based on network ports can effectively solve this problem.
[0003] Improving the performance of Ethernet programmers is a technical problem that urgently needs to be solved. Summary of the Invention
[0004] This application provides an Ethernet programmer with a simple structure that can improve programming speed.
[0005] This invention provides an Ethernet programmer, comprising: a network module and a main control module; wherein,
[0006] The network module is used to receive network signals, convert analog network signals into digital signals, and output the converted digital signals to the main control module through the media-independent interface used to connect the physical layer chip PHY and the media access control layer MAC.
[0007] The main control module is an FPGA with an integrated microprocessor unit (MCU), which is used to extract valid data from the received digital signal and store the extracted valid data in the buffer inside the main control module. The JTAG module is implemented inside the main control module. According to the timing requirements of the JTAG protocol, the valid data buffered through the JTAG interface is converted into JTAG signals and sent to the chip to be programmed.
[0008] The MCU in the main control module communicates with the JTAG module in the main control module through register configuration and the Advanced Peripheral Bus (APB).
[0009] In one exemplary instance, a level conversion module is also included to convert the JTAG signal output from the main control module into a voltage level compatible with the chip to be programmed.
[0010] In one exemplary instance, the JTAG module uses a custom register structure, JTAG_TypeDef, to establish a communication interface with the MCU.
[0011] In one exemplary instance, the media independent interface includes any of the following: Reduced Gigabit Media Independent Interface RGMII, Gigabit Media Independent Interface GMII, and Serial Gigabit Media Independent Interface SGMII.
[0012] In one exemplary instance, the cache includes static random access memory (PSRAM), SRAM, or dynamic random access memory (DRAM).
[0013] In one exemplary instance, the registers include: a data register, a control register, and a command register.
[0014] In one exemplary instance, the data register includes:
[0015] The write data register WDATA stores the data to be sent and is used to send data to the JTAG module;
[0016] The read data register RDATA stores the received data and is used to receive data from the JTAG module.
[0017] In one exemplary instance, the control register includes:
[0018] The CTRL register is used to control the JTAG state machine to enter the data shift state or the idle state.
[0019] In one exemplary instance, the command register includes a CMD register for sending control commands to the JTAG module, instructing data transmission and data reception.
[0020] The STATUS register is used to record the status of peripheral devices;
[0021] The INIT register is used to initialize the JTAG module;
[0022] The RUNTEST register is used to control the continuous generation of clock signals by peripherals;
[0023] The FREQ register is used to set the clock frequency of the JTAG module;
[0024] The DUTYCYCLE register is used to set the duty cycle of the TCK signal.
[0025] In one exemplary instance, the main control module is a GW2AR18 chip; the network module is a B50610 chip; and the level conversion module is an SN74 chip.
[0026] The Ethernet programmer provided in this application adopts an FPGA+MCU architecture for its main control module, which has a simple structure. The JTAG module is implemented inside the main control module, which achieves the purpose of sending the received instruction data or bin file to the target device, i.e. the chip to be programmed, at a higher rate, thereby improving the programming speed.
[0027] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description
[0028] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0029] Figure 1 This is a schematic diagram of the composition structure of the Ethernet programmer in the embodiments of this application;
[0030] Figure 2 This is a schematic diagram showing the connection between the MCU and FPGA via the APB bus in an embodiment of this application;
[0031] Figure 3 This is a schematic diagram illustrating an example of a programming operation page in an embodiment of this application;
[0032] Figure 4(a) illustrates the data interaction between the Ethernet programmer and the JTAG module via the APB bus in an embodiment of this application. Figure 1 ;
[0033] Figure 4(b) illustrates the data interaction between the Ethernet programmer and the JTAG module via the APB bus in an embodiment of this application. Figure 1 ;
[0034] Figure 5 This is a schematic diagram of the composition of a programming system using the Ethernet programmer of this application in an embodiment of this application;
[0035] Figure 6 This is a schematic diagram of the embedded system architecture based on the GW2AR18 chip Cortex-M1 soft core in the embodiments of this application. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.
[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0039] It is understood that the terms "first" and "second" used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0040] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0042] In Ethernet programmer implementations, most use an Advanced RISC Machine (ARM) as the main control chip. The JTAG protocol is an analog protocol, and when simulating JTAG via GPIO, the frequency is limited by the toggle rate of the General Purpose Input / Output (GPIO) interface, typically with an upper limit of 5MHz, thus limiting the programmer's performance. Another implementation uses an FPGA as the main controller; however, this approach involves overly complex circuit design, makes implementing general-purpose Lightweight IP network protocols (LWIP) difficult, and implementing the Transmission Control Protocol / Internet Protocol (TCP / IP) network protocol stack on an FPGA consumes significant resources, requiring a high-density FPGA.
[0043] To improve the performance of Ethernet programmers, embodiments of this application provide an Ethernet programmer, such as... Figure 1 As shown, it includes at least: a network module and a main control module; wherein,
[0044] The network module is used to receive network signals, convert analog network signals into digital signals, and output the converted digital signals to the main control module through a media-independent interface for connecting the physical layer chip (PHY) and the media access control layer (MAC).
[0045] The main control module is an FPGA with an integrated microcontroller unit (MCU). It is used to extract valid data (such as files to be burned) from the received digital signals and store the extracted valid data in the buffer inside the main control module. The JTAG module is implemented inside the main control module. According to the timing requirements of the JTAG protocol, the valid data cached through the JTAG interface is converted into JTAG signals and sent to the chip to be burned.
[0046] The MCU in the main control module communicates with the JTAG module in the main control module through the configuration of registers and the use of the Advanced Peripheral Bus (APB).
[0047] The Ethernet programmer provided in this application adopts an FPGA+MCU architecture for its main control module, which has a simple structure. The JTAG module is implemented inside the main control module, which achieves the purpose of sending the received instruction data or bin file to the target device, i.e. the chip to be programmed, at a higher rate, thereby improving the programming speed.
[0048] In one embodiment, the JTAG module and the MCU inside the main control module can interact via the APB bus, ensuring efficient and stable data transmission. In another embodiment, the JTAG module can use a custom register structure, JTAG_TypeDef, to establish a communication interface with the MCU, thereby achieving efficient control and data transmission of the JTAG module.
[0049] In one embodiment, such as Figure 2 As shown, the MCU and FPGA inside the main control module are connected via the APB bus. The APB interface module is responsible for data transmission between the MCU and FPGA, converting the APB bus signals into a signal format that the FPGA can process, thus enabling communication between the MCU and FPGA within the main control module. The JTAG module may include components such as a frequency adjustment section, an IO timing control section, a TAP status control section, and a counter. Corresponding JTAG signals may include test clock (TCK), test data input (TDI), test data output (TDO), and test mode selection (TMS). In one embodiment, the transmit buffer and receive buffer are each 256 bytes in size. The verification module is used to verify whether the data sent by the JTAG interface is consistent with the data read back from the JTAG interface.
[0050] In one exemplary instance, the media independent interface may include, but is not limited to, Reduced Gigabit Media Independent Interface (RGMII), Gigabit Media Independent Interface (GMII), Serial Gigabit Media Independent Interface (SGMII), etc.
[0051] In one exemplary instance, the cache may include static random access memory (PSRAM), SRAM, dynamic random access memory (DRAM), etc.
[0052] The Ethernet programmer provided in this application adopts an FPGA+MCU architecture for its main control module. The MCU is responsible for receiving and parsing TCP / IP protocol data, while the FPGA processes the parsed data and generates the trigger control signals required by the JTAG protocol. The flexibility of the MCU makes it suitable for handling network communication, while the high-speed parallel processing capability of the FPGA ensures the high accuracy and stability of the JTAG signals, thus achieving a perfect combination of network data reception and parsing with high-speed JTAG signal generation.
[0053] In one exemplary embodiment, the Ethernet programmer provided in this application may further include a level conversion module for converting the JTAG signal output by the self-control module into a voltage level compatible with the chip to be programmed, so as to ensure the correctness and stability of signal transmission.
[0054] In one embodiment, the network module may include, but is not limited to, B50610.
[0055] In one embodiment, the main control module may include, but is not limited to, a chip such as the GW2AR18. The MCU in the GW2AR18 chip can run a lightweight TCP / IP protocol stack (uIP network protocol stack) to receive and parse network data; the FPGA in the GW2AR18 chip can have a customized peripheral interface and be mounted on the APB to implement a custom JTAG module. This JTAG module can be adapted to FPGA products from different manufacturers to ensure compatibility and efficiency, thereby achieving efficient support for high-speed data transmission and programming operations to the target device, i.e., the chip to be programmed.
[0056] In one embodiment, the level conversion module may include, but is not limited to, a chip such as the SN74.
[0057] In this embodiment, the main control module is an FPGA chip with integrated MCU functionality, allowing users to customize the JTAG module. This solves the frequency limitation problem when using an MCU to simulate JTAG, thus improving the programming speed. Furthermore, the FPGA chip with integrated MCU functionality simplifies the system architecture, reduces dependence on external components, and improves system stability and maintainability.
[0058] Furthermore, by using an FPGA chip with integrated MCU functions, such as the GW2AR18 chip, to implement the M1 soft core, the MCU functions are integrated into the FPGA, thereby realizing the control logic of the Ethernet programmer and the MCU functions on the same chip, reducing the cost and complexity of the system.
[0059] Furthermore, FPGA chips with integrated MCU functionality offer greater portability, allowing users to more easily adapt to different network protocol stacks, thus improving the system's versatility and adaptability. In this embodiment, by integrating MCU functionality into the FPGA chip, dependence on external MCUs is reduced, system design is simplified, and the overall system reliability is improved.
[0060] like Figure 3The schematic diagram of the programming operation page shown illustrates the working principle of the Ethernet programmer provided in this application embodiment as follows: The Ethernet programmer is powered on and connected to a network cable; by entering a URL such as 10.10.10.11 in a browser on a PC, the bin file to be programmed is selected at the bottom of the interface, the "Load" option is checked, and the "Send to Programmer" button is clicked to complete the caching of the bin file in the Ethernet programmer; if it is necessary to permanently program the logic to the FPGA, the "Program Flash" button is clicked to execute the programming of the data stream file to the FPGA. Figure 2 The example may include, but is not limited to, the following: Clicking the "program SRAM" button if temporary logic needs to be loaded onto the FPGA; the "read id code" button to read the FPGA's ID code for hardware verification; the "read user code" button to read the user code to check existing user logic in the device; the "read status code" button to read the status code to determine if the device is currently functioning correctly; the "erase SRAM" button to erase the FPGA's SRAM to clear temporarily stored logic; and the "erase Flash" button to erase the FPGA's Flash memory to clear long-term stored logic configuration. In this embodiment, the internally implemented JTAG module sends the received instruction data or bin file to the target device at a higher rate. In one embodiment, an internally built-in verification module enables high-speed processing and comparison of whether the sent data and the read-back data are consistent.
[0061] The following details the process of data interaction between the Ethernet programmer and the JTAG module via the APB bus, including register definition, status control, data transmission and reception.
[0062] Data registers may include: a write data register (WDATA) to store data to be sent to the JTAG module, used for sending data to the JTAG module; and a read data register (RDATA) to store received data, used for receiving data from the JTAG module. Control registers may include: a CTRL register to control the state of the JTAG state machine (e.g., JTAG_CTRL_SHIFT_DR indicates entering the data shift state, SHIFT_IDLE indicates entering the idle state). Command registers may include: a STATUS register to record peripheral status (e.g., whether busy, current state of the state machine); an INIT register to initialize the JTAG module; a RUNTEST register to control the peripheral to continuously generate a clock signal; a FREQ register to set the clock frequency of the JTAG module; and a DUTYCYCLE register to set the duty cycle of the TCK signal. The CMD register is used to send control commands to the JTAG module, including functions for controlling data transmission, data reception, and TMS data bits, such as indicating data transmission (CMD=1), data reception (CMD=2), or controlling TMS bits. An example of data interaction implementation is as follows:
[0063] / / Type definition
[0064] #define JTAG((jtag_TypeDef*)APB2PERIPH_BASE)
[0065] / / Initialize the JTAG module
[0066] JTAG->INIT = 1;
[0067] JTAG->RESET = 1;
[0068] / / Send data to the JTAG module
[0069] JTAG->CTRL = JTAG_CTRL_SHIFT_DR; / / Control the state machine to enter Shift-DR state
[0070] JTAG->CMD = 1; / / CMD_1 is set to control data transmission.
[0071] JTAG->WDATA = data_to_send; / / Put the data to be sent into the WDATA register.
[0072] JTAG->CTRL = JTAG_SHIFT_IDLE; / / Control the state machine to enter the IDLE state / / Receive data from the JTAG module
[0073] JTAG->CTRL = JTAG_SHIFT_DR; / / Controls the state machine to enter Shift-DR state.
[0074] JTAG->CMD = 2; / / CMD_2 is set to control data reception.
[0075] uint16_t received_data = JTAG->RDATA; / / The received data is placed into the RDATA register.
[0076] JTAG->CTRL = JTAG_SHIFT_IDLE; / / Controls the state machine to enter the IDLE state.
[0077] Referring to the data interaction process shown in Figure 4(a) Figure 1 For example, the data transmission process includes: initializing the JTAG module by setting INIT=1 and FREQ=1, initializing the JTAG module, and setting the clock frequency; resetting the JTAG module by setting RESET=1; sending data to the JTAG module by setting CTRL=JTAG_CTRL_SHIFT_DR to control the JTAG state machine to enter the data shift state for data transmission; setting CMD=1 to instruct the JTAG module to enter the data transmission mode; setting WDATA=data_send to write the data to be sent into the write data register WDATA; and setting CTRL=JTAG_CTRL_SHIFT_IDLE to control the JTAG state machine to enter the idle state, thus completing the data transmission process.
[0078] Referring to the data interaction process shown in Figure 4(b) Figure 1 For example, the data receiving process includes: setting CTRL=JTAG_CTRL_SHIFT_DR to control the JTAG state machine to enter the data shift state for sending data; setting CMD=2 to instruct the JTAG module to enter the data receiving mode; waiting for peripheral devices to transmit data, with the peripheral devices outputting data through TDO and the data stored in the RDATA register; reading the data register from the read data register to obtain the received data; setting CTRL=SHIFT_IDLE to control the JTAG state machine to enter the idle state to complete the data sending process.
[0079] Figures 4(a) and 4(b) illustrate the data sending and receiving processes, respectively. In the Ethernet programmer main control module provided in this embodiment, the MCU communicates with the JTAG module in the main control module via the APB bus through register configuration (such as CTRL, CMD, WDATA, and RDATA). By defining the base address of the JTAG module, such as APB2PERIPH_BASE, the MCU can directly access the JTAG module's registers to initialize the JTAG module, send data to the JTAG module, and receive data returned by the JTAG module, ensuring complete programming and communication functions.
[0080] The Ethernet programmer provided in this application embodiment enables rapid interaction between the JTAG module and the MCU via the APB bus; the state machine-based control logic ensures sequential data transmission. Furthermore, the Ethernet programmer provided in this application embodiment supports configuration of parameters such as clock frequency and duty cycle, better adapting to the needs of different target devices, i.e., the chips to be programmed. Moreover, by monitoring the JTAG module status in real time through the STATUS register, data loss or conflicts are prevented, thereby achieving an efficient and stable network programming process.
[0081] This application's embodiments achieve flexible adjustment of the JTAG programming rate by customizing a JTAG module within the main control module chip. In one embodiment, the highest programming rate can reach 60MHz, and the lowest programming rate can reach 60kHz. This demonstrates a large adjustment range for the JTAG programming rate, with stable frequency fluctuations and a stable duty cycle; moreover, it enables programming of JTAG devices at different frequencies.
[0082] In one embodiment, the Ethernet programmer provided in this application can complete the programming of the FPGA to be programmed by connecting to the network, thus overcoming the limitation that the programmer can only interact with a PC via USB.
[0083] In one embodiment, the main control module chip of this application can be a chip such as GW2AR18 that includes embedded large-capacity PSRAM, so there is no need to install SRAM memory separately, thereby reducing wiring and PCB space, making the structure simpler and more stable.
[0084] In one embodiment, the Ethernet programmer provided in this application, combined with the soft core characteristics of the main control module, processes network data packets more simply and generates more stable JTAG protocol signals.
[0085] Figure 5 This is a schematic diagram illustrating the composition of a programming system employing the Ethernet programmer described in this application, as shown in the embodiments of this application. Figure 5The diagram illustrates the overall hardware architecture of an embedded system using a GW2AR18 FPGA as the main control module chip. It primarily includes functional modules for network communication, JTAG downloading, storage, display, buttons, and UART. A detailed description follows:
[0086] The network module is a network PHY chip. In this embodiment, the B50610 is used as an example. The network PHY chip is used to implement the physical layer function of the network communication protocol and supports connection to the main control module via the RGMI interface. The network module provides a high-speed network data communication interface, connecting the network PHY chip to the network logic module of the FPGA.
[0087] Taking the GW2AR18 FPGA chip as an example, the main control module is responsible for logic processing, control, and the collaborative work of multiple modules. The main control module processes network data via RGMI; controls the LCD display module; operates the SPI Flash storage module; supports FPGA configuration and debugging via the JTAG interface; and interacts with buttons, LEDs, and UART.
[0088] Taking the SN74AVC4T245 JTAG as an example, the level conversion module is used to achieve JTAG signal level matching and support signal transmission between different voltage domains. The level conversion module connects the FPGA to an external programming tool via the JTAG interface for logic configuration and debugging.
[0089] An LCD display module is used to provide a graphical user interface to display real-time status or information.
[0090] The SPI interface is used to control the data transmission of the LCD and is connected to the FPGA main control chip.
[0091] File information storage module (i.e.) Figure 5 The SPI Flash memory in the FPGA is used to store FPGA logic configuration files, user data, and other information. The file information storage module connects to the FPGA via the SPI interface, supporting data storage and retrieval operations.
[0092] Button module (i.e.) Figure 5 The system includes two buttons (×2) as user input interfaces, used to control system behavior (such as start, reset, etc.). The buttons are connected to the FPGA via GPIO to capture user input signals.
[0093] LED module (i.e.) Figure 5 The LED module (2 LEDs) is used to display system status or indicate functions (such as running, alarm, etc.). The LED module is connected to the FPGA via GPIO and controlled by the main control chip.
[0094] UART module (i.e.) Figure 5The UART0 module provides serial communication for interaction with a PC or other devices (such as for debugging and data transmission). The UART module connects directly to the FPGA and performs serial data processing through the main control chip.
[0095] Figure 5 The programming system shown is based on an FPGA and is equipped with network communication, storage, display and debugging modules to build a feature-rich, flexible and scalable embedded system, which is especially suitable for application scenarios that require real-time network communication and flexible logic configuration.
[0096] Figure 6 This is a schematic diagram of the embedded system architecture based on the GW2AR18 chip Cortex-M1 soft core in the embodiments of this application, as shown below. Figure 6 As shown, the Cortex-M1 soft core 1 is the core processing unit of the system, used to execute application programs and control peripherals. ITCM (Instruction Tightly-Coupled Memory) provides instruction storage and fast access for the core, while DTCM (Data Tightly-Coupled Memory) provides data storage and fast access for the core. GPIO component 2 connects to the Cortex-M1 via the APB bus, providing a general-purpose input / output interface for controlling external devices or reading status signals, controlling simple devices (such as LEDs and buttons), or receiving switch signals. Ethernet component 3 connects to the Cortex-M1 via the APB bus, providing Ethernet communication functionality for network connectivity, supporting embedded devices to communicate and transmit data over a network. PSRAM component 4 connects to the Cortex-M1 via the APB bus, expanding the system's storage capacity for storing temporary data or large amounts of data requiring fast access. SPI-Flash component 5 connects to the Cortex-M1 via the APB bus and is a non-volatile memory connected via the SPI protocol, used to store programs, configurations, or data, including program code, configuration information, or user data. The AHB2-Extension bus 6, as an extension of the APB bus, is connected to the Cortex-M1 to expand the APB bus functionality, providing connectivity for more peripherals and supporting additional peripheral access (such as custom devices or future expansions). The JTAG component 7 is indirectly connected to the Cortex-M1 via the APB bus and is used to implement chip debugging and programming functions through the JTAG protocol, supporting debugging, diagnosis, and configuration of programs and logic during development.
[0097] Other components, such as DEBUG, are used for debugging and testing functions. IRQ (Interrupt Request): Supports 31 interrupt signals for responding to external device events. The APB bus connects major peripherals (such as GPIO, Ethernet, PSRAM, SPI-Flash, etc.) to the Cortex-M1 core, providing high-performance, low-latency data transmission capabilities and supporting parallel access from multiple devices. The APB bus is also used to connect low-speed peripherals (such as UART, Timer, Watchdog, RTC, I2C, etc.) via the AHB2APB bridge (AHB2APB), supporting energy-saving designs and suitable for peripherals requiring low power consumption.
[0098] The Cortex-M1 soft core 1 directly controls high-speed peripherals (such as Ethernet, PSRAM, and SPI-Flash) via the APB bus. The APB bus enables system function expansion through the AHB2-Extension and APB bus. Low-speed peripherals (such as UART, Timer, and JTAG) are connected to the APB bus through the AHB2APB bridge to meet low-power design requirements.
[0099] Figure 6 In the system shown, the Cortex-M1 soft core 1 provides high-efficiency computing power, supporting multiple interrupts and debugging functions. Storage capacity is expanded via PSRAM and SPI-Flash, effectively supporting program and data storage. Network communication is provided through an Ethernet module, while UART and I2C support external device connections. The JTAG module also provides development and debugging tool interfaces, supporting rapid development. Figure 6 The embedded system architecture shown is based on the Cortex-M1 soft core and features flexible bus design, high-speed peripheral connectivity, and low-speed peripheral support. It is suitable for application scenarios that require efficient processing, rich peripheral expansion, and network communication functions.
[0100] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.
Claims
1. An Ethernet programmer, characterized in that, include: Network module, main control module; among which, The network module is used to receive network signals, convert analog network signals into digital signals, and output the converted digital signals to the main control module through the media-independent interface used to connect the physical layer chip PHY and the media access control layer MAC. The main control module is an FPGA with an integrated microprocessor unit (MCU), which is used to extract valid data from the received digital signal and store the extracted valid data in the buffer inside the main control module. The JTAG module is implemented inside the main control module. According to the timing requirements of the JTAG protocol, the valid data buffered through the JTAG interface is converted into JTAG signals and sent to the chip to be programmed. The MCU in the main control module communicates with the JTAG module in the main control module through register configuration and the Advanced Peripheral Bus (APB).
2. The Ethernet programmer according to claim 1 further includes a level conversion module for converting the JTAG signal output from the main control module into a voltage level compatible with the chip to be programmed.
3. The Ethernet programmer according to claim 1 or 2, wherein, The JTAG module uses a custom register structure, JTAG_TypeDef, to establish a communication interface with the MCU.
4. The Ethernet programmer according to claim 1 or 2, wherein, The media independent interface includes any of the following: Reduced Gigabit Media Independent Interface RGMII, Gigabit Media Independent Interface GMII, and Serial Gigabit Media Independent Interface SGMII.
5. The Ethernet programmer according to claim 1 or 2, wherein, The cache includes static random access memory (PSRAM), SRAM, or dynamic random access memory (DRAM).
6. The Ethernet programmer according to claim 1 or 2, wherein, The registers include: a data register, a control register, and a command register.
7. The Ethernet programmer according to claim 6, wherein, The data register includes: The write data register WDATA stores the data to be sent and is used to send data to the JTAG module; The read data register RDATA stores the received data and is used to receive data from the JTAG module.
8. The Ethernet programmer according to claim 6, wherein, The control register includes: The CTRL register is used to control the JTAG state machine to enter the data shift state or the idle state.
9. The Ethernet programmer according to claim 6, wherein, The command register includes: The CMD register is used to send control commands to the JTAG module, instructing data to be sent or received. The STATUS register is used to record the status of peripheral devices; The INIT register is used to initialize the JTAG module; The RUNTEST register is used to control the continuous generation of clock signals by peripherals; The FREQ register is used to set the clock frequency of the JTAG module; The DUTYCYCLE register is used to set the duty cycle of the TCK signal.
10. The Ethernet programmer according to any one of claims 1-9, wherein, The main control module is a GW2AR18 chip; the network module is a B50610 chip; and the level conversion module is an SN74 chip.