Method and apparatus for synchronous switching multiple-input demodulation comparators

Abstract

Disclosed are a method and apparatus for synchronous switching of multiple-input demodulation comparators. The method includes receiving line signals by a plurality of combined multiple-input comparator demodulation circuits, each combined multiple-input comparator demodulation circuit receiving the line signals according to a corresponding input arrangement related to a corresponding subchannel vector of a plurality of mutually orthogonal subchannel vectors, the line signals including a superposition of a set of baseband symbols and a set of carrier-modulated symbols; generating a set of baseband subchannel outputs by combining the set of line signals according to the corresponding input arrangement; obtaining a phase-adjusted demodulation signal related to the set of carrier-modulated symbols; and generating a set of demodulated subchannel outputs by combining the set of line signals according to the corresponding input arrangement and according to the phase-adjusted demodulation signal, the phase-adjusted demodulation signal configured to constructively combine a first half cycle and a second half cycle of the carrier-modulated signals and destructively cancel the set of baseband symbols.

Description

[0001] This application is a divisional application of patent application No. 201880084127.2, filed on December 28, 2018, entitled "Synchronous Switching Multi-Input Demodulation Comparator".

[0002] Cross-references to related applications

[0003] This application claims the benefit of U.S. Provisional Application No. 62 / 611,523, filed on December 28, 2017, by Armin Tajalli, entitled “Combinatorial Multi-Input Comparator / Demodulator”, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0004] References

[0005] The following references are incorporated herein by reference in their entirety for all purposes:

[0006] The U.S. patent application, titled "Orthogonal Differential Vector Signaling," was filed on May 20, 2010, with publication number 2011 / 0268225, application number 12 / 784,414, and inventors Harm Cronie and Amin Shokrollahi. It is hereinafter referred to as "Cronie1".

[0007] The U.S. patent application with application number 13 / 030,027, filed on February 17, 2011, and inventors Harm Cronie, Amin Shokrollahi, and Armin Tajalli, entitled “Method and System for Noise-resistant, High Pin Utilization, and Low-Power Communication Using Sparse Signaling Codes”, hereinafter referred to as “Cronie 2”;

[0008] The U.S. patent application with application number 14 / 158,452, filed on January 17, 2014, and inventors John Fox, Brian Holden, Peter Hunt, John D Keay, Amin Shokrollahi, Richard Simpson, Anant Singh, Andrew Kevin John Stewart, and Giuseppe Surace, entitled “Low SSO Noise Inter-Chip Communication Method and System”, hereinafter referred to as Fox 1;

[0009] The U.S. patent application with application number 13 / 842,740, filed on March 15, 2013, and inventors Brian Holden, Amin Shokrollahi, and Anant Singh, entitled "Time-biased tolerance method and system for vector signaling codes for inter-chip communication and enhanced detector", hereinafter referred to as Holden 1;

[0010] The U.S. Provisional Patent Application No. 61 / 934,804, filed on February 2, 2014, with Ali Hormati and Amin Shokrollahi as inventors, entitled “Method for Evaluating Codes by ISI Comparison”, hereinafter referred to as Hormati 1;

[0011] The U.S. provisional patent application, entitled "Multipoint Data Transmission," was filed on July 21, 2014, with application number 62 / 026,860 and an application date of July 21, 2014. The inventors are Ali Hormati and Amin Shokrollahi. The application is referred to as "Hormati2."

[0012] The U.S. patent application with application number 15 / 194,497, filed on June 27, 2016, and inventors Ali Hormati, Armin Tajalli, and Amin Shokrollahi, entitled “Method and Apparatus for High-Speed ​​Inter-Chip Communication”, hereinafter referred to as Hormati 3;

[0013] The U.S. patent application with application number 15 / 802,365, filed on November 2, 2017, and inventors Ali Hormati and Armin Tajalli, entitled "Clock Data Recovery for a Multichannel Data Receiver", hereinafter referred to as "Hormati 4";

[0014] The U.S. Provisional Patent Application No. 61 / 934,807, filed on February 2, 2014, with Amin Shokrollahi as the inventor, entitled “High Pin Utilization Vector Signaling Code and Its Application in Inter-Chip Communication and Storage”, hereinafter referred to as “Shokrollahi 1”;

[0015] The U.S. provisional patent application, entitled "Low Receiver Complexity Vector Signaling Code", with application number 61 / 839,360, filed on June 23, 2013, and inventor Amin Shokrollahi, is referred to as "Shokrollahi 2".

[0016] The U.S. provisional patent application, entitled "Clock Embedded Vector Signaling Code", with application number 61 / 946,574 and application date of February 28, 2014, is authored by Amin Shokrollahi, Brian Holden, and Richard Simpson and is referred to as "Shokrollahi 3".

[0017] The U.S. provisional patent application, entitled "High Signal-to-Noise Ratio Characteristic Vector Signaling Code", with application number 62 / 015,172 and application date of July 10, 2014, is authored by Amin Shokrollahi and Roger Ulrich and is referred to as "Shokrollahi 4".

[0018] The U.S. patent application with application number 13 / 895,206, filed on May 15, 2013, and inventors Roger Ulrich and Peter Hunt, entitled “Circuit for Efficient Detection of Vector Signaling Codes for Inter-Chip Communication by Difference Sum”, hereinafter referred to as “Ulrich 1”;

[0019] "Low Inter-symbol Interference Design Techniques for Conventional Interconnect Systems with Data Rates Above 20 Gbps", Wendemagegnehu T. Beyene and Amir Amirkhany, IEEE Transactions on Advanced Packaging, Vol. 31, No. 4, pp. 731-740, November 2008, hereinafter referred to as "Beyene". Technical Field

[0020] This invention relates generally to the field of communications, and more particularly to signal transmission capable of conveying information and the detection of such signals in wired communications. Background Technology

[0021] One objective of a communication system is to transmit information from one physical location to another. Generally, the goal of such information transmission is to be reliable, fast, and consume minimal resources. Broadly speaking, information transmission methods can be divided into "baseband" methods, where the physical communication channel is dedicated to only one transmission method, and "wideband" methods, which divide the physical communication channel into independent frequency channels available for two or more transmission methods in the frequency domain.

[0022] Baseband methods can be further classified according to the physical medium. A common information transmission medium is a serial communication link, which can be based on a single wired circuit that uses the ground or other commonly used reference as a comparison object, or on multiple such circuits that use the ground or other commonly used reference as a comparison object, or on multiple such circuits that use each other as comparison objects. A common example of the latter uses differential signaling (DS). Differential signaling works by transmitting a signal in one line and transmitting the opposite signal in a paired line. The information of this signal is represented by the difference between the two lines, rather than its absolute value relative to the ground or other fixed reference.

[0023] Parallel data transmission is also a common method to increase interconnect bandwidth, with the number of buses increasing from 16 or fewer to 32, 64, and more. Since crosstalk and noise generated on parallel signal lines can lead to reception errors, error detection is improved by adding parity checks, and signal anomalies are addressed through active bus termination methods. However, such wide data transmission widths inevitably lead to data skew, thus becoming a limiting factor for increasing bus data transmission throughput. Developed alternatives employ narrower bus widths and faster operating clock speeds, with significant effort focused on optimizing the transmission line characteristics of the interconnect medium through impedance-controlled connectors and microstrip wiring. Even so, path imperfections are unavoidable, necessitating the use of active equalization and inter-symbol interference (ISI) cancellation techniques. These techniques include active pre-emphasis compensation at the transmitter end and continuous-time linear equalization (CTLE) and decision feedback equalization (DFE) at the receiver end. All of these can increase the complexity and power consumption of the communication interface.

[0024] Compared to differential signaling, several signaling methods can increase pin utilization while maintaining the same beneficial characteristics. One such method is vector signaling. With vector signaling, multiple signals across multiple lines can be treated as a whole while maintaining the independence of each signal. Therefore, vector signaling codes can combine the robustness of single-circuit differential signaling with the high data throughput achieved by parallel data transmission due to a high number of lines. Each signal in the overall signal carrying the vector signaling codeword is called a component, and the number of lines is called the "dimensionality" (sometimes also called a "vector") of the codeword. In binary vector signaling, each component (or "symbol") of the vector takes one of two possible values. In non-binary vector signaling, each symbol takes a value selected from a set of two or more possible values. The set of possible values ​​for vector symbols is called the "symbol set" of the vector signaling code. In this paper, the vector signaling code is a set C consisting of vectors of length N, called codewords. Any suitable subset of a vector signaling code is a "subcode" of that code. Such a subcode can itself be a vector signaling code. In practice, the coordinates of the codewords are bounded coordinates and represented using real numbers between -1 and 1. The ratio between the binary logarithm of size C and the length N is called the pin utilization of the vector signaling code. When the sum of the coordinates of all codewords in a vector signaling code is always zero, the vector signaling code is called a "balanced" code. Other examples of vector signaling methods can be found in Cronie 1, Cronie 2, Cronie 3, Cronie 4, Fox 1, Fox 2, Fox 3, Holden 1, Shokrollahi 1, Shokrollahi 2, and Hormati I.

[0025] As described above, the broadband signaling method divides the available information transmission medium in the frequency domain to generate two or more frequency domain "channels." These channels can then transmit information in a manner similar to baseband circuits, using known carrier modulation methods that convert baseband information into frequency domain channel signals. Because such channels can be independently controlled in terms of amplitude, modulation scheme, and information coding scheme, this set of channels can adapt to a wide range of information transmission medium characteristics, including signal loss, distortion, and noise variations with time and frequency.

[0026] Asymmetric Digital Subscriber Line (ADSL) is a broadband signaling method widely used to transmit digital data over traditional copper telephone circuits. In ADSL, each of the hundreds of frequency-domain channels is independently configured for amplitude, modulation method, and digital carrier capability based on the specific noise and loss characteristics of the copper circuit used for transmission. Summary of the Invention

[0027] In the methods and systems described herein: a set of carrier modulation symbols of carrier modulation codewords is acquired, each carrier modulation symbol being received via a corresponding line among multiple lines of a multi-line bus; each of the carrier modulation symbols in the set is applied to a corresponding transistor in a set of transistors, each transistor in the set being connected to a corresponding output node in a pair of output nodes according to an element of a sub-channel vector; and demodulated sub-channel data output is generated in response to a linear combination of the set of carrier modulation symbols as a differential voltage formed on a pair of output nodes, based on a demodulated signal operating at a frequency recovered from the carrier modulation symbols.

[0028] This paper describes the transmission of digital information over multiple lines by integrating baseband and broadband technologies. In the examples presented, a four-line communication channel with an attenuation of 35 dB at 37.5 GHz is used as the general transmission medium for the systems and methods described herein. In one embodiment, two frequency-based channels are generated in the transmission medium, each channel utilizing vector signaling codes and dual binary encoding to transmit multiple sets of data bits in groups of three on the four lines at an effective rate of 56 Gb / s per line. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating an implementation of the receiver.

[0030] Figure 2 This is a schematic diagram of a circuit implementation for detecting an ENRZ subchannel.

[0031] Figure 3 This is a schematic diagram of another circuit implementation for detecting an ENRZ subchannel.

[0032] Figure 4 A schematic diagram of a circuit implementation for detecting a carrier-modulated ENRZ subchannel.

[0033] Figure 5 A schematic diagram of another circuit implementation for detecting a carrier-modulated ENRZ subchannel.

[0034] Figure 6 This is a schematic diagram of another circuit implementation for detecting a carrier-modulated ENRZ subchannel.

[0035] Figure 7 This is a waveform diagram of carrier modulation data encoding and decoding operations.

[0036] Figure 8A and Figure 8B The diagram shows an alternative implementation for receiver clock generation.

[0037] Figure 9 This is a flowchart of a method according to some implementation methods. Detailed Implementation

[0038] Interconnectivity has always been a limiting factor in the design of large-scale digital systems. Whether at the module level interconnected by the motherboard or at the functional subsystem level interconnected within large printed circuit boards, the need for error-free, reliable, high-speed digital interconnectivity has always put existing technologies to a severe test.

[0039] The system and method described herein enable robust and reliable data transmission between at least one transmitting device and at least one receiving device at a data rate of at least 50 Gb / s on each interconnect line. This is achieved by employing a system with… Figure 1 The illustrated channel model shows the frequency and time domain characteristics. It will be readily understood by those skilled in the art that such a transmission channel is incompatible with conventional communication signaling methods such as simple NRZ signaling, which, for example, has a Nyquist frequency of 56 GHz at 112 Gb / s, and therefore corresponds to an inherent attenuation level of 46 dB in the physical transmission channel of this invention.

[0040] The data rate of this invention also strains the data processing capabilities of the integrated circuits within the attached transmitting and receiving devices. Therefore, high-speed data processing in such devices is configured to be distributed across multiple parallel processing "stages." For example, instead of processing data at a rate of 100 Gb / s (i.e., only 10 picoseconds between bits) along a single data path, the same data stream can be distributed across 16 processing stages, resulting in a more reasonable processing time of 160 picoseconds / bit per stage. However, this increased processing time comes at the cost of significantly increased complexity due to the additional processing elements. Furthermore, this distributed processing leads to a greater delay before a given digital bit result becomes usable, thus limiting the ability to predict subsequent bit results from that result, which is precisely the basis for implementing the Decision Feedback Equalization (DFE) method.

[0041] Furthermore, the increased data transmission rate also presents physical challenges due to the shortening of the propagating signal wavelength on interconnect devices. For example, at 56 GHz, the propagating signal wavelength on a printed circuit microstrip line is approximately 4 millimeters. Therefore, even periodic anomalies that are only a fraction of the wavelength (or even the texture of the impregnated fabric containing the circuit board) can significantly interfere with signal integrity, highlighting the importance of existing equalization and compensation methods.

[0042] Information encoding using the Adamant transformation matrix

[0043] As described in *Cronie 1*, the Hadamard transformation matrix (also known as the Walsh-Hadamard transformation matrix) is a square matrix consisting of +1 and -1, with all rows and columns being mutually orthogonal. The Hadamard matrix is ​​known for its various 2N-sized forms and other chosen sizes. This paper specifically uses an encoder employing a 4×4 Hadamard matrix as an example.

[0044] The 4th order Hadamard matrix used in the example in this article is:

[0045]

[0046] By multiplying the three information bits A, B, and C by the second, third, and fourth rows of the Hadamard matrix H4, these information bits can be encoded to obtain four output values, hereinafter referred to as "symbol values". Conventionally, these results are scaled by an appropriate constant factor so that the symbol value is within the range of +1 to -1. It is worth noting that the first row of H4 corresponds to common-mode signaling, which is not used in this application. Instead, the remaining three vectors are used to encode bits A, B, and C into output values ​​W, X, Y, and Z, respectively. These vectors are also called the "modulus" or "subchannel" of the Hadamard code. Since the encoded output value simultaneously carries information obtained from encoding A, B, and C, the output value is the result of superposition or summation of the modulus, i.e., the sum of the subchannel code vectors of the vector signaling code.

[0047] Those skilled in the art will notice that all possible values ​​obtained after encoding A, B, and C in this manner are modulo sums of W, X, Y, and Z. These values ​​are all balanced, meaning their sum is always zero. If the modulo sum of W, X, Y, and Z is scaled so that its maximum absolute value is 1 (i.e., for ease of description, the signal is in the range of +1 to -1), it should be noted that all realizable values ​​are permutations of the vectors (+1, -1 / 3, -1 / 3, -1 / 3) or (-1, 1 / 3, 1 / 3, 1 / 3). These permutations are called the codewords of the vector signaling code H4. In the following text, this H4 code is referred to as the overall NRZ (ENRZ) and is used as a representative example of the vector signaling code in subsequent examples, but this does not constitute any limitation.

[0048] ENRZ

[0049] Hormati I points out that ENRZ has the best inter-symbol interference (ISI) characteristics, while Holden I and Ulrich I indicate that it can perform efficient detection. As mentioned above, ENRZ encodes three binary data bits into four-symbol codewords for transmission, for example, on four lines of the transmission medium. When ENRZ signaling is used on the four lines of the channel of this invention, the achievable data transmission rate is only a signaling rate of 75 gigabits per second, equivalent to a rate of 112 Gbps for each pair of lines in two pairs of transmission channels.

[0050] Double binary encoding

[0051] Bibinary encoding is a known solution in the art, in which the spectrum of the transmitted data is shaped and constrained by processing consecutive bits in a serially transmitted data stream. It is well known that inter-symbol interference (ISI), caused by disturbances in the transmission medium, can interfere with the amplitude of the received signal within a unit interval due to the residual energy of the previous unit interval. For example, back pulse reflections caused by transmission medium disturbances can weaken the received signal due to the influence of previously transmitted signals. Therefore, a transmitter aware of this effect can combine the current transmitted signal value with the previous transmitted signal value to attempt to prepare for or pre-compensate for this ISI effect. Thus, the use of partial response codes such as bibinary encoding is often described as a specific form of pre-equalization filtering, designed to produce constructive rather than merely literal ISI data encoding.

[0052] As described in Beyene, other known partial response codes also have similar ISI management capabilities.

[0053] For reference purposes, Table 1 lists the characteristic equations describing such coding or filtering methods.

[0054] Partial Response System Characteristic equation Double binary <![CDATA[x n +x n-1 ]]> dual code <![CDATA[x n -x n-1 ]]> Improved binary <![CDATA[x n -x n-2 ]]> Category 2 <![CDATA[x n +2x n-1 +x n-2 ]]>

[0055] Table 1

[0056] Unless otherwise stated, the bibinary processing implemented in this application is assumed to be the addition of the signal transmitted in the current unit interval with the signal transmitted in the previous unit interval after scaling by a factor of 0.5. Optionally, a transmit low-pass filter may also be used to further control the transmit spectrum. In other embodiments, ISI control coding is combined with Hadamard coding in any way, wherein the ISI control coding is any of the bibinary, improved bibinary, dual-code, Class 2, and Hamming filtering methods described below. In such embodiments, the ISI control coding may also be described as being implemented by a partial response encoder employing any of the above-described partial response coding or filtering methods.

[0057] With a thorough understanding of the communication channel characteristics, the transmitter's ISI control operation can be configured so that the receiver does not need to perform an explicit reverse operation, where the channel characteristics themselves effectively serve to perform the reverse operation. In other embodiments, for example, the ternary signal generated from the bibinary encoding of the binary data can be explicitly detected first, followed by an explicit bibinary-to-binary decoding operation. Alternatively, this type of transmitter ISI compensation effect can also be effectively achieved when using common ISI cancellation techniques such as DFE in the receiver. Since the illustrated receivers in this document all employ DFE, further receiver bibinary (or other partial response code) processing is not shown.

[0058] Channelization

[0059] Historically, the development of technologies to provide high-speed digital services over traditional copper-line infrastructure for telephone networks has revealed physical transmission channel limitations, and these limitations have been addressed at data rates far lower than current rates. At the 3Mb data rates required for DSL, the propagating signal wavelength is hundreds of meters, which is closely related to the typical spacing between line ends, connections, and areas of insulation damage found in the field. Therefore, for a typical copper telephone signal path, without frequency response compensation, numerous notches and ramps caused by reflections from these anomalies, lossy attenuation due to deterioration in conductor and insulation quality, and intrusive noise from sources such as AM radio transmitters will be present.

[0060] To address the aforementioned traditional transmission problems, multi-channel frequency domain channelization is ultimately employed to limit their impact. In a commonly used Asymmetric Digital Subscriber Line (ADSL) solution, for example, approximately 1 MHz of available transmission medium bandwidth is divided into 4.3125 kHz channels. Subsequently, the attenuation and signal-to-noise ratio of each channel are independently tested, and based on the test results, different data throughput rates are allocated to each channel. In this way, channel frequencies encountering frequency response notches or large external noise sources can be abandoned, while other channels without such problems can be used at full capacity. However, the generation and detection of such high-channel-number protocols rely on the availability of low-cost digital signal processing solutions, and the performance of this technology varies by a factor of 10 over time, while the data rate of this application increases by a factor of approximately 100,000.

[0061] Therefore, while the aforementioned channel attenuation problem suggests that broadband methods may be more beneficial, conventional high-channel-number implementations known in the art are incompatible with the desired data rate. Therefore, a novel method specifically designed for high-speed processing is described below.

[0062] Broadband dual binary ENRZ

[0063] Hormati 3 provides several embodiments of combining ENRZ signaling with additional serial transmission coding such as bibinary signals using multiple frequency domain channels. These embodiments and technical contents are incorporated herein by reference in their entirety for all purposes.

[0064] Figure 1 This is a block diagram illustrating another receiver implementation for explaining the following examples. Figure 1 In the receiver, four communication lines w0 to w3 carry a mixture of baseband and broadband signals. The first frequency channel is the baseband channel, which is similar to typical line communication channels known in the art. The second frequency channel, referred to herein as the "carrier channel," "carrier modulation channel," or "broadband channel," consists of ENRZ+ dual binary signaling modulated on a sinusoidal carrier, and is selected to minimize the frequency overlap between the spectral components of the baseband channel and the carrier channel.

[0065] Consistent with Hormati 3, the carrier frequency is assumed to be 37.5 GHz. Both the baseband channel and the carrier channel operate at a signaling rate of 37.5 gigabits per second. The first three data bit groups are transmitted via four lines of the baseband channel, while the second three data bit groups are transmitted via the same four lines of the carrier channel.

[0066] In other known implementations, the baseband signaling rate differs from the carrier signaling rate and / or from the carrier frequency. However, generally speaking, it is more advantageous to maintain this relationship as a fixed one (typically expressed as a ratio of small integer values, such as 1:1:1 in the example above). As an example of such advantages, the receiver implementation can then derive and maintain a single local oscillator clock from a corresponding received signal, and then obtain other desired receive clocks from the local oscillator clock using known phase-locked or delay-locked methods.

[0067] Filters 110 and 115 separate the received signal into a wideband component containing a set of carrier modulation symbols with carrier modulation codewords and a baseband component containing a set of baseband symbols with baseband codewords. For simplicity of description, Figure 1The diagram shows the generation of carrier modulation symbols by a high-pass filter 110 and baseband symbols by a low-pass filter 115. However, in practical applications, band-pass or band-stop filters can also be used. After the baseband signal is output from filter 115, the multi-input comparator (MIC) 130, as described in Holden 1 and Ulrich 1, performs a weighted linear combination of the individual line signals represented as baseband symbols to form an output for detecting the data outputs of each subchannel of the ENRZ code. Furthermore, MIC 130 can perform slicing, time sampling, or amplitude measurement operations on each subchannel data output under the control of the sampling clock provided by the clock / data recovery (CDR) subsystem 165.

[0068] like Figure 1 As shown, for CDR 165, different system considerations may include different synchronization sources. In the first embodiment (1), the data sampling clock is obtained from the data transitions of the detected subchannel data itself, as described in Hormati 4. In the second embodiment (2), the subchannels of the ENRZ baseband signal are provided with synchronization sources either by dedicating them to a periodic clock signal or by increasing the transition density of the data stream, to ensure sufficient edge information to maintain clock synchronization. The third embodiment (3) uses a different transmit clock or synchronization signal than the ENRZ data to achieve synchronization of the CDR subsystem, which can be transmitted from the transmitter to the receiver via a pair of dedicated differential lines.

[0069] Consistent with the baseband data path, the wideband data detection path includes the functions of the MIC demodulation circuit 120, the sampler 127, and the CDR 150. However, since the wideband coded data is modulated onto the carrier wave, data detection can only be achieved by processing the carrier signal simultaneously.

[0070] As is common knowledge in the field, for carrier-modulated signals, they can be restored to baseband (heterodyne receiver) by mixing them with, for example, a demodulated signal provided by a local oscillator, or in data detection, timing not only relative to the data sampling frequency but also relative to the carrier frequency (synchronization detector). Figure 1In this context, such operations are performed by the MIC demodulation circuit 120, which will be described below. The demodulated signal can be generated by a frequency multiplier 160, which, in this non-limiting example, obtains the reference carrier frequency from the sampling clock signal generated by the baseband CDR 165. The detected sub-channel information is processed by a low-pass filter 125 to remove residual artifacts from the heterodyne or synchronization detection operations of the MIC demodulation circuit 120. The carrier CDR subsystem 150 generates a data sampling clock suitable for demodulating the wideband channel data sampling 127. Depending on the specific demodulation method used by 120, the demodulation clock manager 140 can provide a demodulated signal such as that generated by the frequency multiplier 160, a data sampling clock such as that provided by 150, or a combined clock for demodulation.

[0071] In alternative implementations: the receiver clock can be synchronized with the carrier and an additional sampling clock can be obtained from the resulting reference source; or the receiver clock can be synchronized with the detected data stream and an additional sampling clock can be obtained from the resulting reference source; or both methods can be used in combination. During synchronization, a local voltage-controlled oscillator (VCO) or voltage-controlled delay element that generates a local clock signal can be used. Alternatively, during synchronization, the phase interpolator or adjustable delay element can be configured based on the phase comparator results to correct the phase of the local clock signal.

[0072] Synchronous switching multi-input demodulation comparator

[0073] Figure 2 This is a schematic diagram of one implementation of a linear-mode ENRZ detector. Input signals w0, w1, w2, and w3 are received line signals carrying baseband symbols after low-pass filtering (not shown), and are connected to transistors according to specific sub-channels of the ENRZ code. That is, a positive value of the sub-channel vector indicates that the corresponding line is connected to a transistor that contributes positively to the output, while a negative value indicates that the corresponding line is connected to a transistor that contributes negatively to the output. Therefore, in Figure 2 In this circuit, each line is connected to a transistor according to the sub-channel vector [1, -1, 1, -1], and the differential outputs QH and QL correspond to the linear combination results generated by the following calculation:

[0074] Q = (w0 + w2) - (w1 + w3) (Equation 2)

[0075] As described in "Holden 1", Equation 2, with three examples of different permutations and combinations of input signals, can effectively detect the three sub-channel data outputs of the ENRZ code. Therefore... Figure 1 The baseband detector 130 can be derived from Figure 2 The circuit consists of three examples.

[0076] Figure 3To implement Figure 2 This document describes an implementation of a synchronously switched demodulation MIC circuit (also referred to as the "MIC demodulation circuit") using the same linear combination of MICs. The demodulation signal CK_d, operating at the carrier frequency, is used to select the operation of this MIC demodulation circuit, thereby achieving synchronous detection of the carrier modulation symbols of the carrier modulation codeword. In the actual implementation, CK_d is phase-locked to... Figure 1 The carrier frequency provided by frequency multiplier 160. For example... Figure 3 As shown, the MIC demodulation circuit acquires a set of carrier modulation symbols from the carrier modulation codeword. Each carrier modulation symbol can be received via a corresponding line of multiple lines on a multi-line bus and can be high-pass (or band-pass) filtered before being applied to the corresponding transistor in the illustrated set of transistors. Each transistor is connected to the corresponding output node in a pair of output nodes according to the elements of the sub-channel vector. For example, in Figure 3 In the example, a set of transistors connected to lines [w0, w1, w2, w3] is connected to a pair of output nodes QL and QH according to the sub-channel vector [1, -1, 1, -1], and the sub-channel vector corresponds to the second row of the H4 Hadamard matrix given in Equation 1. The sets of transistors constituting the other two sub-channels of the MIC are connected to the respective pairs of output nodes according to other sub-channel vectors in the H4 Hadamard matrix that are orthogonal to the [1, -1, 1, -1] sub-channel vector. In some other embodiments, each transistor in the set of transistors can apply a corresponding amplitude weight to the carrier modulation symbol according to the sub-channel vector. Equation 3 below is a specific matrix containing sub-channel vectors with varying amplitudes. The amplitude weights can be applied, for example, according to the relative size of the transistors, the amplitude of the current source, and / or the number of transistors of similar size connected in parallel. The conductivity of the set of transistors is switched synchronously and controlled according to the demodulated signal CK_d operating at the frequency recovered from the carrier modulation symbol, in response to the generation of demodulated sub-channel data output, which is a linear combination of the set of carrier modulation symbols according to Equation 2. This linear combination forms a differential voltage across the pair of output nodes.

[0077]

[0078] Figure 4Another implementation of the MIC demodulation ENRZ detector. The MIC demodulation circuit operates in dynamic mode, charging the node capacitances of the pair of output nodes QH and QL when the sampling clock CK (operating at the symbol frequency) is low, and selectively providing a discharge path to ground through the set of input transistors when CK is high. When the two nodes discharge, output nodes QH and QL generate differential output signals corresponding to the result of Equation 2. In this implementation, the sampling clock also serves as the demodulation signal when demodulating the carrier modulation symbols and sampling the linear combination according to the sampling clock. This implementation can be carried out when the sampling clock frequency and the carrier frequency are equal. In some alternative implementations, as shown, synchronization switching can be achieved through the demodulation signal CK_d to periodically interrupt or select the detector's dynamic operation at the carrier frequency, thereby achieving direct detection of the carrier modulation signal. In some such implementations, the demodulation signal CK_d can be an integer multiple of the baseband symbol baud rate of the sampling clock CK, such as 2 times, 3 times, etc. Alternatively, the frequency of the demodulation signal can be a fraction of the sampling clock frequency.

[0079] Figure 5 for Figure 3 A corresponding full-wave version of the half-wave synchronization detector. Consistent with the half-wave detector, the synchronization switching ENRZ detection is gated by the demodulated signal CK_d+ and its phase-locked-to-carrier frequency inverse signal (or complementary signal) CK_d-. In an alternative implementation, each differential transistor pair can be composed of an NMOS device and a PMOS device receiving the same demodulated signal CK_d+. In this full-wave circuit version, the contribution of each input to the pair of output nodes is alternately guided to the inverted and non-inverted result outputs at half-clock cycles, effectively doubling the output signal and significantly reducing the output filtering requirements. This guidance is implemented by multiple differential transistor pairs connected to the pair of output nodes, such that each transistor in the group is connected to the corresponding output node according to the demodulated signal and its inverse signal. As shown, the group of transistors receiving the carrier modulation symbol is alternately connected between the pair of output nodes via corresponding differential transistor pairs. For each sub-channel MIC, the differential transistor pairs can be connected according to the corresponding sub-channel vectors of multiple mutually orthogonal sub-channel vectors. Figure 5 In this configuration, the differential transistor pair is connected to the pair of output nodes according to the sub-channel vector [1, -1, 1, -1].

[0080] Figure 6 As shown Figure 4A corresponding discrete full-wave version of the discrete half-wave dynamic synchronization detector. The sampling clock CK controls the dynamic charging and discharging operation of the circuit, while the demodulated signal CK_d+ and its complementary signal CK_d- are gated to synchronize the detection with the carrier frequency in the manner described above.

[0081] exist Figure 4 and Figure 6 In the example, the timing of the two clock signals is coordinated to be compatible with the operation of the dynamic circuit. Specifically, in Figure 4 In this process, a pre-charge operation corresponding to a low level of clock CK can be performed before each discharge or integration cycle corresponding to a high level of clock CK_d and CK. Figure 6 In this implementation, the entire cycle of clock CK (i.e., the precharge and discharge cycles) can correspond to half a cycle of CK_d. Alternatively, the integration time of the circuit can be long enough to span two or more half cycles of CK_d. In another alternative implementation, the demodulated signal CK_d+ / - can be an integer multiple of CK. In such implementations, multiple CK_d cycles can essentially gate the signal into or out of the integration cycle. In such implementations, the pair of output nodes are precharged according to the sampling clock, and the pair of output nodes discharges only when the polarity of the carrier modulation symbol at the transistor input is correct. In a full-wave implementation, the pair of output nodes continuously discharges, but simultaneously, as the carrier modulation symbol alternates according to the modulation content, the set of transistors receiving the carrier modulation symbol alternately disconnects from the pair of output nodes according to the demodulated signal.

[0082] The operation of half-wave and full-wave synchronous detectors is shown in Figure 7 Waveform. As described in *Hormati 3*, the transmitter generates a carrier-modulated signal by multiplying the transmitted data by a carrier frequency clock. The receiver locally generates a carrier frequency demodulation clock and combines this demodulation clock with the received signal using a synchronization detector to generate a detectable received data signal. The carrier-modulated signal is encoded into carrier-modulated symbols of carrier-modulated codewords and then transmitted via a multi-line bus.

[0083] Figure 7 The Return-to-Zero (RTZ) waveform shown is an example of the output of a half-wave detector circuit, while the full-wave waveform is an example of the output of a full-wave detector circuit. In some embodiments, both outputs are low-pass filtered to aid in reconstructing the detected waveform and eliminating spurious signal artifacts. Subsequently, as indicated by the vertical hash markers in the figure, each waveform is sampled at the center of the data interval.

[0084] Figure 8A To use existing multi-PLL methods as... Figure 1The block diagram shown illustrates how to generate the required receive clock in various implementations. Here, a correctly timed sampling clock is generated using information obtained directly or indirectly from the received data (which may contain clocks transmitted via dedicated lines, dedicated sub-channels, and / or enhanced edge transition densities, eye diagram widths, or edge measurement results) to achieve optimal sampling of the detected baseband data. This method is commonly referred to as clock data alignment or clock data recovery (CDA or CDR). In a common implementation, a PLL structure is used to generate a local clock signal with the desired characteristics by controlling a voltage-controlled oscillator (VCO) with a phase detector.

[0085] In addition, a local clock signal aligned with the carrier frequency of the received carrier demodulated data and a sampling clock suitable for optimal sampling of the carrier demodulated data are generated by an independent PLL.

[0086] In an alternative implementation, one or more of the desired local clock signals may be obtained from another clock signal. Figure 8B The image shows a local clock signal generated by a PLL, which is locked to a reference signal derived from baseband data. As a representative example, this operation can be facilitated by baseband data containing a dedicated clock signal or by baseband data enhanced with a guaranteed edge transition density. This well-controlled and stable local clock can then be used to generate other local clock signals, which can be achieved through well-known frequency division or multiplication (e.g., using...). Figure 1 The demodulated signal can be generated by a frequency multiplier 160, or by adjusting the relative phase of the resulting clock using only a phase interpolator or an adjustable delay element (such as an offset correction element 140). For example, the local clock signal derived from the baseband data may have the same frequency as the carrier frequency, and thus a demodulated signal can be generated by phase adjustment using a phase detector and a phase interpolator. Furthermore, if the data rate of the demodulated subchannel data is equal to the data rate of the baseband data, the generation of the demodulated subchannel data sampling clock can be driven by the clock derived from the baseband data, and a corresponding phase shift operation can be performed. In some embodiments where the carrier frequency differs from the data rate of the baseband data, a demodulated signal with the carrier frequency (and...) can be generated by multiplying / dividing the sampling clock derived from the baseband data (not shown). Figure 1 (The situation is consistent with that shown). Subsequently, the demodulated signal can be aligned with the carrier modulation symbol by performing phase detection or phase shifting operations. Figure 8B The diagram shows two clocks obtained in this manner, each with phase adjustment operations performed using a corresponding phase detector and phase interpolator. In some embodiments, the purpose of this phase adjustment is to compensate for signal path differences in the baseband / carrier signal as it undergoes different filtering processes.

[0087] In some implementations, a hybrid clock generation implementation may also be used, which includes an implementation where a second local clock is generated from a first local clock generated as described above using an auxiliary or subordinate PLL. In such a system architecture, the auxiliary PLL may have different locking characteristics than the master PLL to allow independent optimization of characteristics such as lock-in time, self-oscillation drift, and jitter.

[0088] Figure 9 The diagram shows a flowchart of method 900 according to some embodiments. As shown, method 900 includes acquiring a set of carrier modulation symbols (902) of carrier modulation codewords, each carrier modulation symbol being received via a corresponding line of a multi-line bus. Each carrier modulation symbol in the set is applied (904) to a corresponding transistor in a set of transistors, the set of transistors being connected to a pair of output nodes according to a sub-channel vector of a plurality of sub-channel vectors. After recovering (906) the demodulated signal CK_d from the set of carrier modulation symbols, the set of carrier modulation symbols is linearly combined by controlling the conductivity of the set of transistors according to the demodulated signal CK_d to generate (908) demodulated sub-channel data output as differential voltages on the pair of output nodes.

[0089] In some implementations, such as Figure 3 and Figure 4 As shown, controlling the conductivity of the set of transistors includes selectively enabling a current source based on the demodulation signal CKd. In such embodiments, as Figure 7 As shown, the demodulation subchannel data output is a return-to-zero (RTZ) signal.

[0090] In some embodiments, controlling the conductivity includes alternately connecting each transistor in the set of transistors between the pair of output nodes according to the demodulated signal. In such embodiments, each transistor circuit is alternately connected between the pair of output nodes via a corresponding differential transistor pair connected to the pair of output nodes according to the sub-channel vector. In some embodiments, the corresponding differential transistor pair receives the demodulated signal and a complementary signal of the demodulated signal, and is composed of transistors of the same type (e.g., NMOS or PMOS only), while in other embodiments, the differential transistor pair may also include NMOS and PMOS transistors that simultaneously receive the demodulated signal CK_d. This configuration is shown in Figure 5 and Figure 6 The differential pair of the received demodulated signal CK_d+ and its complementary signal CK_d- causes the corresponding transistors connected to the carrier modulation symbol to be alternately connected between the two output nodes according to the polarity of the carrier modulation symbol.

[0091] In some embodiments, the conductivity of each transistor in the set of transistors is further controlled by the sign value of the applied carrier modulation symbol. In such embodiments, the amount of current flowing through each transistor is proportional to the sign value applied to each transistor. In one specific embodiment, the signal amplitude is as follows:

[0092] Center voltage 500mV;

[0093] 500 + 180 = 680mV(+1)

[0094] 500-60=440mV(-1 / 3)

[0095] 500-60=440mV(-1 / 3)

[0096] 500-60=440mV(-1 / 3)

[0097] The sign for amplitude "1" indicates a deviation of 180mV from the center voltage of 500mV, while the sign for amplitude "1 / 3" indicates a deviation of 60mV from the center voltage of 500mV.

[0098] In some embodiments, the method further includes pre-charging the pair of output nodes in response to a sampling clock, wherein the conductivity of the set of transistors is also controlled according to the sampling clock. This type of embodiment is the aforementioned "discrete" or "dynamic" MIC demodulation circuit.

[0099] In some embodiments, the differential voltage across the pair of output nodes is formed by allowing current to flow through an impedance element connected to the pair of output nodes. In some embodiments, the impedance element may be a resistor connected between a power source and the pair of output nodes, with the pair of output nodes used to control the voltage drop across the resistor. The differential current flowing through the resistor forms a differential voltage across the pair of output nodes.

[0100] In some implementations, the method further includes low-pass filtering of the demodulated subchannel data output.

[0101] In some implementations, obtaining the set of carrier modulation symbols includes performing high-pass filtering on the superimposed codeword, wherein the superimposed codeword contains a set of carrier modulation symbols of the carrier modulation codeword and a set of baseband symbols of the baseband codeword.

[0102] In some implementations, the subchannel vectors are a subset of a plurality of mutually orthogonal subchannel vectors that form rows of an orthogonal matrix. In some such implementations, the orthogonal matrix is ​​an Hadamard matrix.

[0103] In some implementations, the frequency of the demodulated signal is equal to the frequency of the associated sampling clock of the data stream baud rate. In alternative implementations, the frequency of the demodulated signal is different from the sampling clock frequency. In some such implementations, the demodulated signal can be an integer multiple of the sampling clock and can initiate multiple discharge cycles within a single unit interval. Alternatively, the demodulated signal can be a fraction of the sampling clock. In such implementations, the sampling clock can initiate multiple precharge / discharge cycles within half a cycle of the demodulated signal. In some implementations, the demodulated signal is generated by multiplying the sampling clock using a frequency multiplier. Alternatively, the demodulated signal can be generated by dividing the sampling clock using a frequency divider.

Claims

1. A method for combining multiple input comparator demodulation circuits, characterized by, include: The line signal is received by a plurality of combined multi-input comparator demodulation circuits, wherein each combined multi-input comparator demodulation circuit receives the line signal according to a corresponding input arrangement related to a corresponding sub-channel vector among a plurality of mutually orthogonal sub-channel vectors, wherein the line signal comprises a superposition of a set of baseband symbols and a set of carrier modulation symbols; A set of line signals is combined according to the corresponding input arrangement to generate a set of baseband subchannel outputs; Acquire the phase-adjusted demodulated signal related to the set of carrier modulation symbols; and A set of demodulated subchannel outputs is generated, wherein each demodulated subchannel output is generated by combining a set of the line signals according to the corresponding input arrangement and by guiding the current between the inverted and non-inverted result outputs during alternating half-cycles of the phase-adjusted demodulated signals.

2. The method of claim 1, wherein, The baseband subchannel output is sampled using the baseband clock signal.

3. The method of claim 2, wherein, Also includes: By multiplying the baseband clock signal by frequency, a frequency equal to the carrier frequency related to the set of carrier modulation symbols is obtained, so as to obtain the phase-adjusted demodulated signal from the baseband clock signal.

4. The method of claim 2, wherein, Also includes: By dividing the baseband clock signal by frequency, a frequency equal to the carrier frequency related to the set of carrier modulation symbols is obtained, so as to obtain the phase-adjusted demodulated signal from the baseband clock signal.

5. The method of claim 2, wherein, The frequency of the baseband clock signal is equal to the carrier frequency associated with the set of carrier modulation symbols.

6. The method of claim 5, wherein, Also includes: The phase-adjusted demodulated signal is obtained by adjusting the phase of the baseband clock signal to align it with the set of carrier modulation symbols.

7. The method of claim 1, wherein, Generating each demodulated subchannel output includes forming a differential voltage at a pair of output nodes of the combined multi-input comparator demodulation circuit, wherein the differential voltage is generated by causing a differential current to flow through a pair of load resistors.

8. The method of claim 1, wherein, Generating each demodulation subchannel output includes: initializing a pair of output nodes with a preset charge amount according to the first cycle of the sampling clock, and generating a guided current through the initialized pair of output nodes in response to the second cycle of the sampling clock.

9. The method as described in claim 1, characterized in that, Also includes: Low-pass filtering is applied to the output of the set of demodulation sub-channels.

10. The method of claim 1, wherein, The mutually orthogonal subchannel vectors correspond to rows of the Adama matrix.

11. An apparatus for combining multiple input comparator demodulation circuits, comprising: include: A set of input transistors for receiving a line signal based on a corresponding input arrangement relating to a plurality of mutually orthogonal subchannel vectors, wherein the line signal comprises a superposition of a set of baseband symbols and a set of carrier modulation symbols; A demodulation circuit is configured to acquire a phase-adjusted demodulated signal associated with the set of carrier modulation symbols, combine a set of the line signals according to the input arrangement, and direct current between a pair of output nodes during alternating half-cycles of the phase-adjusted demodulated signal to generate demodulated subchannel data outputs at the pair of output nodes.

12. The apparatus of claim 11, wherein, It also includes a multi-input comparator for generating baseband subchannel outputs; and A sampler used to sample the output of the baseband subchannel using a baseband clock signal.

13. The apparatus of claim 12, wherein, It also includes a clock recovery circuit, wherein the clock recovery circuit is used to obtain a frequency equal to the carrier frequency related to the set of carrier modulation symbols by frequency multiplication of the baseband clock signal, so as to obtain the phase adjustment demodulation signal from the baseband clock signal.

14. The apparatus of claim 12, wherein, It also includes a clock recovery circuit, wherein the clock recovery circuit is used to obtain a frequency equal to the carrier frequency related to the set of carrier modulation symbols by frequency division of the baseband clock signal, so as to obtain the phase adjustment demodulation signal from the baseband clock signal.

15. The apparatus of claim 12, wherein, The frequency of the baseband clock signal is equal to the carrier frequency associated with the set of carrier modulation symbols.

16. The apparatus of claim 15, wherein, It also includes a clock recovery circuit, wherein the clock recovery circuit is used to obtain the phase-adjusted demodulated signal by adjusting the phase of the baseband clock signal to align it with the set of carrier modulation symbols.

17. The apparatus of claim 11, wherein, It also includes a load resistor connected to the pair of output nodes, wherein the demodulation subchannel output is generated by causing a differential current to flow through the load resistor according to the phase-adjusted demodulated signal.

18. The apparatus of claim 11, wherein, It also includes a precharge transistor and an integrating transistor, wherein the precharge transistor is used to initialize the pair of output nodes with a preset charge amount according to the first cycle of the sampling clock, and wherein the integrating transistor is used to generate a guided current through the initialized pair of output nodes in response to the second cycle of the sampling clock.

19. The apparatus of claim 11, wherein, It also includes a low-pass filter for low-pass filtering the demodulated subchannel data output.

20. The apparatus of claim 11, wherein, The mutually orthogonal subchannel vectors correspond to rows of the Adama matrix.

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