Persistent learning index system for dram-nvm hybrid memory

Abstract

The application provides a persistent learning type index system for DRAM-NVM hybrid memory, comprising: a model part: dividing data into sub-data sets, expressing each sub-data set by using a linear regression model, collecting maximum keys covered by each linear regression model, constructing a two-layer recursive model index architecture RMI, indexing local maximum keys, and retrieving a model address to which a target key belongs; a data part: comprising two types of data structures, namely a Node node class and a Buffer buffer block class; a structure type adjustment part: according to the data structure type, being divided into buffer block expansion, buffer block conversion, node conversion and node splitting, and being used for ensuring that the index always remains correct and efficient during the whole working load process. The application solves the problem that the index height is not limited, and ensures that the index can correctly and efficiently access data under any type of working load.

Description

TECHNICAL FIELD

[0001] The present application relates to the fields of machine learning, non-volatile memory, memory indexing, data structure design and algorithm design, in particular, to a persistent learning-oriented index system for DRAM-NVM hybrid memory. BACKGROUND

[0002] Contemporary data processing systems are facing growing demands for high performance services, while being pressed by the ever-expanding data set task size, making it difficult for traditional methods of building memory index with DRAM to achieve a balance between performance and cost configuration. The development of non-volatile memory technology and the concept of learning index provide a new solution to this problem. Non-volatile memory NVM is a new type of memory with large capacity, low latency, high bandwidth, non-volatility and byte addressing. The introduction of NVM to the index system not only relieves the pressure on DRAM to a great extent, but also gives the index data the ability to persist. Learning index learns data distribution, builds models and predicts the location of target data through machine learning algorithms. Learning index only needs to store model parameters, compared with traditional index, which saves a lot of memory space occupied by index structure.

[0003] Non-volatile memory and learned indexing have proposed new optimization schemes for memory indexing from the perspectives of hardware configuration and the index's own structure, respectively. A natural idea is to combine non-volatile memory with learned indexing so that they can leverage their respective strengths. Persistent learned indexing built on NVM simplifies indexing logic by learning data distribution, reducing server memory configuration costs. However, NVM still lags behind DRAM in performance, and building the index entirely in NVM will inevitably lead to a decline in indexing performance. Therefore, the design of learned index structures built using NVM needs to take into account the hardware characteristics of NVM. Currently, two research projects have completed the design and implementation of comprehensive learned index structures for NVM: PLIN and APEX. PLIN uses the OptimalPLR algorithm to learn data distribution. To minimize NVM block accesses, when new data is inserted into the index structure, if the model's predicted location is already in use, the new data is stored in another location within the same 256-byte NVM block. If the block containing the predicted location is full, the new data is inserted into an overflow tree structure. NVM blocks are unordered within the NVM block, but ordered between blocks. APEX's design stores both the model and data components in NVM. To minimize NVM writes, APEX uses a primary array and secondary buffer extension array with different priorities to accept newly inserted data. When new data is inserted into an APEX data node, APEX first searches for an empty location in the node's primary array. If the primary array is full, the data is inserted into the node's two secondary extension arrays.

[0004] Non-volatile memory and learned indexing bring new opportunities to memory indexing from the hardware environment and implementation logic levels, respectively. Non-volatile memory expands the system memory capacity while providing persistent protection for the index. However, the technical means of NVM devices dictate that the introduction of NVM will lead to a performance regression. While reducing the scale of the index structure, learned indexing breaks the limitation of traditional index structures that are agnostic to data distribution, and improves the performance of indexes under data distributions and workloads with certain characteristics. However, the performance of learned indexes varies greatly under different training algorithms and training set qualities, and machine learning models have potential problems such as high training overhead and overfitting, making the selection and organization of learned index models particularly important. Therefore, the work of building learned indexes using non-volatile memory requires consideration from many aspects.

[0005] Patent document CN112732725A (application number: CN202110088720.8) discloses a self-adaptive prefix tree construction method based on NVM hybrid memory, which constructs and maintains the full data and nodes in the NVM address space according to the global index data structure; allocate and maintain the new data and nodes in the DRAM address space according to the shortcut index data structure; when the DRAM address space occupancy reaches a certain proportion, trigger the migration thread to migrate the new data and nodes to the NVM address space, and reduce the DRAM address space storage.

[0006] Currently, only a few research works on building learning indexes using non-volatile memory focus more on the use of NVM devices, and the goal is to achieve a relatively objective index comprehensive performance level in a general scenario through optimization based on NVM. Most (such as APEX) or even all (such as PLIN) structures of this type of work are placed in NVM, which relies too much on NVM and does not fully utilize the advantages of DRAM. However, a test of the performance of persistent indexes has proved that it is desirable to return some of the index pressure to DRAM, or to construct auxiliary data structures that can improve performance at the cost of additional DRAM space. Based on this result, the invention proposal selects DRAM-NVM hybrid memory as the medium for building persistent learning indexes, and designs an adaptive heterogeneous memory allocation manager to provide greater flexibility for the work pre-configuration of the index.

[0007] In addition to the general scenario of index service, there are a large number of special scenarios in the real world, such as highly skewed work business scenarios where most data access is concentrated on a small part of the data (for example: in social media applications, the access frequency of information verification data for user login is much higher than the access frequency of pictures uploaded to personal space by users a year ago), when facing these special workloads, the existing work still uses the general method to complete the series of processes of data request, lacks targeted optimization, resulting in unstable performance of the index (for example: when the concentrated access data is in a position that can be quickly accessed in the index framework, the performance is good, and when the concentrated access data needs to access multiple index data structures to be located, the performance is poor). The invention proposal proposes targeted optimization for such scenarios, aiming to ensure that the index also has stable data processing level in special scenarios.

[0008] Considering the problem of performance degradation of index caused by NVM and the problem of NVM write wear, the design of persistent index needs to minimize the number of writes to NVM as much as possible. Existing works usually adopt two methods: (1) maintain an additional buffer to absorb newly inserted data, however, this method usually manages the buffer at the granularity of data structure (for example: all data in each tree node share a buffer), which is not conducive to the execution of concurrent operations in a multi-threaded environment, and when the buffer structure becomes too large, the entire index degrades to the performance level of internal retrieval of the buffer; (2) maintain an array with free positions (for example: the secondary expansion array in the APEX work), the newly inserted data is inserted into the nearest free position in order, however, this method is also not conducive to multi-threaded concurrent operations, and the competition of multiple threads for positions in the array will cause a performance bottleneck. In order to solve the above problems, the present application proposes a more reasonable data structure and index internal process, which minimizes the number of NVM accesses and improves the performance level of the index in a multi-threaded environment.

[0009] Finally, the existing learning index work has no upper limit guarantee for the height of the index structure, and when the data that needs to be accessed centrally is in the deep part of the index structure, it will cause a large time delay, so the present application needs to design a reasonable index structure adjustment operation to maintain the height of the index structure within a lower range. SUMMARY

[0010] In view of the defects in the prior art, the purpose of the present application is to provide a persistent learning index system for DRAM-NVM hybrid memory.

[0011] The persistent learning index system for DRAM-NVM hybrid memory provided by the present application comprises:

[0012] The model part: divide the data into sub-data sets, express each sub-data set with a linear regression model, collect the maximum key covered by each linear regression model, construct a two-layer recursive model index architecture, index the local maximum key, and retrieve the model address to which the target key belongs;

[0013] The data part: includes two types of data structures, namely Node node class and Buffer buffer block class;

[0014] The structure type adjustment part: according to the type of data structure, it is divided into buffer block expansion, buffer block conversion, node conversion and node splitting, which is used to ensure the correctness and efficiency of the index during the whole workload process.

[0015] Preferably, the model part comprises: subdividing the key space using a greedy algorithm, and dividing data subject to similar linear distribution into the same sub-data set; and using DRAM to allocate space for the model part.

[0016] Preferably, the data part includes: allocating space for the data part using NVM; storing the copy of the node that is frequently accessed in DRAM, which is called a shortcut node, and allocating space for the shortcut node using DRAM.

[0017] Preferably, the Node node class data structure includes:

[0018] The machine learning model of the current level is a d0 level or a d1 level model: the d0 level model is trained and indexed by the model part, is the entrance of the index data part, and is responsible for outputting the location of the target key; the d1 level model is dynamically generated in the workload, and is responsible for outputting the location of the newly inserted key after the initial construction of the index is completed;

[0019] Metadata: used to indicate the state of the current Node and the level at which the current Node is located;

[0020] An array of valid bits: used to indicate whether the elements in the key array are valid, to implement in-place update and deletion operations;

[0021] An array pointing to the lower buffer block class data structure or the d1 level model: used for data operations on newly inserted keys;

[0022] And an array in which the keys and corresponding data are stored.

[0023] Preferably, according to the level of the model contained in the Node node class, the Node node class is further divided into d0_Node and d1_Node, and each d0_Node object is hung with multiple Buffer objects, which are used to absorb new non-repeated data inserted into the coverage range of the node; when the Buffer object grows to a preset size, it is converted into a new Node object and replaces the Buffer object hung under the d0_Node, and according to its hierarchical relationship with the d0_Node object, the Node object converted from the Buffer object is called d1_Node.

[0024] Preferably, the Buffer block class data structure is a data structure dynamically generated in the process of the workload, and is used to store the newly inserted data after the initial construction phase of the index is completed.

[0025] Preferably, buffer expansion: when the buffer reaches its upper limit of capacity, more memory space is allocated for it to accommodate more newly inserted data, and the buffer that can accommodate more data is called alpha-buffer;

[0026] Buffer to Node Conversion: When the alpha-buffer reaches its capacity upper limit, convert the alpha-buffer instance to a Node instance, which only works on the alpha-buffer under the d0 level node and only converts to the d1 level Node object;

[0027] Node Conversion: Convert the d0_Node to a new node object d0_Node_new, which covers the newly inserted data, to enable the DRAM-NVM hybrid memory-oriented persistent learning index to have the ability of adaptive dynamic change of data distribution;

[0028] Node Splitting: Split a large d0_Node_new into two or more small d0_Node objects to ensure that the error of each model is always within the threshold range.

[0029] Preferably, the HybridMemAllocator class and the HybridMemManager class are used to uniformly allocate and release resources for the index structure in the hybrid memory;

[0030] The HybridMemAllocator class includes:

[0031] nvm_file_, which is used to establish the file name of the memory-mapped file stored in the NVM;

[0032] base_nvm_addr_ and curr_nvm_addr_, which respectively mark the starting address and the current address of the NVM memory resource pool. After each successful NVM memory allocation, the curr_nvm_addr_ increases by a corresponding offset relative to the base_nvm_addr_;

[0033] dram_ptrs_, which is used to record the starting address returned by each DRAM memory allocation;

[0034] alloc_in_nvm and alloc_in_dram functions, which respectively allocate a space of a specified size for each memory. The former offsets the data member curr_nvm_addr_ and ensures that it is always within the valid address range of the resource pool, and the latter calls the malloc library function for dynamic DRAM allocation;

[0035] free_nvm and free_dram functions, which release the space of each memory;

[0036] log function, which records the memory usage information;

[0037] The HybridMemManager class provides an interface for applications to allocate or release resources for any number and type of data structures in any memory through the allocate function according to the input parameters.

[0038] Preferably, the first write operation of creating a buffer object under d1_Node and inserting new data k_new triggers the creation of a quick node in DRAM, the creation of d1_Node_quick requires copying the key-value pairs in d1_Node and the model parameters to the DRAM space, after the creation of d1_Node_quick, a new d0_Node is created to point to d1_Node_quick; at the same time, the d1_Node object is not released, the pointer from d0_Node to d1_Node is retained, the d1_Node object is set to a frozen state, and thereafter the read and write operations of d1_Node are redirected to d1_Node_quick in the DRAM space.

[0039] Preferably, d1_Node_quick is periodically migrated to NVM, when the buffer under d1_Node_quick triggers the node transition of d1_Node_quick, the node transition is started to build d0_Node_new in NVM; when d1_Node_quick has not received a read or write operation request for a long time, the background migration thread copies the buffer under d1_Node_quick to the original d1_Node in the frozen state in NVM, and updates the valid bit array in the original d1_Node.

[0040] Compared with the prior art, the present application has the following beneficial effects:

[0041] (1) By proposing the construction and search algorithm for the index model part, the possibility of large error fluctuation between different models is avoided, so that the index model part can simultaneously have the minimum retraining overhead and the minimum average model error;

[0042] (2) By proposing the fine-grained data structure allocation and management strategy for the index data part, the resource competition problem in the high-concurrency scenario is solved, and the scalability of the index system is improved;

[0043] (3) By proposing four types of structural adjustment operations for the index framework, the problem of unlimited index height is solved, and the correct and efficient data access of the index under any type of workload is guaranteed. BRIEF DESCRIPTION OF DRAWINGS

[0044] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings:

[0045] Figure 1 The overall framework of the persistent learning index for DRAM-NVM hybrid memory proposed by the application, the left model part and the data part describe the organization structure of the index, the right SMO describes the workload description index internal data structure, the black downward arrow on the figure identifies a possible path for a request to complete related data operations based on the index, and the black right arrow on the figure identifies the adjustment and transformation of the index internal data structure module. The design of the overall framework consists of three parts, namely the design of the model part, the design of the data part and the design of the structure adjustment operation SMO.

[0046] Figure 2 The core member and method block diagram of the hybrid memory allocation manager;

[0047] Figure 3 The life cycle and maintenance method block diagram of the fast node. DETAILED DESCRIPTION

[0048] The application will be described in detail below with specific embodiments. The following embodiments will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be pointed out that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of protection of the application.

[0049] Embodiment:

[0050] As Figure 1 , the overall framework of the persistent learning index for DRAM-NVM hybrid memory proposed by the application, the left model part and the data part describe the organization structure of the index, the right SMO describes the workload description index internal data structure, the black downward arrow on the figure identifies a possible path for a request to complete related data operations based on the index, and the black right arrow on the figure identifies the adjustment and transformation of the index internal data structure module. The design of the overall framework consists of three parts, namely the design of the model part, the design of the data part and the design of the structure adjustment operation SMO.

[0051] The model part design is described as follows: a greedy algorithm is used to subdivide the key space, which ensures that data conforming to similar linear distribution is divided into the same sub-data set, and a simple linear regression model is used to accurately express each sub-data set; the maximum key covered by each model is collected to build a two-layer recursive model index architecture, and the address of the model to which the target key may belong is retrieved by indexing the local maximum key. Since the model part only needs to store the index structure for organizing the models (generated by the maximum key indexing model algorithm), it occupies a small space, so a faster DRAM is used to allocate space for the model part.

[0052] The data part design is described as follows: the data part mainly exists two types of data structures, one is Node class, represented by a rectangle in Figure 1 , and the other is Buffer class, represented by a rectangle in Figure 1The data part is represented by a triangle. Since the data part occupies the most space in the entire index structure, the data part is allocated space in NVM with higher storage density; considering the hot and cold data effect in real-world workloads, i.e. data accessed recently has a greater likelihood of being accessed again in the near future, the application also uses DRAM space to allocate space for part of the hot data structure (fast node).

[0053] The Node class Node contains:

[0054] (1) A machine learning model of the current level (d0 or d1). The model of the d0 level is obtained by training and indexing in the model part above, is the entrance of the index data part, and is responsible for outputting the location of the target key; the model of the d1 level is dynamically generated in the work load, and is responsible for outputting the location of the newly inserted key after the initial construction of the index. The model of the d1 level is trained by the data in the parent Node of the Node, and the purpose is to reduce the search time of a request in a large Node.

[0055] (2) Metadata, used to indicate the state of the current Node, the level at which the current Node is located, and other information.

[0056] (3) An array in which keys and corresponding data are stored.

[0057] (4) An effective bit array, used to indicate whether the elements in the key array are still valid, to implement in-place update and deletion operations, and to reduce the problem of repeated allocation and release of memory space and fragmentation.

[0058] (5) An array pointing to the lower buffer structure or the d1 level model, used for data operations on newly inserted keys. According to the level of the model contained in the Node (d0 or d1), in order to distinguish the description, the Node class is further divided into d0_Node and d1_Node. Each d0_Node object is hung with multiple Buffer objects, and the role of these Buffer objects is to absorb new non-duplicate data inserted into the coverage range of the node. When the Buffer object grows to a certain size, it will be converted into a new Node object and replace the Buffer hung under the d0_Node, according to its hierarchical relationship relative to the d0_Node object, the Node object converted from the Buffer object is called d1_Node.

[0059] Buffer is a data structure dynamically generated in the process of workload, which is used to store the newly inserted data after the initial construction of the index is completed. Since the buffer structure is independent of the Node, the newly inserted data into the buffer will not affect the accuracy of the trained model. The life cycle of a Buffer instance in the present invention goes through four stages: creation, expansion, transformation, and release.

[0060] The design of the structural adjustment operation SMO is described as follows: index framework structural adjustment refers to that some data operations will trigger structural changes of the index. According to the different objects of structural adjustment (Node type, Buffer type), SMO can be divided into four categories: buffer expansion, buffer transformation, node transformation, and node split. The reason why the index framework is required to make structural adjustments under certain conditions is to ensure that the index always maintains correctness and high efficiency during the entire workload process. If not adjusted, the internal structure of the index (such as buffer) will continue to expand, the index height will continue to increase, and the number of NVM access will continue to increase. These phenomena will greatly increase the time required for data retrieval and become the performance bottleneck of the index work.

[0061] Buffer expansion allocates more memory space for the buffer when it reaches its upper limit of capacity to accommodate more newly inserted data. This buffer that can accommodate more data is called alpha-buffer.

[0062] Buffer transformation converts the alpha-buffer instance into a Node instance when the alpha-buffer reaches its upper limit of capacity. This transformation can only act on the alpha-buffer hanging under the d0 level node and can only be transformed into a d1 level Node object.

[0063] Node transformation converts d0_Node into a new node object d0_Node_new, which covers the newly inserted data. The significance of this is to enable the persistent learning index facing the DRAM-NVM hybrid memory to have the ability of adaptive dynamic change of data distribution.

[0064] Node split splits a large d0_Node_new into two or more small d0_Node objects: d0_Node_i_new→d0_Node_i0+d0_Node_i1+…, which ensures that the error of each model is always within the threshold range.

[0065] AsFigure 2 The core members and method diagram of the hybrid memory allocation manager proposed in the present application. Due to the different memory allocation methods of the hybrid memory, on the one hand, the coding difficulty is increased, and on the other hand, it is difficult to provide a unified memory management calling interface to the external application, so the present application is eager to provide a flexible configuration scheme, so that programmers can flexibly select the storage location of each module according to the different server hardware configuration and business requirements. Based on the above considerations, the present application designs the HybridMemAllocator class and the HybridMemManager class to uniformly allocate and release the resources of the index structure in the hybrid memory. The HybridMemAllocator class provides a specific implementation method for hybrid memory resource management. The core data members of the HybridMemAllocator class are: nvm_file_ is the file name stored in the NVM for establishing memory mapping; base_nvm_addr_ and curr_nvm_addr_ respectively mark the starting address and the current address of the NVM memory resource pool, and after successfully completing each NVM memory allocation, curr_nvm_addr_ increases the offset of the corresponding size relative to base_nvm_addr_; dram_ptrs_ is used to record the starting address returned by each DRAM memory allocation. The core methods of the HybridMemAllocator class are: the alloc_in_nvm and alloc_in_dram functions respectively allocate a space of a specified size for each memory, the former offsets the data member curr_nvm_addr_ and ensures that it is always within the valid address range of the resource pool, and the latter calls the malloc library function to perform dynamic DRAM allocation; the free_nvm and free_dram functions release the space of each memory; the log function records information such as the usage of the two kinds of memories. The HybridMemManager class provides a simple and easy-to-use interface for the application program. The allocate function automatically calls the memory allocation method of the HybridMemAllocator class object hybrid_mem_manager according to the input parameters. In terms of programming level, programmers only need to provide the number of objects that need to be allocated memory and specify which memory to use for allocation, and can complete the resource allocation of any number, any type of data structure in any memory through the allocate function. Similarly, by additionally providing the starting address of the memory that needs to be released, the deallocate function can complete the release of any number, any type of data structure in any memory. The enumeration class MemoryType is defined to select the memory medium; if no memory is specified, the default is to use more abundant NVM resources for memory allocation, reducing the burden of the index structure on DRAM.

[0066] With the hybrid memory allocation manager, the present application proposes to store the data part in the NVM in the DRAM-NVM hybrid memory oriented persistent learning type index, and store the model part and the copy object of a small number of frequently accessed nodes in the DRAM, which are called quick nodes. The management and maintenance of the quick nodes are as shown in Figure 3 The first write operation of creating a buffer object under d1_Node and inserting new data k_new triggers the creation of the quick node in the DRAM. The creation of d1_Node_quick requires copying the key-value pairs in d1_Node and the model parameters to the DRAM space. After the creation of d1_Node_quick, a new d0_Node is created to point to d1_Node_quick; meanwhile, the d1_Node object is not released, and the pointer from d0_Node to d1_Node is retained, but the d1_Node object is set to the "frozen" state, and then the read and write operations on d1_Node are redirected to d1_Node_quick in the DRAM space. d1_Node_quick is periodically migrated to the NVM, and there are two cases that trigger its migration: (1) when the buffer under d1_Node_quick triggers the node transition of d1_Node_quick, the node transition is started to build d0_Node_new in the NVM, as shown in Figure 3 the arrow marked with the node transition word. (2) When d1_Node_quick has not received read and write operation requests for a long time, the background migration thread copies the buffer under d1_Node_quick to the original d1_Node in the "frozen" state in the NVM, and updates the valid bit array in the original d1_Node, as shown in Figure 3 the arrow marked with the node migration word.

[0067] Those skilled in the art know that, in addition to implementing the system, device and each module thereof provided by the present application in a pure computer readable program code manner, the same program can also be realized in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and each module thereof provided by the present application can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures in the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing methods and structures in the hardware component.

[0068] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be combined with each other at will without conflict.

Claims

1. A persistent learning indexing system for DRAM-NVM hybrid memory, characterized by: include: Model part: Divide the data into sub-datasets, express each sub-dataset using a linear regression model, collect the maximum key covered by each linear regression model, build a two-layer recursive model index architecture, index the local maximum key, and retrieve the model address to which the target key belongs; Data part: includes two types of data structures, namely Node node class and Buffer buffer block class; Structural adjustments: Based on the data structure type, these adjustments are divided into buffer block expansion, buffer block conversion, node conversion, and node splitting to ensure that the index remains correct and efficient throughout the entire workload. The model part includes: using a greedy algorithm to subdivide the key space and divide the data that obeys a similar linear distribution into the same sub-dataset; using DRAM to allocate space for the model part; The data part includes: using NVM to allocate space for the data part; storing the copy objects of frequently accessed nodes in DRAM, calling these nodes fast nodes, and using DRAM to allocate space for fast nodes.

2. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 1, characterized in that: The Node class data structure includes: The current level is the d0 or d1 machine learning model: The d0 model is obtained by training and indexing the model part. It is the entry point for the index data part and is responsible for outputting the location of the target key. The d1 model is dynamically generated in the workload and is responsible for outputting the location of newly inserted keys after the initial index construction is completed. Metadata: used to indicate the status of the current Node and the level of the current Node; Valid bit array: used to indicate whether the elements in the key array are valid, and to implement in-place update and delete operations; Points to the underlying buffer block data structure or array of models at the d1 level: used to perform data operations on newly inserted keys; And the array where the keys and corresponding data are stored.

3. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 2, characterized in that: The Node class is further divided into d0_Node and d1_Node according to the different hierarchical levels of the models it contains. Each d0_Node object has multiple Buffer objects attached to it, which are used to absorb new non-duplicate data inserted into the coverage area of ​​the node. When a Buffer object grows to a preset size, it is converted into a new Node object and replaced by the Buffer object under the d0_Node. According to its hierarchical relationship with the d0_Node object, the Node object converted from the Buffer object is called d1_Node.

4. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 1, characterized in that: The buffer block data structure is a data structure dynamically generated during the workload process and is used to store newly inserted data after the initial index construction phase is completed.

5. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 1, characterized in that: Buffer expansion: When the buffer reaches its capacity limit, more memory space is allocated to it to accommodate more newly inserted data. The buffer that can accommodate more data is called an alpha-buffer. Buffer block conversion: When the alpha-buffer reaches its upper limit, the alpha-buffer instance is converted to a Node instance. This conversion only works on the alpha-buffer under the d0 level node and is only converted to the d1 level Node object; Node conversion: Convert d0_Node to a new node object d0_Node_new. d0_Node_new overwrites the newly inserted data, enabling the persistent learning index for DRAM-NVM hybrid memory to adapt to dynamically changing data distribution. Node splitting: Split a large d0_Node_new into two or more small d0_Node objects to ensure that the error of each model is always within the threshold range.

6. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 1, characterized in that: The HybridMemAllocator class and the HybridMemManager class are used to uniformly manage resource allocation and release for the index structure in the hybrid memory. The HybridMemAllocator class includes: nvm_file_, the name of the file stored in NVM used to create the memory map; base_nvm_addr_ and curr_nvm_addr_, respectively mark the starting address and current address of the NVM memory resource pool. Each time an NVM memory allocation is successfully completed, curr_nvm_addr_ increases the offset of the corresponding size relative to base_nvm_addr_; dram_ptrs_, used to record the first address returned by each DRAM memory allocation; The alloc_in_nvm and alloc_in_dram functions allocate a specified size of space for their respective memories. The former offsets the data member curr_nvm_addr_ and ensures that it is always within the valid address range of the resource pool. The latter calls the malloc library function for dynamic DRAM allocation. The free_nvm and free_dram functions release the space of their respective memories; log function, records memory usage information; The HybridMemManager class provides an interface for the application, and completes resource allocation or release for any number and type of data structures in any memory according to the input parameters through the allocate function.

7. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 1, characterized in that: The first write operation that creates a buffer object under d1_Node and inserts new data k_new triggers the creation of a quick node in DRAM. The creation of d1_Node_quick requires copying the key-value pairs and model parameters in d1_Node to the DRAM space. After d1_Node_quick is created, a new pointer from d0_Node to d1_Node_quick is created. At the same time, the d1_Node object is not released, and the pointer from d0_Node to d1_Node is retained. The d1_Node object is set to a frozen state, and all subsequent read and write operations on d1_Node are redirected to d1_Node_quick in the DRAM space.

8. The persistent learning indexing system for DRAM-NVM hybrid memory according to claim 7, characterized in that: d1_Node_quick is periodically migrated to NVM. When the buffer under d1_Node_quick triggers d1_Node_quick to undergo node conversion, the node conversion is initiated to build d0_Node_new in NVM. When d1_Node_quick does not receive any read or write operation requests for a long time, the background migration thread copies the buffer under d1_Node_quick to the original frozen d1_Node in NVM and updates the valid bit array in the original d1_Node.

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