Synaptic weight updating method in event-driven type chip, chip and electronic device

Abstract

The present application relates to the field of artificial intelligence and the field of brain-like intelligent chip, in particular to a synapse weight updating method in event-driven type chip, a chip and an electronic device, the method comprises the following steps: in the training of a deep convolutional neural network of an event-driven type chip, adopting a BP-STDP learning rule to update the weight of each synapse of the convolutional layer of the deep convolutional neural network, and adopting a DFA-STDP learning rule to update the weight of each synapse of the fully connected layer of the deep convolutional neural network. The method can make the neuromorphic chip realize maximum parallel computing, greatly improve the processing speed and enhance the performance of the chip.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence and neuromorphic intelligent chips, specifically to a synaptic weight update method, chip, and electronic device in event-driven chips. Background Technology

[0002] As the AIoT (Artificial Intelligence of Things) enters an "accelerated phase" of industrial growth, the importance of IoT devices is becoming increasingly apparent. More IoT application scenarios, such as facial recognition, low-orbit starlink, autonomous driving, smart healthcare, smart vehicle networking, and spaceborne / airborne applications, are creating an urgent need for high-energy-efficiency real-time intelligent devices. These include mobile IoT devices capable of processing massive real-time visual data with minimal energy consumption, compact size, low cost, and adaptive learning capabilities for dynamic scenes and targets. Traditional AI chips suffer from problems such as synchronous intensive computation, low energy efficiency, slow speed, high cost, large area, and difficulty in on-chip learning, failing to meet the demands of intelligent IoT applications. In contrast, neuromorphic chips running neuromorphic spiking neural networks offer advantages such as spatiotemporal sparse pulse drive, high computational efficiency, low cost, small area, relatively easy on-chip learning, and strong environmental adaptability. Therefore, neuromorphic chips and systems are key to solving the energy efficiency bottleneck of AI on IoT devices.

[0003] The key problems existing in current neuromorphic chips, both domestically and internationally, are as follows: Large-scale general-purpose neuromorphic chips, primarily serving neuroscience research and cognitive computing in data centers, are characterized by their enormous size, excessive power consumption, and weak real-time processing capabilities. Meanwhile, lightweight model-specific neuromorphic chips struggle to map complex SNN models, run high-recognition-rate on-chip learning algorithms, exhibit poor functional flexibility, and severely limit their practicality. Therefore, it is necessary to design a relatively flexible, on-chip learning-supporting, high-recognition-rate, real-time-capable, small-sized, and low-power edge neuromorphic brain-like chip as the core intelligent engine of the system to support real-time edge intelligent application scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a synaptic weight update method, chip, and electronic device for event-driven chips. On the one hand, the BP / DFA-STDP learning algorithm and deep convolution mechanism significantly improve the classification and recognition performance of the network. On the other hand, the pulse event-driven operation can reduce resource consumption and effectively reduce chip power consumption. At the same time, the Direct Feedback Alignment (DFA) theoretical framework enables neuromorphic chips to achieve maximized parallel computing, significantly improving processing speed and chip performance.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a method for updating synaptic weights in an event-driven chip. The method comprises: in the training of a deep convolutional neural network in an event-driven chip, using the BP-STDP learning rule to update the weights of each synapse in the convolutional layer of the deep convolutional neural network, and using the DFA-STDP learning rule to update the weights of each synapse in the fully connected layer of the deep convolutional neural network.

[0007] Furthermore, the BP-STDP learning rule is used to update the weights of each synapse in the convolutional layer of the deep convolutional neural network. Specifically, the BP propagation path error of the deep convolutional neural network is calculated, and the gradient is obtained by convolving the BP propagation path error with the pulse count of the input node or neuron in the previous layer. Then, the gradient is multiplied by the learning rate to obtain the weight update amount of each synapse in the convolutional layer. The weights of each synapse in the convolutional layer of the deep convolutional neural network are updated using the weight update amount.

[0008] Furthermore, the calculation of the backpropagation path error includes the calculation of the error from the network entity layer to the pooling layer and the calculation of the error from the pooling layer to the network entity layer, wherein the network entity layer is a fully connected layer or a convolutional layer. For the error calculation from the network entity layer to the pooling layer, the error of the network entity layer is first padded, and then the padded error is convolved with the corresponding convolutional kernel or fully connected kernel of the network entity layer to obtain the error of the pooling layer. For the error calculation from the pooling layer to the network entity layer, the error in the pooling layer is divided by 4 and then backpropagated to the positions of four adjacent points in the previous convolutional layer. If the neuron at that point has fired a pulse, the error is the corresponding error in the pooling layer divided by 4; if the neuron at that point has not fired a pulse, the error is recorded as 0.

[0009] Furthermore, the DFA-STDP learning rule is used to update the weights of each synapse in the fully connected layer of the deep convolutional neural network. Specifically, the DFA propagation path error of the deep convolutional neural network is calculated, and the weights of each synapse in the fully connected layer of the deep convolutional neural network are updated using the formula Δw = λes. In the formula, Δw represents the amount of synapse weight update, λ is the learning rate, e is the error of the postsynaptic neuron of the corresponding synapse, i.e., the DFA propagation path error, and s is the pulse count of the presynaptic neuron of the corresponding synapse.

[0010] The formula for calculating the DFA propagation path error is:

[0011]

[0012] In the formula, B is the random projection matrix and E0 is the output layer error vector.

[0013] Furthermore, the deep convolutional neural network is a LeNet-5 network.

[0014] Secondly, the present invention provides a chip that applies the synaptic weight update method for event-driven chips described in this invention, comprising: a global controller for overall chip control, data scheduling, and data initialization; a memory for buffering pulses and transmitting them to the next neural computation kernel; a pulse-encoding neural computation kernel for pulse encoding static images, converting static images into pulse forms as pulse input data, or segmenting and processing pulse event stream data generated by a DVS sensor to obtain pulse input data; a convolutional neural computation kernel for performing convolution operations on pulse events and updating the weights of each synapse in the convolutional layer of a deep convolutional neural network using the BP-STDP learning rule; and a fully connected neural computation kernel for performing fully connected operations on pulse events and updating the weights of each synapse in the fully connected layer of a deep convolutional neural network using the DFA-STDP learning rule.

[0015] Furthermore, the convolutional neural computation kernel includes a convolutional neural computation kernel controller, a first parameter register connected to the convolutional neural computation kernel controller, and several convolutional computation slices, as well as a first AER arbitrator connected to the output terminals of the several convolutional computation slices. The convolutional neural computation kernel controller is used for the control and data scheduling of the convolutional neural computation kernel, and cooperates with the global controller to realize the interaction of control signals and data with the outside of the computation kernel, and cooperates with the computation slice controller inside the computation kernel to realize the interaction of control signals and data. The first parameter register is used to cache the configuration parameters related to the computation of the convolutional neural computation kernel, including the number of convolutional computation slices, the first membrane potential threshold, the number of channels, and the learning rate. The convolutional computation slices are used for each convolutional channel. The feedforward and backpropagation path error calculation and convolution kernel weight update include a convolutional computation slice controller, a first neural computation unit, a first learning unit, a first pulse count memory, a first membrane potential memory, a convolution kernel weight memory, and a backpropagation path error memory. The first neural computation unit is responsible for updating the membrane potential and pulse count in the convolutional layer. The first learning unit is used for calculating the backpropagation path error and updating the weights of each synapse in the convolutional layer. The first pulse count memory, the first membrane potential memory, the convolution kernel weight memory, and the backpropagation path error memory are all used to store data. The first AER arbitrator is used to output pulse events sequentially according to the arbitration order when several convolutional computation slices generate pulse events simultaneously.

[0016] Furthermore, the fully connected neural computation kernel includes a fully connected neural computation kernel controller, a second parameter register connected to the fully connected neural computation kernel controller, several fully connected computation chips, and a second AER arbitrator connected to the output terminals of several fully connected computation chips. The fully connected neural computation kernel controller is used for the control and data scheduling of the fully connected neural computation kernel, and cooperates with the global controller to realize the interaction of control signals and data with the outside of the computation kernel, and cooperates with the computation chip controllers inside the computation kernel to realize the interaction of control signals and data. The second parameter register is used to cache configuration parameters related to the computation of the fully connected neural computation kernel, including the number of fully connected computation chips, the second membrane potential threshold, the number of spiking neurons reused by the computation chip, and the learning rate. The fully connected computation chips are used in the computation chip... The fully connected neuron feedforward and DFA propagation path error calculation, as well as the fully connected kernel weight update, include a fully connected computation slice controller, a second neural computation unit, a second learning unit, a second pulse counting memory, a second membrane potential memory, a fully connected kernel weight memory, and a DFA propagation path error memory. The second neural computation unit is responsible for updating the membrane potential and pulse count in the fully connected layer. The first learning unit is used for calculating the DFA propagation path error and updating the weights of each synapse in the fully connected layer. The second pulse counting memory, the second membrane potential memory, the fully connected kernel weight memory, and the DFA propagation path error memory are all used to store data. The second AER arbitrator is used to output pulse events sequentially according to the arbitration order when several fully connected computation slices generate pulse events simultaneously.

[0017] Furthermore, the pulse-coded neural computation kernel is used to pulse-code static images, converting them into pulse forms. It includes an encoding controller, a third parameter register, a multiplexer, and encoding units. The encoding controller is responsible for controlling the pulse-coded neural computation kernel and scheduling data. The third parameter register caches configuration parameters related to encoding. The multiplexer selects a specific encoding unit to execute the corresponding pulse encoding. The encoding unit encodes the input pixels of the static image into a pulse sequence, including rate encoding, first pulse time encoding, pulse interval encoding, and phase encoding.

[0018] Thirdly, the present invention provides an electronic device comprising the chip described in the present invention, the chip receiving input information from a sensor, performing inference operations on the input information to obtain inference results, and the electronic device also making corresponding responses based on the inference results.

[0019] The beneficial effects of this invention are:

[0020] 1. The deep convolutional SNN on-chip learning algorithm based on BP / DFA-STDP proposed in this invention adopts the LeNet-5 network structure. Its BP / DFA-STDP learning algorithm and the deep convolution mechanism based on impulse event driving can significantly improve the classification performance of the network, and also provide a reference for further research on neuromorphic convolutional algorithms that support on-chip learning.

[0021] 2. The neuromorphic chip architecture proposed in this invention is based on impulse event-driven computation, which can reduce resource consumption and effectively lower chip power consumption. Simultaneously, the DFA theoretical framework enables the neuromorphic chip to achieve maximized parallel computing, significantly improving processing speed.

[0022] 3. The neuromorphic chip proposed in this invention supports on-chip learning and is easy to integrate into edge devices or miniaturized devices. Its high real-time performance and high-performance processing are very suitable for edge intelligent application scenarios. Attached Figure Description

[0023] Figure 1 This is a LeNet-5 network model trained based on the BP / DFA-STDP learning algorithm according to an embodiment of the present invention.

[0024] Figure 2 This is a deep convolutional neuromorphic brain-like chip architecture according to an embodiment of the present invention. Detailed Implementation

[0025] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0026] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] Example 1, a method for updating synaptic weights in an event-driven type chip, the method is as follows: In the training of the deep convolutional neural network of the event-driven type chip, the BP-STDP learning rule is used to update the weights of each synapse in the convolutional layer of the deep convolutional neural network, and the DFA-STDP learning rule is used to update the weights of each synapse in the fully connected layer of the deep convolutional neural network. The proposed on-chip learning algorithm for deep convolutional SNN based on BP / DFA-STDP uses the LeNet-5 network structure. Its BP / DFA-STDP learning algorithm and the deep convolutional mechanism based on pulsed event driving can significantly improve the classification performance of the network, and also provide a reference for the further research of the brain-like convolutional algorithm supporting on-chip learning.

[0028] The full English name of the BP-STDP is: Backpropagation using Spike Timing Dependent Plasticity, and the Chinese name is: Plasticity Dependent on Pulse Time Based on Backpropagation.

[0029] The full English name of the DFA-STDP is: Direct Feedback Alignment using Spike Timing Dependent Plasticity, and the Chinese name is: Plasticity Dependent on Pulse Time Based on Direct Feedback Alignment.

[0030] See Figure 1 , the deep convolutional neural network is a LeNet-5 network model trained based on the BP / DFA-STDP learning algorithm. This LeNet-5 network model includes two convolutional layers, namely the first convolutional layer and the second convolutional layer, and three fully connected layers. The last layer of the three fully connected layers is also called the output layer.

[0031] This LeNet-5 network is driven by pulsed events. The pulses are described in the Address Event Representation (AER) format and have a feedforward path, a BP propagation path, and a DFA propagation path.

[0032] The feedforward path includes pulse convolution, pooling of pulses, and pulse transmission in the fully connected layer.

[0033] The pulse convolution is as follows: The size of the convolution kernel is set to 3, and the convolution step is set to 1. When a pulse event AER arrives, less than or equal to 9 convolution operations will be performed. Each convolution operation accumulates the weights in the corresponding convolution kernel to the membrane potential of the corresponding output neuron. When the membrane potential of the neuron is greater than the threshold, the neuron emits a pulse and transmits it to the pooling layer. The position relationship of the center of the convolution kernel is 1≤K x ≤W - 1, 1≤Ky ≤H-1. Where, K x and K y Let W be the coordinates of the center position of the convolution kernel in the feature map, and let W and H be the width and height of the feature map, respectively.

[0034] The pulse pooling is performed by dividing the two-dimensional coordinate addresses x and y of the pulse by 2 and then passing them to the next layer (convolutional layer or fully connected layer).

[0035] The pulse propagation in the fully connected layer is as follows: the synaptic weights corresponding to the pulse event addresses are accumulated onto the neuron membrane potential. When the neuron membrane potential exceeds a threshold, a pulse is emitted and propagated to the next layer. The DFA propagation path and BP propagation path are used for error calculation and weight update.

[0036] The feedforward path involves updating neuron state information, whether a neuron fires a pulse, and counting the pulses of the input node or neuron.

[0037] The update of the neuron's state information is equivalent to the update of the neuron's membrane potential. The neuron model uses an Integrate-and-Fire (IF) model. The membrane potential update formula is: V(t) = V(t) prev )+w, where V(t) is the membrane potential of the neuron at the current time t, t prev It is the moment of the last membrane potential update, and w is the synaptic weight.

[0038] When the neuron's membrane potential V(t) exceeds the threshold V th At this time, the neuronal membrane potential returns to the resting potential V. rest ,Right now:

[0039] V(t)=V rest if V(t)≥V th .

[0040] Whether the neuron fires a pulse is specifically determined by: when the neuron's membrane potential V(t) exceeds a threshold V. th At this point, the neuron is marked as having emitted a pulse. Here, f is a flag indicating whether the neuron has emitted a pulse, i.e., f = 1 if V(t) ≥ V th .

[0041] The pulse count s(t) of the input node or neuron is s(t) = s(t) pres )+1, meaning that when an input node or neuron receives a pulse, the pulse count is incremented by 1. Here, s represents the pulse count of the input node or neuron at the current time t, and t... pres This indicates the time of the last pulse count update.

[0042] In this embodiment, the BP-STDP learning rule is used to update the weights of each synapse in the convolutional layer of the deep convolutional neural network. Specifically, the BP propagation path error of the deep convolutional neural network is calculated, and the gradient is obtained by convolving the BP propagation path error with the pulse count of the input node or neuron in the previous layer. Then, the gradient is multiplied by the learning rate to obtain the weight update amount of each synapse in the convolutional layer. The weights of each synapse in the convolutional layer of the deep convolutional neural network are updated using the weight update amount.

[0043] The calculation of the backpropagation path error includes the calculation of the error from the network entity layer to the pooling layer and the calculation of the error from the pooling layer to the network entity layer. The network entity layer is either a fully connected layer or a convolutional layer. For the error calculation from the network entity layer to the pooling layer, the error of the network entity layer is first padded, and then the padded error is convolved with the corresponding convolutional kernel or fully connected kernel of the network entity layer to obtain the error of the pooling layer. For the error calculation from the pooling layer to the network entity layer, the error in the pooling layer is divided by 4 and then backpropagated to the positions of four adjacent points in the previous convolutional layer. If the neuron at that point has fired a pulse, the error is the corresponding error in the pooling layer divided by 4; if the neuron at that point has not fired a pulse, the error is recorded as 0.

[0044] In this embodiment, the DFA-STDP learning rule is used to update the weights of each synapse in the fully connected layer of the deep convolutional neural network. Specifically, the DFA propagation path error of the deep convolutional neural network is calculated, and the weights of each synapse in the fully connected layer of the deep convolutional neural network are updated using the formula Δw = λes. In the formula, Δw represents the amount of synapse weight update, λ is the learning rate, e is the error of the postsynaptic neuron of the corresponding synapse, i.e., the DFA propagation path error, and s is the pulse count of the presynaptic neuron of the corresponding synapse.

[0045] The formula for calculating the DFA propagation path error is:

[0046]

[0047] In the formula, B is the random projection matrix and E0 is the output layer error vector.

[0048] Example 2: A chip that applies the synaptic weight update method for event-driven chips described in this invention. See [link to example]. Figure 2 The chip is a deep convolutional neuromorphic chip, comprising a global controller, a memory, a pulse-code neural computation kernel, a convolutional neural computation kernel, a fully connected neural computation kernel, and several FIFOs.

[0049] The global controller is used for overall chip control, data scheduling, and data initialization. The memory is used to cache pulses and send them to the next neural computation core. The pulse encoding neural computation core is used to pulse encode static images, converting them into pulse forms as pulse input data, or to segment and process the pulse event stream data generated by the DVS sensor to obtain pulse input data. The convolution operation neural computation core is used to perform convolution operations on pulse events and update the weights of each synapse in the convolutional layer of the deep convolutional neural network using the BP-STDP learning rule. The fully connected neural computation core is used to perform fully connected operations on pulse events and update the weights of each synapse in the fully connected layer of the deep convolutional neural network using the DFA-STDP learning rule. The FIFO is used to cache pulses and send them to the next neural computation core.

[0050] The pulse-code neural computation kernel is used to encode the pixel values ​​of a static image into pulse events (AER), that is, to convert the static image into pulse form. The pulse-code neural computation kernel includes an encoding controller, a third parameter register, a multiplexer, and encoding units; the encoding controller is responsible for controlling the pulse-code neural computation kernel and scheduling data; the third parameter register is used to cache encoding-related configuration parameters; the multiplexer is used to select a specific encoding unit to execute the corresponding pulse encoding.

[0051] The encoding unit is used to encode the input pixels of a static image into a pulse sequence, including rate encoding, time-to-first-spike (TTFS) encoding, inter-spike interval (ISI) encoding, and phase encoding.

[0052] The convolutional neural computation kernel includes a convolutional neural computation kernel controller, a first parameter register connected to the convolutional neural computation kernel controller, several convolutional computation slices, and a first AER arbitrator connected to the outputs of N convolutional computation slices. The convolutional neural computation kernel controller is used for the control and data scheduling of the convolutional neural computation kernel, and cooperates with the global controller to achieve control signal and data interaction with the outside of the computation kernel, as well as with the computation slice controllers inside the computation kernel to achieve control signal and data interaction. The first parameter register is used to cache configuration parameters related to the convolutional neural computation kernel computation, including the number of convolutional computation slices, the first membrane potential threshold, the number of channels, and the learning rate. The convolutional computation slices are used for calculating the feedforward and backpropagation path error for each convolutional channel. The system includes a convolutional computation slice controller, a first neural computation unit, a first learning unit, a first pulse count memory, a first membrane potential memory, a convolutional kernel weight memory, and a BP propagation path error memory. The first neural computation unit is responsible for updating the membrane potential and pulse count in the convolutional layer. The first learning unit is used to calculate the BP propagation path error and update the weights of each synapse in the convolutional layer. The first pulse count memory, the first membrane potential memory, the convolutional kernel weight memory, and the BP propagation path error memory are all used to store data. The first AER arbitrator is used to output pulse events sequentially according to the arbitration order when several convolutional computation slices generate pulse events simultaneously. The data scheduling function coordinates the data flow between the computation unit and the memory.

[0053] The fully connected neural computation kernel includes a fully connected neural computation kernel controller, a second parameter register connected to the fully connected neural computation kernel controller, M fully connected computation chips, and a second AER arbitrator connected to the outputs of several fully connected computation chips. The fully connected neural computation kernel controller is used for the control and data scheduling of the fully connected neural computation kernel, and cooperates with the global controller to realize the interaction of control signals and data with the outside of the computation kernel, as well as with the computation chip controllers inside the computation kernel to realize the interaction of control signals and data. The second parameter register is used to cache configuration parameters related to the computation of the fully connected neural computation kernel, including the number of fully connected computation chips, the second membrane potential threshold, the number of spiking neurons reused by the computation chip, and the learning rate. The fully connected computation chip is used for fully connecting the computation within the computation chip. The system includes a fully connected computation slice controller, a second neural computation unit, a second learning unit, a second pulse counting memory, a second membrane potential memory, a fully connected kernel weight memory, and a DFA propagation path error memory. The second neural computation unit is responsible for updating the membrane potential and pulse count in the fully connected layer. The first learning unit is used for calculating the DFA propagation path error and updating the weights of each synapse in the fully connected layer. The second pulse counting memory, second membrane potential memory, fully connected kernel weight memory, and DFA propagation path error memory are all used to store data. The second AER arbitrator is used to output pulse events sequentially according to the arbitration order when several fully connected computation slices generate pulse events simultaneously. Data scheduling coordinates the data flow between the computation unit and the memory.

[0054] Example 3: An electronic device including the chip described in this invention. The chip receives input information from a sensor, performs inference operations on the input information to obtain inference results, and the electronic device also makes a corresponding response based on the inference results.

[0055] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A method for updating synaptic weights in an event-driven chip, characterized in that: In the training of deep convolutional neural networks for event-driven chips, the BP-STDP learning rule is used to update the weights of each synapse in the convolutional layer of the deep convolutional neural network, and the DFA-STDP learning rule is used to update the weights of each synapse in the fully connected layer of the deep convolutional neural network. The BP-STDP learning rule is used to update the weights of each synapse in the convolutional layer of a deep convolutional neural network. Specifically, the BP propagation path error of the deep convolutional neural network is calculated. The gradient is obtained by convolving the BP propagation path error with the pulse count of the input node or neuron in the previous layer. Then, the gradient is multiplied by the learning rate to obtain the weight update amount of each synapse in the convolutional layer. The weights of each synapse in the convolutional layer of the deep convolutional neural network are updated using the weight update amount. The calculation of BP propagation path error includes the calculation of error from the network entity layer to the pooling layer and the calculation of error from the pooling layer to the network entity layer, wherein the network entity layer is a fully connected layer or a convolutional layer. To calculate the error from the network entity layer to the pooling layer, the error of the network entity layer is first padded, and then the padded error is convolved with the convolution kernel or fully connected kernel corresponding to the network entity layer to obtain the error of the pooling layer. For error calculation from pooling layer to network entity layer, the error in pooling layer is divided by 4 and then backpropagated to the positions of four adjacent points in the previous convolutional layer. If the neuron at that point has emitted a pulse, the error is the corresponding error in pooling layer divided by 4. If the neuron at that point has not fired a pulse, the error is recorded as 0; The DFA-STDP learning rule is used to update the weights of each synapse in the fully connected layer of a deep convolutional neural network. Specifically, the DFA propagation path error of the deep convolutional neural network is calculated using the formula... The weights of each synapse in the fully connected layer of the deep convolutional neural network are updated. In the formula, Δw represents the amount of synapse weight update, λ is the learning rate, e is the error of the postsynaptic neuron of the corresponding synapse, i.e., the DFA propagation path error, and s is the pulse count of the presynaptic neuron of the corresponding synapse. The formula for calculating the DFA propagation path error is: ； In the formula, B is the random projection matrix and E0 is the output layer error vector.

2. The synaptic weight update method in an event-driven chip according to claim 1, characterized in that, The deep convolutional neural network is the LeNet-5 network.

3. A chip, characterized in that, The chip applies the synaptic weight update method in the event-driven type chip as described in claim 1 or 2, including: The global controller is used for overall chip control, data scheduling, and data initialization. Memory, used to buffer pulses and transmit them to the next neural computational kernel; The pulse coding neural computation kernel is used to pulse code static images, converting them into pulse forms as pulse input data, or to segment and process the pulse event stream data generated by the DVS sensor to obtain pulse input data; The convolutional neural computation kernel is used to perform convolution operations on impulse events and updates the weights of each synapse in the convolutional layer of the deep convolutional neural network using the BP-STDP learning rule. The fully connected neural computation kernel is used to perform fully connected operations on impulse events and updates the weights of each synapse in the fully connected layer of the deep convolutional neural network using the DFA-STDP learning rule. The convolution operation neural computation kernel includes a convolution neural computation kernel controller, a first parameter register connected to the convolution neural computation kernel controller, a plurality of convolution computation slices, and a first AER arbitrator connected to the output terminals of the plurality of convolution computation slices; The convolutional neural computation kernel controller is used for the control and data scheduling of the convolutional neural computation kernel, and works with the global controller to realize the interaction of control signals and data with the outside of the computation kernel, as well as with the computation chip controller inside the computation kernel to realize the interaction of control signals and data. The first parameter register is used to cache configuration parameters related to the computation of the convolutional neural computation kernel. The configuration parameters related to the computation of the convolutional neural computation kernel include the number of convolutional computation slices, the first membrane potential threshold, the number of channels, and the learning rate. The convolutional computation chip is used for feedforward and BP propagation path error calculation and convolutional kernel weight update for each convolutional channel, and includes a convolutional computation chip controller, a first neural computation unit, a first learning unit, a first pulse counting memory, a first membrane potential memory, a convolutional kernel weight memory, and a BP propagation path error memory; The first neural computing unit is responsible for updating the membrane potential and pulse count in the convolutional layer; The first learning unit is used to calculate the BP propagation path error and update the weights of each synapse in the convolutional layer; The first pulse count memory, the first membrane potential memory, the convolution kernel weight memory, and the BP propagation path error memory are all used to store data; The first AER arbitrator is used to output pulse events sequentially according to the arbitration order when several convolutional computation chips generate pulse events simultaneously. The fully connected neural computing core includes a fully connected neural computing core controller, a second parameter register connected to the fully connected neural computing core controller, a plurality of fully connected computing chips, and a second AER arbitrator connected to the output terminals of the plurality of fully connected computing chips; The fully connected neural computing core controller is used for the control and data scheduling of the fully connected neural computing core, and works with the global controller to realize the interaction of control signals and data with the outside of the computing core, as well as with the computing chip controller inside the computing core to realize the interaction of control signals and data. The second parameter register is used to cache configuration parameters related to the computation of the fully connected neural computation kernel. The configuration parameters related to the computation of the fully connected neural computation kernel include the number of fully connected computation slices, the second membrane potential threshold, the number of spiking neurons reused by the computation slice, and the learning rate. The fully connected computation chip is used for feedforward and DFA propagation path error calculation of fully connected neurons in the computation chip, as well as full connected kernel weight update, and includes a fully connected computation chip controller, a second neural computation unit, a second learning unit, a second pulse counting memory, a second membrane potential memory, a fully connected kernel weight memory, and a DFA propagation path error memory; The second neural computing unit is responsible for updating the membrane potential and pulse count in the fully connected layer; The first learning unit is used to calculate the DFA propagation path error and update the weights of each synapse in the fully connected layer; The second pulse count memory, the second membrane potential memory, the fully connected kernel weight memory, and the DFA propagation path error memory are all used to store data; The second AER arbitrator is used to output pulse events sequentially according to the arbitration order when several fully connected computing chips generate pulse events simultaneously.

4. The chip according to claim 3, characterized in that: The pulse-coded neural computation kernel is used to pulse-code static images, converting them into pulse forms. It includes an encoding controller, a third parameter register, a multiplexer, and an encoding unit. The encoding controller is responsible for controlling and scheduling data in the pulse-coded neural computation kernel; The third parameter register is used to cache configuration parameters related to encoding; The multiplexer is used to select a specific encoding unit to perform the corresponding pulse encoding; The encoding unit is used to encode the input pixels of a static image into a pulse sequence, including rate encoding, first pulse time encoding, pulse interval encoding, and phase encoding.

5. An electronic device, characterized in that: The electronic device includes a chip as described in claim 3 or 4, which receives input information from a sensor, performs inference operations on the input information to obtain an inference result, and the electronic device also makes a corresponding response based on the inference result.

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