Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of pixel circuit column groups, each of which comprises at least two pixel circuit columns, one pixel circuit column is connected with two signal lines, each signal line transmits a data signal and a bias signal to the pixel circuit in the pixel circuit column in time, and the two pixel circuit columns of the pixel circuit column group are connected with the same first signal end and the same second signal end, the first signal end is used for providing the data signal, and the second signal end is used for providing the bias signal. According to the embodiment of the application, the first pole or the second pole of the driving module of the double data line circuit is periodically reset, and the pixel arrangement design is facilitated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous updating of display panel technology, display panels are gradually developing towards thinness, high screen ratio and ultra-narrow frame.

[0003] In the related art, a single data line circuit can add a bias circuit controlled by a bias signal in a pixel circuit to periodically reset the first pole or the second pole of the driving module, so as to improve the offset or hysteresis phenomenon of the characteristics of the driving module after long-term work. However, for a double data line (DDL) circuit in the related art, if a bias circuit controlled by a bias signal is added, another signal line needs to be added, which is not conducive to pixel layout design. SUMMARY

[0004] The display panel and the display device provided in the embodiments of the present application can periodically reset the first pole or the second pole of the driving module of the double data line circuit, and are conducive to pixel layout design.

[0005] In a first aspect, the embodiments of the present application provide a display panel, which includes a plurality of pixel circuit column groups, each pixel circuit column group including at least two pixel circuit columns, one pixel circuit column being connected to two signal lines, each signal line being used to time-divisionally transmit a data signal and a bias signal to the pixel circuits in the pixel circuit column, and the two pixel circuit columns of the pixel circuit column group being connected to the same first signal end and the same second signal end, the first signal end being used to provide the data signal, and the second signal end being used to provide the bias signal.

[0006] Based on the same inventive concept, in a second aspect, the embodiments of the present application provide a display device, which includes the display panel of the first aspect.

[0007] According to the display panel and the display device provided in the embodiments of the present application, one pixel circuit column is connected to two signal lines, each signal line can time-divisionally transmit a data signal and a bias signal to the pixel circuits in the pixel circuit column, no additional signal line needs to be added, the first pole or the second pole of the driving module can be periodically reset, which is conducive to improving the offset and hysteresis phenomenon of the characteristics of the driving module after long-term work, and is also conducive to pixel layout design. BRIEF DESCRIPTION OF DRAWINGS

[0008] Other features, objects, and advantages of the application will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which like reference numerals indicate identical or similar components, and in which:

[0009] Figure 1 A structural schematic diagram of a display panel in the related art is shown;

[0010] Figure 2 A structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0011] Figure 3 Another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0012] Figure 4 Still another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0013] Figure 5 Still another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0014] Figure 6 Still another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0015] Figure 7 Still another working timing diagram of a display panel provided by an embodiment of the application is shown;

[0016] Figure 8 Still another working timing diagram of a display panel provided by an embodiment of the application is shown;

[0017] Figure 9 Still another working timing diagram of a display panel provided by an embodiment of the application is shown;

[0018] Figure 10 Still another working timing diagram of a display panel provided by an embodiment of the application is shown;

[0019] Figure 11 Still another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0020] Figure 12 Still another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0021] Figure 13 Still another working timing diagram of a display panel provided by an embodiment of the application is shown;

[0022] Figure 14 Still another structural schematic diagram of a display panel provided by an embodiment of the application is shown;

[0023] Figure 15 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0024] Figure 16 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0025] Figure 17 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0026] Figure 18 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0027] Figure 19 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0028] Figure 20 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0029] Figure 21 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0030] Figure 22 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0031] Figure 23 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0032] Figure 24 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application;

[0033] Figure 25 FIG. 6 shows another working timing diagram of the display panel provided by an embodiment of the present application; DETAILED DESCRIPTION

[0034] The features and exemplary embodiments of various aspects of the present application will be described below in detail, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0035] It should be noted that, in this document, the terms such as first and second, etc. are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of additional identical elements in the process, method, article or device including the elements.

[0036] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or can mean that two components are electrically connected via one or more other components.

[0037] Various modifications and changes can be made to the present application without departing from the spirit or scope of the present application, which will be apparent to one skilled in the art. Therefore, the present application is intended to cover modifications and variations of the present application that come within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction, if possible.

[0038] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0039] Organic light emitting diode (OLED) display panel has the advantages of self-illumination, fast response, high brightness, thinness and the like, and has gradually become the mainstream in the display field.

[0040] The inventors have found that, as shown in Figure 1 The related art adds an eighth transistor T8 on the basis of the existing 7T1C pixel circuit, controls the eighth transistor T8 to be turned on by controlling the control signal SP* to be at an on level, writes the signal on the DVH signal line to the N2 node, and resets the N2 node periodically, so as to improve the shift or hysteresis phenomenon of the characteristics of the driving transistor T3 after long-term work by adjusting the potential applied to the N2 node.

[0041] However, for a double data line circuit, if a new DVH signal is added, it is not conducive to the pixel layout design.

[0042] In order to solve the above-mentioned problems in the related technologies, the present application provides a display panel and display device, which facilitates pixel arrangement while realizing the periodic reset of the first or second pole of the driving module of the dual data line circuit.

[0043] The display panel provided in the embodiments of this application will be described first below.

[0044] like Figure 2 As shown, the display panel 1000 may include multiple pixel circuit column groups 100, and each pixel circuit column group 100 may include at least two pixel circuit columns. Each pixel circuit column may be arranged in the row direction X, and each pixel circuit column may include multiple pixel circuits 10 arranged in the column direction Y.

[0045] Figure 2 and Figure 3 Taking a pixel circuit group 100 comprising two pixel circuit columns as an example, but not limited to this, the number of pixel circuit columns included in the pixel circuit group 100 can be set according to the actual situation and is not limited here. For example, a pixel circuit group 100 may include three pixel circuit columns, four pixel circuit columns, etc.

[0046] Each pixel circuit column can connect to two signal lines; that is, each pixel circuit column in pixel circuit column group 100 can connect to two signal lines. Each signal line transmits a data signal and a bias signal to the pixel circuits in the pixel circuit column in a 10-minute time division ratio. Furthermore, two pixel circuit columns in pixel circuit column group 100 can be connected to the same first signal terminal (source) and the same second signal terminal (DVH). The first signal terminal (source) can be used to provide the data signal, and the second signal terminal (DVH) can be used to provide the bias signal.

[0047] For example, at a first moment, the data signal of the first signal terminal (source) can be transmitted to the pixel circuit 10 in the pixel circuit column through one of the two signal lines, and the bias signal of the second signal terminal (DVH) can be transmitted to the pixel circuit 10 in the pixel circuit column through the other of the two signal lines. At a second moment, the bias signal of the second signal terminal (DVH) can be transmitted to the pixel circuit 10 in the pixel circuit column through one of the two signal lines, and the data signal of the first signal terminal (source) can be transmitted to the pixel circuit 10 in the pixel circuit column through the other of the two signal lines. The first moment and the second moment are different moments.

[0048] Thus, this application does not require additional signal lines and can periodically reset the first or second pole of the drive module 11, which is beneficial to improving the offset and hysteresis of the characteristics of the drive module 11 after long-term operation, and also beneficial to pixel arrangement design.

[0049] In some alternative embodiments, the display panel 1000 can further include a first gate circuit 200 and a second gate circuit 300, and the at least two pixel circuit columns can include a first pixel circuit column 110 and a second pixel circuit column 120.

[0050] The two signal lines connected to the first pixel circuit column 110 are connected to the first signal end source through the first gate circuit 200, and the two signal lines connected to the first pixel circuit column 110 are connected to the second signal end DVH through the second gate circuit 300.

[0051] That is, the first end of each of the two signal lines connected to the first pixel circuit column 110 can be connected to the first signal end source through the first gate circuit 200 to receive the data signal of the first signal end source. The second end of each of the two signal lines connected to the first pixel circuit column 110 can be connected to the second signal end DVH through the second gate circuit 300 to receive the bias signal of the second signal end DVH.

[0052] The two signal lines connected to the second pixel circuit column 120 are connected to the first signal end source through the first gate circuit 200, and the two signal lines connected to the second pixel circuit column 120 are connected to the second signal end DVH through the second gate circuit 300.

[0053] That is, the first end of each of the two signal lines connected to the second pixel circuit column 120 can be connected to the first signal end source through the first gate circuit 200 to receive the data signal of the first signal end source. The second end of each of the two signal lines connected to the second pixel circuit column 120 can be connected to the second signal end DVH through the second gate circuit 300 to receive the bias signal of the second signal end DVH.

[0054] The first gate circuit 200 can be used to time-divisionally transmit the data signal provided by the first signal end source to the four signal lines of the pixel circuit column group 100. That is, the first gate circuit 200 can be used to time-divisionally transmit the data signal provided by the first signal end source to the two signal lines connected to the first pixel circuit column 110 and the two signal lines connected to the second pixel circuit column 120.

[0055] The second gate circuit 300 can be used to time-divisionally transmit the bias signal provided by the second signal end DVH to the four signal lines of the pixel circuit column group 100. That is, the second gate circuit 300 can be used to time-divisionally transmit the bias signal provided by the second signal end DVH to the two signal lines connected to the first pixel circuit column 110 and the two signal lines connected to the second pixel circuit column 120.

[0056] In the embodiment, the first gating circuit 200 is arranged between the first signal terminal source and the pixel circuit column group 100, and the second gating circuit 300 is arranged between the second signal terminal DVH and the pixel circuit column group 100. The data signal and the bias signal can be transmitted to the pixel circuit 10 in the pixel circuit column group 100 in time by controlling the on-off of the first gating circuit 200 and the second gating circuit 300.

[0057] In some optional embodiments, the two signal lines connected by the first pixel circuit column 110 can include a first signal line data1 and a third signal line data3, and the two signal lines connected by the second pixel circuit column 120 can include a second signal line data2 and a fourth signal line data4.

[0058] The first gating circuit 200 can include a first switching element K1, a second switching element K2, a third switching element K3, and a fourth switching element K4. The first end of the first switching element K1, the first end of the second switching element K2, the first end of the third switching element K3, and the first end of the fourth switching element K4 are connected with the first signal terminal source. The second end of the first switching element K1 is connected with the first signal line data1. The second end of the third switching element K3 is connected with the third signal line data3. The second end of the fourth switching element K4 is connected with the fourth signal line data4. The second end of the second switching element K2 is connected with the second signal line data2.

[0059] For example, the first switching element K1 can include a first transistor M1, the second switching element K2 can include a second transistor M2, the third switching element K3 can include a third transistor M3, and the fourth switching element K4 can include a fourth transistor M4. The first end of the first switching element K1 can be the first pole of the first transistor M1, and the second end of the first switching element K1 can be the second pole of the first transistor M1. The first end of the second switching element K2 can be the first pole of the second transistor M2, and the second end of the second switching element K2 can be the second pole of the second transistor M2. The first end of the third switching element K3 can be the first pole of the third transistor M3, and the second end of the third switching element K3 can be the second pole of the third transistor M3. The first end of the fourth switching element K4 can be the first pole of the fourth transistor M4, and the second end of the fourth switching element K4 can be the second pole of the fourth transistor M4.

[0060] In the present application, the first pole of each transistor can be one of the source or the drain, and the second pole of each transistor can be the other of the source or the drain.

[0061] The second gating circuit 300 includes a fifth switching element K5, a sixth switching element K6, a seventh switching element K7, and an eighth switching element K8. The first terminal of the fifth switching element K5, the first terminal of the sixth switching element K6, the first terminal of the seventh switching element K7, and the first terminal of the eighth switching element K8 are connected to the second signal terminal DVH. The second terminal of the fifth switching element K5 is connected to the first signal line data1. The second terminal of the sixth switching element K6 is connected to the third signal line data3. The second terminal of the seventh switching element K7 is connected to the fourth signal line data4. The second terminal of the eighth switching element K8 is connected to the second signal line data2.

[0062] The fifth switching element K5 can include a fifth transistor M5, the sixth switching element K6 can include a sixth transistor M6, the seventh switching element K7 can include a seventh transistor M7, and the eighth switching element K8 can include an eighth transistor M8. The first terminal of the fifth switching element K5 can be the first electrode of the fifth transistor M5, and the second terminal of the fifth switching element K5 can be the second electrode of the fifth transistor M5. The first terminal of the sixth switching element K6 can be the first electrode of the sixth transistor M6, and the second terminal of the sixth switching element K6 can be the second electrode of the sixth transistor M6. The first terminal of the seventh switching element K7 can be the first electrode of the seventh transistor M7, and the second terminal of the seventh switching element K7 can be the second electrode of the seventh transistor M7. The first terminal of the eighth switching element K8 can be the first electrode of the eighth transistor M8, and the second terminal of the eighth switching element K8 can be the second electrode of the eighth transistor M8.

[0063] The first switching element K1 and the sixth switching element K6 are turned on or turned off under the control of the first control signal line mux1, the second switching element K2 and the seventh switching element K7 are turned on or turned off under the control of the second control signal line mux2, the third switching element K3 and the fifth switching element K5 are turned on or turned off under the control of the third control signal line mux3, and the fourth switching element K4 and the eighth switching element K8 are turned on or turned off under the control of the fourth control signal line mux4.

[0064] The first control signal on the first control signal line mux1, the second control signal on the second control signal line mux2, the third control signal on the third control signal line mux3, and the fourth control signal on the fourth control signal line mux4 are all different.

[0065] In the present embodiment, by providing a plurality of switching elements in the first gating circuit 200 and the second gating circuit 300 respectively, and further by controlling the turn-on or turn-off of each switching element, the on-off of the first gating circuit 200 and / or the second gating circuit 300 can be controlled, and the data signal and the bias signal can be transmitted to the pixel circuit 10 in the pixel circuit column group 100 in time.

[0066] In addition, since the first switch element K1 and the sixth switch element K6 are simultaneously turned on or turned off, the second switch element K2 and the seventh switch element K7 are simultaneously turned on or turned off, the third switch element K3 and the fifth switch element K5 are simultaneously turned on or turned off, and the fourth switch element K4 and the eighth switch element K8 are simultaneously turned on or turned off, the data signal write time and the bias signal write time are equal for the same pixel circuit 10.

[0067] In other optional embodiments, as shown in FIG. 1C, the two signal lines connected to the first pixel circuit column 110 include a first signal line data1 and a third signal line data3, and the two signal lines connected to the second pixel circuit column 120 include a second signal line data2 and a fourth signal line data4. Figure 4

[0068] The first gating circuit 200 includes a first switch element K1, a second switch element K2, a third switch element K3, and a fourth switch element K4. The first end of the first switch element K1, the first end of the second switch element K2, the first end of the third switch element K3, and the first end of the fourth switch element K4 are connected to a first signal end source. The second end of the first switch element K1 is connected to the first signal line data1. The second end of the second switch element K2 is connected to the second signal line data2. The second end of the third switch element K3 is connected to the third signal line data3. The second end of the fourth switch element K4 is connected to the fourth signal line data4.

[0069] The second gating circuit 300 includes a fifth switch element K5, a sixth switch element K6, a seventh switch element K7, and an eighth switch element K8. The first end of the fifth switch element K5, the first end of the sixth switch element K6, the first end of the seventh switch element K7, and the first end of the eighth switch element K8 are connected to a second signal end DVH. The second end of the fifth switch element K5 is connected to the first signal line data1. The second end of the sixth switch element K6 is connected to the third signal line data3. The second end of the seventh switch element K7 is connected to the fourth signal line data4. The second end of the eighth switch element K8 is connected to the second signal line data2.

[0070] The first switch element K1 is turned on or turned off under the control of a first control signal line mux1. The second switch element K2, the sixth switch element K6, and the seventh switch element K7 are turned on or turned off under the control of a second control signal line mux2. The third switch element K3 is turned on or turned off under the control of a third control signal line mux3. The fourth switch element K4, the fifth switch element K5, and the eighth switch element K8 are turned on or turned off under the control of a fourth control signal line mux4.

[0071] ​In this embodiment, the first switching element K1 is turned on or off under the control of the first control signal line mux1, the second switching element K2, the sixth switching element K6, and the seventh switching element K7 are all turned on or off under the control of the second control signal line mux2, the third switching element K3 is turned on or off under the control of the third control signal line mux3, and the fourth switching element K4, the fifth switching element K5, and the eighth switching element K8 are all turned on or off under the control of the fourth control signal line mux4. This increases the duration of the output data signal, which is beneficial to improving the effect of threshold compensation, improving the uniformity of the display panel 1000, and reducing the afterimage phenomenon. For example, since the first switching element K1 is turned on or off under the control of the first control signal line mux1, and the fifth switching element K5 is turned on or off under the control of the fourth control signal line mux4, for the first signal line data1, when the first control signal on the first control signal line mux1 is at the on level, the data signal is written. When the fourth control signal on the fourth control signal line mux4 is at the on level, the writing of the data signal stops and the writing of the bias signal begins. As a result, the duration of the output data signal is longer than the duration of the output bias signal, which helps to improve the effect of threshold compensation, improve the uniformity of the display panel 1000, and improve the afterimage phenomenon.

[0072] In some optional embodiments, each pixel circuit 10 in the first pixel circuit column 110 can be connected to both the first signal line data1 and the third signal line data3. That is, the first terminal of each pixel circuit 10 in the first pixel circuit column 110 can be connected to the first signal line data1, and the second terminal of each pixel circuit 10 in the first pixel circuit column 110 can be connected to the third signal line data3. In this way, each pixel circuit 10 in the first pixel circuit column 110 can receive the data signal from the first signal terminal source and the bias signal from the second signal terminal DVH.

[0073] For example, for ease of explanation, such as Figure 3 , Figure 4 , Figure 11 and Figure 14 As shown, the first pixel circuit array 110 may include a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2. The first red pixel circuit R1, the first blue pixel circuit B1, the second red pixel circuit R2, and the second blue pixel circuit B2 are all connected to the first signal line data1, and all three are connected to the third signal line data3.

[0074] Each pixel circuit 10 in the second pixel circuit column 120 is connected to both the second signal line data2 and the fourth signal line data4. That is, the first terminal of each pixel circuit 10 in the second pixel circuit column 120 can be connected to the second signal line data2, and the second terminal of each pixel circuit 10 in the second pixel circuit column 120 can be connected to the fourth signal line data4. Thus, each pixel circuit 10 in the second pixel circuit column 120 can receive the data signal from the first signal terminal source and the bias signal from the second signal terminal DVH.

[0075] For example, such as Figure 3 As shown, the second pixel circuit array 120 may include a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The first green pixel circuit G1, the second green pixel circuit G2, the third green pixel circuit G3, and the fourth green pixel circuit G4 may all be connected to the second signal line data2, and the first green pixel circuit G1, the second green pixel circuit G2, the third green pixel circuit G3, and the fourth green pixel circuit G4 may all be connected to the fourth signal line data4.

[0076] In some alternative implementations, such as Figure 5 As shown, the pixel circuit 10 may include a driving module 11, a data writing module 12, and a bias module 13. The data writing module 12 can be used to transmit data signals to the driving module 11, and the bias module 13 can be used to transmit bias signals to the driving module 11.

[0077] The data writing module 12 of the odd-numbered row pixel circuit 10 in the first pixel circuit column 110 can be connected to the first signal line data1, and the bias module 13 of the odd-numbered row pixel circuit 10 in the first pixel circuit column 110 is connected to the third signal line data3.

[0078] The data writing module 12 of the even-numbered row pixel circuit 10 in the first pixel circuit column 110 can be connected to the third signal line data3, and the bias module 13 of the even-numbered row pixel circuit 10 in the first pixel circuit column 110 is connected to the first signal line data1.

[0079] In this embodiment, since the data writing modules 12 of the odd-numbered row pixel circuits 10 and the even-numbered row pixel circuits 10 in the first pixel circuit column 110 are connected to different signal lines, the data signal writing time of each pixel circuit 10 in the first pixel circuit column 110 can be greater than the scanning time of a row pixel circuit 10. This is beneficial to improve the threshold compensation effect of each pixel circuit 10 in the first pixel circuit column 110, improve the uniformity of the display panel 1000, and improve the image retention problem of the display panel 1000.

[0080] Optionally, the data writing module 12 can be electrically connected between one of the two signal lines to which the pixel circuit column is connected and the control end of the driving module 11, and the control end of the data writing module 12 can be electrically connected with the first scanning signal line scan1. The biasing module 13 can be electrically connected between the other of the two signal lines to which the pixel circuit column is connected and the first end of the driving module 11, and the control end of the biasing module 13 can be electrically connected with the second scanning signal line scan2.

[0081] Exemplarily, as shown in Figure 3 For example, still taking the first pixel circuit column 110 including the first red pixel circuit R1, the first blue pixel circuit B1, the second red pixel circuit R2 and the second blue pixel circuit B2 as an example, the data writing module 12 of the first red pixel circuit R1 and the data writing module 12 of the second red pixel circuit R2 can be connected with the first signal line data1, and the biasing module 13 of the first red pixel circuit R1 and the biasing module 13 of the second red pixel circuit R2 can be connected with the third signal line data3. The data writing module 12 of the first blue pixel circuit B1 and the data writing module 12 of the second blue pixel circuit B2 can be connected with the third signal line data3, and the biasing module 13 of the first blue pixel circuit B1 and the biasing module 13 of the second blue pixel circuit B2 can be connected with the first signal line data1.

[0082] Since the data writing module 12 of the first red pixel circuit R1 is connected with the first signal line data1, the data writing module 12 of the first blue pixel circuit B1 is connected with the second signal line data2, and the data writing module 12 of the second red pixel circuit R2 is connected with the first signal line data1, the data signal writing time length of the first red pixel circuit R1 can be greater than the row scanning time length of the first red pixel circuit R1 row, and the first red pixel circuit R1 only needs to stop writing data signal before the data signal writing of the second red pixel circuit R2.

[0083] The data writing module 12 of the odd row pixel circuit 10 in the second pixel circuit column 120 is connected with the second signal line data2, and the biasing module 13 of the odd row pixel circuit 10 in the second pixel circuit column 120 is connected with the fourth signal line data4.

[0084] The data writing module 12 of the even row pixel circuit 10 in the second pixel circuit column 120 is connected with the fourth signal line data4, and the biasing module 13 of the even row pixel circuit 10 in the second pixel circuit column 120 is connected with the second signal line data2.

[0085] In the embodiment, since the data writing module 12 of the odd row pixel circuit 10 in the second pixel circuit column 120 is connected to a different signal line from the data writing module 12 of the even row pixel circuit 10, the data signal writing time length of each pixel circuit 10 in the second pixel circuit column 120 can be greater than the scanning time length of one row of pixel circuits 10, thereby facilitating to improve the threshold compensation effect of each pixel circuit 10 in the second pixel circuit column 120, improve the uniformity of the display panel 1000, and improve the residual image problem of the display panel 1000.

[0086] Exemplarily, as shown in Figure 3 , still taking that the second pixel circuit column 120 includes the first green pixel circuit G1, the second green pixel circuit G2, the third green pixel circuit G3 and the fourth green pixel circuit G4 for example. The data writing module 12 of the first green pixel circuit G1 and the data writing module 12 of the third green pixel circuit G3 can be connected to the second signal line data2, and the biasing module 13 of the first green pixel circuit G1 and the biasing module 13 of the third green pixel circuit G3 can be connected to the fourth signal line data4. The data writing module 12 of the second green pixel circuit G2 and the data writing module 12 of the fourth green pixel circuit G4 can be connected to the fourth signal line data4, and the biasing module 13 of the second green pixel circuit G2 and the biasing module 13 of the fourth green pixel circuit G4 can be connected to the second signal line data2.

[0087] Since the data writing module 12 of the first green pixel circuit G1 is connected to the second signal line data2, the data writing module 12 of the second green pixel circuit G2 is connected to the fourth signal line data4, and the data writing module 12 of the third green pixel circuit G3 is connected to the second signal line data2, the data signal writing time length of the first green pixel circuit G1 can be greater than the row scanning time length of the first green pixel circuit G1, and the first green pixel circuit G1 only needs to stop writing data signal before the data signal of the third green pixel circuit G3 is written.

[0088] Alternatively, as shown in Figure 5As shown, the display panel 1000 may further include a light-emitting module 20, and the pixel circuit 10 may further include a first reset module 14, a second reset module 15, a threshold compensation module 16, a light-emitting control module 17, and a storage module 18. The first reset module 14 is electrically connected between a first reset signal line and the control terminal of the drive module 11, and can be used to write a first reset signal on the first reset signal line to the control terminal of the drive module 11 to reset the control terminal of the drive module 11. The second reset module 15 is electrically connected between a second reset signal line and the first terminal of the light-emitting module 20, and can be used to write a second reset signal on the second reset signal line to the first terminal of the light-emitting module 20 to reset the first terminal of the light-emitting module 20. The threshold compensation module 16 is electrically connected between the control terminal and the second terminal of the drive module 11, and can be used to compensate for the threshold voltage of the drive module 11. The light-emitting control module 17 is connected in series with the light-emitting module 20 between the first power line PVDD and the second power line PVEE, and can be used to control the light-emitting module 20 to enter the light-emitting stage. The storage module 18 can be electrically connected between the first power line PVDD and the control terminal of the drive module 11, and can be used to maintain the potential of the control terminal of the drive module 11. The light emission control module 17 may include a first light emission control module 171 and a second light emission control module 172. The first light emission control module 171 can be electrically connected between the first power line PVDD and the first terminal of the drive module 11, and the second light emission control module 172 can be electrically connected between the second terminal of the drive module 11 and the first terminal of the light emission module 20.

[0089] For example, such as Figure 6 As shown, the driving module 11 may include a ninth transistor M9, the data writing module 12 may include a tenth transistor M10, the biasing module 13 may include an eleventh transistor M11, the first reset module 14 may include a twelfth transistor M12, the second reset module 15 may include a thirteenth transistor M13, the threshold compensation module 16 may include a fourteenth transistor M14, the first light-emitting control module 171 may include a fifteenth transistor M15, the second light-emitting control module 172 may include a sixteenth transistor M16, and the storage module 18 may include a first capacitor. The light-emitting module 20 may include a light-emitting element D. Both the twelfth transistor M12 and the fourteenth transistor M14 may be dual-gate transistors.

[0090] In this design, the control terminal of the driving module 11 can be the gate of the ninth transistor M9, the first terminal of the driving module 11 can be one of the source and drain of the ninth transistor M9, and the second terminal of the driving module 11 can be the other of the source and drain of the ninth transistor M9. The first terminal of the light-emitting module 20 can be the first electrode of the light-emitting element D, and the second terminal of the light-emitting module 20 can be the second electrode of the light-emitting element D. The first electrode of the light-emitting element D can be the anode, and the second electrode of the light-emitting element D can be the cathode.

[0091] In some alternative embodiments, as shown in Figure 7 and Figure 8 The display panel 1000 can include a plurality of rows of pixel circuits 10, and the working process of each row of pixel circuits 10 can include a data writing stage, the data writing stage can include a data writing sub-stage and a first biasing sub-stage, the data writing sub-stage can be before the first biasing sub-stage, in the data writing sub-stage, the driving module 11 of the pixel circuit 10 can write a data signal, in the first biasing sub-stage, the driving module 11 of the pixel circuit 10 can write a bias signal; the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 can be turn-on level in turn.

[0092] In order to distinguish the first biasing sub-stage of different rows of pixel circuits 10, Figure 7 and Figure 8 In the data writing sub-stage d(i) and the first biasing sub-stage c(i) correspond to the i-th row of pixel circuits 10, and the data writing sub-stage d(i+1) and the first biasing sub-stage c(i+1) correspond to the i+1-th row of pixel circuits 10.

[0093] The data writing sub-stage of the i+2-th row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the i-th row of pixel circuits 10, the data writing sub-stage of any two rows of pixel circuits 10 can not overlap, and the first biasing sub-stage of any two rows of pixel circuits 10 can not overlap; wherein i is a positive integer.

[0094] For example, the data writing sub-stage d(1) of the third row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the first row of pixel circuits 10, the data writing sub-stage of the first row of pixel circuits 10 and the data writing sub-stage of the second row of pixel circuits 10 do not overlap, and the first biasing sub-stage of the first row of pixel circuits 10 and the first biasing sub-stage of the second row of pixel circuits 10 do not overlap.

[0095] In the embodiment, the data writing sub-stage of the i+2-th row of pixel circuits 10 at least partially overlaps with the first biasing sub-stage of the i-th row of pixel circuits 10, that is, when the driving module 11 of the i+2-th row of pixel circuits 10 writes a data signal, the driving module 11 of the i-th row of pixel circuits 10 writes a bias signal, the data signal and the bias signal are transmitted to the same pixel circuit 10 by different signal lines at different times, without increasing additional signal lines, the first electrode or the second electrode of the driving module 11 in the pixel circuit 10 can be periodically reset, which is beneficial to improve the offset and hysteresis of the characteristics of the driving module 11 after long-term work, and is also beneficial to the pixel arrangement design.

[0096] As an example, please refer to Figure 3、 Figure 6 and Figure 7 For the two adjacent rows of pixel circuits 10, the change process of the control signal on the first control signal line mux1 to the control signal on the fourth control signal line mux4 can include stages a1 to a4, and the working process of the display panel 1000 can be as follows:

[0097] In the first sub-stage of stage a1, the control signal on the first control signal line mux1 can be at the on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 can all be at the off level, the first transistor M1 and the sixth transistor M6 are both turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the i-th row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal end DVH is transmitted to the source or drain of the eleventh transistor M11 in the first red pixel circuit R1 of the i-th row through the third signal line data3 and the sixth transistor M6.

[0098] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the i-th row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the i+1-th row of pixel circuits 10 are all at the off level, the i-th row of pixel circuits 10 and the i+1-th row of pixel circuits 10 are not written with data signals and bias signals.

[0099] In the second sub-stage of stage a1, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the second transistor M2 and the seventh transistor M7 are both turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6, and the eighth transistor M8 are all turned off, the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the i-th row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal end DVH is transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 of the i-th row through the fourth signal line data4 and the seventh transistor M7.

[0100] In the data writing sub-stage d(i), the first scan signal on the first scan signal line scan1 connected with the i-th row of pixel circuits 10 is at the turn-on level, the data writing module 12 of the i-th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the data signal.

[0101] In the first sub-stage of stage a2, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the turn-off level, the control signal on the third control signal line mux3 is at the turn-on level, the control signal on the fourth control signal line mux4 is at the turn-off level, the third transistor M3 and the fifth transistor M5 are both turned on, the first transistor M1, the second transistor M2, the fourth transistor M4, and the sixth transistor M6 to the eighth transistor M8 are all turned off, and the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the i+1-th row of first blue pixel circuits B1 through the third signal line data3 and the third transistor M3, and the bias signal of the second signal end DVH is transmitted to the source or drain of the eleventh transistor M11 in the i+1-th row of first blue pixel circuits B1 through the first signal line data1 and the fifth transistor M5.

[0102] Since the first scan signal on the first scan signal line scan1 connected with the i-th row of pixel circuits 10 and the second scan signal on the second scan signal line scan* are both at the turn-off level, and the first scan signal on the first scan signal line scan1 connected with the i+1-th row of pixel circuits 10 and the second scan signal on the second scan signal line scan* are both at the turn-off level, the i-th row of pixel circuits 10 and the i+1-th row of pixel circuits 10 do not write the data signal and the bias signal.

[0103] In the second sub-stage of stage a2, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the turn-off level, the control signal on the fourth control signal line mux4 is at the turn-on level, the fourth transistor M4 and the eighth transistor M8 are both turned on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the i+1-th row of second green pixel circuits G2 through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second green pixel circuit G2 through the second signal line data2 and the eighth transistor M8.

[0104] In the data writing sub-stage d(i+1), the second scan signal on the first scan signal line scan1 of the i+1th row is at the turn-on level, and the data writing module 12 of the i+1th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0105] In the first sub-stage of stage a3, the control signal on the first control signal line mux1 is at the turn-on level, the control signals on the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are all at the turn-off level, the first transistor M1 and the sixth transistor M6 are both turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the i+2th row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second red pixel circuit R2 of the i+2th row through the third signal line data3 and the sixth transistor M6.

[0106] Since the first scan signal on the first scan signal line scan1 connected to the i th row of pixel circuits 10 and the second scan signal on the second scan signal line scan* are both at the turn-off level, and the first scan signal on the first scan signal line scan1 connected to the i+1th row of pixel circuits 10 and the second scan signal on the second scan signal line scan* are both at the turn-off level, therefore, the i th row of pixel circuits 10 and the i+1th row of pixel circuits 10 do not write data signals and bias signals.

[0107] In the second sub-stage of stage a3, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the first scan signal on the first scan signal line scan1 of the first row is at the off level, the second transistor M2 and the seventh transistor M7 are both turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be written into the ninth transistor M9 in the third green pixel circuit G3 through the second signal line data2, the second transistor M2 and the tenth transistor M10 in the second green pixel circuit G3 of the i+2th row, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 in the third green pixel circuit G3 of the i+2th row through the fourth signal line data4 and the seventh transistor M7.

[0108] In the first biasing sub-stage c(i), the second scan signal on the second scan signal line scan* of the i th row is at the on level, and the biasing module 13 of the i th row of pixel circuits 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both written with a biasing signal.

[0109] In the first sub-stage of stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 and the fifth transistor M5 are both turned on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all turned off, the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the i+3th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second blue pixel circuit B2 of the i+3th row through the first signal line data1 and the fifth transistor M5.

[0110] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the i-th row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the i+1-th row of pixel circuits 10 are all at the off level, the i-th row of pixel circuits 10 and the i+1-th row of pixel circuits 10 do not write the data signal and the bias signal.

[0111] In the second sub-stage of stage a4, the control signal on the first control signal line mux1, the control signal on the second control signal line mux2, and the control signal on the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4 and the eighth transistor M8 are both turned on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the i+3-th row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 of the fourth green pixel circuit G4 through the second signal line data2 and the eighth transistor M8.

[0112] In the first biasing sub-stage c(i+1), the second scan signal on the second scan signal line scan* of the i+1-th row is at the on level, and the biasing module 13 of the i+1-th row of pixel circuits 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2 both write the bias signal.

[0113] By analogy.

[0114] Exemplarily, i can be 1.

[0115] As another example, please refer to Figure 4 , Figure 6 and Figure 8 , for the two adjacent rows of pixel circuits 10, the change process of the control signal on the first control signal line mux1 to the control signal on the fourth control signal line mux4 can include stages a1 to a4, and the working process of the display panel 1000 can be as follows:

[0116] In the first sub-stage of stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 is turned on, the second transistor M2 to the eighth transistor M8 are all turned off, and the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the ith row through the first signal line data1 and the first transistor M1.

[0117] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the ith row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the ith+1 row of pixel circuits 10 are all at an off level, the ith row of pixel circuits 10 and the ith+1 row of pixel circuits 10 are not written with data signals and bias signals.

[0118] In the second sub-stage of stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3, the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are all turned off, the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the ith row through the second signal line data2 and the second transistor M2, the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 of the first green pixel circuit G1 of the ith row through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal end DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the first red pixel circuit R1 of the ith row through the third signal line data3 and the sixth transistor M6.

[0119] In the first sub-stage of the data writing sub-stage d(i), the first scan signal on the first scan signal line scan1 connected to the ith row of pixel circuits 10 is at an on level, the data writing module 12 of the ith row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write data signals.

[0120] In the first sub-stage of stage a2, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 is turned on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source is transmitted to the source electrode of the tenth transistor M10 in the first blue pixel circuit B1 of the i+1th row through the third signal line data3 and the third transistor M3.

[0121] In the second sub-stage of the data writing sub-stage d(i), the first scan signal on the first scan signal line scan1 connected with the i-th row of pixel circuits 10 is at the on level, the data writing module 12 of the i-th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the data signal.

[0122] In the second sub-stage of stage a2, the control signals on the first control signal line mux1, the second control signal line mux2 and the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4, the fifth transistor M5 and the eighth transistor M8 are all turned on, the first transistor M1 to the third transistor M3, the sixth transistor M6 and the seventh transistor M7 are all turned off, the data signal of the first signal terminal source can be transmitted to the source electrode or the drain electrode of the tenth transistor M10 in the second green pixel circuit G2 of the i+1th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source electrode or the drain electrode of the eleventh transistor M11 of the second green pixel circuit G2 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal terminal DVH can also be transmitted to the source electrode or the drain electrode of the eleventh transistor M11 of the first red pixel circuit R1 through the first signal line data1 and the fifth transistor M5.

[0123] In the first sub-stage of the data writing sub-stage d(i+1), the first scan signal on the first scan signal line scan1 of the i+1th row is at the on level, the data writing module 12 of the i+1th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0124] In the first sub-stage of stage a3, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are all at an off level, the first transistor M1 is turned on, the second transistor M2 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source is transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the i+2th row through the first signal line data1 and the first transistor M1.

[0125] In the second sub-stage of the data writing sub-stage d(i+1), the first scan signal on the first scan signal line scan1 of the i+1th row is at an on level, the data writing module 12 of the i+1th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0126] In the second sub-stage of stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G3 of the i+2th row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 of the i+2th row through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the second red sub-pixel R2 of the i+2th row through the third signal line data3 and the sixth transistor M6.

[0127] In the first biasing sub-stage c(i), the second scan signal on the second scan signal line scan* of the i-th row is at an on level, the biasing module 13 of the i-th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the bias signal.

[0128] In the first sub-stage of stage a4, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the cutoff level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the cutoff level, the third transistor M3 is on, and the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all off. The data signal at the first signal terminal source can be transmitted through the third signal line data3 and the third transistor M3 to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 in the i+3 row.

[0129] In the second sub-stage of stage a4, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the cutoff level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all on, and the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all off. The data signal at the first signal terminal source can be transmitted through the fourth signal line data4 and the fourth transistor M4 to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 in the fourth row. The bias signal at the second signal terminal DVH can be transmitted through the second signal line data2 and the eighth transistor M8 to the source or drain of the eleventh transistor M11 in the fourth green pixel circuit G4. The bias signal at the second signal terminal DVH can also be transmitted through the first signal line data1 and the fifth transistor M5 to the source or drain of the eleventh transistor M11 in the second blue pixel circuit B2.

[0130] In the first bias sub-stage c(i+1), the second scan signal on the second scan signal line scan* of the i+1th row is at the on level, and the bias module 13 of the pixel circuit 10 of the i+1th row is turned on. That is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2 are both written with bias signals.

[0131] And so on.

[0132] For example, i can be 1.

[0133] Figure 7 and Figure 8 The difference is that, Figure 7 The duration of the data writing sub-stage for each row of pixel circuit 10 is equal to the duration of the first bias sub-stage, while Figure 8The duration of the data writing sub-stage of each row of pixel circuits 10 is greater than the duration of the first biasing sub-stage. As a result Figure 8 The duration of the data writing sub-stage of each row of pixel circuits 10 is greater than the duration of the first biasing sub-stage, which is conducive to improving the threshold compensation effect, improving the uniformity of the display panel 1000, and improving the residual image phenomenon.

[0134] In other optional embodiments, as shown in Figure 9 and Figure 10 The display panel 1000 can include multiple rows of pixel circuits 10. In the display time of one frame of picture, the working process of each row of pixel circuits 10 can include a data writing stage. The data writing sub-stage can be after the first biasing sub-stage. The data writing stage can include the data writing sub-stage and the first biasing sub-stage. In the data writing sub-stage, the driving module 11 of the pixel circuit 10 can write a data signal. In the first biasing sub-stage, the driving module 11 of the pixel circuit 10 can write a bias signal. The control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3, and the fourth control signal line mux4 can be in turn at the on level.

[0135] The data writing sub-stage of the jth row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the j+2th row of pixel circuits 10. The data writing sub-stage of any two rows of pixel circuits 10 can not overlap. The first biasing sub-stage of any two rows of pixel circuits 10 can not overlap.

[0136] Wherein, j is a positive integer.

[0137] In the embodiment, the data writing sub-stage of the jth row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the j+2th row of pixel circuits 10. That is, when the driving module 11 of the jth row of pixel circuits 10 writes a data signal, the driving module 11 of the j+2th row of pixel circuits 10 writes a bias signal. By time-sharing transmission of the data signal and the bias signal to the same pixel circuit 10 through different signal lines, without increasing additional signal lines, the first electrode or the second electrode of the driving module 11 in the pixel circuit 10 can be periodically reset, which is conducive to improving the offset and hysteresis phenomenon of the characteristics of the driving module 11 after long-term work, and is also conducive to pixel arrangement design.

[0138] Figure 9 The difference between Figure 7 and Figure 7 is that Figure 9 the data writing sub-stage of each row of pixel circuits 10 is after the first biasing sub-stage. Figure 9 The corresponding implementation principle is the same as Figure 7The corresponding implementation principle is similar, and will not be described here.

[0139] Figure 10 Different from Figure 8 , the data writing sub-stage of each row of pixel circuits 10 in Figure 8 is before the first biasing sub-stage, while the data writing sub-stage of each row of pixel circuits 10 in Figure 10 is after the first biasing sub-stage. Figure 10 The corresponding implementation principle is similar to Figure 8 , and will not be described here.

[0140] In some optional embodiments, as shown in Figure 11 , the odd-numbered row pixel circuits 10 in the first pixel circuit column 110 can be connected with the first signal line data1, and the even-numbered row pixel circuits 10 in the first pixel circuit column 110 can be connected with the third signal line data3.

[0141] For example, still taking the case that the first pixel circuit column 110 includes the first red pixel circuit R1, the first blue pixel circuit B1, the second red pixel circuit R2 and the second blue pixel circuit B2 as an example. The first red pixel circuit R1 and the second red pixel circuit R2 are both connected with the first signal line data1, and the first blue pixel circuit B1 and the second blue pixel circuit B2 are both connected with the third signal line data3.

[0142] The odd-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected with the second signal line data2, and the even-numbered row pixel circuits 10 in the second pixel circuit column 120 are connected with the fourth signal line data4.

[0143] For example, still taking the case that the second pixel circuit column 120 includes the first green pixel circuit G1, the second green pixel circuit G2, the third green pixel circuit G3 and the fourth green pixel circuit G4 as an example. The first green pixel circuit G1 and the third green pixel circuit G3 are both connected with the second signal line data2, and the second green pixel circuit G2 and the fourth green pixel circuit G4 are both connected with the fourth signal line data4.

[0144] That is, the data signal and the bias signal are transmitted to each pixel circuit 10 of the first pixel circuit column 110 and each pixel circuit 10 of the second pixel circuit column 120 through the same signal line at different times. For example, the data signal and the bias signal are transmitted to the first red pixel circuit R1 through the first signal line data1 at different times.

[0145] In the embodiment, the odd row pixel circuits 10 in the first pixel circuit column 110 are connected with the first signal line data1, the even row pixel circuits 10 in the first pixel circuit column 110 are connected with the third signal line data3, the odd row pixel circuits 10 in the second pixel circuit column 120 are connected with the second signal line data2, and the even row pixel circuits 10 in the second pixel circuit column 120 are connected with the fourth signal line data4. Each signal line can transmit data signals and bias signals to the pixel circuits 10 in the pixel circuit column in time, without increasing additional signal lines, and the first electrode or the second electrode of the driving module 11 can be periodically reset, which is beneficial to improve the offset and hysteresis of the characteristics of the driving module 11 after long-term work, and is also beneficial to the pixel arrangement design.

[0146] In some optional embodiments, as shown in Figure 14 The pixel circuit 10 can include a driving module 11, a data writing module 12 and a bias module 13. The data writing module 12 can be used to transmit data signals to the driving module 11, and the bias module 13 can be used to transmit bias signals to the driving module 11. The data signals and the bias signals can be the same.

[0147] The data writing module 12 and the bias module 13 of the odd row pixel circuit 10 in the first pixel circuit column 110 are connected with the first signal line data1 respectively, and the data writing module 12 and the bias module 13 of the even row pixel circuit 10 in the first pixel circuit column 110 are connected with the third signal line data3 respectively.

[0148] For example, still taking the first pixel circuit column 110 including the first red pixel circuit R1, the first blue pixel circuit B1, the second red pixel circuit R2 and the second blue pixel circuit B2 as an example. The data writing module 12 of the first red pixel circuit R1 and the bias module 13 of the first red pixel circuit R1 can be connected with the first signal line data1 respectively, and the data writing module 12 of the first blue pixel circuit B1 and the bias module 13 of the first blue pixel circuit B1 can be connected with the third signal line data3 respectively.

[0149] The data writing module 12 and the bias module 13 of the odd row pixel circuit 10 in the second pixel circuit column 120 are connected with the second signal line data2 respectively, and the data writing module 12 and the bias module 13 of the even row pixel circuit 10 in the second pixel circuit column 120 are connected with the fourth signal line data4 respectively.

[0150] For example, the second pixel circuit array 120 is still described as including a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The data writing module 12 and the biasing module 13 of the first green pixel circuit G1 can be connected to the second signal line data2, respectively. The data writing module 12 and the biasing module 13 of the second green pixel circuit G2 can be connected to the fourth signal line data4, respectively.

[0151] In this embodiment, for the same pixel circuit 10, the data writing module 12 and the bias module 13 are both connected to the same signal line, which can reduce the number of signal lines in the same pixel circuit 10; in addition, the data signal and the bias signal are the same, which can avoid the signal crosstalk problem caused by the difference between the data signal and the bias signal.

[0152] Optionally, such as Figure 12 As shown, the display panel 1000 may also include a light-emitting module 20, and the pixel circuit 10 may also include a first reset module 14, a second reset module 15, a threshold compensation module 16, a light-emitting control module, and a storage module 18. Figure 12 The display panel 1000 and Figure 5 and Figure 6 The difference between the display panel 1000 and the previous one is that... Figure 5 and Figure 6 The data writing module 12 and the bias module 13 are respectively connected to different signal lines, while Figure 12 The data writing module 12 and the bias module 13 are connected to the same signal line Data or Data*. Specifically, signal line Data can be connected to the first signal line data1 or the third signal line data3, and signal line Data* can be connected to the second signal line data2 or the fourth signal line data4. Figure 12 The specific circuit structure of the display panel 1000 and Figure 5 and Figure 6 The specific circuit structure is similar, and will not be described in detail here.

[0153] In some alternative implementations, such as Figure 13 and 15As shown, the display panel 1000 can include a plurality of rows of pixel circuits 10, and the working process of each row of pixel circuits 10 can include a data writing stage, the data writing stage can include a data writing sub-stage and a first biasing sub-stage, the data writing sub-stage is before the first biasing sub-stage, in the data writing sub-stage, the driving module 11 of the pixel circuit 10 writes a data signal, and in the first biasing sub-stage, the driving module 11 of the pixel circuit 10 writes a bias signal; the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are turn on level in turn;

[0154] The data writing sub-stage of the (n+1)th row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the nth row of pixel circuits 10, the data writing sub-stage of any two rows of pixel circuits 10 can not overlap, and the first biasing sub-stage of any two rows of pixel circuits 10 can not overlap;

[0155] Wherein, n is a positive integer.

[0156] In this embodiment, the data writing sub-stage of the (n+1)th row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the nth row of pixel circuits 10, that is, when the driving module 11 of the (n+1)th row of pixel circuits 10 writes a data signal, the driving module 11 of the nth row of pixel circuits 10 writes a bias signal, the data signal and the bias signal are transmitted to the same pixel circuit 10 by the same signal line at different times, without increasing additional signal lines, the first electrode or the second electrode of the driving module 11 in the pixel circuit 10 can be periodically reset, which is conducive to improving the offset and hysteresis of the characteristics of the driving module 11 after long-term work, and is also conducive to the pixel arrangement design.

[0157] As an example, please refer to Figure 11 , Figure 12 and Figure 13 , the working process of the display panel 1000 can be as follows:

[0158] In the first sub-stage of stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 and the sixth transistor M6 are both turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the nth row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first blue pixel circuit B1 of the nth+1 row through the third signal line data3 and the sixth transistor M6.

[0159] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth+1 row of pixel circuits 10 are both at an off level, the nth row of pixel circuits 10 and the nth+1 row of pixel circuits 10 are not written with data signals and bias signals.

[0160] In the second sub-stage of stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are both turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6, and the eighth transistor M8 are all turned off, the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the nth row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal end DVH is transmitted to the source or drain of the eleventh transistor M11 in the second green pixel circuit G2 of the nth+1 row through the fourth signal line data4 and the seventh transistor M7.

[0161] In the data writing sub-stage d(n), the first scan signal on the first scan signal line scan1 connected to the nth row of pixel circuits 10 is at an on level, the data writing module 12 of the nth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write data signals.

[0162] In a first sub-stage of stage a2, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 and the fifth transistor M5 are both turned on, the first transistor M1, the second transistor M2, the fourth transistor M4, and the sixth transistor M6 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the nth+1 row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first red pixel circuit R1 of the nth row through the first signal line data1 and the fifth transistor M5.

[0163] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth+1 row of pixel circuits 10 are both at the off level, the nth row of pixel circuits 10 and the nth+1 row of pixel circuits 10 are not written with data signals and bias signals.

[0164] In a second sub-stage of stage a2, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the off level, the fourth transistor M4 and the eighth transistor M8 are both turned on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the nth+1 row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 through the second signal line data2, the eighth transistor M8, and the eleventh transistor M11 of the first green pixel circuit G1.

[0165] In the first bias sub-stage c(n), the second scan signal on the second scan signal line scan* connected to the nth row of pixel circuits 10 is at the on level, the bias module 13 of the nth row of pixel circuits 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the bias signal.

[0166] In the data writing sub-stage d(n+1), the first scan signal on the first scan signal line scan1 of the n+1th row is at the turn-on level, the data writing module 12 of the n+1th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0167] In the first sub-stage of stage a3, the control signal on the first control signal line mux1 is at the turn-on level, the control signals on the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are all at the turn-off level, the first transistor M1 and the sixth transistor M6 are both turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the n+2th row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal end DVH is transmitted to the source or drain of the eleventh transistor M11 in the first blue pixel circuit B1 of the n+1th row through the third signal line data3 and the sixth transistor M6.

[0168] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row pixel circuit 10, and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the n+1th row pixel circuit 10 are all at the turn-off level, therefore, the nth row pixel circuit 10 and the n+1th row pixel circuit 10 do not write the data signal and the bias signal.

[0169] In the second sub-stage of stage a3, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the second transistor M2 and the seventh transistor M7 are both turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the nth+2 row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G2 of the nth+1 row through the fourth signal line data4 and the seventh transistor M7.

[0170] In the first biasing sub-stage c(n+1), the second scan signal on the second scan signal line scan* of the nth+1 row is at the on level, and the biasing module 13 of the nth+1 row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2 both write the biasing signal.

[0171] In the first sub-stage of stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 and the fifth transistor M5 are both turned on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the nth+3 row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH is transmitted to the source or drain of the eleventh transistor M11 in the second red pixel circuit R2 of the nth+2 row through the first signal line data1 and the fifth transistor M5.

[0172] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row pixel circuit 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth+1 row pixel circuit 10 are both at the off level, the nth row pixel circuit 10 and the nth+1 row pixel circuit 10 do not write the data signal and the bias signal.

[0173] In the second sub-stage of stage a4, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4 and the eighth transistor M8 are both turned on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the nth+3 row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the tenth transistor M10 of the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8.

[0174] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row of pixel circuits 10, and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth+1 row of pixel circuits 10 are all at the off level, the nth row of pixel circuits 10 and the nth+1 row of pixel circuits 10 are not written with data signals and bias signals.

[0175] By analogy.

[0176] Exemplarily, j can be 1.

[0177] As another example, please refer to Figure 12 , Figure 14 and Figure 15 , the working process of the display panel 1000 can be as follows:

[0178] In the first sub-stage of stage a1, the control signal on the first control signal line mux1 is at the on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at the off level, the first transistor M1 is turned on, the second transistor M2 to the eighth transistor M8 are all turned off, and the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the first row through the first signal line data1 and the first transistor M1.

[0179] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the (n+1)th row of pixel circuits 10 are all at the off level, the nth row of pixel circuits 10 and the (n+1)th row of pixel circuits 10 do not write the data signal and the bias signal.

[0180] In the second sub-stage of stage a1, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the first scan signal on the first scan signal line scan1 of the first row is at the on level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3 to the fifth transistor M5 and the eighth transistor M8 are all turned off, the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the nth row through the second signal line data2 and the second transistor M2, the bias signal of the second signal end DVH can be transmitted to the source or drain of the eleventh transistor M11 in the second green pixel circuit G2 of the second row through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal end DVH can also be transmitted to the source or drain of the eleventh transistor M11 in the first blue pixel circuit B1 through the third signal line data3 and the sixth transistor M6.

[0181] In the first sub-stage of the data writing sub-stage d(n), the first scan signal on the first scan signal line scan1 connected to the nth row of pixel circuits 10 is at the on level, and the data writing module 12 of the nth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the data signal.

[0182] In the first sub-stage of stage a2, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 is turned on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the n+1th row through the third signal line data3 and the third transistor M3.

[0183] In the second sub-stage of the data writing sub-stage d(n), the first scan signal on the first scan signal line scan1 connected with the n th row of pixel circuit 10 is at the on level, the data writing module 12 of the n th row of pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the data signal.

[0184] In the second sub-stage of stage a2, the control signals on the first control signal line mux1, the second control signal line mux2 and the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4, the fifth transistor M5 and the eighth transistor M8 are all turned on, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the seventh transistor M7 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the n+1th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 in the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the eleventh transistor M11 in the first red pixel circuit R1 through the first signal line data1 and the fifth transistor M5.

[0185] In the first biasing sub-stage c(n), the second scan signal on the second scan signal line scan* of the n th row is at the on level, the biasing module 13 of the n th row of pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the bias signal.

[0186] In the first sub-stage of the data writing sub-stage d(n+1), the first scan signal on the first scan signal line scan1 of the n+1th row is at the turn-on level, and the data writing module 12 of the n+1th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0187] In the first sub-stage of stage a3, the control signal on the first control signal line mux1 is at the turn-on level, the control signals on the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are all at the turn-off level, the first transistor M1 is turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the n+2th row through the first signal line data1 and the first transistor M1.

[0188] In the second sub-stage of the data writing sub-stage d(n+1), the first scan signal on the first scan signal line scan1 of the n+1th row is at the turn-on level, and the data writing module 12 of the n+1th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0189] In the second sub-stage of stage a3, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3 to the fifth transistor M5 and the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the n+3th row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the eleventh transistor M11 of the second green pixel circuit G2 of the n+1th row through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the first blue pixel circuit B1 of the n+1th row through the third signal line data3 and the sixth transistor M6.

[0190] In the first biasing sub-stage c(n+1), the second scan signal on the second scan signal line scan* of the n+1th row is at the on level, and the biasing module 13 of the n+1th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2 both write the biasing signal.

[0191] In the first sub-stage of stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 is turned on, and the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the n+3th row through the third signal line data3 and the third transistor M3.

[0192] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the n th row pixel circuit 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the n+1th row pixel circuit 10 are both at the off level, the n th row pixel circuit 10 and the n+1th row pixel circuit 10 do not write the data signal and the biasing signal.

[0193] In a second sub-stage of stage a4, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all turned on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the nth+3 row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal end DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal end DVH can also be transmitted to the source or drain of the eleventh transistor M11 of the second red pixel circuit R2 through the first signal line data1 and the fifth transistor M5.

[0194] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the nth+1 row of pixel circuits 10 are all at the off level, the nth row of pixel circuits 10 and the nth+1 row of pixel circuits 10 are not written with data signals and bias signals.

[0195] By analogy.

[0196] Exemplarily, j can be 1.

[0197] In other optional embodiments, as shown in Figure 16 and Figure 17 Exemplarily, the display panel 1000 can include a plurality of rows of pixel circuits 10; the working process of each row of pixel circuits 10 in the display time of one frame of picture can include a data writing stage, the data writing stage can include a data writing sub-stage and a first bias sub-stage, the data writing sub-stage can be after the first bias sub-stage, in the data writing sub-stage, the driving module 11 of the pixel circuit 10 writes a data signal, in the first bias sub-stage, the driving module 11 of the pixel circuit 10 writes a bias signal; the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3, and the fourth control signal line mux4 are sequentially at the on level;

[0198] The data writing sub-stage of the mth row of pixel circuits 10 at least partially overlaps with the first biasing sub-stage of the (m+1)th row of pixel circuits 10, the data writing sub-stage of any two rows of pixel circuits 10 does not overlap, and the first biasing sub-stage of any two rows of pixel circuits 10 does not overlap.

[0199] wherein m is a positive integer.

[0200] In the embodiment, the data writing sub-stage of the mth row of pixel circuits 10 at least partially overlaps with the first biasing sub-stage of the (m+1)th row of pixel circuits 10, that is, when the driving module 11 of the mth row of pixel circuits 10 writes a data signal, the driving module 11 of the (m+1)th row of pixel circuits 10 writes a biasing signal, the data signal and the biasing signal are transmitted to the same pixel circuit 10 by the same signal line at different times, without the need to increase additional signal lines, the first electrode or the second electrode of the driving module 11 in the pixel circuit 10 can be periodically reset, which is conducive to improving the offset and hysteresis of the characteristics of the driving module 11 after a long period of work, and is also conducive to the pixel arrangement design.

[0201] Figure 16 and the difference between Figure 13 lies in that, Figure 13 the data writing sub-stage of each row of pixel circuits 10 in Figure 16 is before the first biasing sub-stage. Figure 13 The corresponding implementation principle is similar to that of Figure 16 and will not be described here.

[0202] Figure 17 and the difference between Figure 15 lies in that, Figure 16 the data writing sub-stage of each row of pixel circuits 10 in Figure 18 is after the first biasing sub-stage. Figure 17 The corresponding implementation principle is similar to that of Figure 15 and will not be described here.

[0203] In some optional embodiments, as shown in Figure 18 , the pixel circuit 10 can include a driving module 11 and a data writing module 12, and the data writing module 12 can be used to transmit a data signal and a biasing signal to the driving module 11 at different times.

[0204] The data writing module 12 of the odd-numbered row of pixel circuits 10 in the first pixel circuit column 110 can be connected with the first signal line data1, and the data writing module 12 of the even-numbered row of pixel circuits 10 in the first pixel circuit column 110 can be connected with the third signal line data3.

[0205] For example, the first pixel circuit array 110 includes a first red pixel circuit R1, a first blue pixel circuit B1, a second red pixel circuit R2, and a second blue pixel circuit B2. The data writing module 12 of the first red pixel circuit R1 and the data writing module 12 of the second red pixel circuit R2 can both be connected to the first signal line data1. The data writing module 12 of the first blue pixel circuit B1 and the data writing module 12 of the second blue pixel circuit B2 can both be connected to the third signal line data3.

[0206] The data writing module 12 of the odd-numbered row pixel circuit 10 in the second pixel circuit column 120 can be connected to the second signal line data2, and the data writing module 12 of the even-numbered row pixel circuit 10 in the second pixel circuit column 120 can be connected to the fourth signal line data4.

[0207] For example, the second pixel circuit array 120 is still described as including a first green pixel circuit G1, a second green pixel circuit G2, a third green pixel circuit G3, and a fourth green pixel circuit G4. The data writing module 12 of the first green pixel circuit G1 and the data writing module 12 of the third green pixel circuit G3 can both be connected to the second signal line data2, and the data writing module 12 of the second green pixel circuit G2 and the data writing module 12 of the fourth green pixel circuit G4 can both be connected to the fourth signal line data4.

[0208] In other words, the data writing module 12 is multiplexed as the bias module 13, and the data signal and bias signal are transmitted to the odd-numbered row pixel circuit 10 or the even-numbered row pixel circuit 10 through the same signal line in a time-division manner. There is no need to add an additional bias module 13 and additional signal lines. This can periodically reset the first or second pole of the driving module 11, which is beneficial to improving the offset and hysteresis phenomenon of the characteristics of the driving module 11 after long-term operation, and also beneficial to the pixel layout design.

[0209] Optionally, such as Figure 18 As shown, the display panel 1000 may also include a light-emitting module 20, and the pixel circuit 10 may also include a first reset module 14, a second reset module 15, a threshold compensation module 16, a light-emitting control module, and a storage module 18. Figure 18 The display panel 1000 and Figure 12 The difference between the 1000 display panel and the 1000 is that... Figure 12 The display panel 1000 includes a bias module 13, while Figure 18 The display panel 1000 in the middle does not include the bias module 13. Figure 18 The specific circuit structure of the display panel 1000 and Figure 12 The specific circuit structure is similar, and will not be described in detail here.

[0210] In some optional embodiments, as shown in Figure 19 and Figure 20 , the display panel 1000 can include multiple rows of pixel circuits 10, and the working process of each row of pixel circuits 10 can include a data writing stage, the data writing stage can include a data writing sub-stage and a first biasing sub-stage, the data writing sub-stage can be before the first biasing sub-stage, in the data writing sub-stage, the driving module 11 of the pixel circuit 10 can write a data signal, in the first biasing sub-stage, the driving module 11 of the pixel circuit 10 can write a bias signal; the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 can be turn-on level in sequence.

[0211] The data writing sub-stage of the (k+1)th row of pixel circuits 10 at least partially overlaps with the first biasing sub-stage of the kth row of pixel circuits 10, the data writing sub-stage of any two rows of pixel circuits 10 does not overlap, and the first biasing sub-stage of any two rows of pixel circuits 10 does not overlap.

[0212] wherein k is a positive integer.

[0213] In the embodiment, the data writing sub-stage of the (k+1)th row of pixel circuits 10 at least partially overlaps with the first biasing sub-stage of the kth row of pixel circuits 10, that is, when the driving module 11 of the (k+1)th row of pixel circuits 10 writes a data signal, the driving module 11 of the kth row of pixel circuits 10 writes a bias signal, the data signal and the bias signal are transmitted to the same pixel circuit 10 in time division through the same signal line, without increasing additional signal lines, the first electrode or the second electrode of the driving module 11 in the pixel circuit 10 can be periodically reset, which is beneficial to improve the offset and hysteresis phenomenon of the characteristics of the driving module 11 after long-term work, and is also beneficial to the pixel arrangement design.

[0214] As an example, please refer to Figure 14 , Figure 18 and Figure 19 , the working process of the display panel 1000 can be as follows:

[0215] In the first sub-stage of stage a1, the control signal on the first control signal line mux1 is at an on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at an off level, the first transistor M1 and the sixth transistor M6 are both turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be transmitted to the source electrode of the tenth transistor M10 in the first red pixel circuit R1 of the kth row through the first signal line data1 and the first transistor M1.

[0216] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10, and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the k+1th row of pixel circuits 10 are all at an off level, the kth row of pixel circuits 10 and the k+1th row of pixel circuits 10 are not written with data signals and bias signals.

[0217] In the second sub-stage of stage a1, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at an off level, the second transistor M2 and the seventh transistor M7 are both turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6, and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be transmitted to the source electrode or the drain electrode of the tenth transistor M10 in the first green pixel circuit G1 of the kth row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal end DVH can be transmitted to the source electrode or the drain electrode of the tenth transistor M10 of the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the seventh transistor M7.

[0218] In the data writing sub-stage d(k), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10 are both at an on level, the data writing module 12 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 are both written with data signals.

[0219] In a first sub-stage of stage a2, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 and the fifth transistor M5 are both turned on, the first transistor M1, the second transistor M2, the fourth transistor M4, and the sixth transistor M6 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the k+1th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the kth row through the first signal line data1 and the fifth transistor M5.

[0220] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the k+1th row of pixel circuits 10 are both at the off level, the kth row of pixel circuits 10 and the k+1th row of pixel circuits 10 are not written with the data signal and the bias signal.

[0221] In a second sub-stage of stage a2, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4 and the eighth transistor M8 are both turned on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M8.

[0222] In the first biasing sub-stage c(k), the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10 is at the on level, the biasing module 13 of the kth row of pixel circuits 10 is turned on, that is, the eleventh transistor M11 in the first red pixel circuit R1 and the eleventh transistor M11 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the bias signal.

[0223] In the data writing sub-stage d(k+1), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* are both at the turn-on level, and the data writing module 12 of the (k+1)th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0224] In the first sub-stage of stage a3, the control signal on the first control signal line mux1 is at the turn-on level, the control signals on the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are all at the turn-off level, the first transistor M1 and the sixth transistor M6 are both turned on, the second transistor M2 to the fifth transistor M5, and the seventh transistor M7 and the eighth transistor M8 are all turned off, and the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the (k+2)th row through the first signal line data1 and the first transistor M1, and the bias signal of the second signal end DVH can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the (k+1)th row through the third signal line data3 and the sixth transistor M6.

[0225] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10, and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the (k+1)th row of pixel circuits 10 are both at the turn-off level, therefore, the kth row of pixel circuits 10 and the (k+1)th row of pixel circuits 10 do not write the data signal and the bias signal.

[0226] In the second sub-stage of stage a3, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the second transistor M2 and the seventh transistor M7 are both turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the k+2th row through the second signal line data2 and the second transistor M2, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 through the fourth signal line data4 and the seventh transistor M7.

[0227] In the first biasing sub-stage c(k+1), the second scan signal on the second scan signal line scan* of the k+1th row is at the on level, and the biasing module 13 of the k+1th row pixel circuit 10 is turned on, that is, the eleventh transistor M11 in the first blue pixel circuit B1 and the eleventh transistor M11 in the second green pixel circuit G2 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2 both write the biasing signal.

[0228] In the first sub-stage of stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 and the fifth transistor M5 are both turned on, the first transistor M1, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 to the eighth transistor M8 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the k+3th row through the third signal line data3 and the third transistor M3, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the k+2th row through the first signal line data1 and the fifth transistor M5.

[0229] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row pixel circuit 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the k+1th row pixel circuit 10 are both at the off level, the kth row pixel circuit 10 and the k+1th row pixel circuit 10 do not write the data signal and the bias signal.

[0230] In a second sub-stage of stage a4, the control signals on the first control signal line mux1, the second control signal line mux2, and the third control signal line mux3 are all at the off level, the control signal on the fourth control signal line mux4 is at the on level, the fourth transistor M4 and the eighth transistor M8 are both turned on, the first transistor M1 to the third transistor M3, and the fifth transistor M5 to the seventh transistor M7 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the k+3th row through the fourth signal line data4 and the fourth transistor M4, and the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 of the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8.

[0231] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10, and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the k+1th row of pixel circuits 10 are all at the off level, the kth row of pixel circuits 10 and the k+1th row of pixel circuits 10 are not written with the data signal and the bias signal.

[0232] By analogy.

[0233] Exemplarily, k can be 1.

[0234] As another example, please refer to Figure 14 , Figure 18 and Figure 20 , the working process of the display panel 1000 can be as follows:

[0235] In a first sub-stage of stage a1, the control signal on the first control signal line mux1 is at the on level, the control signals on the second control signal line mux2 to the fourth control signal line mux4 are all at the off level, the first transistor M1 is turned on, the second transistor M2 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 of the kth row through the first signal line data1 and the first transistor M1.

[0236] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the k+1th row of pixel circuits 10 are all at the off level, the kth row of pixel circuits 10 and the k+1th row of pixel circuits 10 do not write the data signal and the bias signal.

[0237] In the second sub-stage of stage a1, the control signal on the first control signal line mux1 is at the off level, the control signal on the second control signal line mux2 is at the on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at the off level, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3 to the sixth transistor M6 and the eighth transistor M8 are all turned off, the data signal of the first signal end source can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 of the kth row through the second signal line data2 and the second transistor M2, the bias signal of the second signal end DVH can be transmitted to the source or drain of the tenth transistor M10 of the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal end DVH can also be transmitted to the source or drain of the tenth transistor M10 of the first blue pixel circuit B1 of the k+1th row through the third signal line data3 and the sixth transistor M6.

[0238] In the first sub-stage of the data writing sub-stage d(k), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10 are both at the on level, and the data writing module 12 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the data signal.

[0239] In the first sub-stage of stage a2, the control signals on the first control signal line mux1 and the second control signal line mux2 are both at the off level, the control signal on the third control signal line mux3 is at the on level, the control signal on the fourth control signal line mux4 is at the off level, the third transistor M3 is turned on, the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 of the k+1th row through the third signal line data3 and the third transistor M3.

[0240] In the second sub-stage of the data writing sub-stage d(k), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row of pixel circuits 10 are both at the on level, the data writing module 12 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the data signal.

[0241] In the second sub-stage of stage a2, the control signals on the first control signal line mux1, the second control signal line mux2 and the third control signal line mux3 are all at the off level, the fourth transistor M4, the fifth transistor M5 and the eighth transistor M8 are all turned on, the first transistor M1 to the third transistor M3, and the sixth transistor M6 to the seventh transistor M7 are all turned off, the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 of the k+1th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the first green pixel circuit G1 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the tenth transistor M10 in the first red pixel circuit R1 through the first data line and the fifth transistor M5.

[0242] In the first biasing sub-stage c(k), the second scan signal on the second scan signal line scan* of the kth row is at the on level, the biasing module 13 of the kth row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first red pixel circuit R1 and the tenth transistor M10 in the first green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first red pixel circuit R1 and the ninth transistor M9 in the first green pixel circuit G1 both write the bias signal.

[0243] In the first sub-stage of the data writing sub-stage d(k+1), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* of the k+1th row are both at the turn-on level, and the data writing module 12 of the k+1th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0244] In the first sub-stage of the stage a3, the control signal on the first control signal line mux1 is at the turn-on level, the control signals on the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 are all at the turn-off level, the first transistor M1 is turned on, and the second transistor M2 and the eighth transistor M8 are both turned off, and the data signal of the first signal end source is transmitted to the source or drain of the tenth transistor M10 in the second red pixel circuit R2 of the k+2th row through the first signal line data1 and the first transistor M1.

[0245] In the second sub-stage of the data writing sub-stage d(k+1), the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* of the k+1th row are both at the turn-on level, and the data writing module 12 of the k+1th row of pixel circuits 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G1 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G1 both write the data signal.

[0246] In a second sub-stage of stage a3, the control signal on the first control signal line mux1 is at an off level, the control signal on the second control signal line mux2 is at an on level, the control signals on the third control signal line mux3 and the fourth control signal line mux4 are at off levels, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are all turned on, the first transistor M1, the third transistor M3 to the fifth transistor M5 and the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the third green pixel circuit G3 of the k+2th row through the second signal line data2 and the second transistor M2, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 in the second green pixel circuit G2 through the fourth signal line data4 and the seventh transistor M7, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the tenth transistor M10 in the first blue pixel circuit B1 through the third signal line data3 and the sixth transistor M6.

[0247] In the first biasing sub-stage c(k+1), the second scan signal on the second scan signal line scan* of the k+1th row is at an on level, and the biasing module 13 of the k+1th row pixel circuit 10 is turned on, that is, the tenth transistor M10 in the first blue pixel circuit B1 and the tenth transistor M10 in the second green pixel circuit G2 are both turned on, and the ninth transistor M9 in the first blue pixel circuit B1 and the ninth transistor M9 in the second green pixel circuit G2 both write the biasing signal.

[0248] In the first sub-stage of stage a4, the control signal on the first control signal line mux1 and the control signal on the second control signal line mux2 are both at off levels, the control signal on the third control signal line mux3 is at an on level, the control signal on the fourth control signal line mux4 is at an off level, the third transistor M3 is turned on, and the first transistor M1, the second transistor M2, the fourth transistor M4 to the eighth transistor M8 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the second blue pixel circuit B2 of the k+3th row through the third signal line data3 and the third transistor M3.

[0249] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the kth row pixel circuit 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan* connected to the k+1th row pixel circuit 10 are both at off levels, the kth row pixel circuit 10 and the k+1th row pixel circuit 10 do not write the data signal and the biasing signal.

[0250] In a second sub-stage of stage a4, the control signals on the first control signal line mux1, the second control signal line mux2 and the third control signal line mux3 are all at the off level, the fourth transistor M4, the fifth transistor M5 and the eighth transistor M8 are all turned on, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the seventh transistor M7 are all turned off, and the data signal of the first signal terminal source can be transmitted to the source or drain of the tenth transistor M10 in the fourth green pixel circuit G4 of the k+3th row through the fourth signal line data4 and the fourth transistor M4, the bias signal of the second signal terminal DVH can be transmitted to the source or drain of the tenth transistor M10 of the third green pixel circuit G3 through the second signal line data2 and the eighth transistor M8, and the bias signal of the second signal terminal DVH can also be transmitted to the source or drain of the tenth transistor M10 of the second red pixel circuit R2 through the first signal line data1 and the fifth transistor M5.

[0251] Since the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan2 connected to the kth row of pixel circuits 10 and the first scan signal on the first scan signal line scan1 and the second scan signal on the second scan signal line scan2 connected to the k+1th row of pixel circuits 10 are all at the off level, the kth row of pixel circuits 10 and the k+1th row of pixel circuits 10 are not written with data signals and bias signals.

[0252] By analogy.

[0253] Exemplarily, k can be 1.

[0254] In other optional embodiments, as shown in Figure 21 and Figure 22 , the display panel 1000 can include multiple rows of pixel circuits 10, and the working process of each row of pixel circuits 10 in the display time of one frame of picture can include a data writing stage, the data writing stage can include a data writing sub-stage and a first bias sub-stage, the data writing sub-stage is after the first bias sub-stage, in the data writing sub-stage, the driving module 11 of the pixel circuit 10 writes a data signal, and in the first bias sub-stage, the driving module 11 of the pixel circuit 10 writes a bias signal; the control signals on the first control signal line mux1, the second control signal line mux2, the third control signal line mux3 and the fourth control signal line mux4 can be in turn at the on level;

[0255] The data writing sub-stage of the pth row of pixel circuits 10 can at least partially overlap with the first bias sub-stage of the p+1th row of pixel circuits 10, the data writing sub-stage of any two rows of pixel circuits 10 can not overlap, and the first bias sub-stage of any two rows of pixel circuits 10 can not overlap.

[0256] wherein p is a positive integer.

[0257] In the embodiment, the data writing sub-stage of the pth row of pixel circuits 10 can at least partially overlap with the first biasing sub-stage of the (p+1)th row of pixel circuits 10, that is, when the driving module 11 of the pth row of pixel circuits 10 writes a data signal, the driving module 11 of the (p+1)th row of pixel circuits 10 writes a biasing signal, the data signal and the biasing signal are transmitted to the same pixel circuit 10 in time division through the same signal line, without increasing additional signal lines, the first electrode or the second electrode of the driving module 11 in the pixel circuit 10 can be periodically reset, which is beneficial to improve the offset and hysteresis of the characteristics of the driving module 11 after long-term work, and is also beneficial to the pixel arrangement design.

[0258] Figure 21 and the difference between Figure 19 lies in that, Figure 19 the data writing sub-stage of each row of pixel circuits 10 in Figure 20 is before the first biasing sub-stage. Figure 21 The corresponding implementation principle is similar to that of Figure 19 and will not be described here.

[0259] Figure 22 and the difference between Figure 20 lies in that, Figure 20 the data writing sub-stage of each row of pixel circuits 10 in Figure 22 is after the first biasing sub-stage. Figure 22 The corresponding implementation principle is similar to that of Figure 20 and will not be described here.

[0260] In some optional embodiments, as shown in Figure 23 , the working process of each row of pixel circuits 10 can further include a data retention stage, and at least one of the data retention stages can include a second biasing sub-stage, in which the driving module 11 of the pixel circuit 10 can write a biasing signal, and the first signal end source can be in a floating state or used to provide a biasing signal.

[0261] In the embodiment, the working process of each row of pixel circuits 10 can further include a data retention stage, and the data retention stage can at least include a second biasing sub-stage, in which the driving module 11 of the pixel circuit 10 can write a biasing signal, thereby facilitating low-frequency display of the display panel 1000. In addition, when the first signal end source is used to provide a biasing signal, it is beneficial to prevent short circuit of the display panel 1000.

[0262] In order to distinguish the bias sub-stage of different row pixel circuits 10, Figure 23 In the embodiment, the second bias sub-stage e(i) corresponds to the i-th row pixel circuit 10, and the second bias sub-stage e(i+1) corresponds to the i+1-th row pixel circuit 10.

[0263] As an example, in the case that the display panel 1000 includes both the first signal end source and the second signal end DVH, in the data writing stage, the first signal end source can be used to provide the data signal, and the second signal end DVH can be used to provide the bias signal. In the data retention stage, the data signal end can be in a suspended state or used to provide the bias signal.

[0264] As another example, in the case that the first signal end source of the display panel 1000 can be used to provide the data signal and the bias signal in time sharing, in the data retention stage, the first signal end source can provide the data signal and the bias signal in time sharing, and in the data retention stage, the first signal end source can continuously provide the bias signal.

[0265] Figure 23 In the embodiment, the data writing sub-stage of the same row pixel circuit 10 in the data writing stage is before the first bias sub-stage, but this is not limited thereto. In other embodiments, the data writing sub-stage of the same row pixel circuit 10 in the data writing stage can be after the first bias sub-stage.

[0266] In the embodiment, the values of i, j, n, m, k and p can be equal or not equal, which is not limited herein. For example, i=j=n=m=k=p=100, or i=98, j=99, n=100, m=101, k=102, p=103, and the like.

[0267] It should be noted that the signal on the third scan signal line scan2 is not shown in each timing diagram provided by the embodiment, and it can be understood that, for the same row pixel circuit 10, the off period of the emission control signal line emit should cover the on period of the third scan signal line scan2. For example, Figure 7 For example, the on period of the third scan signal line scan2 can be before the on period of the first scan signal line scan1, and for the same row pixel circuit 10, in the data writing sub-stage, the off period of the emission control signal line emit should cover the on period of the first scan signal line scan1, the on period of the second scan signal line scan2 and the on period of the third scan signal line scan2.

[0268] Optionally, asFigure 24 As shown, the display panel 1000 may include a display area AA and a non-display area NA that at least partially surrounds the display area AA. The non-display area NA may include a first non-display area NA1 and a second non-display area NA2 that are opposite each other in the column direction Y, with the first non-display area NA1 and the second non-display area NA2 spaced apart from the display area AA. The first non-display area NA1 may include a bonding area BA, which can be used to bond a driver chip.

[0269] As an example, the first gating circuit 200 and the second gating circuit 300 may be set in the first non-display area NA1.

[0270] As another example, one of the first gating circuit 200 and the second gating circuit 300 may be located in the first non-display area NA1, and the other may be located in the second non-display area NA2. For example, the first gating circuit 200 may be located in the first non-display area NA1, and the second gating circuit 300 may be located in the second non-display area NA2.

[0271] In some alternative implementations, the first signal terminal (source) and the second signal terminal (DVH) can be located at opposite ends of the pixel circuit column. The signal line connected to the second signal terminal (DVH) can be located in the non-display area NA of the display panel 1000, or it can be located in the display area AA of the display panel 1000. Since the signal line connected to the second signal terminal (DVH) is relatively large, it is preferable to place the signal line connected to the second signal terminal (DVH) in the non-display area NA. For example, as... Figure 3 and Figure 4 As shown, the first signal terminal source can be located at the lower end of the pixel circuit column, and the second signal terminal DVH can be located at the upper end of the pixel circuit column. In some other embodiments, the first signal terminal source can also be located at the lower end of the pixel circuit column, and the second signal terminal DVH can also be located at the upper end of the pixel circuit column; this is not limited here.

[0272] In some alternative embodiments, the first signal terminal (source) and the second signal terminal (DVH) may both be located at the same end of the pixel circuit column. The signal line connected to the second signal terminal (DVH) may be located in the non-display area NA of the display panel 1000. For example, as Figure 11 and Figure 14 As shown, the first signal terminal source and the second signal terminal DVH can both be located at the lower end of the pixel circuit column. In some other embodiments, the first signal terminal source and the second signal terminal DVH can both be located at the upper end of the pixel circuit column.

[0273] This application also provides a display device, including the display panel 1000 provided in this application. Please refer to... Figure 25 , Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 25The display device 10000 provided comprises the display panel 1000 provided in any of the above embodiments of the present application. Figure 25 The embodiments are described only by taking the mobile phone as an example to describe the display device 10000, and it can be understood that the display device provided in the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device or other display devices having a display function, and the present application does not make a specific limitation thereon. The display device provided in the embodiments of the present application has the beneficial effects of the display panel 1000 provided in the embodiments of the present application, and specific descriptions can be made with reference to the specific descriptions of the display panel 1000 in the above embodiments, which will not be described herein again.

[0274] In accordance with the embodiments of the present application as described above, the embodiments do not describe all the details and limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. The embodiments are selected and specifically described in the present specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, The system includes multiple pixel circuit arrays, each pixel circuit array comprising at least two pixel circuit arrays. Each pixel circuit array is connected to two signal lines. Each signal line transmits a data signal and a bias signal to the pixel circuits in the pixel circuit array in a time-division multiplexing manner. The two pixel circuit arrays of the pixel circuit array are connected to the same first signal terminal and the same second signal terminal. The first signal terminal is used to provide the data signal, and the second signal terminal is used to provide the bias signal. The display panel further includes a first gating circuit and a second gating circuit, and the at least two pixel circuit columns include a first pixel circuit column and a second pixel circuit column; The two signal lines connected to the first pixel circuit column are connected to the first signal terminal through the first gating circuit, and the two signal lines connected to the first pixel circuit column are connected to the second signal terminal through the second gating circuit. The two signal lines connected to the second pixel circuit column are connected to the first signal terminal through the first gating circuit, and the two signal lines connected to the second pixel circuit column are connected to the second signal terminal through the second gating circuit. The first gating circuit is used to transmit the data signal provided by the first signal terminal to the four signal lines of the pixel circuit array in a time-division manner, and the second gating circuit is used to transmit the bias signal provided by the second signal terminal to the four signal lines of the pixel circuit array in a time-division manner. The first pixel circuit column is connected to two signal lines, including a first signal line and a third signal line; the second pixel circuit column is connected to two signal lines, including a second signal line and a fourth signal line. The first gating circuit includes a first switching element, a second switching element, a third switching element, and a fourth switching element. The first end of the first switching element, the first end of the second switching element, the first end of the third switching element, and the first end of the fourth switching element are all connected to the first signal terminal. The second end of the first switching element is connected to the first signal line. The second end of the third switching element is connected to the third signal line. The second end of the fourth switching element is connected to the fourth signal line. The second end of the second switching element is connected to the second signal line. The second gating circuit includes a fifth switching element, a sixth switching element, a seventh switching element, and an eighth switching element. The first ends of the fifth switching element, the sixth switching element, the seventh switching element, and the eighth switching element are all connected to the second signal terminal. The second end of the fifth switching element is connected to the first signal line. The second end of the sixth switching element is connected to the third signal line. The second end of the seventh switching element is connected to the fourth signal line. The second end of the eighth switching element is connected to the second signal line. The first switching element is turned on or off under the control of the first control signal line; the second and seventh switching elements are turned on or off under the control of the second control signal line; the third switching element is turned on or off under the control of the third control signal line; and the fourth and eighth switching elements are turned on or off under the control of the fourth control signal line. The sixth switching element is turned on or off under the control of the first control signal line, and the fifth switching element is turned on or off under the control of the third control signal line. or, The sixth switching element is turned on or off under the control of the second control signal line, and the fifth switching element is turned on or off under the control of the fourth control signal line.

2. The display panel according to claim 1, characterized in that, Each pixel circuit in the first pixel circuit column is connected to both the first signal line and the third signal line. Each pixel circuit in the second pixel circuit column is connected to both the second signal line and the fourth signal line.

3. The display panel according to claim 2, characterized in that, The pixel circuit includes a driving module, a data writing module, and a bias module. The data writing module is used to transmit the data signal to the driving module, and the bias module is used to transmit the bias signal to the driving module. The data writing module of the pixel circuit in the odd-numbered row of the first pixel circuit column is connected to the first signal line, and the bias module of the pixel circuit in the odd-numbered row of the first pixel circuit column is connected to the third signal line. The data writing module of the pixel circuit in the even-numbered row of the first pixel circuit column is connected to the third signal line, and the bias module of the pixel circuit in the even-numbered row of the first pixel circuit column is connected to the first signal line. The data writing module of the pixel circuit in the odd-numbered row of the second pixel circuit column is connected to the second signal line, and the bias module of the pixel circuit in the odd-numbered row of the second pixel circuit column is connected to the fourth signal line; The data writing module of the pixel circuit in the even-numbered row of the second pixel circuit column is connected to the fourth signal line, and the bias module of the pixel circuit in the even-numbered row of the second pixel circuit column is connected to the second signal line.

4. The display panel according to claim 3, characterized in that, The display panel includes multiple rows of pixel circuits. During the display time of one frame, the operation process of each row of pixel circuits includes a data writing stage. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is before the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level; The data writing sub-stage of the pixel circuit in the (i+2)th row overlaps at least partially with the first bias sub-stage of the pixel circuit in the ith row, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit. Where i is a positive integer.

5. The display panel according to claim 3, characterized in that, The display panel includes multiple rows of pixel circuits. During the display time of one frame, the operation process of each row of pixel circuits includes a data writing stage. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is after the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level; The data writing sub-stage of the pixel circuit in row j overlaps at least partially with the first bias sub-stage of the pixel circuit in row j+2, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit. Where j is a positive integer.

6. The display panel according to claim 1, characterized in that, In the first pixel circuit column, the pixel circuits in the odd-numbered rows are connected to the first signal line, and the pixel circuits in the even-numbered rows are connected to the third signal line. The pixel circuits in the odd-numbered rows of the second pixel circuit column are connected to the second signal line, and the pixel circuits in the even-numbered rows of the second pixel circuit column are connected to the fourth signal line.

7. The display panel according to claim 6, characterized in that, The pixel circuit includes a driving module, a data writing module, and a bias module. The data writing module is used to transmit the data signal to the driving module, and the bias module is used to transmit the bias signal to the driving module. The data signal and the bias signal are the same. In the first pixel circuit column, the data writing module and the bias module of the pixel circuit in the odd-numbered rows are respectively connected to the first signal line, and the data writing module and the bias module of the pixel circuit in the even-numbered rows are respectively connected to the third signal line. In the second pixel circuit column, the data writing module and the bias module of the pixel circuit in the odd-numbered rows are respectively connected to the second signal line, and the data writing module and the bias module of the pixel circuit in the even-numbered rows are respectively connected to the fourth signal line.

8. The display panel according to claim 7, characterized in that, The display panel includes multiple rows of pixel circuits. During the display time of one frame, the operation process of each row of pixel circuits includes a data writing stage. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is before the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level; The data writing sub-stage of the pixel circuit in row (n+1) overlaps at least partially with the first bias sub-stage of the pixel circuit in row (n). The data writing sub-stages of any two rows of pixel circuits do not overlap, and the first bias sub-stages of any two rows of pixel circuits do not overlap. Where n is a positive integer.

9. The display panel according to claim 7, characterized in that, The display panel includes multiple rows of pixel circuits; During the display time of one frame, the operation process of the pixel circuit in each row includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is after the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level; The data writing sub-stage of the pixel circuit in row m overlaps at least partially with the first bias sub-stage of the pixel circuit in row m+1, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit. Where m is a positive integer.

10. The display panel according to claim 7, characterized in that, The pixel circuit includes a driving module and a data writing module. The data writing module is used to transmit the data signal and the bias signal to the driving module in a time-division manner. The data writing module of the pixel circuit in the odd-numbered row of the first pixel circuit column is connected to the first signal line, and the data writing module of the pixel circuit in the even-numbered row of the first pixel circuit column is connected to the third signal line. The data writing module of the pixel circuit in the odd-numbered row of the second pixel circuit column is connected to the second signal line, and the data writing module of the pixel circuit in the even-numbered row of the second pixel circuit column is connected to the fourth signal line.

11. The display panel according to claim 10, characterized in that, The display panel includes multiple rows of pixel circuits. During the display time of one frame, the operation process of each row of pixel circuits includes a data writing stage. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is before the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level; The data writing sub-stage of the pixel circuit in row (k+1) at least partially overlaps with the first bias sub-stage of the pixel circuit in row (k), the data writing sub-stages of any two rows of pixel circuits do not overlap, and the first bias sub-stages of any two rows of pixel circuits do not overlap; where k is a positive integer.

12. The display panel according to claim 10, characterized in that, The display panel includes multiple rows of pixel circuits. During the display time of one frame, the operation process of each row of pixel circuits includes a data writing stage. The data writing stage includes a data writing sub-stage and a first bias sub-stage. The data writing sub-stage is after the first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal. In the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. The control signals on the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are sequentially at the on level; The data writing sub-stage of the pixel circuit in row p overlaps at least partially with the first bias sub-stage of the pixel circuit in row p+1, and the data writing sub-stages of any two rows of the pixel circuit do not overlap, nor do the first bias sub-stages of any two rows of the pixel circuit. Where p is a positive integer.

13. The display panel according to claim 4, 5, 8, 9, 11, or 12, characterized in that, The data holding phase includes at least one second bias sub-phase, in which the driving module of the pixel circuit writes the bias signal, and the first signal terminal is either floating or used to provide the bias signal.

14. A display device comprising a display panel according to any one of claims 1 to 13.

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