Pixel unit, display panel, compensation method and device of pixel unit

Abstract

The present disclosure relates to a pixel unit, a display panel, a compensation method and device of the pixel unit. The pixel unit comprises: a light emitting circuit; a driving circuit connected with the light emitting circuit; a data writing circuit connected with the driving circuit; a first initialization circuit connected with the driving circuit; a compensation control circuit comprising: a first circuit connecting a first power supply end and an input end of the driving circuit; a second circuit connecting a second signal end and the input end of the driving circuit; wherein the on-off states of the first circuit and the second circuit are opposite; a control circuit connected with the first circuit and the second circuit respectively, for controlling the first circuit to be turned on before the data writing circuit writes the first data signal into the driving circuit, so that the voltage drop of the driving circuit is compensated by the first power supply signal output from the first power supply end.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel unit, a display panel, a pixel unit compensation method, a device, and a storage medium. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are gradually replacing liquid crystal display (LCD) display panels due to their wide color gamut, high contrast, and flexibility.

[0003] Since OLED display panels are driven by current, the signal attenuation of the ELVDD signal received by the pixel units within the OLED display panel has a significant impact on the color and brightness accuracy of the OLED display panel.

[0004] In related technologies, compensation algorithms are usually used to compensate OLED panels, but this compensation method can only compensate the display panel as a whole, which can easily lead to a reduction in the peak brightness of the display panel. Summary of the Invention

[0005] To overcome the problems existing in the related technologies, this disclosure provides a pixel unit, a display panel, a pixel unit compensation method, a device, and a storage medium.

[0006] According to a first aspect of the present disclosure, a pixel unit is provided, comprising:

[0007] Light-emitting circuit;

[0008] A driving circuit, connected to the light-emitting circuit, is used to output a driving electrical signal to the light-emitting circuit to drive the light-emitting circuit to emit light;

[0009] A data writing circuit, connected to the driving circuit, is used to receive a first data signal and a scan signal, and to write the first data signal into the driving circuit according to the scan signal;

[0010] A first initialization circuit, connected to the driving circuit, is used to initialize the potential at the input terminal of the driving circuit.

[0011] The compensation control circuit includes:

[0012] The first line connects the first power supply terminal and the input terminal of the drive circuit;

[0013] The second line connects the second signal terminal and the input terminal of the driving circuit; wherein the on / off states of the first line and the second line are opposite.

[0014] A control circuit, connected to the first line and the second line respectively, is used to control the first line to be turned on before the data writing circuit writes the first data signal into the driving circuit, so that the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

[0015] Optionally, the first line has a first switching transistor, wherein the controlled terminal of the first switching transistor is connected to the control circuit, and the input terminal and output terminal of the first switching transistor are connected to the first line.

[0016] The second line has a second switching transistor, wherein the controlled terminal of the second switching transistor is connected to the control circuit, and the input and output terminals of the second switching transistor are connected to the second line;

[0017] The control circuit outputs a first compensation signal to the first switch and the second switch, turning on the first switch and turning off the second switch.

[0018] The control circuit outputs a second compensation signal to the first switch and the second switch, in which the first switch is turned off and the second switch is turned on.

[0019] Optionally, the control circuit includes:

[0020] The array substrate row driver (GOA) unit includes at least:

[0021] The first control circuit has its input terminals connected to the constant voltage high potential terminal and the constant voltage low potential terminal respectively, and its output terminal connected to the data writing circuit. It is used to output the scan signal to the data writing circuit under the control of the scan signal output by the cascaded upper-level GOA unit.

[0022] The second control circuit has its input terminals connected to the constant high voltage and the first control terminal, respectively, and its output terminals connected to the first line and the second line. Under the control of the scanning signal output by the cascaded upper-level GOA unit, it outputs the first compensation signal or the second compensation signal to the first line and the second line based on the first electrical signal output by the first control terminal.

[0023] Optionally, the driving circuit includes:

[0024] The driver transistor has its input terminals connected to the output terminals of the first line and the second line, respectively, and its output terminal connected to the input terminal of the light-emitting circuit.

[0025] The first capacitor has its first end connected to the output terminal of the data writing circuit and its second end connected to the controlled terminal of the driving transistor.

[0026] The second capacitor has its first end connected to the controlled terminal of the driving transistor and its second end connected to the first power supply terminal.

[0027] A third switching transistor is connected between the controlled terminal and the output terminal of the driving transistor; the controlled terminal is connected to the second control terminal.

[0028] Optionally, the light-emitting circuit includes:

[0029] Light-emitting elements;

[0030] The second initialization circuit includes: a fourth switching transistor connected between the input terminal of the light-emitting element and the initial power supply; the controlled terminal of the fourth switching transistor is connected to the second control terminal;

[0031] The light-emitting control circuit includes: a fifth switching transistor connected between the output terminal of the driving circuit and the input terminal of the light-emitting element, wherein the controlled terminal of the fifth switching transistor is connected to the light-emitting control terminal.

[0032] According to a second aspect of the present disclosure, a display panel is provided, comprising:

[0033] Multiple pixel units as described in the first aspect of the present disclosure; and the multiple pixel units are arranged in a matrix.

[0034] According to a third aspect of the present disclosure, a pixel unit compensation method is provided, applied to the display panel described in the second aspect of the present disclosure, comprising:

[0035] Obtain the row of target pixels to be compensated in a frame of the image to be displayed on the display panel;

[0036] Determine whether the nth row of pixel units in the display panel to be written with the first data signal is the target pixel row to be compensated; wherein, n is a positive integer less than or equal to N, and N is the number of rows of the pixel array of the display panel;

[0037] If the nth row of pixel units is the target pixel row to be compensated, the voltage drop of the nth row of pixel units is compensated using a compensation control circuit.

[0038] Optionally, the compensation of the voltage drop of the nth row of pixel units using the compensation control circuit includes:

[0039] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the first line to be turned on, and the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

[0040] Optionally, the step of using a control circuit to control the conduction of the first line, and compensating for the voltage drop of the drive circuit by the first power supply terminal, includes:

[0041] The first control terminal outputs a first electrical signal with a first preset value. Under the control of the scanning signal output by the cascaded upper-level GOA unit, the second control circuit of the GOA unit outputs a first compensation signal to the first and second switching transistors.

[0042] Under the control of the first compensation signal, the first switch is turned on and the second switch is turned off, and the voltage drop of the drive circuit is compensated by the first power signal output from the first power supply terminal.

[0043] Optionally, the compensation of the voltage drop of the nth row of pixel units using the compensation control circuit includes:

[0044] Determine the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit;

[0045] Based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated;

[0046] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the second line to be turned on, and the voltage drop of the driving circuit is compensated by the compensated second data signal.

[0047] Optionally, determining the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit includes:

[0048] The first power signal received by the first row of pixel units in the pixel array of the display panel and the first power signal output by the first power terminal are obtained.

[0049] Based on the difference between the preset signal value of the first power supply terminal and the signal value of the first power supply signal of the first row pixel unit and the signal value of the first power supply signal of the Nth row pixel unit, the first attenuation amount of the first power supply signal of the first row pixel unit and the second attenuation amount of the first power supply signal of the Nth row pixel unit are determined respectively.

[0050] Based on the first attenuation amount and the second attenuation amount, and the position of the nth row pixel unit within the pixel array, the attenuation amount of the first power signal output from the first power supply terminal received by the nth row pixel unit is determined; wherein, the signal value of the first power signal attenuates linearly row by row within the pixel array.

[0051] Optionally, obtaining the target pixel row to be compensated in a frame of the image to be displayed within the display panel includes:

[0052] Acquire the first data signal of each row of pixel units in a frame to be displayed;

[0053] Based on the histogram of the first data signals, the pixel rows in which the signal difference between the first data signals is less than a preset difference are determined as the target pixel rows to be compensated.

[0054] Optionally, determining whether the nth row of pixel units in the display panel to be written with the first data signal is the target pixel row to be compensated includes:

[0055] Acquire frame synchronization signals and line synchronization signals;

[0056] Based on the frame synchronization signal and the line synchronization signal, the nth row pixel unit in the display panel to be written with the first data signal is determined.

[0057] Based on the position of the target pixel row within the pixel array, determine whether the nth row pixel unit is the target pixel row to be compensated.

[0058] According to a fourth aspect of the present disclosure, a pixel unit compensation device is provided, applied to the display panel described in the second aspect of the present disclosure, comprising:

[0059] The acquisition module is used to acquire the target pixel row to be compensated in a frame of the image to be displayed in the display panel;

[0060] The determining module is used to determine whether the nth row of pixel units in the display panel to be written the first data signal is the target pixel row to be compensated; wherein, n is a positive integer less than or equal to N, and N is the number of rows of the pixel array of the display panel;

[0061] The compensation module is used to compensate for the voltage drop of the nth row of pixel units by means of a compensation control circuit if the nth row of pixel units is the target pixel row to be compensated.

[0062] Optionally, the compensation module is used for:

[0063] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the first line to be turned on, and the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

[0064] Optionally, the compensation module is used for:

[0065] The first control terminal outputs a first electrical signal with a first preset value. Under the control of the scanning signal output by the cascaded upper-level GOA unit, the second control circuit of the GOA unit outputs a first compensation signal to the first and second switching transistors.

[0066] Under the control of the first compensation signal, the first switch is turned on and the second switch is turned off, and the voltage drop of the drive circuit is compensated by the first power signal output from the first power supply terminal.

[0067] Optionally, the compensation module is used for:

[0068] Determine the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit;

[0069] Based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated;

[0070] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the second line to be turned on, and the voltage drop of the driving circuit is compensated by the compensated second data signal.

[0071] Optionally, the compensation module is used for:

[0072] The first power signal received by the first row of pixel units in the pixel array of the display panel and the first power signal output by the first power terminal are obtained.

[0073] Based on the difference between the preset signal value of the first power supply terminal and the signal value of the first power supply signal of the first row pixel unit and the signal value of the first power supply signal of the Nth row pixel unit, the first attenuation amount of the first power supply signal of the first row pixel unit and the second attenuation amount of the first power supply signal of the Nth row pixel unit are determined respectively.

[0074] Based on the first attenuation amount and the second attenuation amount, and the position of the nth row pixel unit within the pixel array, the attenuation amount of the first power signal output from the first power supply terminal received by the nth row pixel unit is determined; wherein, the signal value of the first power signal attenuates linearly row by row within the pixel array.

[0075] Optionally, the acquisition module is used to:

[0076] Acquire the first data signal of each row of pixel units in a frame to be displayed;

[0077] Based on the histogram of the first data signals, the pixel rows in which the signal difference between the first data signals is less than a preset difference are determined as the target pixel rows to be compensated.

[0078] Optionally, the determining module is configured to:

[0079] Acquire frame synchronization signals and line synchronization signals;

[0080] Based on the frame synchronization signal and the line synchronization signal, the nth row pixel unit in the display panel to be written with the first data signal is determined.

[0081] Based on the position of the target pixel row within the pixel array, determine whether the nth row pixel unit is the target pixel row to be compensated.

[0082] According to a fifth aspect of the present disclosure, a compensation device for a pixel unit is provided, comprising:

[0083] processor;

[0084] Memory used to store executable instructions;

[0085] The processor is configured to implement the pixel unit compensation method described in the third aspect above when executing executable instructions stored in the memory.

[0086] According to a fourth aspect of the present disclosure, a readable storage medium is provided, comprising:

[0087] When the instructions in the storage medium are executed by the processor of the pixel unit compensation device, the processor of the pixel unit compensation device is able to execute the pixel unit compensation method as described in the third aspect above.

[0088] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0089] This embodiment of the disclosure provides a first line and a second line within a pixel unit. The first line is connected to the input terminal of the first power supply and the driving circuit; the second line is connected to the input terminal of the second signal and the driving circuit. A control circuit controls the on / off state of the first and second lines to turn on or off voltage drop compensation for the pixel unit. This allows for both voltage drop compensation for pixel units within the display panel, improving brightness uniformity, and voltage drop compensation for a portion of the pixel rows while omitting voltage drop compensation for another portion, thereby increasing the peak brightness of the display panel.

[0090] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0091] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0092] Figure 1 This is a structural diagram of the display panel and pixel unit in related technologies.

[0093] Figure 2 This is a schematic diagram illustrating the effect of the first power signal on the Gamma brightness of the pixel units within the display panel.

[0094] Figure 3 This is a schematic diagram illustrating the effect of the first power supply signal on chromaticity under different loading conditions.

[0095] Figure 4 This is a schematic diagram of the operation interface of the compensation algorithm in related technologies.

[0096] Figure 5 This is a schematic diagram of the circuit structure of a pixel unit according to an exemplary embodiment. Figure 1 .

[0097] Figure 6 This is a schematic diagram of the circuit structure of a pixel unit according to an exemplary embodiment. Figure 2 .

[0098] Figure 7 This is a flowchart illustrating a pixel unit compensation method according to an exemplary embodiment. Figure 1 .

[0099] Figure 8 This is a schematic diagram of the circuit structure of a pixel unit according to an exemplary embodiment. Figure 3 .

[0100] Figure 9 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during the initialization phase, according to an exemplary embodiment.

[0101] Figure 10 This is a schematic diagram illustrating the timing changes of a pixel unit receiving a signal during the initialization phase, according to an exemplary embodiment.

[0102] Figure 11 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during the compensation stage when voltage drop compensation is disabled, according to an exemplary embodiment.

[0103] Figure 12 This is a schematic diagram illustrating the timing changes of the signal received by a pixel unit during the compensation stage when voltage drop compensation is off, according to an exemplary embodiment.

[0104] Figure 13 This is a schematic diagram illustrating the on / off state of each transistor in a pixel unit during the compensation stage when voltage drop compensation is enabled, according to an exemplary embodiment.

[0105] Figure 14 This is a schematic diagram illustrating the timing changes of the signal received by a pixel unit during the compensation stage when voltage drop compensation is enabled, according to an exemplary embodiment.

[0106] Figure 15 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during a data writing stage, according to an exemplary embodiment.

[0107] Figure 16 This is a schematic diagram illustrating the timing changes of a pixel unit receiving a signal during a data writing stage, according to an exemplary embodiment.

[0108] Figure 17 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during a light-emitting stage, according to an exemplary embodiment.

[0109] Figure 18 This is a schematic diagram illustrating the timing changes of a pixel unit receiving a signal during a light-emitting stage, according to an exemplary embodiment.

[0110] Figure 19 This is a schematic diagram of the circuit structure of a control circuit according to an exemplary embodiment.

[0111] Figure 20 This is a timing diagram illustrating the output signal of the second control circuit when the first control terminal outputs a high-level signal, according to an exemplary embodiment.

[0112] Figure 21 This is a timing diagram illustrating the output signal of the second control circuit when the first control terminal outputs a low-level signal, according to an exemplary embodiment.

[0113] Figure 22 This is a flowchart illustrating a pixel unit compensation method according to an exemplary embodiment. Figure 2 .

[0114] Figure 23 This is a schematic diagram of a compensation structure for a display panel according to an exemplary embodiment.

[0115] Figure 24 This is a schematic diagram illustrating the signal timing changes during voltage drop compensation of a pixel unit according to an exemplary embodiment.

[0116] Figure 25 This is a schematic diagram illustrating the structure of a compensation device for a pixel unit according to an exemplary embodiment.

[0117] Figure 26 This is a block diagram of a compensation device for a pixel unit according to an exemplary embodiment. Detailed Implementation

[0118] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0119] In OLED display panels, there is a voltage drop (IR Drop) phenomenon. The voltage drop is caused by the voltage division of the conductors in the display panel due to their own resistance. That is, when current passes through the conductors in the display panel, a certain voltage drop will be generated on the conductors.

[0120] like Figure 1-3 As shown, Figure 1 This is a schematic diagram of the structure of the display panel and pixel unit in related technologies; Figure 2 This is a schematic diagram illustrating the effect of the first power signal on the Gamma brightness of the pixel units within the display panel. Figure 3 This is a schematic diagram illustrating the effect of the first power signal on chroma under different loading conditions. Since the above display panel is current-driven, the light-emitting current output by the driving transistor in the pixel unit is affected by the first power signal ELVDD output from the first power terminal, thus affecting the brightness of the pixel unit and the accuracy of chroma / brightness.

[0121] The degree to which pixel units located in different positions are affected by voltage drop varies, resulting in uneven display on the display panel. Therefore, it is necessary to compensate for the voltage drop in the OLED display panel.

[0122] In related technologies, voltage drop compensation algorithms are used to reduce the impact of pixel unit voltage drop on display brightness and color.

[0123] For example, compensation can be performed using a GIR / LIR compensation algorithm, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of the user interface for the compensation algorithm in related technologies. Specifically:

[0124] First, determine the white reference brightness and reference color, and use the LIR algorithm reference design. Calculate the brightness compensation for four different grayscale blocks of different sizes, and determine the panel compensation value based on the upper and lower compensation limits. Due to the suppression of compensation coefficients for different chromaticities (i.e., R, G, B), calibrate the RGB of the large blocks according to the RGB of the small blocks. Since the IR drop of the small blocks is negligible, the brightness difference of the calibrated W-RGB of the large blocks is very small. Adjust the RGB compensation ratio according to the color shift problem of the small blocks after compensation.

[0125] However, this algorithm has a complex calculation logic and cannot accurately compensate for all scenarios, nor can it simultaneously enable and disable voltage drop compensation within the same frame of the display.

[0126] This disclosure proposes a pixel unit, such as... Figure 5 As shown, Figure 5 This is a schematic diagram of the circuit structure of a pixel unit according to an exemplary embodiment. Figure 1 The pixel unit includes:

[0127] Light-emitting circuit;

[0128] A driving circuit, connected to the light-emitting circuit, is used to output a driving electrical signal to the light-emitting circuit to drive the light-emitting circuit to emit light;

[0129] A data writing circuit, connected to the driving circuit, is used to receive a first data signal and a scan signal, and to write the first data signal into the driving circuit according to the scan signal;

[0130] A first initialization circuit, connected to the driving circuit, is used to initialize the potential at the input terminal of the driving circuit.

[0131] The compensation control circuit includes:

[0132] The first line connects the first power supply terminal and the input terminal of the drive circuit;

[0133] The second line connects the second signal terminal and the input terminal of the driving circuit; wherein the on / off states of the first line and the second line are opposite.

[0134] A control circuit, connected to the first line and the second line respectively, is used to control the first line to be turned on before the data writing circuit writes the first data signal into the driving circuit, so that the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

[0135] It should be noted that the pixel unit can be applied to any terminal device with a display panel, such as a smartphone, tablet computer, or wearable electronic device. Multiple pixel units can form a pixel array, which can be used to display images.

[0136] In this embodiment of the disclosure, the first initialization circuit initializes the input terminal of the driving circuit, and the compensation control circuit compensates for the voltage drop at the controlled terminal of the driving circuit before the data writing circuit writes the first data signal to the driving circuit. Under the trigger of the scanning signal, the data writing circuit writes the received first data signal into the driving circuit. Under the trigger of the first data signal, the driving circuit outputs a driving electrical signal to the light-emitting circuit, driving the light-emitting circuit to emit light.

[0137] It should be noted that due to the voltage drop (IR Drop) phenomenon in the display panel, the distance between the pixel unit at different positions in the display panel and the first power supply terminal is different. This causes the first power signal ELVDD received by different pixel units from the first power supply terminal to be attenuated, resulting in different brightness of the pixel units at different positions in the display panel and poor brightness uniformity of the display panel.

[0138] In addition, considering that the display panel has certain requirements for peak brightness, and that turning off voltage drop compensation can improve the peak brightness of the display panel; and since the signal value of the first power signal output from the first power terminal decreases linearly line by line in the pixel unit of the display panel, there are some pixel rows in the display panel that need voltage drop compensation, while other pixel rows may not need voltage drop compensation.

[0139] Based on this, the embodiments of this disclosure set up two compensation control lines, namely a first line and a second line. The first line is connected to the input terminal of the first power supply terminal and the driving circuit; the second line is connected to the input terminal of the second signal terminal and the driving circuit. The control circuit controls the on / off state of the first line and the second line to turn on or off the voltage drop compensation for the pixel unit. This allows for voltage drop compensation for the pixel units in the display panel, improving brightness uniformity, and also enables voltage drop compensation for a portion of the pixel rows in the display panel while not compensating for another portion.

[0140] In this embodiment of the disclosure, the pixel unit includes: a light-emitting circuit, a driving circuit, a data writing circuit, a first initialization circuit, and a compensation control circuit;

[0141] The input terminal of the light-emitting circuit is connected to the output terminal of the driving circuit, and the output terminal of the light-emitting circuit can be connected to the second power supply terminal ELVSS; the light-emitting circuit includes a light-emitting element, which can be an organic light-emitting diode (OLED).

[0142] The data writing circuit is connected to the first signal source, the scanning end, and the driving circuit, respectively, and is used to receive the first data signal output by the first signal source and the scanning signal output by the scanning end, and write the first data signal into the driving circuit according to the scanning signal.

[0143] The data writing circuit may include: a sixth switching transistor connected between the first signal source and the input terminal of the driving circuit, with the controlled terminal connected to the scanning terminal.

[0144] The first initialization circuit may include: a seventh switching transistor connected between the initial power supply and the input terminal of the drive circuit, with the controlled terminal connected to the second control terminal.

[0145] Before the data writing circuit writes the first data signal into the driving circuit, the second control terminal controls the seventh switch to turn on, and uses the first initialization electrical signal output by the initial power supply to initialize the voltage at the input terminal of the driving circuit, so that the voltage value at the input terminal of the driving circuit is the same as the voltage value of the first initialization electrical signal.

[0146] Here, the seventh switch can be a transistor.

[0147] The driving circuit may include: a driving transistor and a storage capacitor;

[0148] One end of the storage capacitor is connected to the controlled terminal of the driving transistor, and the other end is connected to the input terminal of the driving transistor; the input terminal of the driving transistor is connected to the first power supply terminal, and the output terminal is connected to the input terminal of the light-emitting circuit.

[0149] When triggered by a scan signal, the data writing circuit outputs a first data signal. At this time, the first data signal can charge the driving transistor and the storage capacitor. After charging is completed, the driving transistor outputs a driving electrical signal to the light-emitting circuit, which is used to drive the light-emitting element in the light-emitting circuit to emit light.

[0150] It should be noted that the driving transistor generally operates in the saturation region, and its gate-source voltage VGS determines the magnitude of the current flowing through it, thereby providing a stable current for the light-emitting circuit.

[0151] The gate-source voltage VGS of the driving transistor is:

[0152] VGS = ELVDD - Vdata1;

[0153] Wherein, ELVDD is the voltage value of the first power signal output from the first power supply terminal received by the driving transistor; and Vdata1 is the voltage value of the first data signal received by the driving transistor.

[0154] The function of the storage capacitor is to maintain the stability of the gate voltage (controlled terminal voltage) of the driving transistor within one frame.

[0155] It is understandable that the voltage values ​​of the first power signal received by pixel units at different positions within the display panel may be different, resulting in different gate-source voltages of the driving transistors in the pixel units at different positions. Consequently, the light-emitting currents output to the light-emitting circuit are also different, and the light-emitting brightness of the light-emitting elements in the light-emitting circuit is also different, leading to uneven brightness of the display panel.

[0156] The compensation control circuit includes: a first line, a second line, and a control circuit;

[0157] The first line is connected between the first power supply terminal and the drive circuit, and the second line is connected between the second signal terminal and the drive circuit.

[0158] The control circuit is connected to the first line and the second line respectively, and is used to control the on / off state of the first line and the second line.

[0159] Here, the on / off states of the first and second lines are reversed.

[0160] It is understood that when the first line is turned on, the first power supply terminal outputs a first power signal ELVDD to compensate the driving transistor, so that the voltage value at the input terminal of the driving transistor is equal to the voltage value of the first power signal ELVDD; the data writing circuit, triggered by the scan signal, uses the first data signal to charge the driving transistor and the storage capacitor.

[0161] At this time, the voltage at the input terminal of the driving transistor is the sum of the voltage values ​​of the first power supply signal and the first data signal. The gate-source voltage VGS of the driving transistor is only related to the voltage value of the first data signal. The signal attenuation of the first power supply signal does not affect the signal value of the driving signal output by the driving transistor. That is, when the first line is turned on, the first power supply signal output from the first power supply terminal compensates for the voltage drop of the driving transistor.

[0162] When the second line is turned on, the second data signal output from the second signal terminal compensates the driving transistor, making the voltage value at the input terminal of the driving transistor equal to the voltage value of the second data signal; the data writing circuit, triggered by the scan signal, uses the first data signal to charge the driving transistor and the storage capacitor.

[0163] At this time, the voltage value at the input terminal of the driving transistor is the sum of the voltage values ​​of the first data signal and the second data signal. The gate-source voltage VGS of the driving transistor is related to the voltage values ​​of the first data signal, the second data signal, and the first power supply signal. That is, the attenuation of the first power supply signal will affect the signal value of the driving electrical signal output by the driving transistor. The second data signal output by the second data source does not compensate for the voltage drop of the driving transistor.

[0164] The control circuit can turn on or off voltage drop compensation for pixel units by controlling the different on / off states of the first and second lines.

[0165] It is understandable that the target pixel unit to be compensated in the display panel can be determined based on the signal difference between the first data signals of each pixel unit in the display panel. The control circuit of the target pixel unit is used to control the first line in the target pixel unit to be turned on and the second line to be turned off before the data writing circuit writes the first data signal to the driving circuit, so as to compensate for the voltage drop of the target pixel unit.

[0166] In the first stage (i.e. the initial stage), the control circuit can control the first line to be turned on and the second line to be turned off. At this time, the seventh switch in the first initialization circuit is turned on, and the voltage at the input terminal of the drive circuit is initialized by the first initialization electrical signal output by the initial power supply, so that the voltage value at the input terminal of the drive circuit is the same as the voltage value of the first initialization electrical signal.

[0167] In the second stage (i.e., the compensation stage), the control circuit can control the first line to be turned on and the second line to be turned off, thus enabling voltage drop compensation for the driving transistor; at this time, the voltage value at the input terminal of the driving transistor is equal to the voltage value of the first power supply signal ELVDD.

[0168] Alternatively, the control circuit can control the first line to be disconnected and the second line to be connected, thereby disabling voltage drop compensation for the driving transistor; at this time, the voltage value at the input terminal of the driving transistor is equal to the voltage value of the second data signal.

[0169] In the third stage (i.e., the data writing stage), the control circuit can control the first line to be turned on and the second line to be turned off; the data writing circuit writes the first data signal to the driving transistor under the trigger of the scanning signal.

[0170] In the second stage, if the control circuit enables voltage drop compensation for the driving transistor, the voltage at the input of the driving transistor is the sum of the voltage of the first power supply signal and the voltage of the first data signal; the gate-source voltage VGS of the driving transistor is only related to the voltage of the first data signal.

[0171] In the second stage, if the control circuit controls the voltage drop compensation of the driving transistor to be turned off, the voltage value at the input terminal of the driving transistor is the sum of the voltage values ​​of the first data signal and the second data signal. The gate-source voltage VGS of the driving transistor is related to the voltage values ​​of the first data signal, the second data signal and the first power supply signal.

[0172] In the fourth stage (i.e., the light-emitting stage), the control circuit can control the first line to be turned on and the second line to be turned off; the driving transistor outputs a driving electrical signal to the light-emitting circuit to drive the light-emitting element in the light-emitting circuit to emit light. Here, the current value of the driving electrical signal is related to the gate-source voltage VGS of the driving transistor.

[0173] This embodiment of the disclosure provides a first line and a second line within a pixel unit. The first line is connected to the input terminal of the first power supply and the driving circuit; the second line is connected to the input terminal of the second signal and the driving circuit. A control circuit controls the on / off state of the first and second lines to turn on or off voltage drop compensation for the pixel unit. This allows for both voltage drop compensation for pixel units within the display panel, improving brightness uniformity, and voltage drop compensation for a portion of the pixel rows while omitting voltage drop compensation for another portion, thereby increasing the peak brightness of the display panel.

[0174] Optionally, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the circuit structure of a pixel unit according to an exemplary embodiment. Figure 2 .

[0175] The first line has a first switching transistor, wherein the controlled terminal of the first switching transistor is connected to the control circuit, and the input terminal and output terminal of the first switching transistor are connected to the first line.

[0176] The second line has a second switching transistor, wherein the controlled terminal of the second switching transistor is connected to the control circuit, and the input and output terminals of the second switching transistor are connected to the second line;

[0177] The control circuit outputs a first compensation signal to the first switch and the second switch, turning on the first switch and turning off the second switch.

[0178] The control circuit outputs a second compensation signal to the first switch and the second switch, in which the first switch is turned off and the second switch is turned on.

[0179] In this embodiment of the disclosure, the compensation control circuit includes: a first switching transistor and a second switching transistor;

[0180] The first switching transistor is disposed in the first line. The input terminal of the first switching transistor is connected to the first power supply terminal, the output terminal of the first switching transistor is connected to the input terminal of the drive circuit, and the controlled terminal is connected to the output terminal of the control circuit. The first switching transistor is used to control the on / off state of the first line.

[0181] The second switch is disposed in the second line. The input terminal of the second switch is connected to the second signal terminal, the output terminal of the second switch is connected to the drive circuit, and the controlled terminal is connected to the output terminal of the control circuit. The second switch is used to control the on / off state of the second line.

[0182] When the pixel unit is in the compensation stage, the control circuit outputs a compensation signal to control the on / off state of the first switch and the second switch. Under the trigger of the same compensation signal, the on / off state of the first switch and the on / off state of the second switch are opposite.

[0183] When the control circuit outputs a first compensation signal to the first switch and the second switch, the first switch is turned on and the second switch is turned off; the control circuit controls the activation of voltage drop compensation for the driving transistor, and the first power supply terminal outputs a first power supply signal ELVDD to compensate the driving transistor.

[0184] Understandably, after voltage drop compensation is enabled, the voltage at the input of the driving transistor is equal to the voltage of the first power supply signal ELVDD. The data writing circuit, triggered by the scan signal, charges the driving transistor and the storage capacitor using the first data signal. The voltage at the input of the driving transistor is the sum of the voltages of the first power supply signal and the first data signal; the gate-source voltage VGS of the driving transistor is only related to the voltage of the first data signal. The signal attenuation of the first power supply signal does not affect the signal value of the driving signal output by the driving transistor.

[0185] When the control circuit outputs the second compensation signal to the first switch and the second switch, the first switch is turned off and the second switch is turned on; the control circuit controls the voltage drop compensation of the driving transistor to be turned off, and the second data signal output by the second signal source compensates the driving transistor.

[0186] Understandably, after disabling voltage drop compensation, the voltage at the input of the driving transistor equals the voltage of the second data signal. Triggered by the scan signal, the data writing circuit charges the driving transistor and the storage capacitor using the first data signal. The voltage at the input of the driving transistor is the sum of the voltages of the first and second data signals. The gate-source voltage VGS of the driving transistor is related to the voltages of the first data signal, the second data signal, and the first power supply signal; that is, the attenuation of the first power supply signal affects the signal value of the driving signal output by the driving transistor.

[0187] Optionally, the first switch is an NMOS transistor, and the second switch is a PMOS transistor.

[0188] In this embodiment of the disclosure, the first switch and the second switch are transistors, wherein the first switch is an NMOS transistor and the second switch is a PMOS transistor.

[0189] It is understood that the input terminal of the NMOS transistor is the drain and the output terminal is the source, and the NMOS transistor is turned on when the controlled terminal (i.e., the gate) is connected to a high-level signal.

[0190] The input terminal of the PMOS transistor is the source, and the output terminal is the drain. The PMOS transistor is turned on when the controlled terminal (i.e., the gate) is connected to a low level.

[0191] Therefore, when the control circuit outputs a high-level first compensation signal, the NMOS transistor is turned on and the PMOS transistor is turned off, thus enabling voltage drop compensation for the driving transistor.

[0192] When the control circuit outputs a low-level second compensation signal, the NMOS transistor is turned off and the PMOS transistor is turned on, thus disabling voltage drop compensation for the driving transistor.

[0193] Optionally, the control circuit includes:

[0194] GOA units, including at least:

[0195] The first control circuit has its input terminals connected to the constant voltage high potential terminal and the constant voltage low potential terminal respectively, and its output terminal connected to the data writing circuit. It is used to output the scan signal to the data writing circuit under the control of the scan signal output by the cascaded upper-level GOA unit.

[0196] The second control circuit has its input terminals connected to the constant high voltage and the first control terminal, respectively, and its output terminals connected to the first line and the second line. Under the control of the scanning signal output by the cascaded upper-level GOA unit, it outputs the first compensation signal or the second compensation signal to the first line and the second line based on the first electrical signal output by the first control terminal.

[0197] In this embodiment of the disclosure, the control circuit includes a GOA unit.

[0198] It should be noted that the display panel contains a GOA circuit, which includes multiple cascaded GOA units. Pixel units in the same row within the pixel array can share a single GOA unit, or the GOA units in the same row can be synchronized. In this way, the GOA circuit is used to scan the pixel array within the display panel line by line.

[0199] The GOA unit includes at least:

[0200] First control circuit and second control circuit;

[0201] The input terminal of the first control circuit is connected to the constant voltage high potential terminal VGH and the constant voltage low potential terminal VGL, respectively, and the output terminal is connected to the controlled terminal of the data writing circuit. Under the control of the scan signal output by the cascaded upper-level GOA unit, the control circuit outputs a scan signal to the data writing circuit to trigger the data writing circuit to write the first data signal into the driving circuit.

[0202] It is understood that the output terminal of the first control circuit is connected to the input terminal of the cascaded next-level GOA unit, and is used to output a scan signal to the next-level GOA unit under the control of the scan signal output by the cascaded previous-level GOA unit, so as to trigger the next-level GOA unit to output a scan signal.

[0203] The input terminal of the second control circuit is connected to the constant voltage high potential terminal VGH and the first control terminal VSS respectively; the output terminal is connected to the controlled terminals of the first line and the second line, and is used to output a first compensation signal or a second compensation signal to the first line and the second line based on the first electrical signal output by the first control terminal under the control of the scanning signal output by the cascaded upper-level GOA unit.

[0204] Here, the first control terminal can be the output terminal of the control chip. The control chip can acquire the first data signal of each row of pixel units in the pixel array, determine the target pixel row to be compensated based on the signal difference between the first data signals of each row of pixel units, and output the first electrical signal of the first preset value within the time period corresponding to the target pixel row.

[0205] Here, the first electrical signal of the first preset value can be a high-level signal. Specifically, the signal value of the first electrical signal (i.e. the first preset value) can be set according to actual needs. For example, the first preset value can be 5V, etc.

[0206] After receiving the high-level signal output from the first control terminal VSS, the second control circuit controls the output of the first compensation signal to the first line and the second line to turn on the first line and turn off the second line.

[0207] In this embodiment, the second control circuit within the GOA unit outputs a first compensation signal or a second compensation signal to the first and second lines within the pixel unit, thereby controlling the opening or closing of voltage drop compensation for the driving transistors within the pixel unit line by line.

[0208] Optionally, the driving circuit includes:

[0209] The driver transistor has its input terminals connected to the output terminals of the first line and the second line, respectively, and its output terminal connected to the input terminal of the light-emitting circuit.

[0210] The first capacitor has its first end connected to the output terminal of the data writing circuit and its second end connected to the controlled terminal of the driving transistor.

[0211] The second capacitor has its first end connected to the controlled terminal of the driving transistor and its second end connected to the first power supply terminal.

[0212] A third switching transistor is connected between the controlled terminal and the output terminal of the driving transistor; the controlled terminal is connected to the second control terminal.

[0213] In this embodiment of the disclosure, the driving circuit includes: a driving transistor, a first capacitor, a second capacitor, and a third switching transistor.

[0214] The first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor is connected to the second node.

[0215] The first end of the second capacitor is connected to the second node, and the second end is connected to the first power supply terminal.

[0216] The controlled terminal of the driving transistor is connected to the second node, the input terminal is connected to the output terminal of the first line and the output terminal of the second line, and the output terminal is connected to the input terminal of the light-emitting circuit.

[0217] The third switch has its input terminal connected to the output terminal of the driving transistor, and its output terminal connected to the controlled terminal of the driving transistor. The controlled terminal of the third switch is connected to the second control terminal. Here, the third switch is used to compensate for the threshold voltage of the driving transistor.

[0218] It should be noted that since the driving transistor itself has a threshold voltage (Vth), this threshold voltage will also affect the light emission current output by the driving transistor. Due to the influence of manufacturing process, temperature change, etc., the threshold voltage of the driving transistor may be different for different pixel units. Therefore, the threshold voltage of the driving transistor can be compensated by the third switch to reduce the impact of the threshold voltage on the light emission current output by the driving transistor.

[0219] The first node is connected to the output of the data writing circuit and the output of the first initialization circuit.

[0220] In the first stage, the seventh switch in the first initialization circuit is turned on, and the third switch in the drive circuit is turned on; the voltage values ​​of the first node and the second node are the same as the voltage values ​​of the first initial electrical signal output by the initial power supply.

[0221] In the second stage, the seventh switch in the first initialization circuit is turned on, and the voltage value of the first node is the same as the voltage value of the first initial electrical signal output by the initial power supply; the third switch in the driving circuit is turned on, and the driving transistor forms a diode structure.

[0222] When the first line is on and the second line is off, the first power signal ELVDD output from the first power supply terminal compensates the driving transistor. Since the driving transistor forms a diode connection structure, the voltage value at the second node is equal to the sum of the signal value of the first power signal ELVDD and the signal value of the threshold voltage Vth of the driving transistor.

[0223] When the first line is disconnected and the second line is connected, the second data signal output by the second signal source compensates the driving transistor. Since the driving transistor forms a diode structure, the voltage value at the second node is the sum of the signal value of the second data signal and the signal value of the threshold voltage Vth of the driving transistor.

[0224] In the third stage, the seventh switch in the first initialization circuit is turned off, and the sixth switch in the data writing circuit is turned on. Under the trigger of the scan signal, the data writing circuit writes the first data signal into the driving circuit. At this time, the voltage value of the first node is the same as the voltage value of the first data signal.

[0225] The first data signal is coupled to the second node through the first capacitor, and the first capacitor and the second capacitor are connected in series to divide the voltage. At this time, the voltage value of the second node is related to the voltage value of the first data signal (Vdata1), the capacitance value of the first capacitor (C1), the capacitance value of the second capacitor (C2), and the voltage value of the second node in the previous stage.

[0226] If, during the second stage, the first line of a pixel unit is on and the second line is off, then the voltage value of the second node in the third stage is (Vdata1-Vint)*C1 / (C1+C2)+ELVDD+|Vth|.

[0227] If, during the second stage, the first line of a pixel unit is disconnected and the second line is connected, then the voltage value of the second node in the third stage is (Vdata1-Vint)*C1 / (C1+C2)+Vdata2+|Vth|.

[0228] In the fourth stage, the seventh switch in the first initialization circuit is turned off, the sixth switch in the data writing circuit is turned off, the third switch is turned off, the driving transistor is in saturation, and the light-emitting current output by the driving transistor is related to the gate-source voltage VGS of the driving transistor.

[0229] If, during the second stage, the first line is on and the second line is off, the gate voltage of the driving transistor (i.e., the voltage of the second node) is (Vdata1-Vint)*C1 / (C1+C2)+ELVDD+|Vth|; the gate-source voltage VGS of the driving transistor is:

[0230]

[0231] The light-emitting current output by the driving transistor is:

[0232] I = 0.5K(VGS - |Vth|) 2 =0.5K((Vdata1-Vint)*C1 / (C1+C2)) 2 ;

[0233] Where K = u * W / L, u is the mobility of the driving transistor; W is the channel width; and L is the length.

[0234] The light-emitting current output by the driving transistor is independent of the first power supply signal ELVDD. The signal attenuation of the first power supply signal does not affect the current value of the light-emitting current output by the driving transistor. Therefore, the light-emitting brightness of different pixel units is not affected by the attenuation of the first power supply signal ELVDD.

[0235] If, during the second stage, the first line is disconnected and the second line is connected, the gate voltage of the driving transistor (i.e., the voltage of the second node) is (Vdata1-Vint)*C1 / (C1+C2)+Vdata2+|Vth|; the gate-source voltage VGS of the driving transistor is:

[0236] VGS=(Vdata1-Vint)*C1 / (C1+C2)+Vdata2+|Vth|-ELVDD;

[0237] The light-emitting current output by the driving transistor is:

[0238] I = 0.5K(VGS - |Vth|) 2 =0.5K((Vdata1-Vint)*C1 / (C1+C2)+Vdata2-ELVDD) 2 ;

[0239] The light-emitting current output by the driving transistor is related to the first power supply signal ELVDD. The signal attenuation of the first power supply signal will affect the current value of the light-emitting current output by the driving transistor.

[0240] Optionally, the light-emitting circuit includes:

[0241] Light-emitting elements;

[0242] The second initialization circuit includes: a fourth switching transistor connected between the input terminal of the light-emitting element and the initial power supply; the controlled terminal of the fourth switching transistor is connected to the second control terminal;

[0243] The light-emitting control circuit includes: a fifth switching transistor connected between the output terminal of the driving circuit and the input terminal of the light-emitting element, wherein the controlled terminal of the fifth switching transistor is connected to the light-emitting control terminal.

[0244] In this embodiment of the disclosure, the input terminal of the fifth switching transistor in the light-emitting control circuit is connected to the output terminal of the driving transistor, and the output terminal of the fifth switching transistor is connected to the input terminal of the light-emitting element; the controlled terminal of the fifth switching transistor is connected to the light-emitting control terminal, and is used to turn the light-emitting circuit on or off under the control of the light-emitting control signal output by the light-emitting control terminal.

[0245] The input terminal of the light-emitting element is connected to the output terminal of the driving transistor through a light-emitting control circuit, and the output terminal of the light-emitting element is connected to the second power supply terminal ELVSS. Here, the light-emitting element can be an OLED, the input terminal of the light-emitting element is the anode of the OLED, and the output terminal of the light-emitting element is the cathode of the OLED.

[0246] The output terminal of the fourth switch of the second initialization circuit is connected to the input terminal of the light-emitting element, and the input terminal of the fourth switch is connected to the initial power supply; the controlled terminal is connected to the second control terminal.

[0247] In the first stage, the second control terminal controls the second initialization circuit to turn on, and initializes the input terminal of the light-emitting element according to the second initialization electrical signal output by the initial power supply, so that the voltage value of the input terminal of the light-emitting element is the same as the voltage value of the second initialization electrical signal.

[0248] In the fourth stage, the light-emitting control terminal outputs a light-emitting control signal to control the fifth switch in the light-emitting control circuit to turn on, driving the light-emitting current output by the transistor to flow to the light-emitting element, driving the light-emitting element to emit light.

[0249] This disclosure provides a display panel, including:

[0250] Multiple pixel units as described in one or more of the above technical solutions, and the multiple pixel units are arranged in a matrix.

[0251] In this embodiment of the disclosure, the display panel includes a plurality of pixel units, and the plurality of pixel units are arranged in a matrix to form a pixel array.

[0252] The display panel shown in this disclosure can be used in any product and component with display function, such as smartphones, tablets, televisions, monitors, and laptops.

[0253] The embodiments disclosed herein can perform voltage drop compensation on the pixel array within the display panel, thereby improving the uniformity of the luminous current output by each pixel unit within the pixel array and enhancing the uniformity of the display panel display. Furthermore, the compensation control circuit can be used to control the voltage drop compensation to be turned on or off row by row, thereby improving the peak brightness of the display panel.

[0254] This disclosure provides a method for compensating pixel units, such as... Figure 7 As shown, Figure 7 This is a flowchart illustrating a pixel unit compensation method according to an exemplary embodiment. Figure 1 The method includes:

[0255] Step S101: Obtain the row of target pixels to be compensated in a frame of the image to be displayed in the display panel;

[0256] Step S102: Determine whether the nth row of pixel units of the data signal to be written in the display panel is the target pixel row to be compensated; wherein, n is a positive integer less than or equal to N, and N is the number of rows of the pixel array of the display panel;

[0257] Step S103: If the nth row of pixel units is the target pixel row to be compensated, the voltage drop of the nth row of pixel units is compensated using the compensation control circuit.

[0258] In this embodiment of the disclosure, the pixel unit compensation method can be applied to the display panel shown in the above technical solution.

[0259] In step S101, image data of a frame of the screen to be displayed in the display panel can be obtained, and the target pixel row to be compensated in the screen to be displayed can be determined based on the image data.

[0260] It is understandable that because the pixel units at different positions within the display panel receive different signal values ​​of the first power signal output from the first power terminal, the brightness of the light-emitting elements within the pixel units varies, which can easily lead to uneven brightness. Therefore, voltage drop compensation is required for the pixel units.

[0261] However, for some special images, such as high dynamic range images, uneven brightness may occur. In this case, if voltage drop compensation is also performed on the pixel units, it may reduce the image display effect. Furthermore, voltage drop compensation on the pixel units in the display panel will reduce the peak brightness of the display panel.

[0262] Based on this, the embodiments of this disclosure determine the target pixel rows to be compensated within the display screen according to the image data of the display screen, so as to perform voltage drop compensation only on the target pixel rows to be compensated.

[0263] In step S102, the driving signal input to each row of pixel units can be obtained, and the nth row of pixel units to be written to the first data signal can be determined according to the driving signal; and the position of the nth row of pixel units in the pixel array can be used to determine whether the nth row of pixel units is the target pixel row to be compensated.

[0264] It is understood that, since the embodiments of this disclosure can control the voltage drop compensation of the pixel unit to be turned on or off by controlling the compensation control circuit in the pixel unit, the voltage drop compensation of a portion of the pixel rows in the pixel array can be turned on and the voltage drop compensation of another portion of the pixel rows can be turned off.

[0265] In step S103, if it is determined that the nth row of pixel units is the target pixel row to be compensated, the voltage drop compensation for the nth row of pixel units can be enabled by the compensation control circuit.

[0266] Optionally, the compensation of the voltage drop of the nth row of pixel units using the compensation control circuit includes:

[0267] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the first line to be turned on, and the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

[0268] In this embodiment of the disclosure, if the nth row of pixel units is the target pixel row that needs to be compensated, before the data writing circuit of the nth row of pixel units writes the first data signal into the driving circuit, specifically, in the second stage of the nth row of pixel units, the control circuit in the compensation control circuit can be used to turn on the first line and disconnect the second line, so that the first power signal output from the first power supply terminal connected to the first line can be used to compensate for the voltage drop of the driving transistor in the nth row of pixel units.

[0269] It is understood that when the first line is turned on, the first power supply terminal outputs a first power signal ELVDD to compensate the driving transistor, so that the voltage value at the input terminal of the driving transistor is equal to the voltage value of the first power signal ELVDD; the data writing circuit, triggered by the scan signal, uses the first data signal to charge the driving transistor and the storage capacitor.

[0270] At this time, the voltage at the input terminal of the driving transistor is the sum of the voltage values ​​of the first power supply signal and the first data signal. The gate-source voltage VGS of the driving transistor is only related to the voltage value of the first data signal. The signal attenuation of the first power supply signal does not affect the signal value of the driving signal output by the driving transistor. That is, when the first line is turned on, the first power supply signal output from the first power supply terminal compensates for the voltage drop of the driving transistor.

[0271] Optionally, the step of using a control circuit to control the conduction of the first line, and compensating for the voltage drop of the drive circuit by the first power supply terminal, includes:

[0272] The first control terminal outputs a first electrical signal with a first preset value. Under the control of the scanning signal output by the cascaded upper-level GOA unit, the second control circuit of the GOA unit outputs a first compensation signal to the first and second switching transistors.

[0273] Under the control of the first compensation signal, the first switch is turned on and the second switch is turned off, and the voltage drop of the drive circuit is compensated by the first power signal output from the first power supply terminal.

[0274] In this embodiment of the disclosure, the first control terminal VSS can be the output terminal of the control chip. After the control chip determines that the nth row of pixel units is the target pixel row to be compensated, it controls the first control terminal VSS to output a first electrical signal with a first preset value in the second stage corresponding to the nth row of pixel units.

[0275] Here, the first electrical signal of the first preset value can be a high-level signal. Specifically, the signal value of the first electrical signal (i.e. the first preset value) can be set according to actual needs. For example, the first preset value can be 5V, etc.

[0276] After receiving the first electrical signal of the first preset value, the second control circuit of the GOA unit in the nth row pixel unit controls the output of the first compensation signal to the first switch and the second switch; the first compensation signal is used to turn on the first switch and turn off the second switch.

[0277] The first power signal output from the first power supply terminal is input to the driving transistor through the first switching transistor to compensate the driving transistor.

[0278] Since the gate voltage of the compensated driving transistor is:

[0279] (Vdata1-Vint)*C1 / (C1+C2)+ELVDD+|Vth|;

[0280] The gate-source voltage VGS of the driving transistor is:

[0281]

[0282] The light-emitting current output by the driving transistor is:

[0283] I = 0.5K(VGS - |Vth|) 2 =0.5K((Vdata1-Vint)*C1 / (C1+C2)) 2 ;

[0284] Where K = u * W / L, u is the mobility of the driving transistor; W is the channel width; and L is the length.

[0285] The light-emitting current output by the driving transistor is independent of the first power supply signal ELVDD. The signal attenuation of the first power supply signal does not affect the current value of the light-emitting current output by the driving transistor. Therefore, the light-emitting brightness of different pixel units is not affected by the attenuation of the first power supply signal ELVDD.

[0286] Optionally, the compensation of the voltage drop of the nth row of pixel units using the compensation control circuit includes:

[0287] Determine the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit;

[0288] Based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated;

[0289] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the second line to be turned on, and the voltage drop of the driving circuit is compensated by the compensated second data signal.

[0290] It should be noted that, because the signal attenuation of the first power supply signal corresponding to different pixel units is different, the current value of the light emission current output by the driving transistor of different pixel units is also different.

[0291] In order to reduce the impact of the signal attenuation of the first power signal on the driving transistor, the embodiments of this disclosure determine the attenuation of the first power signal output from the first power terminal received by the nth row pixel unit; based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated so that the signal difference between the compensated second data signal and the first power signal is the same as the signal difference between the unattenuated first power signal and the uncompensated second data signal.

[0292] The second signal source can be the second signal source output terminal of the control chip. After the control chip determines that the nth row of pixel units is the target pixel row to be compensated, it determines the attenuation of the first power supply signal of the nth row of pixel units, determines the compensated second data signal, and controls the first control terminal VSS to output the first electrical signal of the second preset value in the second stage corresponding to the nth row of pixel units; and controls the second signal source to output the compensated second data signal.

[0293] Here, the first electrical signal of the second preset value can be a low-level signal. Specifically, the signal value of the first electrical signal (i.e. the second preset value) can be set according to actual needs.

[0294] After receiving the first electrical signal of the second preset value, the second control circuit of the GOA unit in the nth row pixel unit controls the output of the second compensation signal to the first switch and the second switch; the second compensation signal is used to disconnect the first switch and turn on the second switch.

[0295] The second data signal output from the second signal source is input to the driving transistor through the second switching transistor to compensate the driving transistor.

[0296] At this time, the gate voltage of the driving transistor is (Vdata1-Vint)*C1 / (C1+C2)+Vdata2′+|Vth|; where Vdata2′ is the voltage value of the compensated second data signal; Vdata2′=Vdata2+△V, and △V is the attenuation of the first power supply signal.

[0297] The gate-source voltage VGS of the driving transistor is:

[0298]

[0299] Wherein, ELVDD′ is the actual voltage value of the first power supply signal received by the nth row pixel unit.

[0300] The light-emitting current output by the driving transistor is:

[0301] I = 0.5K(VGS - |Vth|) 2 =0.5K((Vdata1-Vint)*C1 / (C1+C2)+Vdata2-ELVDD) 2 ;

[0302] The light-emitting current output by the driving transistor is related to the first power supply signal ELVDD. The signal attenuation of the first power supply signal will affect the current value of the light-emitting current output by the driving transistor. However, in this embodiment, the second data signal is compensated according to the attenuation of the first power supply signal, so that the difference between the second data signal and the first power supply signal remains different, thereby reducing the influence of the signal attenuation of the first power supply signal on the light-emitting current and realizing voltage drop compensation for the driving transistor.

[0303] Optionally, determining the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit includes:

[0304] The first power signal received by the first row of pixel units in the pixel array of the display panel and the first power signal output by the first power terminal are obtained.

[0305] Based on the difference between the preset signal value of the first power supply terminal and the signal value of the first power supply signal of the first row pixel unit and the signal value of the first power supply signal of the Nth row pixel unit, the first attenuation amount of the first power supply signal of the first row pixel unit and the second attenuation amount of the first power supply signal of the Nth row pixel unit are determined respectively.

[0306] Based on the first attenuation amount and the second attenuation amount, and the position of the nth row pixel unit within the pixel array, the attenuation amount of the first power signal output from the first power supply terminal received by the nth row pixel unit is determined; wherein, the signal value of the first power signal attenuates linearly row by row within the pixel array.

[0307] In this embodiment of the disclosure, the signal value of the first power signal output from the first power terminal decreases linearly row by row within the pixel array; since the first row of pixel units in the pixel array is closest to the first power terminal, the attenuation of the first power signal received by the first row of pixel units is relatively minimal; the Nth row of pixel units (i.e., the last row of pixel units) in the pixel array is farthest from the first power terminal, and the attenuation of the first power signal received by the Nth row of pixel units is relatively maximum.

[0308] The first attenuation of the first power signal of the first row of pixel units can be determined by acquiring the first power signal received by the first row of pixel units and the difference between the signal value of the first power signal of the first row of pixel units and the preset signal value of the first power signal output by the first power terminal.

[0309] By acquiring the first power signal received by the Nth row of pixel units, and based on the difference between the signal value of the first power signal of the Nth row of pixel units and the preset signal value of the first power signal output by the first power terminal, the second attenuation amount of the first power signal of the Nth row of pixel units is determined.

[0310] It is understandable that, as the distance between the pixel unit and the first power supply terminal increases, the attenuation of the first power signal received by the pixel unit increases. Therefore, the first attenuation can be the minimum attenuation of the first power signal in the pixel array, and the second attenuation can be the maximum attenuation of the first power signal in the pixel array.

[0311] Since the first power signal decays linearly row by row within the pixel array, the decay amount of the first power signal of the nth row pixel unit can be determined by linear interpolation based on the first decay amount and the second decay amount.

[0312] In some embodiments, the attenuation ΔV(n) of the first power supply signal of the nth row pixel unit is:

[0313] △V(n)=(offset_max-offset_min)*n / N;

[0314] Wherein, offset_min is the first attenuation amount; offset_max is the second attenuation amount.

[0315] Optionally, obtaining the target pixel row to be compensated in a frame of the image to be displayed within the display panel includes:

[0316] Acquire the first data signal of each row of pixel units in a frame to be displayed;

[0317] Based on the histogram of the first data signals, the pixel rows in which the signal difference between the first data signals is less than a preset difference are determined as the target pixel rows to be compensated.

[0318] It should be noted that while voltage drop compensation for pixel units can improve the display brightness, some special images, such as high dynamic range images, may also exhibit uneven brightness. In such cases, voltage drop compensation for pixel units may reduce the image display effect, and voltage drop compensation for pixel units within the display panel will reduce the peak brightness of the display panel.

[0319] Therefore, before performing voltage drop compensation on pixel units, it is necessary to determine the target pixel row to be compensated from within the pixel array.

[0320] Here, the target pixel row is used at least to indicate the row number of the pixel unit to be compensated within the pixel array.

[0321] By acquiring the first data signal of each row of pixel units in a frame to be displayed, it can be understood that the signal value of the first data signal of a pixel unit can be used to indicate the image brightness of that pixel unit.

[0322] Based on the first data signal of each row of pixel units, determine the histogram of the first data signal;

[0323] Since the histogram is used to indicate the number of pixel rows corresponding to different signal values ​​of the first data signal, the signal difference between different signal values ​​of the first data signal can be determined according to the histogram of the first data signal. If the signal difference between multiple pixel arrays is less than a preset difference, it indicates that the image brightness difference between the multiple pixel arrays is small. Therefore, voltage drop compensation can be enabled for the multiple pixel arrays, that is, the multiple pixel arrays are the target pixel rows to be compensated.

[0324] Optionally, determining whether the nth row of pixel units in the display panel to be written with the first data signal is the target pixel row to be compensated includes:

[0325] Acquire frame synchronization signals and line synchronization signals;

[0326] Based on the frame synchronization signal and the line synchronization signal, the nth row pixel unit in the display panel to be written with the first data signal is determined.

[0327] Based on the position of the target pixel row within the pixel array, determine whether the nth row pixel unit is the target pixel row to be compensated.

[0328] In this embodiment of the disclosure, the frame synchronization signal is used to determine the number of frames scanned by the pixel array in the display panel; it can be understood that since the frame synchronization signal marks the start of the pixel array scanning a frame of image, the number of frames scanned by the pixel array in the display panel, that is, the number of frames scanned within the pixel array, can be determined based on the frame synchronization signal.

[0329] The line synchronization signal is used to determine the number of rows of pixels being scanned within the pixel array. It can be understood that, since the line synchronization signal marks the start of scanning a row of pixel units within the pixel array, the number of rows of pixels currently to be scanned within the pixel array can be determined based on the line synchronization signal.

[0330] The driving device within the display panel sends a driving signal to the pixel array according to the frame synchronization signal to drive the pixel array to start scanning a frame of image; and sends a scanning signal to each row of pixel units in the pixel array according to the line synchronization signal to drive the pixel array to perform line-by-line scanning.

[0331] Therefore, the frame synchronization signal and the line synchronization signal can be directly obtained, and the nth row pixel unit of the first data signal to be written (i.e., scan) can be determined based on the frame synchronization signal and the line synchronization signal.

[0332] Since the target pixel row is used to indicate at least the row number of the pixel unit to be compensated in the pixel array, it is determined whether the row number matches the row number indicated by the target pixel row based on the row number of the nth row pixel unit in the pixel array.

[0333] If the row number of the nth row pixel unit in the pixel array matches the row number indicated by the target pixel row, it means that the nth row pixel unit is the target pixel row to be compensated, and voltage drop compensation for the nth row pixel unit can be enabled.

[0334] If the row number of the nth row pixel unit in the pixel array does not match the row number indicated by the target pixel row, it means that the nth row pixel unit is not the target pixel row to be compensated, and voltage drop compensation for the nth row pixel unit can be turned off.

[0335] The following provides a specific example using any of the above technical solutions, such as... Figure 8 As shown, Figure 8 This is a schematic diagram of the circuit structure of a pixel unit according to an exemplary embodiment. Figure 3 This disclosure provides a display panel, the display panel comprising:

[0336] Multiple pixel units, and the multiple pixel units are arranged in a matrix;

[0337] The pixel unit includes: a light-emitting circuit, a data writing circuit, a driving circuit, a compensation control circuit, and a first initialization circuit.

[0338] The compensation control circuit includes: a first transistor T1, a second transistor T2, and a control circuit;

[0339] The driving circuit includes: a driving transistor D-TFT, a first capacitor C1, a second capacitor C2, and a third transistor T3;

[0340] The light-emitting circuit includes:

[0341] The second initialization circuit includes: a fourth transistor T4;

[0342] The light-emitting control circuit includes the fifth transistor T5;

[0343] Light-emitting elements;

[0344] The data writing circuit includes: a sixth transistor T6;

[0345] The first initialization circuit includes: a seventh transistor T7;

[0346] The input terminal of the first transistor T1 is connected to the first voltage source ELVDD, and the output terminal is connected to the input terminal of the driving transistor D-TFT; the controlled terminal is connected to the output terminal scan-b of the control circuit.

[0347] The input terminal of the second transistor T2 is connected to the second signal source data2, and the output terminal is connected to the input terminal of the driving transistor D-TFT; the controlled terminal is connected to the output terminal of the control circuit.

[0348] The output terminal of the driving transistor D-TFT is connected to the input terminal of the third transistor T3; the controlled terminal of the driving transistor D-TFT is connected to the second node b.

[0349] The output terminal of the third transistor T3 is connected to the second node b, and the controlled terminal is connected to the second control terminal comp.

[0350] The first terminal of the first capacitor C1 is connected to the first node a, and the second terminal is connected to the second node b;

[0351] The first terminal of the second capacitor C2 is connected to the first power supply terminal ELVDD, and the second terminal is connected to the second node b.

[0352] The input terminal of the fourth transistor T4 is connected to the initial power supply Vint, the output terminal is connected to the anode of the light-emitting element, and the controlled terminal is connected to the second control terminal comp.

[0353] The input terminal of the fifth transistor T5 is connected to the output terminal of the driving transistor D-TFT, the output terminal is connected to the anode of the light-emitting element, and the controlled terminal is connected to the light-emitting control terminal EM.

[0354] The cathode of the light-emitting element is connected to the second power supply terminal ELVSS;

[0355] The input terminal of the sixth transistor T6 is connected to the first signal source data1, the output terminal is connected to the first node a, and the controlled terminal is connected to the drive signal terminal scan-c.

[0356] The input terminal of the seventh transistor T7 is connected to the initial power supply Vint, the output terminal is connected to the first node a, and the controlled terminal is connected to the second control terminal comp.

[0357] Among them, the first transistor T1 is an NMOS transistor, and the other transistors are all PMOS transistors.

[0358] In this example, the compensation control circuit of the pixel unit can be used to control the on or off of voltage drop compensation for the pixel unit based on timing control.

[0359] The different timing stages of a pixel unit are described below:

[0360] Initialization phase:

[0361] like Figure 9-10 As shown, Figure 9 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during the initialization phase, according to an exemplary embodiment. Figure 10 This is a schematic diagram illustrating the timing changes of a pixel unit receiving a signal during the initialization phase, according to an exemplary embodiment.

[0362] The drive signal terminal scan-c and the output terminal scan-b of the control circuit output high-level signals, while the light-emitting control terminal EM and the second control terminal comp output low-level signals. At this time, the second transistor T2 and the sixth transistor T6 are disconnected, while the other transistors are turned on; that is, the first initialization circuit and the second initialization circuit are turned on, initializing the first capacitor and the anode of the light-emitting element.

[0363] The voltages at the first nodes a and b are: Va = Vb = Vint.

[0364] For the compensation phase, it is necessary to explain the two cases separately: enabling voltage drop compensation and disabling voltage drop compensation.

[0365] Compensation phase (voltage drop compensation off):

[0366] like Figure 11-12 As shown, Figure 11 This is a schematic diagram illustrating the on / off state of each transistor in a pixel unit during the compensation stage when voltage drop compensation is off, according to an exemplary embodiment. Figure 12 This is a schematic diagram illustrating the timing changes of the signal received by a pixel unit during the compensation stage when voltage drop compensation is off, according to an exemplary embodiment.

[0367] The drive signal terminal scan-c and the light emission control terminal EM output high-level signals, while the control circuit output terminal scan-b and the second control terminal comp output low-level signals. At this time, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are off, while the other transistors are on. The second signal terminal data2 outputs the second data signal to compensate the drive transistors.

[0368] The voltages at the first nodes a and b are: Va = Vint, Vb = Vdata1 + |Vth|;

[0369] Compensation phase (voltage drop compensation enabled):

[0370] like Figure 13-14 As shown, Figure 13 This is a schematic diagram illustrating the on / off state of each transistor in a pixel unit during the compensation stage when voltage drop compensation is enabled, according to an exemplary embodiment. Figure 14 This is a schematic diagram illustrating the timing changes of the signal received by a pixel unit during the compensation stage when voltage drop compensation is enabled, according to an exemplary embodiment.

[0371] The drive signal terminal scan-c and the light emission control terminal EM output high-level signals, while the control circuit output terminal scan-b and the second control terminal comp output low-level signals. At this time, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are off, while the other transistors are on. The first power supply terminal ELVDD outputs the first power supply signal to compensate the drive transistors.

[0372] The voltages at the first nodes a and b are: Va = Vint, Vb = ELVDD + |Vth|.

[0373] Data writing phase:

[0374] like Figure 15-16 As shown, Figure 15 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during a data writing stage, according to an exemplary embodiment. Figure 16 This is a schematic diagram illustrating the timing changes of a pixel unit receiving a signal during a data writing stage, according to an exemplary embodiment.

[0375] The drive signal terminal scan-c outputs a low-level signal, while the light emission control terminal EM, the control circuit output terminal scan-b, and the second control terminal comp output high-level signals. At this time, the first transistor T1 and the sixth transistor T5 are turned on, and the other transistors are turned off. Triggered by the drive signal, the sixth transistor writes the first data signal output from the first signal terminal into the drive transistor.

[0376] At this moment, the voltage at the first node a is: Va = Vdata1;

[0377] Because the voltage value of the second node b after voltage drop compensation is enabled is different from the voltage value of the second node b after voltage drop compensation is disabled;

[0378] Therefore, at this time, the voltage at the second node b after voltage drop compensation is enabled is:

[0379] Vb=(Vdata1-Vint)*C1 / (C1+C2)+ELVDD+|Vth|;

[0380] The voltage at the second node b after voltage drop compensation is turned off is:

[0381] Vb=(Vdata1-Vint)*C1 / (C1+C2)+Vdata2+|Vth|

[0382] Luminescence stage:

[0383] like Figure 17-18 As shown, Figure 17 This is a schematic diagram illustrating the on / off state of each transistor within a pixel unit during a light-emitting stage, according to an exemplary embodiment. Figure 18 This is a schematic diagram illustrating the timing changes of a pixel unit receiving a signal during a light-emitting stage, according to an exemplary embodiment.

[0384] The control circuit outputs a high-level signal at the scan-b terminal, and low-level signals at the scan-c drive signal terminal, the EM light-emitting control terminal, and the comp second control terminal. At this time, the first transistor T1 and the fifth transistor T5 are turned on, while the other transistors are turned off.

[0385] Because the voltage value of the second node b after voltage drop compensation is enabled is different from the voltage value of the second node b after voltage drop compensation is disabled;

[0386] Therefore, after enabling voltage drop compensation, the gate-source voltage VGS of the driving transistor D-TFT is:

[0387]

[0388] The luminous current output by the driving transistor D-TFT is:

[0389]

[0390] The luminous current of the light-emitting element is independent of the first power supply signal ELVDD and is not affected by the attenuation of the first power supply signal.

[0391] After disabling voltage drop compensation, the gate-source voltage VGS of the driving transistor D-TFT is:

[0392] VGS=(Vdata1-Vint)*C1 / (C1+C2)+Vdata2+|Vth|-ELVDD;

[0393] The luminous current output by the driving transistor D-TFT is:

[0394]

[0395] The luminous current of the light-emitting element is related to the first power supply signal ELVDD and is affected by the attenuation of the first power supply signal.

[0396] In this example, such as Figure 19 As shown, Figure 19This is a schematic diagram of a control circuit structure according to an exemplary embodiment. The control circuit includes: a GOA unit, comprising at least:

[0397] The first control circuit has its input terminals connected to the constant voltage high potential terminal and the constant voltage low potential terminal respectively, and its output terminal connected to the data writing circuit. It is used to output the scan signal to the data writing circuit under the control of the scan signal output by the cascaded upper-level GOA unit.

[0398] The second control circuit has its input terminals connected to the constant high voltage terminal and the first control terminal, respectively, and its output terminals connected to the first line and the second line. Under the control of the scanning signal output by the cascaded upper-level GOA unit, it outputs the first compensation signal or the second compensation signal to the first line and the second line based on the first electrical signal output by the first control terminal.

[0399] The compensation signal scan-b output by the control circuit is generated by the GOA unit. The GOA unit includes a first control circuit and a second control circuit. The first control circuit outputs a scan signal, which is input to the data writing circuit and the input terminal of the cascaded next-stage GOA unit. The second control circuit outputs either a first compensation signal or a second compensation signal.

[0400] Here, since the input terminal of the second control circuit is connected to the constant voltage high voltage terminal VGH and the first control terminal VSS respectively, the second control circuit can be driven to output a first compensation signal by controlling the first control terminal VSS to output a high-level signal; the second control circuit can be driven to output a second compensation signal by controlling the first control terminal VSS to output a low-level signal.

[0401] like Figure 20-21 As shown, Figure 20 This is a timing diagram illustrating the output signal of the second control circuit when the first control terminal outputs a high-level signal, according to an exemplary embodiment. Figure 21 This is a timing diagram illustrating the output signal of the second control circuit when the first control terminal outputs a low-level signal, according to an exemplary embodiment.

[0402] Under the control of the first compensation signal, the first transistor T1 is turned on and the second transistor T2 is turned off;

[0403] Under the control of the second compensation signal, the first transistor T1 is turned off and the second transistor T2 is turned on.

[0404] This example also provides a method for compensating pixel units, such as... Figure 22 As shown, Figure 22 This is a flowchart illustrating a pixel unit compensation method according to an exemplary embodiment. Figure 2 .

[0405] Step S201: Obtain the first data signal of each row of pixel units in a frame to be displayed; based on the histogram of the first data signal, determine the pixel rows whose signal difference between the first data signals is less than a preset difference as the target pixel rows to be compensated.

[0406] Step S202: Obtain frame synchronization signal and line synchronization signal; based on the frame synchronization signal and line synchronization signal, determine the nth row pixel unit in the display panel to be written with the first data signal; based on the position of the target pixel row in the pixel array, determine whether the nth row pixel unit is the target pixel row to be compensated.

[0407] Step S203: If the nth row pixel unit is the target pixel row to be compensated, obtain the first power signal output from the first power terminal received by the first row pixel unit in the pixel array of the display panel and the first power signal output from the first power terminal received by the Nth row pixel unit.

[0408] Step S204: Based on the difference between the preset signal value of the first power supply terminal and the signal value of the first power supply signal of the first row pixel unit and the signal value of the first power supply signal of the Nth row pixel unit, determine the first attenuation amount of the first power supply signal of the first row pixel unit and the second attenuation amount of the first power supply signal of the Nth row pixel unit respectively.

[0409] Step S205: Based on the first attenuation amount and the second attenuation amount, and the position of the nth row pixel unit in the pixel array, determine the attenuation amount of the first power signal output from the first power supply terminal received by the nth row pixel unit; wherein, the signal value of the first power signal attenuates linearly row by row in the pixel array.

[0410] Step S206: Based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated; before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the second line is controlled to be turned on by the control circuit, and the voltage drop of the driving circuit is compensated by the compensated second data signal.

[0411] In this example, the compensation control circuit of the pixel unit can be used to control the voltage drop compensation of the pixel unit to be turned on or off based on the control chip control method.

[0412] like Figure 23 As shown, Figure 23This is a schematic diagram of a compensation structure for a display panel according to an exemplary embodiment. Sensing lines can be drawn from the near end (i.e., the first row of pixel units) and the far end (i.e., the Nth row of pixel units) of the first power signal trace on the display panel. The signal values ​​of the first power signal received by the first row of pixel units and the signal values ​​of the first power signal received by the Nth row of pixel units are detected through these sensing lines.

[0413] The first power supply signal of the first row of pixel units and the first power supply signal of the Nth row of pixel units are input to the control chip through the sensing line. Based on the ELVDD standard value, the first attenuation amount offset_min of the first row of pixel units and the second attenuation amount offset_max of the Nth row of pixel units are determined. Based on the first attenuation amount and the second attenuation amount, the attenuation amount of the nth row of pixel units is determined. The attenuation amount of the nth row of pixel units is input to the VGSP / VGMP generation unit and directly applied to the VGSP and VGMP voltages to achieve compensation for the second data signal.

[0414] It should be noted that since the traces of the first power signal in the display panel are made of a metal mesh structure and the first power signal decays linearly row by row, the amount of decay of the first power signal in any row of the pixel array at any time can be determined by linear interpolation by obtaining the decay of the first power signal of the first row of pixel units and the last row of pixel units in the pixel array at any time.

[0415] Since the second data signal is generated by voltage division through series connection of VGSP and VGMP resistors, the attenuation of the nth row pixel unit is input to the VGSP / VGMP generation unit and directly applied to the VGSP and VGMP voltages, so that the second data signal generated by the VGSP / VGMP generation unit also has the attenuation of the nth row pixel unit added to it.

[0416] In this way, by using the attenuation of the nth row of pixel units to compensate for the second data signal, the difference between (Vdata1-Vint)*C1 / (C1+C2)+Vdata2-ELVDD can be kept unaffected by the attenuation of the first power supply signal, thus achieving voltage drop compensation for the pixel units.

[0417] In practical applications, the attenuation amount of the nth row of pixel units can be determined, and the second data signal of the (n+1)th row of pixel units can be compensated based on this attenuation amount. For example... Figure 24 As shown, Figure 24 This is a schematic diagram illustrating the signal timing changes during voltage drop compensation of a pixel unit according to an exemplary embodiment.

[0418] This disclosure provides a pixel unit compensation device, such as... Figure 25 As shown, Figure 25This is a schematic diagram illustrating the structure of a pixel unit compensation device according to an exemplary embodiment. The device 100 includes:

[0419] The acquisition module 101 is used to acquire the target pixel row to be compensated in a frame of the image to be displayed in the display panel;

[0420] The determining module 102 is used to determine whether the nth row of pixel units in the display panel to be written the first data signal is the target pixel row to be compensated; wherein, n is a positive integer less than or equal to N, and N is the number of rows of the pixel array of the display panel;

[0421] The compensation module 103 is used to compensate the voltage drop of the nth row of pixel units by means of a compensation control circuit if the nth row of pixel units is the target pixel row to be compensated.

[0422] Optionally, the compensation module 103 is used for:

[0423] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the first line to be turned on, and the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

[0424] Optionally, the compensation module 103 is used for:

[0425] The first control terminal outputs a first electrical signal with a first preset value. Under the control of the scanning signal output by the cascaded upper-level GOA unit, the second control circuit of the GOA unit outputs a first compensation signal to the first switch and the second switch.

[0426] Under the control of the first compensation signal, the first switch is turned on and the second switch is turned off, and the voltage drop of the drive circuit is compensated by the first power signal output from the first power supply terminal.

[0427] Optionally, the compensation module 103 is used for:

[0428] Determine the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit;

[0429] Based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated;

[0430] Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the second line to be turned on, and the voltage drop of the driving circuit is compensated by the compensated second data signal.

[0431] Optionally, the compensation module 103 is used for:

[0432] The first power signal received by the first row of pixel units in the pixel array of the display panel and the first power signal output by the first power terminal are obtained.

[0433] Based on the difference between the preset signal value of the first power supply terminal and the signal value of the first power supply signal of the first row pixel unit and the signal value of the first power supply signal of the Nth row pixel unit, the first attenuation amount of the first power supply signal of the first row pixel unit and the second attenuation amount of the first power supply signal of the Nth row pixel unit are determined respectively.

[0434] Based on the first attenuation amount and the second attenuation amount, and the position of the nth row pixel unit within the pixel array, the attenuation amount of the first power signal output from the first power supply terminal received by the nth row pixel unit is determined; wherein, the signal value of the first power signal attenuates linearly row by row within the pixel array.

[0435] Optionally, the acquisition module 101 is configured to:

[0436] Acquire the first data signal of each row of pixel units in a frame to be displayed;

[0437] Based on the histogram of the first data signals, the pixel rows in which the signal difference between the first data signals is less than a preset difference are determined as the target pixel rows to be compensated.

[0438] Optionally, the determining module 102 is configured to:

[0439] Acquire frame synchronization signals and line synchronization signals;

[0440] Based on the frame synchronization signal and the line synchronization signal, the nth row pixel unit in the display panel to be written with the first data signal is determined.

[0441] Based on the position of the target pixel row within the pixel array, determine whether the nth row pixel unit is the target pixel row to be compensated.

[0442] Figure 26 This is a block diagram illustrating a pixel unit compensation device according to an exemplary embodiment. For example, device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0443] Reference Figure 26The device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0444] Processing component 802 typically controls the overall operation of device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0445] Memory 804 is configured to store various types of data to support the operation of device 800. Examples of this data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0446] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device 800.

[0447] Multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0448] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0449] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0450] Sensor assembly 814 includes one or more sensors for providing status assessments of various aspects of device 800. For example, sensor assembly 814 may detect the on / off state of device 800, the relative positioning of components such as the display and keypad of device 800, changes in the position of device 800 or a component of device 800, the presence or absence of user contact with device 800, the orientation or acceleration / deceleration of device 800, and temperature changes of device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0451] Communication component 816 is configured to facilitate wired or wireless communication between device 800 and other devices. Device 800 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0452] In an exemplary embodiment, the apparatus 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0453] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of the device 800 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0454] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of a pixel unit compensation device, enables the pixel unit compensation device to perform a pixel unit compensation method.

[0455] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0456] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A pixel unit, characterized in that, include: Light-emitting circuit; A driving circuit includes: a driving transistor, a first capacitor, a second capacitor, and a third switching transistor; wherein, the output terminal of the driving transistor is connected to the light-emitting circuit and is used to output a driving electrical signal to the light-emitting circuit to drive the light-emitting circuit to emit light; the first terminal of the second capacitor is connected to the second terminal of the first capacitor, and the second terminal of the second capacitor is connected to a first power supply terminal; the input terminal of the third switching transistor is connected to the output terminal of the driving transistor, the output terminal of the third switching transistor is connected to the controlled terminal of the driving transistor, and the controlled terminal of the third switching transistor is connected to a second control terminal; A data writing circuit is connected to the first end of the first capacitor and is used to receive a first data signal and a scan signal, and write the first data signal into the driving circuit according to the scan signal. A first initialization circuit is connected to the first terminal of the first capacitor and is used to initialize the potential of the first terminal of the first capacitor. The compensation control circuit includes: The first line connects the first power supply terminal and the input terminal of the driving transistor; The second line connects the second signal terminal and the input terminal of the driving transistor; wherein the on / off states of the first line and the second line are opposite. A control circuit, connected to the first line and the second line respectively, is used to control the first line to be turned on before the data writing circuit writes the first data signal into the driving circuit, so that the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

2. The pixel unit according to claim 1, characterized in that, The first line has a first switching transistor, wherein the controlled terminal of the first switching transistor is connected to the control circuit, the input terminal of the first switching transistor is connected to the first power supply terminal, and the output terminal of the first switching transistor is connected to the input terminal of the driving transistor. The second line has a second switching transistor, wherein the controlled terminal of the second switching transistor is connected to the control circuit, the input terminal of the second switching transistor is connected to the second signal terminal, and the output terminal of the second switching transistor is connected to the input terminal of the driving transistor; The control circuit outputs a first compensation signal to the first switch and the second switch, turning on the first switch and turning off the second switch. The control circuit outputs a second compensation signal to the first switch and the second switch, causing the first switch to turn off and the second switch to turn on.

3. The pixel unit according to claim 2, characterized in that, The control circuit includes: GOA units, including at least: The first control circuit has its input terminals connected to the constant voltage high potential terminal and the constant voltage low potential terminal, respectively, and its output terminal connected to the input terminals of the data writing circuit and the next-level GOA unit in the cascade. It is used to generate and output a scan signal to the data writing circuit and the next-level GOA unit in the cascade under the control of the scan signal output by the previous-level GOA unit in the cascade. The second control circuit has its input terminals connected to the constant voltage high potential terminal and the first control terminal, respectively, and its output terminal connected to the first line and the second line. Under the control of the scanning signal output by the cascaded upper-level GOA unit, it outputs the first compensation signal or the second compensation signal to the first line and the second line based on the first electrical signal output by the first control terminal.

4. The pixel unit according to claim 1, characterized in that, The light-emitting circuit includes: Light-emitting elements; The second initialization circuit includes: a fourth switching transistor, the output terminal of which is connected to the input terminal of the light-emitting element, the input terminal of which is connected to the initial power supply, and the controlled terminal of which is connected to the second control terminal; The light-emitting control circuit includes: a fifth switching transistor, the input terminal of which is connected to the output terminal of the driving transistor, the output terminal of which is connected to the input terminal of the light-emitting element, and the controlled terminal of which is connected to the light-emitting control terminal.

5. A display panel, characterized in that, include: A plurality of pixel units as described in any one of claims 1-4, wherein the plurality of pixel units are arranged in a matrix.

6. A method for compensating pixel units, characterized in that, The method, applied to the display panel of claim 5, comprises: Obtain the row of target pixels to be compensated in a frame of the image to be displayed on the display panel; Determine whether the nth row of pixel units in the display panel to be written with the first data signal is the target pixel row to be compensated; wherein, n is a positive integer less than or equal to N, and N is the number of rows of the pixel array of the display panel; If the nth row of pixel units is the target pixel row to be compensated, the voltage drop of the nth row of pixel units is compensated using a compensation control circuit.

7. The method according to claim 6, characterized in that, The compensation control circuit for voltage drop compensation of the nth row pixel unit includes: Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the first line to be turned on, and the first power signal output from the first power supply terminal compensates for the voltage drop of the driving circuit.

8. The method according to claim 7, characterized in that, The method of using a control circuit to control the conduction of the first line, and compensating for the voltage drop of the drive circuit by the first power supply terminal, includes: The first control terminal outputs a first electrical signal with a first preset value. Under the control of the scanning signal output by the cascaded upper-level GOA unit, the second control circuit of the GOA unit outputs a first compensation signal to the first and second switching transistors. Under the control of the first compensation signal, the first switch is turned on and the second switch is turned off, and the voltage drop of the drive circuit is compensated by the first power signal output from the first power supply terminal.

9. The method according to claim 6, characterized in that, The compensation control circuit for voltage drop compensation of the nth row pixel unit includes: Determine the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit; Based on the attenuation of the first power signal, the second data signal output by the second signal source is compensated; Before the data writing circuit of the nth row pixel unit writes the first data signal into the driving circuit, the control circuit controls the second line to be turned on, and the voltage drop of the driving circuit is compensated by the compensated second data signal.

10. The method according to claim 9, characterized in that, Determining the attenuation of the first power signal output from the first power supply terminal received by the nth row pixel unit includes: The first power signal received by the first row of pixel units in the pixel array of the display panel and the first power signal output by the first power terminal are obtained. Based on the difference between the preset signal value of the first power supply terminal and the signal value of the first power supply signal of the first row pixel unit and the signal value of the first power supply signal of the Nth row pixel unit, the first attenuation amount of the first power supply signal of the first row pixel unit and the second attenuation amount of the first power supply signal of the Nth row pixel unit are determined respectively. Based on the first attenuation amount and the second attenuation amount, and the position of the nth row pixel unit within the pixel array, the attenuation amount of the first power signal output from the first power supply terminal received by the nth row pixel unit is determined; wherein, the signal value of the first power signal attenuates linearly row by row within the pixel array.

11. The method according to claim 6, characterized in that, The step of obtaining the target pixel row to be compensated in a frame of the image to be displayed on the display panel includes: Acquire the first data signal of each row of pixel units in a frame to be displayed; Based on the histogram of the first data signals, the pixel rows in which the signal difference between the first data signals is less than a preset difference are determined as the target pixel rows to be compensated.

12. The method according to claim 6, characterized in that, Determining whether the nth row of pixel units in the display panel to be written with the first data signal is the target pixel row to be compensated includes: Acquire frame synchronization signals and line synchronization signals; Based on the frame synchronization signal and the line synchronization signal, the nth row pixel unit in the display panel to be written with the first data signal is determined. Based on the position of the target pixel row within the pixel array, determine whether the nth row pixel unit is the target pixel row to be compensated.

13. A compensation device for a pixel unit, characterized in that, Applied to the display panel of claim 5, comprising: The acquisition module is used to acquire the target pixel row to be compensated in a frame of the image to be displayed in the display panel; The determining module is used to determine whether the nth row of pixel units in the display panel to be written the first data signal is the target pixel row to be compensated; wherein, n is a positive integer less than or equal to N, and N is the number of rows of the pixel array of the display panel; The compensation module is used to compensate for the voltage drop of the nth row of pixel units by means of a compensation control circuit if the nth row of pixel units is the target pixel row to be compensated.

14. A compensation device for a pixel unit, characterized in that, include: processor; Memory used to store executable instructions; The processor is configured to, when executing executable instructions stored in the memory, implement the pixel unit compensation method according to any one of claims 6-12.

15. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the pixel unit compensation device, the pixel unit compensation device is able to perform the pixel unit compensation method according to any one of claims 6-12.

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