A DICE-based latch against multi-node and clock single event upsets

Abstract

The application discloses a D-type latch based on DICE and resisting multi-node single event upset and clock signal single event upset. Through designing an input circuit composed of one C unit and a delay structure, single event transient pulse of an input signal can be resisted; through composing a latch circuit from four clock-controlled transmission units and a DICE structure, and composing an output circuit from three C units and one inverter, multi-node single event upset can be resisted; through composing a double clock signal circuit from four inverters, the latch can resist clock signal single event upset.

Description

Technical Field

[0001] This invention relates to a novel latch, particularly a D-type latch based on DICE that resists multi-node single-event flips and clock signal single-event flips, belonging to the field of circuit-level radiation hardening technology. Background Technology

[0002] With the continuous development of my country's aerospace field, the research and development of aerospace components is becoming increasingly important. The working environment of aerospace components is subject to a large amount of particle radiation: cosmic rays, solar flare radiation, and the inner and outer Van Allen radiation belts, etc. As the core of various spacecraft systems, semiconductors and microelectronic devices are highly sensitive to radiation. Radiation can affect their performance and function to varying degrees, causing temporary or permanent failures of spacecraft. Radiation has become a major factor in the failure of aerospace components. Radiation-hardened integrated circuits have become a key technology supporting the entire aerospace application.

[0003] Due to the different types and energies of radiating particles and based on the different mechanisms of their generation, irradiation effects can be classified into: total dose effect, single-event effect, and displacement damage effect. The single-event effect is a transient effect. When a single high-energy particle is incident on a semiconductor device, it undergoes an ionization reaction along its incident trajectory, generating a large number of electron-hole pairs. Under the influence of an electric field, these electron-hole pairs are collected by sensitive nodes in the semiconductor device, causing transient or permanent malfunctions.

[0004] Single-event effects can be categorized into two types: permanent hard errors and non-permanent soft errors. Hard errors include single-event burn-out (SEB) and single-event gate breakdown (SEGR); soft errors include single-event upset (SEU) and single-event transient (SET). A single-event upset occurs when a single high-energy particle enters a semiconductor device, generating a charge that is collected by a sensitive node, causing a flip in the logic state of the memory circuit, resulting in a soft error. A single-event transient occurs when a single high-energy particle enters a semiconductor device, generating a charge that is collected by a sensitive node, producing a transient current or voltage that propagates through the circuit, leading to a soft error. The reduction in process size leads to lower supply voltages, smaller node capacitances, and weaker electrical shielding, thus increasing the probability of soft errors caused by single-event effects. Soft errors such as single-event upsets and single-event transients will become major causes of failure in aerospace devices, making radiation hardening technologies for soft errors a key research focus.

[0005] Radiation-hardened integrated circuits (ICs) are generally classified into three types: system-level hardening, device-level hardening, and circuit-level hardening. Circuit-level hardening is typically known as design-based hardening (RHBD). RHBD improves the radiation resistance of ICs by modifying circuitry and layout, requiring no changes to the manufacturing process, resulting in low cost and wide applicability, making it the mainstream hardening method. The DICE (Diverterless Interruptible Electron Device) structure is a widely used circuit-level radiation-hardened structure targeting single-event upsets (SEE). A traditional DICE structure consists of four mutually coupled inverters, with each pair of transistors forming a sensitive node pair. A SEE in any one node will not change the data in other nodes, and the flipped data is not latched. However, the DICE structure also has drawbacks: 1. It cannot immunize against SEE introduced from the clock input; 2. As device size shrinks, the spacing between the sensitive nodes in the DICE structure decreases, expanding the range of influence of a single high-energy particle, which can affect multiple nodes, thus reducing the hardening effect of the DICE structure. Summary of the Invention

[0006] The technical problem solved by this invention is to improve the DICE structure based on circuit-level design hardening, and to provide a D-type latch with significantly improved resistance to single-event upsets.

[0007] The technical solution of this invention is:

[0008] A DICE-based latch resistant to multi-node and clock single-event flip-flops includes: an input circuit, a latch circuit, an output circuit, a clock signal circuit CLK1, and a clock signal circuit CLK2.

[0009] Input circuit: Receives externally transmitted data signal D, flips the data signal D to obtain data signal D' and transmits it to the latch circuit;

[0010] Clock signal circuit CLK1: Receives the first clock signal CLK from the outside, flips it to obtain the second clock signal and transmits it to the latch circuit to control the working state of the latch circuit; the second clock signal includes: the clock signal of the common node CLKN1 that is flipped once and the clock signal of the common node CLKNN1 that is flipped twice.

[0011] Clock signal circuit CLK2: Receives the first clock signal CLK from the outside, flips it to obtain the third clock signal and transmits it to the latch circuit to control the working state of the latch circuit. The third clock signal includes: the clock signal of the common node CLKN2 that is flipped once and the clock signal of the common node CLKNN2 that is flipped twice.

[0012] Latch circuit: Controlled by the second clock signal of clock signal circuit CLK1 and the third clock signal of clock signal circuit CLK2, when the first clock signal CLK is high, it receives the data signal D' transmitted from the input circuit. The latch circuit is in a transparent state, and it flips the data signal D' input from the input circuit in real time to obtain the data signal D” and transmits the data signal D” to the output circuit. When the first clock signal CLK is low, it does not receive the data signal D' transmitted from the input circuit. The latch circuit is in a latching state, latching the last data signal D' received from the input circuit when the first clock signal CLK is high. It flips the data signal D' to obtain the data signal D” and repeatedly transmits the data signal D” to the output circuit.

[0013] Output circuit: Receives the data signal D” transmitted by the latch circuit, flips the data signal D” transmitted by the latch circuit n times and outputs the output signal, where n is a positive integer.

[0014] Preferably, the clock signals of the common node CLKN1 and the common node CLKN2 are synchronized in terms of high and low levels.

[0015] Preferably, the clock signals of the common node CLKNN1 and the common node CLKNN2 are synchronized in terms of high and low levels.

[0016] Preferably, when the first clock signal CLK is low, the clock signals of common node CLKN1 and common node CLKN2 are high, and the clock signals of common node CLKNN1 and common node CLKNN2 are low.

[0017] Preferably, the output circuit flips the data signal transmitted by the latch circuit n times and outputs an output signal, where n ≥ 3 and is an odd number, and the level of the output signal is consistent with the level of the data signal D.

[0018] Preferably, the clock signal circuit CLK1 includes: inverter INV1 and inverter INV2;

[0019] Inverter INV1 includes: PMOS transistor p1 and NMOS transistor n1;

[0020] The source of PMOS transistor p1 is connected to the power supply voltage VDD, and the gate of PMOS transistor p1 receives the first clock signal CLK.

[0021] The source of NMOS transistor n1 is grounded, the gate of NMOS transistor n1 receives the first clock signal CLK, the drain of NMOS transistor n1 is connected to the drain of PMOS transistor p1 to form a common node CLKN1, and the common node CLKN1 serves as the output terminal to output the second clock signal.

[0022] Inverter INV2 consists of: PMOS transistor p2 and NMOS transistor n2;

[0023] The source of PMOS transistor p2 is connected to the power supply voltage VDD, and the gate of PMOS transistor p2 receives the second clock signal output by the common node CLKN1.

[0024] The source of NMOS transistor n2 is grounded, and the gate of NMOS transistor n2 receives the clock signal of common node CLKN1. The drain of NMOS transistor n2 is connected to the drain of PMOS transistor p2 to form common node CLKNN1. Common node CLKNN1 serves as the output terminal to output the second clock signal.

[0025] Preferably, the clock signal circuit CLK2 includes: inverter INV3 and inverter INV4;

[0026] Inverter INV3 includes: PMOS transistor p3 and NMOS transistor n3;

[0027] The source of PMOS transistor p3 is connected to the power supply voltage VDD, and the gate of PMOS transistor p3 receives the first clock signal CLK.

[0028] The source of NMOS transistor n3 is grounded, the gate of NMOS transistor n3 receives the first clock signal CLK, the drain of NMOS transistor n3 is connected to the drain of PMOS transistor p3 to form a common node CLKN2, and the common node CLKN2 serves as the output terminal to output the third clock signal.

[0029] Inverter INV4 includes: PMOS transistor p4 and NMOS transistor n4;

[0030] The source of PMOS transistor p4 is connected to the power supply voltage VDD, and the gate of PMOS transistor p4 receives the third clock signal output by the common node CLKN2.

[0031] The source of NMOS transistor n4 is grounded, and the gate of NMOS transistor n4 receives the clock signal of common node CLKN2. The drain of NMOS transistor n4 is connected to the drain of PMOS transistor p4 to form common node CLKNN2. Common node CLKNN2 serves as the output terminal to output the third clock signal.

[0032] Preferably, the input circuit includes: a delay structure and a C unit C1;

[0033] The delay structure includes: inverter INV6 and inverter INV7;

[0034] Inverter INV6 includes: PMOS transistor p28 and NMOS transistor n28;

[0035] The source of PMOS transistor p28 is connected to the power supply voltage VDD, and the gate of PMOS transistor p28 receives the externally input data signal D.

[0036] The source of NMOS transistor n28 is grounded, the gate of NMOS transistor n28 receives the data signal D, and the drain of NMOS transistor n28 is connected to the drain of PMOS transistor p28 to form a common node D0.

[0037] Inverter INV7 includes: PMOS transistor p29 and NMOS transistor n29;

[0038] The source of PMOS transistor p29 is connected to the power supply voltage VDD, and the gate of PMOS transistor p29 receives the signal from the common node D0.

[0039] The source of NMOS transistor n29 is grounded, the gate of NMOS transistor n29 receives the signal of common node D0, and the drain of NMOS transistor n29 is connected to the drain of PMOS transistor p29 to form common node D1.

[0040] Unit C1 includes: PMOS transistor p5, PMOS transistor p6, NMOS transistor n5, and NMOS transistor n6;

[0041] The source of PMOS transistor p5 is connected to the power supply voltage VDD, and the gate of PMOS transistor p5 receives the externally input data signal D.

[0042] The source of PMOS transistor p6 is connected to the drain of PMOS transistor p5, and the gate of PMOS transistor p6 receives the signal from common node D1.

[0043] The source of NMOS transistor n5 is grounded, and the gate of NMOS transistor n5 receives the externally input data signal D.

[0044] The source of NMOS transistor n6 is connected to the drain of NMOS transistor n5. The gate of NMOS transistor n6 receives the signal from the common node D1. The drain of NMOS transistor n6 is connected to the drain of PMOS transistor p6, forming a common node DN. The common node DN serves as the output terminal, outputting the data signal D'.

[0045] Preferably, the latching circuit includes: a clock-controlled transmission unit C2, a clock-controlled transmission unit C3, a clock-controlled transmission unit C4, a clock-controlled transmission unit C5, and a DICE structure;

[0046] The clock-controlled transmission unit C2 includes: PMOS transistor p7, PMOS transistor p8, NMOS transistor n7, and NMOS transistor n8;

[0047] The source of PMOS transistor p7 is connected to the power supply voltage VDD, and the gate of PMOS transistor p7 receives the data signal D' output from the common node DN.

[0048] The source of PMOS transistor p8 is connected to the drain of PMOS transistor p7, and the gate of PMOS transistor p8 receives the second clock signal output by the common node CLKN1.

[0049] The source of NMOS transistor n7 is grounded, and the gate of NMOS transistor n7 receives the data signal D' output from the common node DN;

[0050] The source of NMOS transistor n8 is connected to the drain of NMOS transistor n7, the gate of NMOS transistor n8 receives the second clock signal output by the common node CLKNN1, and the drain of NMOS transistor n8 is connected to the drain of PMOS transistor p8, forming a common node N5.

[0051] The clock-controlled transmission unit C3 includes: PMOS transistor p9, PMOS transistor p10, NMOS transistor n9, and NMOS transistor n10;

[0052] The source of PMOS transistor p9 is connected to the power supply voltage VDD, and the gate of PMOS transistor p9 receives the data signal D' output from the common node DN.

[0053] The source of PMOS transistor p10 is connected to the drain of PMOS transistor p9, and the gate of PMOS transistor p10 receives the third clock signal output by the common node CLKN2.

[0054] The source of NMOS transistor n9 is grounded, and the gate of NMOS transistor n9 receives the data signal D' output from the common node DN;

[0055] The source of NMOS transistor n10 is connected to the drain of NMOS transistor n9. The gate of NMOS transistor n10 receives the third clock signal output by the common node CLKNN2. The drain of NMOS transistor n10 is connected to the drain of PMOS transistor p10, forming a common node N4.

[0056] The clock-controlled transmission unit C4 includes: PMOS transistor p11, PMOS transistor p12, NMOS transistor n11, and NMOS transistor n12;

[0057] The source of PMOS transistor p11 is connected to the power supply voltage VDD, and the gate of PMOS transistor p11 receives the data signal D' output from the common node DN;

[0058] The source of PMOS transistor p12 is connected to the drain of PMOS transistor p11, and the gate of PMOS transistor p12 receives the second clock signal output by the common node CLKN1.

[0059] The source of NMOS transistor n11 is grounded, and the gate of NMOS transistor n11 receives the data signal D' output from the common node DN;

[0060] The source of NMOS transistor n12 is connected to the drain of NMOS transistor n11, the gate of NMOS transistor n12 receives the second clock signal output by the common node CLKNN1, and the drain of NMOS transistor n12 is connected to the drain of PMOS transistor p12, forming a common node N2.

[0061] The clock-controlled transmission unit C5 includes: PMOS transistor p13, PMOS transistor p14, NMOS transistor n13, and NMOS transistor n14;

[0062] The source of PMOS transistor p13 is connected to the power supply voltage VDD, and the gate of PMOS transistor p13 receives the signal from the common node N5.

[0063] The source of PMOS transistor p14 is connected to the drain of PMOS transistor p13, and the gate of PMOS transistor p14 receives the second clock signal output by the common node CLKN1.

[0064] The source of NMOS transistor n13 is grounded, and the gate of NMOS transistor n13 receives the signal from the common node N5.

[0065] The source of NMOS transistor n14 is connected to the drain of NMOS transistor n13. The gate of NMOS transistor n14 receives the second clock signal output from the common node CLKNN1. The drain of NMOS transistor n14 is connected to the drain of PMOS transistor p14, forming the common node N6 output data signal D”.

[0066] The DICE structure includes: a transmission unit C9, a clock-controlled transmission unit C10, a transmission unit C11, and a clock-controlled transmission unit C12.

[0067] Transmission unit C9 includes: PMOS transistor p22 and NMOS transistor n22;

[0068] The source of PMOS transistor p22 is connected to the power supply voltage VDD, and the gate of PMOS transistor p22 receives the signal from the common node N4.

[0069] The source of NMOS transistor n22 is grounded, the gate of NMOS transistor n22 receives the signal of common node N2, and the drain of NMOS transistor n22 is connected to the drain of PMOS transistor p22, forming a common node N1 output data signal D”;

[0070] The clock-controlled transmission unit C10 includes: PMOS transistor p23, PMOS transistor p24, NMOS transistor n23, and NMOS transistor n24;

[0071] The source of PMOS transistor p23 is connected to the power supply voltage VDD, and the gate of PMOS transistor p23 receives the data signal D” output from the common node N1.

[0072] The source of PMOS transistor p24 is connected to the drain of PMOS transistor p23, the gate of PMOS transistor p24 receives the second clock signal output from common node CLKNN1, and the drain of PMOS transistor p24 is connected to common node N2.

[0073] The source of NMOS transistor n23 is grounded, and the gate of NMOS transistor n23 receives the data signal D” output from the common node N3;

[0074] The source of NMOS transistor n24 is connected to the drain of NMOS transistor n23, the gate of NMOS transistor n24 receives the second clock signal output by common node CLKN1, and the drain of NMOS transistor n24 is connected to common node N2.

[0075] Transmission unit C11 includes: NMOS transistor n25 and PMOS transistor p25;

[0076] The source of PMOS transistor p25 is connected to the power supply voltage VDD, and the gate of PMOS transistor p25 receives the signal from the common node N2.

[0077] The source of NMOS transistor n25 is grounded, the gate of NMOS transistor n25 receives the signal of common node N4, and the drain of NMOS transistor n25 is connected to the drain of PMOS transistor p25, forming a common node N3 output data signal D”;

[0078] The clock-controlled transmission unit C12 includes: PMOS transistor p26, PMOS transistor p27, NMOS transistor n26, and NMOS transistor n27;

[0079] The source of PMOS transistor p26 is connected to the power supply voltage VDD, and the gate of PMOS transistor p26 receives the data signal D” output from the common node N3.

[0080] The source of PMOS transistor p27 is connected to the drain of PMOS transistor p26, the gate of PMOS transistor p27 receives the third clock signal output by common node CLKNN2, and the drain of PMOS transistor p27 is connected to common node N4.

[0081] The source of NMOS transistor n26 is grounded, and the gate of NMOS transistor n26 receives the data signal D” output from the common node N1;

[0082] The source of NMOS transistor n27 is connected to the drain of NMOS transistor n26, the gate of NMOS transistor n27 receives the third clock signal output from common node CLKN2, and the drain of NMOS transistor n27 is connected to common node N4.

[0083] Preferably, the output circuit includes: C unit C6, C unit C7, C unit C8 and inverter INV5;

[0084] Unit C6 includes: PMOS transistor p15, PMOS transistor p16, NMOS transistor n15, and NMOS transistor n16;

[0085] The source of PMOS transistor p15 is connected to the power supply voltage VDD, and the gate of PMOS transistor p15 receives the data signal D” output from the common node N3.

[0086] The source of PMOS transistor p16 is connected to the drain of PMOS transistor p15, and the gate of PMOS transistor p16 receives the data signal D” output from common node N6;

[0087] The source of NMOS transistor n15 is grounded, and the gate of NMOS transistor n15 receives the data signal D” output from the common node N3;

[0088] The source of NMOS transistor n16 is connected to the drain of NMOS transistor n15, the gate of NMOS transistor n16 receives the data signal D” output from the common node N6, and the drain of NMOS transistor n16 is connected to the drain of PMOS transistor p16, forming a common node N7;

[0089] Unit C7 includes: PMOS transistor p17, PMOS transistor p18, NMOS transistor n17, and NMOS transistor n18;

[0090] The source of PMOS transistor p17 is connected to the power supply voltage VDD, and the gate of PMOS transistor p17 receives the data signal D” output from the common node N6.

[0091] The source of PMOS transistor p18 is connected to the drain of PMOS transistor p17, and the gate of PMOS transistor p18 receives the data signal D” output from common node N1;

[0092] The source of NMOS transistor n17 is grounded, and the gate of NMOS transistor n17 receives the data signal D” output from the common node N6;

[0093] The source of NMOS transistor n18 is connected to the drain of NMOS transistor n17, and the gate of NMOS transistor n18 receives the data signal D” output from the common node N1. The drain of NMOS transistor n18 is connected to the drain of PMOS transistor p18, forming a common node N8.

[0094] Unit C8 includes: PMOS transistor p19, PMOS transistor p20, NMOS transistor n19 and NMOS transistor n20;

[0095] The source of PMOS transistor p19 is connected to the power supply voltage VDD, and the gate of PMOS transistor p19 receives the signal from the common node N7.

[0096] The source of PMOS transistor p20 is connected to the drain of PMOS transistor p19, and the gate of PMOS transistor p20 receives the signal from the common node N8.

[0097] The source of NMOS transistor n19 is grounded, and the gate of NMOS transistor n19 receives the signal from the common node N7.

[0098] The source of NMOS transistor n20 is connected to the drain of NMOS transistor n19. The gate of NMOS transistor n20 receives the signal of common node N8. The drain of NMOS transistor n20 is connected to the drain of PMOS transistor p20, forming a common node QN.

[0099] Inverter INV5 includes: PMOS transistor p21 and NMOS transistor n21;

[0100] The source of PMOS transistor p21 is connected to the power supply voltage VDD, and the gate of PMOS transistor p21 receives the common node QN signal.

[0101] The source of NMOS transistor n21 is grounded, and the gate of NMOS transistor n21 receives the common node QN signal. The drain of NMOS transistor n21 is connected to the drain of PMOS transistor p21 to form a common node Q. The common node Q serves as the output terminal of the output circuit and outputs the output signal to the outside.

[0102] The advantages of this invention compared to the prior art are:

[0103] This invention provides a D-type latch based on DICE (Digital Event-Conveyor Interface) that is resistant to multiple nodes and single-event clock flips. The clock signal circuit is redundantly divided into two identical clock signal circuits, CLK1 and CLK2. The operating state of the latch circuit is controlled by the clock signals of these two circuits. When the DICE structure is in latching mode, if the clock signal of one of the clock signal circuits is flipped by a single event, only one input node is affected. Based on the characteristics of the DICE structure, when one node flips, its redundant structure restores it, and the flipped data is not latched. Only when the clock signals of both clock signal circuits CLK1 and CLK2 flip, causing an overall malfunction in the latch circuit, will the output circuit output an incorrect result. This improves the DICE structure's resistance to single-event clock flips.

[0104] When the redundant nodes of a traditional DICE structure all flip, the data output by the DICE structure will also flip, resulting in erroneous data. This invention provides a D-type latch based on DICE that is resistant to multiple nodes and single-event clock flips. It adds a transmission circuit consisting of a transmission unit C2 controlled by the clock signal of clock signal circuit CLK1 and a clock-controlled transmission unit C5. This, along with clock-controlled transmission units C3 and C4 and the DICE structure, forms a three-output latch circuit. C units C6, C7, C8, and inverter INV5 constitute the output circuit. The output circuit will only output an erroneous result when the signals of common nodes N6, N3, and N1 all flip. When multiple nodes in the DICE structure flip, causing errors in the output signals of common nodes N3 and N1, the output of common node N6 of another transmission circuit, which is composed of transmission unit C2 controlled by the clock signal circuit CLK1 and transmission unit C5 controlled by the clock signal, does not flip. Units C6 and C7 are in a high-impedance state, and the output signal of unit C8 remains unchanged. The latch will not output incorrect results, thus improving the DICE structure's ability to resist multi-node single-event flips. Attached Figure Description

[0105] Figure 1 This is a schematic diagram of the structure of the D-type latch of the present invention;

[0106] Figure 2 This is a schematic diagram of the DICE structure in a latch;

[0107] Figure 3 This is a schematic diagram of the clock signal in the latch;

[0108] Figure 4 This is a schematic diagram of the delay structure in a latch. Detailed Implementation

[0109] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0110] In one embodiment of the present invention, a D-type latch is provided, which is an improvement on the DICE structure to enhance its resistance to clock signal single-event flips (SETs) and multi-node SETs. Specifically, as shown... Figure 1The diagram shown is a schematic diagram of the structure of the D-type latch of the present invention. The D-type latch includes: an input circuit, a latching circuit, an output circuit, a clock signal circuit CLK1, and a clock signal circuit CLK2.

[0111] Input circuit: Receives externally transmitted data signal D, flips the data signal D to obtain data signal D' and transmits it to the latch circuit;

[0112] Clock signal circuit CLK1: Receives the first clock signal CLK from the outside, flips it to obtain the second clock signal and transmits it to the latch circuit to control the working state of the latch circuit; the second clock signal includes: the clock signal of the common node CLKN1 that is flipped once and the clock signal of the common node CLKNN1 that is flipped twice.

[0113] Clock signal circuit CLK2: Receives the first clock signal CLK from the outside, flips it to obtain a third clock signal, and transmits it to the latch circuit to control the operating state of the latch circuit. The third clock signal includes: a clock signal of common node CLKN2 that undergoes one flip and a clock signal of common node CLKNN2 that undergoes two flips; the clock signals of common node CLKN1 and common node CLKN2 are synchronized in high and low levels. The clock signals of common node CLKNN1 and common node CLKNN2 are synchronized in high and low levels.

[0114] The latch circuit is controlled by the second clock signal of clock signal circuit CLK1 and the third clock signal of clock signal circuit CLK2. When the first clock signal CLK is high, it receives the data signal D' transmitted from the input circuit. The latch circuit is in a transparent state, and it flips the data signal D' input by the input circuit in real time to obtain the data signal D” and transmits the data signal D” to the output circuit. When the first clock signal CLK is low (the clock signals of common node CLKN1 and common node CLKN2 are high, and the clock signals of common node CLKNN1 and common node CLKNN2 are high), it receives the data signal D' transmitted from the input circuit. When the clock signal level of 2 is low, the input circuit does not receive the data signal D' transmitted by the input circuit. The latch circuit is in latching state and latches the last data signal D' transmitted by the input circuit when the first clock signal CLK is high. The data signal D' is flipped and processed to obtain the data signal D''', and the data signal D'''' is repeatedly transmitted to the output circuit. The output circuit receives the data signal D''' transmitted by the latch circuit, flips the data signal D'''' transmitted by the latch circuit n times, and outputs the output signal, where n ≥ 3 and is an odd number. The output signal level of the output circuit is consistent with the data signal D''''s level.

[0115] like Figure 3As shown, the clock signal circuit includes clock signal circuit CLK1 and clock signal circuit CLK2. For details, please refer to [link / reference needed]. Figure 3 The clock signal circuit CLK1 includes inverters INV1 and INV2. Inverter INV1 includes a PMOS transistor p1 and an NMOS transistor n1.

[0116] PMOS transistor p1, the source of PMOS transistor p1 is connected to the power supply voltage VDD, and the gate of PMOS transistor p1 receives the first clock signal CLK;

[0117] The source of NMOS transistor n1 is grounded, the gate of NMOS transistor n1 receives the first clock signal CLK, the drain of NMOS transistor n1 is connected to the drain of PMOS transistor p1 to form a common node CLKN1, and the common node CLKN1 serves as the output terminal to output the second clock signal.

[0118] The inverter INV2 consists of a PMOS transistor p2 and an NMOS transistor n2.

[0119] The source of PMOS transistor p2 is connected to the power supply voltage VDD, and the gate of PMOS transistor p2 receives the second clock signal output by the common node CLKN1.

[0120] The source of NMOS transistor n2 is grounded, and the gate of NMOS transistor n2 receives the clock signal of common node CLKN1. The drain of NMOS transistor n2 is connected to the drain of PMOS transistor p2 to form common node CLKNN1. Common node CLKNN1 serves as the output terminal to output the second clock signal.

[0121] like Figure 3 As shown, the clock signal circuit CLK2 includes inverters INV3 and INV4.

[0122] The source of PMOS transistor p3 is connected to the power supply voltage VDD, and the gate of PMOS transistor p3 receives the first clock signal CLK.

[0123] The source of NMOS transistor n3 is grounded, and the gate of NMOS transistor n3 receives the first clock signal CLK. The drain of NMOS transistor n3 is connected to the drain of PMOS transistor p3 to form a common node CLKN2. The common node CLKN2 serves as the output terminal to output the third clock signal.

[0124] The inverter INV4 consists of: PMOS transistor p4 and NMOS transistor n4.

[0125] The source of PMOS transistor p4 is connected to the power supply voltage VDD, and the gate of PMOS transistor p4 receives the third clock signal output by the common node CLKN2.

[0126] The source of NMOS transistor n4 is grounded, and the gate of NMOS transistor n4 receives the clock signal of common node CLKN2. The drain of NMOS transistor n4 is connected to the drain of PMOS transistor p4 to form common node CLKNN2. Common node CLKNN2 serves as the output terminal to output the third clock signal.

[0127] like Figure 4 As shown, the input circuit includes a delay structure and a C unit C1.

[0128] The delay structure includes inverters INV6 and INV7; inverter INV6 includes a PMOS transistor p28 and an NMOS transistor n28. The source of PMOS transistor p28 is connected to the power supply voltage VDD, and the gate of PMOS transistor p28 receives the externally input data signal D; the source of NMOS transistor n28 is grounded, the gate of NMOS transistor n28 receives the data signal D, and the drain of NMOS transistor n28 is connected to the drain of PMOS transistor p28, forming a common node D0.

[0129] Inverter INV7 includes: PMOS transistor p29 and NMOS transistor n29. The source of PMOS transistor p29 is connected to the power supply voltage VDD, and the gate of PMOS transistor p29 receives the signal of common node D0; the source of NMOS transistor n29 is grounded, the gate of NMOS transistor n29 receives the signal of common node D0, and the drain of NMOS transistor n29 is connected to the drain of PMOS transistor p29 to form common node D1.

[0130] like Figure 1 As shown, unit C1 includes: PMOS transistor p5, PMOS transistor p6, NMOS transistor n5 and NMOS transistor n6.

[0131] The source of PMOS transistor p5 is connected to the power supply voltage VDD, and the gate of PMOS transistor p5 receives the data signal D.

[0132] The source of PMOS transistor p6 is connected to the drain of PMOS transistor p5, and the gate of PMOS transistor p6 receives the signal from common node D1.

[0133] The source of NMOS transistor n5 is grounded, and the gate of NMOS transistor n5 receives the data signal D.

[0134] The source of NMOS transistor n6 is connected to the drain of NMOS transistor n5. The gate of NMOS transistor n6 receives the signal from the common node D1. The drain of NMOS transistor n6 is connected to the drain of PMOS transistor p6 to form a common node DN. The common node DN serves as the output terminal, outputting the data signal D'.

[0135] like Figure 1As shown, the latching circuit includes: clock-controlled transmission unit C2, clock-controlled transmission unit C3, clock-controlled transmission unit C4, clock-controlled transmission unit C5, and a DICE structure.

[0136] The clock-controlled transmission unit C2 includes: PMOS transistor p7, PMOS transistor p8, NMOS transistor n7, and NMOS transistor n8.

[0137] The source of PMOS transistor p7 is connected to the power supply voltage VDD, and the gate of PMOS transistor p7 receives the data signal D' output from the common node DN.

[0138] The source of PMOS transistor p8 is connected to the drain of PMOS transistor p7, and the gate of PMOS transistor p8 receives the second clock signal output by the common node CLKN1.

[0139] The source of NMOS transistor n7 is grounded, and the gate of NMOS transistor n7 receives the data signal D' output from the common node DN;

[0140] The source of NMOS transistor n8 is connected to the drain of NMOS transistor n7. The gate of NMOS transistor n8 receives the second clock signal output from the common node CLKNN1. The drain of NMOS transistor n8 is connected to the drain of PMOS transistor p8, forming a common node N5.

[0141] The clock-controlled transmission unit C3 includes: PMOS transistor p9, PMOS transistor p10, NMOS transistor n9, and NMOS transistor n10;

[0142] The source of PMOS transistor p9 is connected to the power supply voltage VDD, and the gate of PMOS transistor p9 receives the data signal D' output from the common node DN.

[0143] The source of PMOS transistor p10 is connected to the drain of PMOS transistor p9, and the gate of PMOS transistor p10 receives the third clock signal output by the common node CLKN2.

[0144] The source of NMOS transistor n9 is grounded, and the gate of NMOS transistor n9 receives the signal from the common node DN.

[0145] The source of NMOS transistor n10 is connected to the drain of NMOS transistor n9. The gate of NMOS transistor n10 receives the third clock signal output by the common node CLKNN2. The drain of NMOS transistor n10 is connected to the drain of PMOS transistor p10, forming a common node N4, which serves as the output terminal.

[0146] The clock-controlled transmission unit C4 includes: PMOS transistor p11, PMOS transistor p12, NMOS transistor n11, and NMOS transistor n12;

[0147] The source of PMOS transistor p11 is connected to the power supply voltage VDD, and the gate of PMOS transistor p11 receives the data signal D' output from the common node DN;

[0148] The source of PMOS transistor p12 is connected to the drain of PMOS transistor p11, and the gate of PMOS transistor p12 receives the second clock signal output by the common node CLKN1.

[0149] The source of NMOS transistor n11 is grounded, and the gate of NMOS transistor n11 receives the data signal D' output from the common node DN;

[0150] The source of NMOS transistor n12 is connected to the drain of NMOS transistor n11. The gate of NMOS transistor n12 receives the second clock signal output from the common node CLKNN1. The drain of NMOS transistor n12 is connected to the drain of PMOS transistor p12, forming a common node N2, which serves as the output terminal.

[0151] The clock-controlled transmission unit C5 includes: PMOS transistor p13, PMOS transistor p14, NMOS transistor n13, and NMOS transistor n14;

[0152] The source of PMOS transistor p13 is connected to the power supply voltage VDD, and the gate of PMOS transistor p13 receives the signal from the common node N5.

[0153] The source of PMOS transistor p14 is connected to the drain of PMOS transistor p13, and the gate of PMOS transistor p14 receives the second clock signal output by the common node CLKN1.

[0154] The source of NMOS transistor n13 is grounded, and the gate of NMOS transistor n13 receives the signal from the common node N5.

[0155] The source of NMOS transistor n14 is connected to the drain of NMOS transistor n13. The gate of NMOS transistor n14 receives the second clock signal output from the common node CLKNN1. The drain of NMOS transistor n14 is connected to the drain of PMOS transistor p14, forming a common node N6. The common node N6 outputs the data signal D”.

[0156] like Figure 2 As shown, the DICE structure includes: a transmission unit C9, a clock-controlled transmission unit C10, a transmission unit C11, and a clock-controlled transmission unit C12.

[0157] Transmission unit C9 includes: PMOS transistor p22 and NMOS transistor n22;

[0158] The source of PMOS transistor p22 is connected to the power supply voltage VDD, and the gate of PMOS transistor p22 receives the signal from the common node N4.

[0159] The source of NMOS transistor n22 is grounded, the gate of NMOS transistor n22 receives the signal of common node N2, and the drain of NMOS transistor n22 is connected to the drain of PMOS transistor p22 to form common node N1. Common node N1 outputs data signal D”.

[0160] The clock-controlled transmission unit C10 includes: PMOS transistor p23, PMOS transistor p24, NMOS transistor n23, and NMOS transistor n24;

[0161] The source of PMOS transistor p23 is connected to the power supply voltage VDD, and the gate of PMOS transistor p23 receives the data signal D” output from the common node N1;

[0162] The source of PMOS transistor p24 is connected to the drain of PMOS transistor p23, the gate of PMOS transistor p24 receives the second clock signal output from common node CLKNN1, and the drain of PMOS transistor p24 is connected to common node N2.

[0163] The source of NMOS transistor n23 is grounded, and the gate of NMOS transistor n23 receives the data signal D” output from the common node N3;

[0164] The source of NMOS transistor n24 is connected to the drain of NMOS transistor n23, the gate of NMOS transistor n24 receives the second clock signal output by common node CLKN1, and the drain of NMOS transistor n24 is connected to common node N2.

[0165] Transmission unit C11 includes: NMOS transistor n25 and PMOS transistor p25;

[0166] The source of PMOS transistor p25 is connected to the power supply voltage VDD, and the gate of PMOS transistor p25 receives the signal from the common node N2.

[0167] The source of NMOS transistor n25 is grounded, the gate of NMOS transistor n25 receives the signal from common node N4, and the drain of NMOS transistor n25 is connected to the drain of PMOS transistor p25, forming common node N3. Common node N3 outputs the data signal D.

[0168] The clock-controlled transmission unit C12 includes: PMOS transistor p26, PMOS transistor p27, NMOS transistor n26, and NMOS transistor n27.

[0169] The source of PMOS transistor p26 is connected to the power supply voltage VDD, and the gate of PMOS transistor p26 receives the data signal D” output from the common node N3.

[0170] The source of PMOS transistor p27 is connected to the drain of PMOS transistor p26, the gate of PMOS transistor p27 receives the third clock signal output by common node CLKNN2, and the drain of PMOS transistor p27 is connected to common node N4.

[0171] The source of NMOS transistor n26 is grounded, and the gate of NMOS transistor n26 receives the data signal D” output from the common node N1;

[0172] The source of NMOS transistor n27 is connected to the drain of NMOS transistor n26, the gate of NMOS transistor n27 receives the third clock signal output by common node CLKN2, and the drain of NMOS transistor n27 is connected to common node N4.

[0173] like Figure 1 As shown, the output circuit includes: C unit C6, C unit C7, C unit C8 and inverter INV5.

[0174] Unit C6 includes: PMOS transistor p15, PMOS transistor p16, NMOS transistor n15, and NMOS transistor n16.

[0175] The source of PMOS transistor p15 is connected to the power supply voltage VDD, and the gate of PMOS transistor p15 receives the data signal D” output from the common node N3.

[0176] The source of PMOS transistor p16 is connected to the drain of PMOS transistor p15, and the gate of PMOS transistor p16 receives the data signal D” output from common node N6;

[0177] The source of NMOS transistor n15 is grounded, and the gate of NMOS transistor n15 receives the data signal D” output from the common node N3;

[0178] The source of NMOS transistor n16 is connected to the drain of NMOS transistor n15, the gate of NMOS transistor n16 receives the data signal D” output from the common node N6, and the drain of NMOS transistor n16 is connected to the drain of PMOS transistor p16, forming a common node N7;

[0179] Unit C7 includes: PMOS transistor p17, PMOS transistor p18, NMOS transistor n17, and NMOS transistor n18.

[0180] The source of PMOS transistor p17 is connected to the power supply voltage VDD, and the gate of PMOS transistor p17 receives the data signal D” output from the common node N6.

[0181] The source of PMOS transistor p18 is connected to the drain of PMOS transistor p17, and the gate of PMOS transistor p18 receives the data signal D” output from common node N1;

[0182] The source of NMOS transistor n17 is grounded, and the gate of NMOS transistor n17 receives the data signal D” output from the common node N6;

[0183] The source of NMOS transistor n18 is connected to the drain of NMOS transistor n17, and the gate of NMOS transistor n18 receives the data signal D” output from the common node N1. The drain of NMOS transistor n18 is connected to the drain of PMOS transistor p18, forming a common node N8.

[0184] Unit C8 includes: PMOS transistor p19, PMOS transistor p20, NMOS transistor n19, and NMOS transistor n20.

[0185] The source of PMOS transistor p19 is connected to the power supply voltage VDD, and the gate of PMOS transistor p19 receives the signal from the common node N7.

[0186] The source of PMOS transistor p20 is connected to the drain of PMOS transistor p19, and the gate of PMOS transistor p20 receives the signal from the common node N8.

[0187] The source of NMOS transistor n19 is grounded, and the gate of NMOS transistor n19 receives the signal from the common node N7.

[0188] The source of NMOS transistor n20 is connected to the drain of NMOS transistor n19. The gate of NMOS transistor n20 receives the signal from the common node N8. The drain of NMOS transistor n20 is connected to the drain of PMOS transistor p20, forming a common node QN.

[0189] The inverter INV5 includes: PMOS transistor p21 and NMOS transistor n21.

[0190] The source of PMOS transistor p21 is connected to the power supply voltage VDD, and the gate of PMOS transistor p21 receives the common node QN signal.

[0191] The source of NMOS transistor n21 is grounded, the gate of NMOS transistor n21 receives the common node QN signal, and the drain of NMOS transistor n21 is connected to the drain of PMOS transistor p21 to form a common node Q. The common node Q serves as the output terminal, outputting the output signal of the output latch.

[0192] See Figure 1 , Figure 2 , Figure 3 , Figure 4It can be seen that when the first clock signal CLK is high, the MOS transistors whose gates are controlled by the clock signal in clock-controlled transmission units C2, C3, C4, and C5 are turned on, while the MOS transistors whose gates are controlled by the clock signal in clock-controlled transmission units C10 and C12 are turned off. At this time, clock-controlled transmission units C2, C3, C4, and C5 are turned on, and the D-type latch of this invention is in a transparent state. The total delay time of the delay structure is t. Due to the delay of the delay structure, the D-type latch of this invention can shield SET pulses of input signals with a width less than t. At time t1, the data signal D is high. At time t1+t, the signal of common node D1 is high. Therefore, at time t1+t, NMOS transistors n5 and n6 are turned on. At this time, the signal of common node DN is low. Therefore, PMOS transistors p7, p8, p9, p10, p11, and p12 are turned on. At this time, the signals of common nodes N5, N4, and N2 are high. Therefore, NMOS transistors n13 and n6 are high. When N14, NMOS transistors n22, and NMOS transistors n25 are turned on, the signals of common nodes N6, N3, and N1 are at a low level. Then, PMOS transistors p15, p16, p17, and p18 are turned on, and the signals of common nodes N7 and N8 are at a high level. Then, NMOS transistors n19 and n20 are turned on, and the QN signal of common nodes is at a low level. Then, PMOS transistor p21 is turned on, and the output signal of common node Q is at a high level. At time t2, the data signal D is low. At time t2+t, the signal at common node D1 is low. Therefore, at time t2+t, PMOS transistors p5 and p6 are turned on. At this time, the signal at common node DN is high. Therefore, NMOS transistors n7, n8, n9, n10, n11, and n12 are turned on. At this time, the signals at common nodes N5, N4, and N2 are low. Therefore, PMOS transistors p13 and p6 are low. When P14, P22, and P25 are turned on, the signals of common nodes N6, N3, and N1 are at a high level. Then, NMOS transistors n15, n16, n17, and n18 are turned on, and the signals of common nodes N7 and N8 are at a low level. Then, PMOS transistors p19 and p20 are turned on, and the QN signal of common node is at a high level. Then, NMOS transistor n21 is turned on, and the output signal of common node Q is at a low level.When the first clock signal CLK goes low, the MOS transistors whose gates are controlled by the clock signal in clock-controlled transmission units C2, C3, C4, and C5 are turned off, and the MOS transistors whose gates are controlled by the clock signal in clock-controlled transmission units C10 and C12 are turned on. The signals of common nodes N6, N3, and N1 remain unchanged, and C units C6, C7, and C8 are normally turned on. The output signal of common node Q remains unchanged. At this time, the D-type latch of the present invention is in a holding state. When the common node signals N6, N3, and N1 are high, NMOS transistors n15, n16, n17, and n18 are turned on. At this time, the common node signals N7 and N8 are low, and PMOS transistors p19 and p20 are turned on, resulting in a high common node signal QN. Conversely, when the common node signals N6, N3, and N1 are low, PMOS transistors p15, p16, p17, and p18 are turned on, and the common node signals N7 and N8 are high, NMOS transistors n19 and n20 are turned on, resulting in a low common node signal QN. The D-type latch logic function of this invention is normal.

[0193] According to the characteristics of the DICE structure, the signal stored in any one of the common nodes N1, N2, N3, and N4 will be flipped due to a single-event injection, but will be recovered after a period of time. The signals of common nodes N6, N3, and N1 will remain consistent, and C units C6, C7, and C8 will not enter a high-impedance state. In traditional DICE structures, if all redundant nodes flip, the output signal of the DICE structure will also flip, resulting in incorrect output results. In one embodiment of this invention, when the signals of common nodes N1 and N3 or N2 and N4 change, the other two nodes will also flip. The signals of common nodes N3 and N1 will differ from the signal of common node N6. At this time, C units C6 and C7 will enter a high-impedance state and will not output a single-event flip signal. The signals of common nodes N7 and N8 will remain unchanged, and will not affect the signal of common node QN. As shown in Table 1, only when the signals of common nodes N6, N3, and N1 all flip will common node QN output an incorrect signal, reducing the probability of incorrect output results. This embodiment of the invention has significant resistance to multi-node single-event flips.

[0194] Table 1 Truth Table of Output Circuit

[0195] N6 N3 N1 Q 1 1 1 0 0 0 0 1 0 0 1 Hold 0 1 0 Hold 0 1 1 Hold 1 1 0 Hold 1 0 1 Hold 1 0 0 Hold

[0196] According to the traditional DICE structure, when the clock signal flips due to a single-event event, the latch changes from a latched state to a transparent state, altering the latch's operating state and resulting in an incorrect output. In one embodiment of this invention, the clock signal circuit is redundantly divided into two identical clock signal circuits, CLK1 and CLK2. When the first clock signal CLK is low, a single-event event causes the clock signal of the common node CLKN2 to flip to low. At this time, PMOS transistors p9 and p10 are turned on, while PMOS transistors p27 and nMOS transistor n27 are turned off. If the common node DN signal is the same as the latched signal at this time, the signals of common nodes N2, N5, N4, N6, N3, and N1 remain unchanged, and the common node Q output signal remains unchanged. At this time, the common node DN signal is the same as the latched signal. Conversely, the signals of common nodes N2, N5, and N6 remain unchanged, the signal of common node N4 changes, the signal of common node N3 or N1 flips, and C unit C6 or C unit C7 enters a high-impedance state. The signals of common nodes N7 and N8 remain unchanged and will not affect the output signal of common node QN. After the clock signal of common node CLKN2 is restored to its original value, due to the inherent characteristics of the DICE structure, the node signals will be restored after a period of time. Therefore, the signals of common nodes N6, N3, and N1 remain consistent, C unit C6, C unit C7, and C unit C8 will not enter a high-impedance state, and the output signal of common node Q remains unchanged. When the first clock signal CLK is low, a single event causes the clock signal of the common node CLKN1 to flip to low. At this time, PMOS transistors p7, p8, p11, p12, p13, and p14 are turned on, while PMOS transistors p24 and NMOS transistor n24 are turned off. If the common node DN signal is the same as the latched signal, the common node N2, N5, N4, N6, N3, and N1 signals remain unchanged, and the common node Q output signal remains unchanged. If the common node DN signal is opposite to the latched signal, the common node N4 signal remains unchanged, the common node N2 signal changes, and the common node N3 or N1 signal flips. Signals N5 and N6 flip. One of C units C6 and C7 enters a high-impedance state, while the other does not, but its output signal changes. The signals of common nodes N7 and N8 are inconsistent. C unit C8 enters a high-impedance state, which does not affect the output signal of common node QN. The output signal of common node Q remains unchanged. After the clock signal of common node CLKN1 is restored to its original value, due to the inherent characteristics of the DICE structure, the node signals will be restored after a period of time. Therefore, the signals of common nodes N3 and N1 remain consistent, while the signal of common node N6 is not restored and is inconsistent with the signals of common nodes N3 and N1. C units C6 and C7 enter a high-impedance state. The output signals of common nodes N7, N8, and QN remain unchanged, and the output signal of common node Q remains unchanged.Only when the clock signals of clock signal circuits CLK1 and CLK2 both flip, and the common node DN signal is opposite to the latched signal, the clock-controlled transmission units C2, C3, C4, and C5 are turned on, the common node N6, N3, and N1 signals flip, and C units C6, C7, and C8 are turned on, resulting in an error in the common node Q output signal. This embodiment of the invention has a significant ability to resist single-event upsets of clock signals.

[0197] Further analysis based on the same principle shows that when the gate of PMOS transistor p10 receives the clock signal of common node CLKN1, the gate of NMOS transistor n10 receives the clock signal of common node CLKNN1, the gate of PMOS transistor p12 receives the clock signal of common node CLKN2, and the gate of NMOS transistor n10 receives the clock signal of common node CLKNN2, another embodiment of the present invention also has obvious resistance to single-event upsets of clock signals.

[0198] In summary, one embodiment of the present invention exhibits significant resistance to single-event faults (SIFs) of clock signals and resistance to multi-node SIFs. By designing an input circuit consisting of one C-cell and a delay structure, it can resist single-event transient pulses of the input signal; a latch circuit consisting of four clock-controlled transmission units and a DICE structure, and an output circuit consisting of three C-cells and one inverter, can resist multi-node SIFs; a dual-clock signal circuit consisting of four inverters enables the latch to resist clock signal SIFs.

[0199] The above description is merely a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. For those skilled in the art, the present invention can have various modifications and substitutions. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A DICE-based latch resistant to multi-node and clock single-event flips, characterized in that, include: Input circuit, latch circuit, output circuit, clock signal circuit CLK1 and clock signal circuit CLK2; Input circuit: Receives externally transmitted data signal D, flips the data signal D to obtain data signal D' and transmits it to the latch circuit; Clock signal circuit CLK1: Receives the first clock signal CLK from the outside, flips it to obtain the second clock signal and transmits it to the latch circuit to control the working state of the latch circuit; The second clock signal includes: the clock signal of the common node CLKN1 that undergoes one flip and the clock signal of the common node CLKNN1 that undergoes two flips; Clock signal circuit CLK2: Receives the first clock signal CLK from the outside, flips it to obtain the third clock signal and transmits it to the latch circuit to control the working state of the latch circuit. The third clock signal includes: the clock signal of the common node CLKN2 that is flipped once and the clock signal of the common node CLKNN2 that is flipped twice. Latch circuit: Controlled by the second clock signal of clock signal circuit CLK1 and the third clock signal of clock signal circuit CLK2, when the first clock signal CLK is high, it receives the data signal D' transmitted from the input circuit. The latch circuit is in a transparent state, and it flips the data signal D' input from the input circuit in real time to obtain the data signal D'' and transmits the data signal D'' to the output circuit. When the first clock signal CLK is low, it does not receive the data signal D' transmitted from the input circuit. The latch circuit is in a latching state, latching the last data signal D' received from the input circuit when the first clock signal CLK is high. It flips the data signal D' to obtain the data signal D'' and repeatedly transmits the data signal D'' to the output circuit. Output circuit: Receives the data signal D'' transmitted by the latch circuit, flips the data signal D'' transmitted by the latch circuit n times and outputs the output signal, where n is a positive integer; The latching circuit includes: clock-controlled transmission unit C2, clock-controlled transmission unit C3, clock-controlled transmission unit C4, clock-controlled transmission unit C5, and a DICE structure; The clock-controlled transmission unit C2 includes: PMOS transistor p7, PMOS transistor p8, NMOS transistor n7, and NMOS transistor n8; The source of PMOS transistor p7 is connected to the power supply voltage VDD, and the gate of PMOS transistor p7 receives the data signal D' output from the common node DN of the input circuit. The source of PMOS transistor p8 is connected to the drain of PMOS transistor p7, and the gate of PMOS transistor p8 receives the second clock signal output by the common node CLKN1. The source of NMOS transistor n7 is grounded, and the gate of NMOS transistor n7 receives the data signal D' output from the common node DN in the input circuit; The source of NMOS transistor n8 is connected to the drain of NMOS transistor n7, the gate of NMOS transistor n8 receives the second clock signal output by the common node CLKNN1, and the drain of NMOS transistor n8 is connected to the drain of PMOS transistor p8, forming a common node N5. The clock-controlled transmission unit C3 includes: PMOS transistor p9, PMOS transistor p10, NMOS transistor n9, and NMOS transistor n10; The source of PMOS transistor p9 is connected to the power supply voltage VDD, and the gate of PMOS transistor p9 receives the data signal D' output from the common node DN of the input circuit. The source of PMOS transistor p10 is connected to the drain of PMOS transistor p9, and the gate of PMOS transistor p10 receives the third clock signal output by the common node CLKN2. The source of NMOS transistor n9 is grounded, and the gate of NMOS transistor n9 receives the data signal D' output from the common node DN in the input circuit; The source of NMOS transistor n10 is connected to the drain of NMOS transistor n9. The gate of NMOS transistor n10 receives the third clock signal output by the common node CLKNN2. The drain of NMOS transistor n10 is connected to the drain of PMOS transistor p10, forming a common node N4.

2. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 1, characterized in that, The clock signals of common node CLKN1 and common node CLKN2 are synchronized in terms of high and low levels.

3. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 2, characterized in that, The clock signals of common node CLKNN1 and common node CLKNN2 are synchronized in terms of high and low levels.

4. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 1, characterized in that, When the first clock signal CLK is low, the clock signals of common node CLKN1 and common node CLKN2 are high, while the clock signals of common node CLKNN1 and common node CLKNN2 are low.

5. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 1, characterized in that, The output circuit flips the data signal transmitted by the latch circuit n times and outputs an output signal, where n ≥ 3 and is an odd number. The level of the output signal is consistent with the level of the data signal D.

6. A DICE-based latch resistant to multi-node and clock single-event flips according to any one of claims 1 to 5, characterized in that, The clock signal circuit CLK1 includes: inverter INV1 and inverter INV2; Inverter INV1 includes: PMOS transistor p1 and NMOS transistor n1; The source of PMOS transistor p1 is connected to the power supply voltage VDD, and the gate of PMOS transistor p1 receives the first clock signal CLK. The source of NMOS transistor n1 is grounded, the gate of NMOS transistor n1 receives the first clock signal CLK, the drain of NMOS transistor n1 is connected to the drain of PMOS transistor p1 to form a common node CLKN1, and the common node CLKN1 serves as the output terminal to output the second clock signal. Inverter INV2 consists of: PMOS transistor p2 and NMOS transistor n2; The source of PMOS transistor p2 is connected to the power supply voltage VDD, and the gate of PMOS transistor p2 receives the second clock signal output by the common node CLKN1. The source of NMOS transistor n2 is grounded, and the gate of NMOS transistor n2 receives the clock signal of common node CLKN1. The drain of NMOS transistor n2 is connected to the drain of PMOS transistor p2 to form common node CLKNN1. Common node CLKNN1 serves as the output terminal to output the second clock signal.

7. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 6, characterized in that, The clock signal circuit CLK2 includes: inverter INV3 and inverter INV4; Inverter INV3 includes: PMOS transistor p3 and NMOS transistor n3; The source of PMOS transistor p3 is connected to the power supply voltage VDD, and the gate of PMOS transistor p3 receives the first clock signal CLK. The source of NMOS transistor n3 is grounded, the gate of NMOS transistor n3 receives the first clock signal CLK, the drain of NMOS transistor n3 is connected to the drain of PMOS transistor p3 to form a common node CLKN2, and the common node CLKN2 serves as the output terminal to output the third clock signal. Inverter INV4 includes: PMOS transistor p4 and NMOS transistor n4; The source of PMOS transistor p4 is connected to the power supply voltage VDD, and the gate of PMOS transistor p4 receives the third clock signal output by the common node CLKN2. The source of NMOS transistor n4 is grounded, and the gate of NMOS transistor n4 receives the clock signal of common node CLKN2. The drain of NMOS transistor n4 is connected to the drain of PMOS transistor p4 to form common node CLKNN2. Common node CLKNN2 serves as the output terminal to output the third clock signal.

8. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 7, characterized in that, The input circuit includes: a delay structure and a C unit C1; The delay structure includes: inverter INV6 and inverter INV7; Inverter INV6 includes: PMOS transistor p28 and NMOS transistor n28; The source of PMOS transistor p28 is connected to the power supply voltage VDD, and the gate of PMOS transistor p28 receives the externally input data signal D. The source of NMOS transistor n28 is grounded, the gate of NMOS transistor n28 receives the data signal D, and the drain of NMOS transistor n28 is connected to the drain of PMOS transistor p28 to form a common node D0. Inverter INV7 includes: PMOS transistor p29 and NMOS transistor n29; The source of PMOS transistor p29 is connected to the power supply voltage VDD, and the gate of PMOS transistor p29 receives the signal from the common node D0. The source of NMOS transistor n29 is grounded, the gate of NMOS transistor n29 receives the signal of common node D0, and the drain of NMOS transistor n29 is connected to the drain of PMOS transistor p29 to form common node D1. Unit C1 includes: PMOS transistor p5, PMOS transistor p6, NMOS transistor n5, and NMOS transistor n6; The source of PMOS transistor p5 is connected to the power supply voltage VDD, and the gate of PMOS transistor p5 receives the externally input data signal D. The source of PMOS transistor p6 is connected to the drain of PMOS transistor p5, and the gate of PMOS transistor p6 receives the signal from common node D1. The source of NMOS transistor n5 is grounded, and the gate of NMOS transistor n5 receives the externally input data signal D. The source of NMOS transistor n6 is connected to the drain of NMOS transistor n5. The gate of NMOS transistor n6 receives the signal from the common node D1. The drain of NMOS transistor n6 is connected to the drain of PMOS transistor p6, forming a common node DN. The common node DN serves as the output terminal, outputting the data signal D'.

9. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 8, characterized in that, The latch circuit also includes: a clock-controlled transmission unit C4, a clock-controlled transmission unit C5, and a DICE structure; The clock-controlled transmission unit C4 includes: PMOS transistor p11, PMOS transistor p12, NMOS transistor n11, and NMOS transistor n12; The source of PMOS transistor p11 is connected to the power supply voltage VDD, and the gate of PMOS transistor p11 receives the data signal D' output from the common node DN; The source of PMOS transistor p12 is connected to the drain of PMOS transistor p11, and the gate of PMOS transistor p12 receives the second clock signal output by the common node CLKN1. The source of NMOS transistor n11 is grounded, and the gate of NMOS transistor n11 receives the data signal D' output from the common node DN; The source of NMOS transistor n12 is connected to the drain of NMOS transistor n11, the gate of NMOS transistor n12 receives the second clock signal output by the common node CLKNN1, and the drain of NMOS transistor n12 is connected to the drain of PMOS transistor p12, forming a common node N2. The clock-controlled transmission unit C5 includes: PMOS transistor p13, PMOS transistor p14, NMOS transistor n13, and NMOS transistor n14; The source of PMOS transistor p13 is connected to the power supply voltage VDD, and the gate of PMOS transistor p13 receives the signal from the common node N5. The source of PMOS transistor p14 is connected to the drain of PMOS transistor p13, and the gate of PMOS transistor p14 receives the second clock signal output by the common node CLKN1. The source of NMOS transistor n13 is grounded, and the gate of NMOS transistor n13 receives the signal from the common node N5. The source of NMOS transistor n14 is connected to the drain of NMOS transistor n13. The gate of NMOS transistor n14 receives the second clock signal output from the common node CLKNN1. The drain of NMOS transistor n14 is connected to the drain of PMOS transistor p14, forming the common node N6 output data signal D''. The DICE structure includes: a transmission unit C9, a clock-controlled transmission unit C10, a transmission unit C11, and a clock-controlled transmission unit C12. Transmission unit C9 includes: PMOS transistor p22 and NMOS transistor n22; The source of PMOS transistor p22 is connected to the power supply voltage VDD, and the gate of PMOS transistor p22 receives the signal from the common node N4. The source of NMOS transistor n22 is grounded, the gate of NMOS transistor n22 receives the signal of common node N2, and the drain of NMOS transistor n22 is connected to the drain of PMOS transistor p22, forming a common node N1 output data signal D''. The clock-controlled transmission unit C10 includes: PMOS transistor p23, PMOS transistor p24, NMOS transistor n23, and NMOS transistor n24; The source of PMOS transistor p23 is connected to the power supply voltage VDD, and the gate of PMOS transistor p23 receives the data signal D'' output from the common node N1; The source of PMOS transistor p24 is connected to the drain of PMOS transistor p23, the gate of PMOS transistor p24 receives the second clock signal output from common node CLKNN1, and the drain of PMOS transistor p24 is connected to common node N2. The source of NMOS transistor n23 is grounded, and the gate of NMOS transistor n23 receives the data signal D'' output from the common node N3; The source of NMOS transistor n24 is connected to the drain of NMOS transistor n23, the gate of NMOS transistor n24 receives the second clock signal output by common node CLKN1, and the drain of NMOS transistor n24 is connected to common node N2. Transmission unit C11 includes: NMOS transistor n25 and PMOS transistor p25; The source of PMOS transistor p25 is connected to the power supply voltage VDD, and the gate of PMOS transistor p25 receives the signal from the common node N2. The source of NMOS transistor n25 is grounded, the gate of NMOS transistor n25 receives the signal of common node N4, and the drain of NMOS transistor n25 is connected to the drain of PMOS transistor p25, forming a common node N3 to output data signal D''. The clock-controlled transmission unit C12 includes: PMOS transistor p26, PMOS transistor p27, NMOS transistor n26, and NMOS transistor n27; The source of PMOS transistor p26 is connected to the power supply voltage VDD, and the gate of PMOS transistor p26 receives the data signal D'' output from the common node N3; The source of PMOS transistor p27 is connected to the drain of PMOS transistor p26, the gate of PMOS transistor p27 receives the third clock signal output by common node CLKNN2, and the drain of PMOS transistor p27 is connected to common node N4. The source of NMOS transistor n26 is grounded, and the gate of NMOS transistor n26 receives the data signal D'' output from the common node N1; The source of NMOS transistor n27 is connected to the drain of NMOS transistor n26, the gate of NMOS transistor n27 receives the third clock signal output from common node CLKN2, and the drain of NMOS transistor n27 is connected to common node N4.

10. A DICE-based latch resistant to multi-node and clock single-event flips according to claim 9, characterized in that, The output circuit includes: C6, C7, C8 and inverter INV5; Unit C6 includes: PMOS transistor p15, PMOS transistor p16, NMOS transistor n15, and NMOS transistor n16; The source of PMOS transistor p15 is connected to the power supply voltage VDD, and the gate of PMOS transistor p15 receives the data signal D'' output from the common node N3; The source of PMOS transistor p16 is connected to the drain of PMOS transistor p15, and the gate of PMOS transistor p16 receives the data signal D'' output from common node N6; The source of NMOS transistor n15 is grounded, and the gate of NMOS transistor n15 receives the data signal D'' output from the common node N3; The source of NMOS transistor n16 is connected to the drain of NMOS transistor n15, the gate of NMOS transistor n16 receives the data signal D'' output from common node N6, and the drain of NMOS transistor n16 is connected to the drain of PMOS transistor p16, forming common node N7; Unit C7 includes: PMOS transistor p17, PMOS transistor p18, NMOS transistor n17, and NMOS transistor n18; The source of PMOS transistor p17 is connected to the power supply voltage VDD, and the gate of PMOS transistor p17 receives the data signal D'' output from the common node N6; The source of PMOS transistor p18 is connected to the drain of PMOS transistor p17, and the gate of PMOS transistor p18 receives the data signal D'' output from the common node N1; The source of NMOS transistor n17 is grounded, and the gate of NMOS transistor n17 receives the data signal D'' output from the common node N6; The source of NMOS transistor n18 is connected to the drain of NMOS transistor n17. The gate of NMOS transistor n18 receives the data signal D'' output from the common node N1. The drain of NMOS transistor n18 is connected to the drain of PMOS transistor p18, forming a common node N8. Unit C8 includes: PMOS transistor p19, PMOS transistor p20, NMOS transistor n19 and NMOS transistor n20; The source of PMOS transistor p19 is connected to the power supply voltage VDD, and the gate of PMOS transistor p19 receives the signal from the common node N7. The source of PMOS transistor p20 is connected to the drain of PMOS transistor p19, and the gate of PMOS transistor p20 receives the signal from the common node N8. The source of NMOS transistor n19 is grounded, and the gate of NMOS transistor n19 receives the signal from the common node N7. The source of NMOS transistor n20 is connected to the drain of NMOS transistor n19. The gate of NMOS transistor n20 receives the signal of common node N8. The drain of NMOS transistor n20 is connected to the drain of PMOS transistor p20, forming a common node QN. Inverter INV5 includes: PMOS transistor p21 and NMOS transistor n21; The source of PMOS transistor p21 is connected to the power supply voltage VDD, and the gate of PMOS transistor p21 receives the common node QN signal. The source of NMOS transistor n21 is grounded, and the gate of NMOS transistor n21 receives the common node QN signal. The drain of NMOS transistor n21 is connected to the drain of PMOS transistor p21 to form a common node Q. The common node Q serves as the output terminal of the output circuit and outputs the output signal to the outside.

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