FPGA-based UART transmission VGA image display system
The FPGA-based UART transmission VGA image display system solves the problem of slow image display speed in small and medium-sized embedded devices, realizes fast storage and display of image data, and improves processing efficiency and display clarity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NINGBO UNIVERSITY OF TECHNOLOGY
- Filing Date
- 2023-06-05
- Publication Date
- 2026-05-29
AI Technical Summary
The slow image display speed of existing small and medium-sized embedded devices results in low image processing efficiency.
An FPGA-based UART transmission VGA image display system is adopted, including image preprocessing, serial port reception, write data channel, storage, data expansion, read data channel and display control module. Through format conversion, jitter signal elimination, address writing, data expansion and VGA horizontal and vertical scan timing counting, the system realizes fast storage and display of image data.
It improves the storage and display speed of image data, enhances image processing efficiency, and achieves clear and stable image display.
Smart Images
Figure CN116634088B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of video processing technology, and in particular to an FPGA-based UART transmission VGA image display system. Background Technology
[0002] With the increasing informatization of society, video processing technology in embedded systems has gradually become a major consideration for video display applications. Multimedia devices are currently diverse in type and size, and for the display interfaces of small and medium-sized embedded devices, the interface types are gradually becoming standardized, leading to the standardization of video display interface usage.
[0003] Existing technologies use traditional microcontrollers as the core of small and medium-sized embedded devices to achieve image transmission and processing. Traditional microprocessors read address data using instructions in each instruction cycle. The data for each address needs to be executed serially, which results in slow image data processing speed and slow image display. Summary of the Invention
[0004] The purpose of this invention is to solve the problem that the image display of existing small and medium-sized embedded devices is slow due to slow image data processing speed, and proposes an FPGA-based UART transmission VGA image display system.
[0005] The FPGA-based UART transmission VGA image display system includes: an image preprocessing module, a serial port receiving module, a write data channel module, a storage module, a data expansion module, a read data channel module, and a display control module.
[0006] The image preprocessing module is used to convert the image data into a format, obtain serial image data, and input the serial image data into the serial port receiving module;
[0007] The serial port receiving module is used to eliminate the metastability of jitter signals in serial image data, obtain a write control signal, and then transmit the write control signal to the storage module.
[0008] The write data channel is used to write the address of serial image data into the storage module;
[0009] The storage module is used to store write control signals according to the serial image data address, and input the stored write control signals to the data expansion module;
[0010] The data expansion module is used to convert the format of the write control signal and input the converted write control signal into the read data channel module.
[0011] The read data channel module is used to perform VGA line and field scanning on the format-converted write control signal, obtain the pixel clock cycle count of the VGA line and field scanning timing in four different stages: synchronization, trailing edge, finite image display, and leading edge, and transmit the pixel clock cycle count of the VGA line and field scanning timing in the four different stages to the display control module.
[0012] The display control module is used to perform local data state jumps based on the pixel clock cycle count in four different stages—synchronization, trailing edge, finite image display, and leading edge—according to the VGA line and field scanning timing sequence, thereby displaying the image within the effective area.
[0013] Furthermore, the process of converting the image data into a format to obtain serial image data specifically involves:
[0014] First, the image data is processed using the phase AND function and shift function in Matlab to generate image information with an eight-bit width and depth.
[0015] Then, the 8-bit wide-depth image information is processed to convert the RGB color output format, that is, the RGB888 color format is converted to the RGB332 color format for output.
[0016] Furthermore, the serial port receiving module is used to eliminate the metastability of jitter signals in the serial image data, obtain a write control signal, and then transmit the write control signal to the storage module, specifically:
[0017] Step 1: Under the system clock, input serial image data through the host device;
[0018] Step 2: Under the system clock, based on the serial asynchronous transceiver protocol, serial image data is transmitted serially to obtain the write control signal, specifically as follows:
[0019] Step 2: Set the input bit width of the serial image data pixels to 8 bits, and transmit each 8-bit data group as a set of data.
[0020] Step 22: Input each group of transmitted data into a multi-stage serial shift register to eliminate metastability of jitter signals;
[0021] Step 23: Use the data processed in Step 22 to perform serial image data shifting and transmission.
[0022] Furthermore, the write data channel is used to write the address of serial image data into the storage module, and includes: a data selector, an address controller, a first counter, and a first comparator;
[0023] The data selector: determines whether the address of the data transmitted by the serial port receiving module is consistent with the preset address, and sends the comparison result to the address controller and the first counter;
[0024] The address controller: when the address of the data transmitted by the serial port receiving module is consistent with the preset address, inputs the address of the data transmitted by the serial port receiving module into the storage module;
[0025] The first counter: When the address of the data transmitted by the serial port receiving module is inconsistent with the preset address, the first counter increments from 0 and inputs the address after each increment into the first comparator;
[0026] The first comparator compares the address incremented by the first counter with the size of the image to be displayed. If the incremented address is less than the size of the image to be displayed, the comparison result is transmitted to the first counter, and the first counter continues to increment the address. If the incremented address is equal to the size of the image to be displayed, the incremented address is input to the data selector, and the comparison result is transmitted to the first counter, and the first counter stops incrementing the address.
[0027] Furthermore, the data expansion module is used to perform format conversion on the write control signal, specifically by converting the data format stored in the storage module from RGB332 to RGB888.
[0028] Furthermore, the read data channel module includes: a second counter and a second comparator;
[0029] The second counter: performs VGA line and field scanning on the data output by the data expansion module to obtain the pixel clock cycle count in four different stages of VGA line and field scanning timing: synchronization, trailing edge, finite image display, and leading edge.
[0030] The second comparator compares the read address of the counting signal read from the second counter with the size of the image to be displayed, and obtains a read address that is larger than the size of the image to be displayed.
[0031] Furthermore, the data reading channel module has the following processing flow:
[0032] The pixel clock cycles are counted for the VGA line and field scanning timing in four different stages: synchronization, trailing edge, finite image display, and leading edge. This yields the number of pixel clock cycles required for each stage of the VGA timing. The second counter is used to determine whether valid information is displayed and the current scan position information in the valid image display area.
[0033] Furthermore, the display control module is used to perform local data state transitions based on pixel clock cycle counts in four different stages—synchronization, trailing edge, finite image display, and leading edge—according to the VGA line and field scan timing sequence, thereby displaying the image within the effective area, as detailed below:
[0034] When the position of the effective image display area of the field synchronization signal is determined, the line synchronization signal outputs the image within the effective image display area. Before the output of the effective signal, it is state S1. Scanning starts from the initial position. Within one field cycle scan cycle, the line scan count needs to pass through n effective image pixels to output the image color value, which is state S2, S3, and S4. When the line scan is completed, the field scan count is incremented by 1 to state S5. The line scan count signal is reset to zero, and the scan output under the next field signal is performed, returning to state S2. This process continues until the state transition ends and state S6 is reached.
[0035] Wherein, S1 indicates the state during the entire display interval of the vertical sync signal when pixel position scanning begins; S2 indicates the state of the horizontal sync signal counting when the vertical scan is effectively output; S3 indicates the state of outputting the data of the pixel at the current position when the horizontal scan is in an effective display interval; S4 indicates the state of counting the leading edge clock cycle after the effective output state ends; S5 indicates the state after the vertical signal changes after all the pixels in the current row of the horizontal signal have been output; and S6 indicates the state after the effective output of the vertical sync signal has ended.
[0036] Furthermore, within each valid image display, when the field synchronization signal is determined, the display control module increments the horizontal position counter corresponding to the horizontal synchronization signal at the synchronization position by 1. When the horizontal synchronization signal meets the clearing condition, the vertical synchronization signal position counter increments by 1, and the vertical position signal increments by 1, thereby correspondingly outputting position information and reading image information at the current position.
[0037] Furthermore, the system also includes: a phase-locked loop module;
[0038] The phase-locked loop module controls the data address received by the serial port receiving module to be written or the counter to be incremented, reads the clock of the incremented counter, and forms the clock for the data output by the display control module.
[0039] The beneficial effects of this invention are as follows:
[0040] This invention analyzes the VGA horizontal and vertical synchronization timing in the display control module, and outputs valid image data and corresponding position information by changing the state through counting under the horizontal and vertical scanning signals, and finally displays the image. The VGA interface circuit is designed through digital logic circuits, which can effectively transmit and display image information. According to the set input and output clock, the storage and reading speed of image data is improved, thereby improving the speed of image data processing and image display. Attached Figure Description
[0041] Figure 1 This is a block diagram of the interface circuit module;
[0042] Figure 2 A schematic diagram of the UART module receiving signals;
[0043] Figure 3 This is a schematic diagram of the displacement for UART data reception.
[0044] Figure 4 Output image for RGB888 to RGB332 color format;
[0045] Figure 5 This is a timing diagram for VGA horizontal and vertical scans;
[0046] Figure 6 This is a diagram showing the state transitions between row and field counting.
[0047] Figure 7 For RTL Viewer diagrams;
[0048] Figure 8 This is a simulation diagram for RTL Viewer;
[0049] Figure 9 To display the final image. Detailed Implementation
[0050] This invention utilizes a UART (Asynchronous Receiver / Transmitter) to calculate the data count during serial transmission of image data within the system clock at a defined baud rate, thereby obtaining the data shift change under the given formula. Simultaneously, a PLL (Phase Locked Loop) IP uses frequency division input to configure the required frequencies in the display control module, i.e., outputting the system clock and VGA display control clock. Data processing occurs within the write data channel. After the system clock is processed by the PLL clock, the received image data is serially transmitted to RAM (random access memory) via the input clock. By using different input and output clocks, the problem of cross-clock domain data processing (serial input and parallel output) is solved. To meet design requirements, the bit width requirement of the VGA interface schematic on the DE2-115 development board is used, expanding RGB322 to RGB888 for output. The image control module determines the position and color information of each pixel under horizontal and vertical synchronization signals, and outputs the data according to the VGA interface specification through horizontal and vertical scanning to achieve image display. This invention uses Altera's Cyclone IV series EP4CE115F29C7 as the chip to implement the module's logic functions, and employs the ADV7173 multi-format video encoder to convert the digital RGB signal output from the video data transmission conversion circuit into an analog RGB signal, which is then connected to a VGA interface to achieve image output and display. The invention will now be described in conjunction with specific implementation methods.
[0051] Specific Implementation Method 1: This implementation method is based on an FPGA-based UART transmission VGA image display system, including: an image preprocessing module, a serial port receiving module, a write data channel module, a storage module (RAM), a read data channel module, a data expansion module, a phase-locked loop module, and a display control module;
[0052] The image preprocessing module converts the image data into a format to obtain serial image data.
[0053] The serial port receiving module acquires serial image data. Under the system clock, based on UART (serial asynchronous transceiver protocol), it inputs the serial image data into a multi-stage serial shift register to eliminate the metastability of jitter signals. Then, it obtains the clock cycle of each bit of serial transmission of serial image data through the first counter, thereby performing serial transmission of serial image data, obtaining a write control signal (FLAG signal), and inputting the write control signal into the storage module.
[0054] The write data channel module includes: a data selector, an address controller, a first comparator, and a first counter;
[0055] The data selector is used to determine whether the address of the serial image data received by the serial port receiving module is consistent with the preset address.
[0056] The address controller: When the address of the data received by the serial port receiving module is consistent with the preset address, it writes the address of the data received by the serial port into the storage module;
[0057] The first counter: When the address of the data received by the serial port receiving module is inconsistent with the preset address, the first counter starts from 0 and increments itself. After each increment, it is input to the first comparator to compare the image size until the image size is consistent with the size of the image to be displayed (that is, the address is incremented from 0 to 100*100). Then it enters the data selector.
[0058] The first comparator compares the address after incrementing the first counter with the size of the image to be displayed.
[0059] Storage module: Stores the input 8-bit image signal according to the FLAG signal address obtained from the write data channel module;
[0060] The data expansion module converts the image signal stored in the storage module from 8 bits to 24 bits (RGB332 to RGB888);
[0061] The data read channel module includes: a second counter and a second comparator;
[0062] The second comparator compares the read address of the counting signal read from the second counter with the size of the image to be displayed, and obtains a read address that is larger than the size of the image to be displayed;
[0063] The second counter: performs VGA line and field scanning on the data output by the data expansion module to obtain the pixel clock cycle count in four different stages of VGA line and field scanning timing: synchronization, trailing edge, finite image display, and leading edge.
[0064] The display control module performs data state transitions based on the clock cycle count obtained from the second counter, thereby displaying the image within the effective area.
[0065] The phase-locked loop module controls the data address received by the serial port receiving module to be written or the counter to be incremented, reads the clock of the incremented counter, and forms the clock for the data output by the display control module.
[0066] Specific Implementation Method Two: The step of converting the image data to obtain serial image data specifically involves:
[0067] First, the data in the storage module is processed using the phase AND function and shift function in Matlab to generate image information with an eight-bit width and depth.
[0068] Then, the image information with defined width and depth is processed to convert it to RGB color output format, that is, RGB888 color format is converted to RGB332 color format for output, to meet the design requirements of UART module transmission.
[0069] like Figure 4 As shown, in RGB, R represents red, G represents green, and B represents blue. Their 8-bit wide data are subjected to bitwise AND and bitshift operations. The high 3 or high 2 bits of the three primary colors are retained, with the rest set to zero. The red primary color remains unchanged after the bitwise AND. The green primary color is shifted 3 bits to the right, resulting in a [4:2] range of valid data. B is shifted 5 bits to the right, resulting in a [1:0] range of valid data bits. These data are then added together, achieving the conversion from RGB888 to RGB332 color format for output. Therefore, in the RGB332 color output format, each frame outputs an image with an 8-bit width and a depth of 100*100 pixels.
[0070] The other steps are the same as in Specific Implementation Method 1.
[0071] Specific implementation method three: such as Figure 2 As shown, serial image data is acquired. Under the system clock, based on UART (Used Serial Asynchronous Receiver / Transmitter), the serial image data is input into a multi-stage serial shift register to eliminate metastability of jitter signals. Then, the clock cycle of each bit of serial image data transmission is obtained through the first counter, thereby performing serial transmission of serial image data and obtaining the write control signal (FLAG signal). Specifically:
[0072] Step 1: Under the system clock, input serial image data (RXD) through host devices, etc.;
[0073] Step 2: Under the system clock, based on the UART protocol, serially transmit serial image data to obtain the FLAG signal, specifically as follows:
[0074] Step 2: 1. Set the input bit width of the serial image data pixels (8 bits). Based on the bit width, transmit each bit of data as a group.
[0075] In UART data transmission, a start bit (START), a stop bit (STOP), and 8 data bits are transmitted.
[0076] Step 22: Input each set of transmitted data into the start register to eliminate the metastability of jitter signals;
[0077] Step Two Three: Use the data obtained in Step Two Two to perform serial image data shifting and transmission:
[0078] Using an RS232 interface with a baud rate of 9600bps, the count value per bit is approximately 5208 at a system clock of 50MHz. Therefore, the clock cycle of each bit is counted by the first counter, and the FLAG signal is used to count each bit within this counting range, thereby performing shift transmission.
[0079] The UART used in this embodiment is a serial asynchronous transceiver protocol, widely used in serial communication. The UART works by transmitting data bit by bit serially. In the UART communication protocol, a high level on the signal line represents '1', and a low level represents '0'.
[0080] The other steps are the same as in Specific Implementation Method 1.
[0081] Specific implementation method four: Write data channel module, the specific processing flow is as follows:
[0082] In the write data channel, there are an address controller and a comparator. When the address controller is active, the address of the input data is controlled by the address information input to the address controller. If the address controller is inactive, a counter increments from 0, and then the comparator compares the value with the image size to complete the address increment from 0 to 100*100. Figure 3 As shown, CNT is a counter, and RX_DATA is the data obtained from the write data channel.
[0083] The other steps are the same as those in specific implementation methods one and two.
[0084] Specific implementation method five: The storage module is specifically:
[0085] The storage module needs to process the input FLAG signal, inputting data based on address position counting or position information. The input position information determines the row and field timing scan information. Write signals and write address information, as well as read signals and read address information, enable sequential reading and writing of data from contiguous RAM storage or writing to specific addresses, and sequential reading.
[0086] The write signal is synchronously input when data is written externally, and the write address is incremented with each write signal. Since reading and writing convert serial data to parallel data, controlled by different clock frequencies, the horizontal and vertical count signals must remain within the effective image range under the VGA control module for normal display. Figure 6The horizontal and vertical synchronization signals in the image are displayed within the effective image area, and the display position information is output. This sends a read request signal and the corresponding display position information to the VGA image module. Only then will the VGA image module read the image signal through RAM and output it, and the data will be output under the display control module.
[0087] The other steps are the same as those in implementation methods one through three.
[0088] Specific Implementation Method Six: The display control module: performs data state transitions based on the clock cycle count obtained from the second counter, thereby displaying the image within the effective area, specifically as follows:
[0089] Step 1: In the display control module, the first step is to count the pixel clock cycles in the four different stages of the VGA line and field scan timing under the determined VGA display mode: synchronization, trailing edge, finite image display, and leading edge. This yields the number of pixel clock cycles required for each stage of the VGA timing. The counter count is then used to determine whether valid information is displayed and the current scan position information in the valid image display area.
[0090] The synchronization signal was calculated using a VGA 640x480 (60Hz) display mode, with trailing edge, display time interval, and leading edge times of 95, 48, 635, and 15 system pixel clock cycles, respectively. Similarly, the field synchronization signal also requires counting 2, 33, 480, and 10 pixel clock cycles at different stages.
[0091] Step 2: Perform data state transitions based on clock cycle counting to display the image within the valid area.
[0092] First, set the transition state:
[0093] like Figure 6 The state transition diagram shown is as follows: S0 represents the initial reset state; S1 represents the state during the entire display interval of the vertical sync signal when pixel position scanning begins; S2 represents the horizontal sync signal line scan counting state when the vertical scan is in valid display interval; S3 represents the state of outputting the data of the pixel at the current position when the horizontal scan is in valid display interval; S4 represents the leading edge clock cycle counting state after the valid output state ends; S5 represents the state after the vertical signal changes after all pixels in the current row of the horizontal signal have been output; and S6 represents the state after the valid output portion of the vertical sync signal has ended.
[0094] Then, line and field scanning is performed within the valid image area to complete the state transition, thereby displaying the image within the valid area (the displayed image format is RGB888):
[0095] Of the seven state transitions, for both horizontal and vertical scanning, the first state is S1. First, with the effective image area position determined by the vertical sync signal, the horizontal sync signal outputs the image within that effective area. Scanning begins from the top-left corner of the initial value (the top-left corner of the display screen is the starting position, i.e., the starting address). Within one vertical scan cycle, the horizontal scan count needs to pass through 640 effective image pixels to output the image color value (states S2, S3, and S4). When one horizontal scan line is completed, the vertical scan count increments by 1 (state S5), the horizontal scan count signal returns to zero, and the next vertical scan outputs, returning to state S2. Simultaneously, the horizontal and vertical sync signals output a duration that satisfies the VGA scan timing level through counters. When inputting image information, the image information is output via RGB digital signals during the scan timing.
[0096] Figure 5 In this context, VSYNK is the vertical sync signal, HSYNC is the vertical sync signal, Back porch is the display trailing edge, and Front porch is the display leading edge. Figure 5 From the horizontal and vertical scanning timings, it can be seen that within the effective area of the vertical sync signal, and within the defined effective image display area of the vertical signal, the color image data of one pixel is output and displayed within one display interval (the effective display area in the VGA timing) of the horizontal sync signal. Figure 1 In the interface module circuit, the data in the read / write data channel module is transmitted to the display control module as RGB image information under the control of the display control module. Therefore, given the determination of valid image output and position information, the input image information needs to be displayed at the output display position to read the corresponding image display data for effective display. Within each valid image display, when the vertical synchronization signal is determined, the horizontal position counter of the corresponding display position is incremented by 1 each time the horizontal synchronization signal is at the synchronization position. When the horizontal synchronization signal meets the reset condition, the vertical synchronization signal position counter is incremented by 1, and the vertical position signal is incremented by 1, thus corresponding to the output position information and the image information read at that position, such as... Figure 6 As shown, rst_n is the reset to S0, RGB_VAILD is the valid image, MAX_H is the maximum line scan value, MAX_V is the maximum field scan value, CTN_V is the field scan counter, and CNT_H is the line scan counter.
[0097] Specific Implementation Method Seven: An FPGA-based UART transmission VGA image display device, comprising: a processor and a memory, wherein the memory stores at least one instruction, and the at least one instruction is loaded and executed by the processor.
[0098] Specific implementation method eight: A storage medium storing at least one instruction, which is loaded and executed by a processor to realize an FPGA-based UART transmission VGA image display system.
[0099] The specific steps are the same as those in Specific Implementation Methods One through Five.
[0100] Example: To verify the beneficial effects of the present invention, the following experiments were conducted:
[0101] In the Quartus Prime environment, a top-level file for pin assignment is written, pin assignment is performed by importing the official pin assignment text file, and the corresponding RTL Viewer is obtained through EDA software, such as... Figure 7 As shown. The RTL Viewer is simulated using Modelsim to analyze whether its logical functions meet the requirements, such as... Figure 8 As shown. Under this field signal, after a full line of horizontal sync signal scanning, within the effective image display area of the field sync signal, each of the effective image display areas of the horizontal sync signal will output the corresponding RGB888 color format display. Then, the compiled .sof (Altera SRAM object file) is downloaded to EP4CE115F29C7 in DE2-115 using Programmer for board-level verification. The results are as follows. Figure 9 As shown in the test results, an image with a width of 100*100 pixels is displayed within the image display area, and the image is clear and stable.
[0102] Based on the above experimental principles and analysis, a Verilog HDL script was written to describe the UART transmission VGA image display module. By analyzing the VGA horizontal and vertical synchronization timing in the sub-module display control module, and demonstrating how counting changes the state under horizontal and vertical scanning signals to output valid image data and corresponding position information, this function was successfully implemented in board-level verification. In embedded small and medium-sized video displays, small screens require fast response times and good display clarity, both of which are met by VGA displays. Furthermore, the use of standard DB9 and VGA interfaces is of great significance in embedded video displays.
Claims
1. An FPGA-based UART transmission VGA image display system, characterized in that... The system includes: an image preprocessing module, a serial port receiving module, a write data channel module, a storage module, a data expansion module, a read data channel module, and a display control module; The image preprocessing module is used to convert the image data into a format, obtain serial image data, and input the serial image data into the serial port receiving module; The serial port receiving module is used to eliminate the metastability of jitter signals in serial image data, obtain a write control signal, and then transmit the write control signal to the storage module. The write data channel is used to write the address of serial image data into the storage module, and includes: a data selector, an address controller, a first counter, and a first comparator; The data selector: determines whether the address of the data transmitted by the serial port receiving module is consistent with the preset address, and sends the comparison result to the address controller and the first counter; The address controller: when the address of the data transmitted by the serial port receiving module is consistent with the preset address, inputs the address of the data transmitted by the serial port receiving module into the storage module; The first counter: When the address of the data transmitted by the serial port receiving module is inconsistent with the preset address, the first counter increments from 0 and inputs the address after each increment into the first comparator; The first comparator compares the address incremented by the first counter with the size of the image to be displayed. If the incremented address is less than the size of the image to be displayed, the comparison result is transmitted to the first counter, and the first counter continues to increment the address. If the incremented address is equal to the size of the image to be displayed, the incremented address is input to the data selector, and the comparison result is transmitted to the first counter, and the first counter stops incrementing the address. The storage module is used to store write control signals according to the serial image data address, and input the stored write control signals to the data expansion module; The data expansion module is used to convert the format of the write control signal and input the converted write control signal into the read data channel module. The read data channel module is used to perform VGA line and field scanning on the format-converted write control signal, obtain the pixel clock cycle count of the VGA line and field scanning timing in four different stages: synchronization, trailing edge, finite image display, and leading edge, and transmit the pixel clock cycle count of the VGA line and field scanning timing in the four different stages to the display control module. The display control module is used to perform local data state jumps based on the pixel clock cycle count in four different stages—synchronization, trailing edge, finite image display, and leading edge—according to the VGA line and field scanning timing sequence, thereby displaying the image within the effective area.
2. The FPGA-based UART transmission VGA image display system according to claim 1, characterized in that: The process of converting the image data to obtain serial image data specifically involves: First, the image data is processed using the phase AND function and shift function in Matlab to generate image information with an eight-bit width and depth. Then, the 8-bit wide-depth image information is processed to convert the RGB color output format, that is, the RGB888 color format is converted to the RGB332 color format for output.
3. The FPGA-based UART transmission VGA image display system according to claim 2, characterized in that: The serial port receiving module is used to eliminate the metastability of jitter signals in serial image data, obtain a write control signal, and then transmit the write control signal to the storage module, specifically: Step 1: Under the system clock, input serial image data through the host device; Step 2: Under the system clock, based on the serial asynchronous transceiver protocol, serial image data is transmitted serially to obtain the write control signal, specifically as follows: Step 2: Set the input bit width of the serial image data pixels to 8 bits, and transmit each 8-bit data group as a set of data. Step 22: Input each group of transmitted data into a multi-stage serial shift register to eliminate metastability of jitter signals; Step 23: Use the data processed in Step 22 to perform serial image data shifting and transmission.
4. The FPGA-based UART transmission VGA image display system according to claim 3, characterized in that: The data expansion module is used to perform format conversion on the write control signal, specifically by converting the data format stored in the storage module from RGB332 to RGB888.
5. The FPGA-based UART transmission VGA image display system according to claim 4, characterized in that: The read data channel module includes: a second counter and a second comparator; The second counter: performs VGA line and field scanning on the data output by the data expansion module to obtain the pixel clock cycle count in four different stages of VGA line and field scanning timing: synchronization, trailing edge, finite image display, and leading edge. The second comparator compares the read address of the counting signal read from the second counter with the size of the image to be displayed, and obtains a read address that is larger than the size of the image to be displayed.
6. The FPGA-based UART transmission VGA image display system according to claim 5, characterized in that: The data read channel module processes data as follows: The pixel clock cycles are counted for the VGA line and field scanning timing in four different stages: synchronization, trailing edge, finite image display, and leading edge. This yields the number of pixel clock cycles required for each stage of the VGA timing. The second counter is used to determine whether valid information is displayed and the current scan position information in the valid image display area.
7. The FPGA-based UART transmission VGA image display system according to claim 6, characterized in that: The display control module is used to perform local data state transitions based on pixel clock cycle counts in four different stages—synchronization, trailing edge, finite image display, and leading edge—according to the VGA line and field scan timing sequence, thereby displaying the image within the effective area, as detailed below: When the position of the effective image display area of the field synchronization signal is determined, the line synchronization signal outputs the image within the effective image display area. Before the output of the effective signal, it is state S1. Scanning starts from the initial position. Within one field cycle scan cycle, the line scan count needs to pass through n effective image pixels to output the image color value, which is state S2, S3, and S4. When the line scan is completed, the field scan count is incremented by 1 to state S5. The line scan count signal is reset to zero, and the scan output under the next field signal is performed, returning to state S2. This process continues until the state transition ends and state S6 is reached. Wherein, S1 indicates the state during the entire display interval of the vertical sync signal when pixel position scanning begins; S2 indicates the state of the horizontal sync signal counting when the vertical scan is effectively output; S3 indicates the state of outputting the data of the pixel at the current position when the horizontal scan is in an effective display interval; S4 indicates the state of counting the leading edge clock cycle after the effective output state ends; S5 indicates the state after the vertical signal changes after all the pixels in the current row of the horizontal signal have been output; and S6 indicates the state after the effective output of the vertical sync signal has ended.
8. The FPGA-based UART transmission VGA image display system according to claim 7, characterized in that: Within each valid image display, when the field synchronization signal is determined, the display control module increments the horizontal position counter corresponding to the horizontal synchronization signal at the synchronization position by 1. When the horizontal synchronization signal meets the clearing condition, the vertical position counter increments by 1, thereby correspondingly outputting position information and reading image information at the current position.
9. The FPGA-based UART transmission VGA image display system according to claim 8, characterized in that: The system also includes: a phase-locked loop module; The phase-locked loop module controls the data address received by the serial port receiving module to be written or the counter to be incremented, reads the clock of the incremented counter, and forms the clock for the data output by the display control module.