Low power voltage regulator with fast transient response

Abstract

In certain aspects, a voltage regulator includes a pass device coupled between an input of the voltage regulator and an output of the voltage regulator. The voltage regulator also includes an amplification circuit having a first input configured to receive a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output coupled to a gate of the pass device. The voltage regulator further includes a first current source coupled between a supply rail and the amplification circuit, and a capacitor coupled between the first current source and the output of the voltage regulator.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to non-provisional application No. 17 / 154,865, filed with the U.S. Patent and Trademark Office on January 21, 2021, the entire contents of which are incorporated herein by reference as if they were fully set forth herein for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to voltage regulators, and more specifically to low dropout (LDO) regulators. Background Technology

[0004] Voltage regulators are used in various systems to provide regulated voltages to the power supply circuits within those systems. A commonly used voltage regulator is the low-dropout (LDO) regulator. An LDO regulator typically includes a pass device and an amplifier coupled in a feedback loop to provide a regulated output voltage based on a reference voltage. Summary of the Invention

[0005] The following is a simplified overview of one or more implementations to provide a basic understanding of such implementations. This overview is not a comprehensive overview of all anticipated implementations, and is neither intended to identify key or fundamental elements of all implementations, nor to define the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] The first aspect relates to a voltage regulator. The voltage regulator includes a transfer device coupled between an input and an output of the voltage regulator. The voltage regulator also includes an amplifier circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transfer device. The voltage regulator also includes a first current source coupled between a power supply rail and the amplifier circuit, and a capacitor coupled between the first current source and the output of the voltage regulator.

[0007] The second aspect relates to a method of operating a voltage regulator. The voltage regulator includes a transfer device coupled between the input and output of the voltage regulator and an amplifier circuit coupled to the gate of the transfer device. The method includes detecting a transient voltage drop at the output of the voltage regulator via a capacitor and increasing a bias current to the amplifier circuit based on the detected transient voltage drop.

[0008] The third aspect relates to a chip. The chip includes pads, a power rail, a reference circuit configured to generate a reference voltage, and a voltage regulator. The voltage regulator includes a transfer device coupled between an input and an output of the voltage regulator, wherein the input of the voltage regulator is coupled to the power rail. The voltage regulator also includes an amplifier circuit having a first input, a second input, and an output, wherein the first input is coupled to the reference circuit, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transfer device. The voltage regulator also includes a first current source coupled between the power rail and the amplifier circuit, and a capacitor coupled between the first current source and the output of the voltage regulator. Attached Figure Description

[0009] Figure 1 An example of a low-dropout (LDO) regulator is shown.

[0010] Figure 2 An example of fluctuations in the output voltage of an LDO regulator caused by changes in load current, according to certain aspects of this disclosure, is shown.

[0011] Figure 3 An example of an LDO regulator with adaptive current bias according to certain aspects of this disclosure is shown.

[0012] Figure 4 An exemplary implementation of an adaptive current source according to certain aspects of this disclosure is shown.

[0013] Figure 5 An example of the response time for adaptive current bias is shown according to certain aspects of this disclosure.

[0014] Figure 6 An LDO regulator with dynamic current bias and adaptive current bias according to certain aspects of this disclosure is shown.

[0015] Figure 7 An exemplary implementation of a current source for dynamic current biasing according to certain aspects of this disclosure is shown.

[0016] Figure 8 An exemplary implementation of an amplifier circuit according to certain aspects of this disclosure is shown.

[0017] Figure 9 Exemplary implementations of bias circuitry, error amplifiers, and buffers according to certain aspects of this disclosure are shown.

[0018] Figure 10 An example of a chip including an LDO regulator is shown according to certain aspects of this disclosure.

[0019] Figure 11This is a flowchart illustrating a method of operating a voltage regulator according to certain aspects of this disclosure. Detailed Implementation

[0020] The detailed description that follows, taken in conjunction with the accompanying drawings, is intended as a description of various configurations, and not as representing the only configuration in which the concepts described herein can be practiced. The detailed description includes specific details used to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in the form of block diagrams to avoid obscuring such concepts.

[0021] Voltage regulators can be used to provide a supply voltage different from the main supply voltage to the circuit block and / or to convert a noisy supply voltage into a clean supply voltage.

[0022] A commonly used voltage regulator is the low-dropout (LDO) regulator, an example of which is shown below. Figure 1 As shown. Figure 1 The exemplary LDO regulator 110 shown has an input 105 coupled to a voltage supply rail 112 and an output 130 coupled to a circuit block 170. The LDO regulator 110 is configured to adjust the supply voltage V on the supply rail 112. DD Converted to the regulated output voltage V at output 130 of LDO regulator 110 out .

[0023] LDO regulator 110 includes a transmission device 115 coupled between input 105 and output 130 of LDO regulator 110. Figure 1 In the example shown, the transfer device 115 is implemented using a p-type field-effect transistor (PFET) having a source coupled to input 105 and a drain coupled to output 130. However, it should be understood that in other implementations, the transfer device 115 may be implemented using another type of transistor (e.g., an n-type field-effect transistor (NFET)). It should also be understood that the transfer device 115 may be implemented using multiple transistors coupled in parallel.

[0024] LDO regulator 110 also includes amplifier circuit 120, which has an output 126 coupled to the gate of transfer device 115 and coupled to reference voltage V. ref The first input 122 and the second input 124 are coupled to the output 130 via feedback path 150. Reference voltage V ref This can be provided by a bandgap reference circuit or another type of circuit. The LDO regulator 110 may also include a voltage divider 160 coupled between the output 130 and ground. Figure 1In the example shown, voltage divider 160 includes a first feedback resistor R1 and a second feedback resistor R2 coupled in series between output 130 and ground. In this example, the second input 124 of amplifier circuit 120 is coupled to node 165 between the first feedback resistor R1 and the second feedback resistor R2. Voltage divider 160 is configured to generate a feedback voltage V at node 165. fb The feedback voltage V fb It is fed to the second input 124 of amplifier circuit 120. Feedback voltage V fb With the output voltage V of LDO regulator 110 out Proportional, and given by the following formula:

[0025]

[0026] Where R1 is the resistance of the first feedback resistor R1, and R2 is the resistance of the second feedback resistor R2.

[0027] During operation, amplifier circuit 120 reduces the reference voltage V. ref With feedback voltage V fb The gate voltage of the transfer device 115 is adjusted in the direction of the difference (i.e., the error) between the two. This forces the output voltage V of the LDO regulator 110 to be adjusted. out Approximately equal to the following values:

[0028]

[0029] Therefore, by setting the resistances of the feedback resistors R1 and R2 and / or accordingly setting the reference voltage V ref The output voltage V can be out Set to the desired voltage.

[0030] Output voltage V out At load current I Load (That is, the current drawn by circuit block 170) exhibits fluctuations during its variation. At this point, Figure 2 It shows the load current I Load The change in output voltage V out An example of fluctuation. In this example, the load current I... Load Rise ΔI Load Then decrease ΔI Load For example, this can happen when circuit block 170 transitions from a standby state to an active state and then back from an active state to a standby state.

[0031] like Figure 2 As shown, the load current I Load The increase in output voltage V out The undershoot 210, and the load current ILoad The decrease in output voltage V out The overshoot is 220. The desired reduction is in the output voltage V. out Undershoot and overshoot (i.e., reducing the output voltage V) out (fluctuations) to ensure the accurate performance of circuit block 170.

[0032] Reduce output voltage V out The first method to address the fluctuations is to couple a large off-chip capacitor to the output 130 of the LDO regulator 110 to absorb load current variations. However, this method increases area and cost. A second method is to provide a large, constant bias current to the amplifier circuit 120 to increase the loop bandwidth of the LDO regulator 110, which gives the LDO regulator 110 a faster transient response. This faster transient response allows the LDO regulator 110 to quickly reduce the output voltage V. out Fluctuations. However, a large constant bias current leads to higher power consumption.

[0033] In another approach, the LDO regulator 110 uses adaptive current bias, where the bias current to the amplifier circuit 120 is adjusted based on the load current. At this point, Figure 3 An example of an LDO regulator 110 with adaptive current bias is shown, according to certain aspects. In this example, the LDO regulator 110 includes a current source 310 coupled between a supply rail 112 and an amplifier circuit 120, wherein the current source 310 is configured to provide a bias current to the amplifier circuit 120. The current source 310 is also coupled to the gate of a transfer device 115. The current source 310 is configured to sense the load current from the gate voltage of the transfer device 115 and to adjust the bias current to the amplifier circuit 120 based on the sensed load current. In some aspects, the current source 310 is configured to increase the bias current when the sensed load current increases and decrease the bias current when the sensed load current decreases. By increasing the bias current when the sensed load current is higher (i.e., heavier), the current source 310 increases the loop bandwidth of the LDO regulator 110 (and thus reduces the transient response time) when the sensed load current is higher.

[0034] Figure 4 An exemplary implementation of a current source 310 according to certain aspects is shown. In this example, the current source 310 includes a transistor 410 coupled between a power supply rail 112 and an amplifier circuit 120. Figure 4In the example, transistor 410 is implemented using a PFET having a source coupled to power rail 112 and a drain coupled to amplifier circuit 120. However, it should be understood that in other implementations, transistor 410 may be implemented using another type of transistor. It should also be understood that transistor 410 may include multiple transistors coupled between power rail 112 and amplifier circuit 120. In this example, the gate of transistor 410 is coupled to the gate of transfer device 115, which allows transistor 410 to sense load current from the gate voltage of transfer device 115 and adjust the bias current based on the sensed load current.

[0035] Adaptive current bias is more advantageous than the first method by eliminating the need for the large off-chip capacitors used in the first method. Furthermore, adaptive current bias reduces the bias current when the sensed load current is light, for example, when circuit block 170 is in standby mode. Reducing the bias current during light load current periods lowers power consumption compared to the second method which uses a large, constant bias current.

[0036] However, adaptive current bias may not provide sufficient reduction in voltage undershoot caused by load current changes from light to heavy loads. An example of this is... Figure 5 As shown in the figure, Figure 5 The bias current I is shown Bias and load current I Load Example. In this example, the load current I... Load It rises at time T1 and falls at time T2.

[0037] Before time T1, the load current I Load Lower (i.e., lighter). As a result, the bias current I... Bias It is also lower, which reduces the loop bandwidth of the LDO regulator 110 (and thus increases the transient response time). At time T1, the load current I... Load The increase causes the output voltage V to rise. out The voltage undershoot (e.g., undershoot 210). For example... Figure 5 As shown, at the start of voltage downsampling, the bias current I... Bias Initially, the current is low, therefore the loop bandwidth of the LDO regulator 110 is initially small. This is because the current source 310 senses the load current I from the gate voltage of the transfer device 115. Load The change in gate voltage affects the load current I. Load The response to changes is limited by the loop bandwidth of the LDO regulator 110 (which is initially small), therefore, in the case of load current I... Load The rise and bias current I Bias There is a relatively long delay T between the increase.Delay The initial small loop bandwidth of the LDO regulator 110 (and therefore the initial slow transient response) may result in a large output voltage undershoot.

[0038] At time T2, the load current I Load The voltage drops, causing the output voltage V to... out Voltage overshoot (e.g., overshoot 220). Figure 5 As shown, at the start of voltage overshoot, the bias current I Bias Initially, the current is relatively high, therefore the loop bandwidth of LDO regulator 110 is initially large. As a result, LDO regulator 110 can respond quickly to the load current I. Load The decrease in voltage and thus a significant reduction in voltage overshoot.

[0039] Therefore, although adaptive current bias significantly reduces voltage overshoot, when the load current I... Load When transitioning from a light load to a heavy load, the adaptive current bias may not provide sufficient reduction in voltage undershoot due to the initial small loop bandwidth of the LDO regulator 110.

[0040] To address this issue, various aspects of this disclosure provide dynamic current biasing to reduce the load current I from light load to heavy load. LOAD The change in output voltage V out The undershoot, as discussed further below. The dynamic current bias according to various aspects of this disclosure can be used in conjunction with adaptive current bias, or can be used without adaptive current bias.

[0041] Figure 6 An example of an LDO regulator 110 with dynamic current bias is shown, depending on certain aspects. In this example, the LDO regulator 110 also includes the current source 310 for adaptive current bias discussed above. However, it should be understood that the current source 310 may be omitted in some implementations.

[0042] In this example, the LDO regulator 110 also includes a bias current source 610 and a feedback capacitor 615 for providing dynamic current bias. In the following discussion, the bias current source 610 is referred to as the first bias current source, and the bias current source 610 is referred to as the second bias current source.

[0043] A first current source 610 is coupled between the power supply rail 112 and the amplifier circuit 120, wherein the first current source 610 is configured to provide bias current to the amplifier circuit 120. A feedback capacitor 615 is coupled between the first current source 610 and the output 130 of the LDO regulator 110. Therefore, the first bias current source 610 is capacitively coupled to the output 130 of the LDO regulator 110 via the feedback capacitor 615. The capacitive coupling reduces the output voltage V during voltage undershoot. out The transient voltage drop in the load is coupled to the first bias current source 610. This allows the first bias current source 610 to detect the load current I from light load to heavy load. Load The change in output voltage V out The transient voltage drop in the output voltage V. In some respects, the transient voltage drop can have a duration between 10 nanoseconds and 1 microsecond. Since the first bias current source 610 is capacitively coupled to the output 130 of the LDO regulator 110 through the feedback capacitor 615, the first bias current source 610 can quickly detect the output voltage V. out The transient voltage drop in the LDO regulator 110 discussed above is not limited by its initially small loop bandwidth. Instead, because the second current source 310 detects the increase in load current from the gate voltage of the transfer device 115, the response time of the adaptive current bias is limited by the loop bandwidth of the LDO regulator 110 (which is initially small).

[0044] In response to the output voltage V out Upon detecting a transient voltage drop, the first current source 610 boosts (i.e., increases) the bias current of the amplifier circuit 120. This increased bias current increases the loop bandwidth of the LDO regulator 110 (i.e., reduces the transient response time), allowing the LDO regulator 110 to respond quickly to voltage undershoot and thus reduce voltage undershoot.

[0045] Therefore, by responding to the output voltage V out The bias current of amplifier circuit 120 is rapidly increased to compensate for the transient drop in voltage, and the first bias current source 610 and feedback capacitor 615 provide LDO regulator 110 with a fast transient response to voltage undershoot. Adaptive current bias can also be helpful during voltage undershoot. This is because, during the transition from light load current to heavy load current, adaptive bias helps to increase loop bandwidth as the load current increases.

[0046] exist Figure 6In the example shown, dynamic current biasing is used in combination with adaptive current biasing. In this example, dynamic current biasing can be used to reduce voltage undershoot caused by load current changes from light load to heavy load, and adaptive current biasing can be used to reduce voltage overshoot caused by load current changes from heavy load to light load. However, it should be understood that in some implementations, dynamic current biasing can be used without adaptive current biasing (e.g., where voltage overshoot is not a problem or is mitigated by another technique). In these implementations, the second current source 310 can be omitted.

[0047] Figure 7 An exemplary implementation of a first current source 610 according to certain aspects is shown. In this example, the first current source 610 includes a transistor 710 coupled between a power supply rail 112 and an amplifier circuit 120. Figure 7 In the example shown, transistor 710 is implemented using a PFET having a source coupled to power rail 112 and a drain coupled to amplifier circuit 120. However, it should be understood that in other implementations, transistor 710 may be implemented using another type of transistor. It should also be understood that transistor 710 may include multiple transistors coupled between power rail 112 and amplifier circuit 120. Furthermore, in this example, the second current source 310 uses the referenced above... Figure 4 The transistor 410 is discussed for implementation.

[0048] exist Figure 7 In the example, the LDO regulator 110 also includes a voltage biasing circuit 725 coupled to the gate of the transistor 710. In this example, the voltage biasing circuit 725 is configured to generate a DC bias voltage Vb, which is applied to the gate of the transistor 710 to bias the gate of the transistor 710.

[0049] In this example, feedback capacitor 615 is coupled between the gate of transistor 710 and the output 130 of LDO regulator 110. Therefore, the gate of transistor 710 is capacitively coupled to the output 130 of LDO regulator 110 via feedback capacitor 615. This capacitive coupling will affect the output voltage V. outA transient voltage drop in the circuit is coupled to the gate of transistor 710, simultaneously blocking the bias voltage Vb from the output 130 of LDO regulator 110. This transient voltage drop, coupled to the gate of transistor 710 through feedback capacitor 615, causes the gate voltage of transistor 710 to decrease from the bias voltage Vb. This decrease in gate voltage causes transistor 710 (implemented as a PFET in this example) to increase the bias current to amplifier circuit 120. Therefore, transistor 710 increases the bias current to amplifier circuit 120 in response to the transient voltage drop at the output 130 of LDO regulator 110 caused by the load current transition from a light load to a heavy load.

[0050] Figure 8 An exemplary implementation of an amplifier circuit 120 according to certain aspects of this disclosure is shown. In this example, the amplifier circuit 120 includes an error amplifier 820 and an output buffer 830. The error amplifier 820 is configured to provide high gain for the amplifier circuit 120 and may have high output impedance. The error amplifier 820 may be implemented using a cascode amplifier or another type of amplifier. The output buffer 830 is configured to provide low output impedance at the output 126 of the amplifier circuit 120 to drive the gate of the pass device 115. The output buffer 830 may be implemented using a source follower or another type of buffer circuit.

[0051] exist Figure 8 In the example, the error amplifier 820 is coupled to a reference voltage V. ref The first input 822 (e.g., negative input), the second input 824 (e.g., positive input) coupled to the output 130 via feedback path 150, and the output 826. The output buffer 830 has an input 832 coupled to the output 826 of the error amplifier 820 and an output 834 coupled to the gate of the transfer device 115.

[0052] exist Figure 8 In the example, Figure 7The illustrated transistor 410 includes a first transistor 410-1 coupled between the power supply rail 112 and the error amplifier 820, and a second transistor 410-2 coupled between the power supply rail 112 and the output buffer 830. In this example, the first transistor 410-1 is implemented using a PFET having a source coupled to the power supply rail 112 and a drain coupled to the error amplifier 820, and the second transistor 410-2 is implemented using a PFET having a source coupled to the power supply rail 112 and a drain coupled to the output buffer 830. However, it should be understood that in other implementations, each of transistors 410-1 and 410-2 may be implemented using a different type of transistor. The gate of each of transistors 410-1 and 410-2 is coupled to the gate of the transfer device 115 to sense load current from the gate voltage of the transfer device 115. In response to a sensed increase in load current, the first transistor 410-1 increases the bias current of the error amplifier 820 and the second transistor 410-2 increases the bias current of the output buffer 830. Therefore, in this example, the first transistor 410-1 provides an adaptive current bias for the error amplifier 820, and the second transistor 410-2 provides an adaptive current bias for the output buffer 830.

[0053] exist Figure 8 In the example, Figure 7 The transistor 710 shown includes a first transistor 710-1 coupled between the power supply rail 112 and the error amplifier 820, and a second transistor 710-2 coupled between the power supply rail 112 and the output buffer 830. Figure 8 In the example, the first transistor 710-1 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to error amplifier 820, and the second transistor 710-2 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to output buffer 830. However, it should be understood that in other implementations, each of transistors 710-1 and 710-2 may be implemented using a different type of transistor. In this example, voltage biasing circuitry 725 is coupled to the gate of each of transistors 710-1 and 710-2 to bias the gates of transistors 710-1 and 710-2.

[0054] A feedback capacitor 615 is coupled between the output 130 and the gate of each of transistors 710-1 and 710-2. Therefore, the gate of each of transistors 710-1 and 710-2 is capacitively coupled to the output 130 via the feedback capacitor 615. This capacitive coupling reduces the output voltage V during voltage downscaling. outThe transient voltage drop is coupled to the gates of transistors 710-1 and 710-2. In response to the transient voltage drop, the first transistor 710-1 increases the bias current to the error amplifier 820, and the second transistor 710-2 increases the bias current to the output buffer 830. Therefore, in this example, the first transistor 710-1 provides dynamic current bias to the error amplifier 820, and the second transistor 710-2 provides dynamic current bias to the output buffer 830.

[0055] Figure 9 An exemplary implementation of a bias circuit 725, an error amplifier 820, and an output buffer 830 according to certain aspects is shown. In this example, the bias circuit 725 includes a transistor 910 (e.g., a PFET) and a resistor 912. The source of the transistor 910 is coupled to a power supply rail 112, and the drain and gate of the transistor 910 are coupled (i.e., bonded) together. The resistor 912 is coupled between the drain of the transistor 910 and ground. In this example, a bias voltage Vb is generated at the gate of the transistor 910.

[0056] Error amplifier 820 includes a first input transistor 920 and a second input transistor 922. The gate of the first input transistor 920 is coupled to the first input 822 of error amplifier 820, and the gate of the second input transistor 922 is coupled to the second input 824 of error amplifier 820. Therefore, the reference voltage V ref The voltage V is applied to the gate of the first input transistor 920, and the feedback voltage V fb It is applied to the gate of the second input transistor 922. Figure 9 In the example, each of input transistors 920 and 922 is implemented using a PFET. However, it should be understood that each of input transistors 920 and 922 can be implemented using another type of transistor (e.g., an NFET).

[0057] Error amplifier 820 also includes transistors 924, 926, 930, 932, 934, 940, 942, and 944. Transistors 924 and 934 are coupled in a current mirror configuration, wherein the drain of transistor 924 is coupled to the drain of the first input transistor 920, and the gate of transistor 924 is coupled to the gate and drain of transistor 934. The sources of transistors 924 and 934 are coupled to ground. The source of transistor 932 is coupled to the drain of transistor 934, and the gate of transistor 932 is biased by a bias voltage Vcas. Transistors 930 and 940 are coupled in a current mirror configuration, wherein the drain of transistor 930 is coupled to the drain of transistor 932, and the gate of transistor 930 is coupled to the gate and drain of transistor 940. The drain of transistor 940 is coupled to the output 826 of error amplifier 820.

[0058] Transistors 926 and 944 are coupled in a current mirror configuration, wherein the drain of transistor 926 is coupled to the drain of the second input transistor 922, and the gate of transistor 926 is coupled to the gate of transistor 944 and the drain of transistor 926. The sources of transistors 926 and 944 are coupled to ground. The source of transistor 942 is coupled to the drain of transistor 944, the gate of transistor 942 is biased by a bias voltage Vcas, and the drain of transistor 942 is coupled to the output 826 of error amplifier 820.

[0059] In operation, current from the first input transistor 920 flows through transistor 924 and is mirrored at the drain of transistor 934. Current from transistor 934 flows through transistors 932 and 930 and is mirrored at the drain of transistor 940, which is coupled to output 826. Current from the second input transistor 922 flows through transistor 926 and is mirrored at the drain of transistor 944. Current from transistor 944 flows through transistor 942 and is coupled to output 826. In this example, transistor 942 is coupled to transistor 944 in a cascaded configuration, which increases the output impedance and gain of error amplifier 820.

[0060] In this example, according to certain aspects, the LDO regulator 110 includes a bias generation circuit 915 configured to generate a bias voltage Vcas. The bias generation circuit 915 includes a bias transistor 914, a resistor Rb, and a capacitor Cb. The resistor Rb and capacitor Cb are coupled in parallel between nodes 916 and 918, where a bias voltage Vcas is generated at node 916. The drain of transistor 914 is coupled to node 918 and the gate of transistor 914, and the source of transistor 914 is coupled to ground. Node 916 is coupled to the bias input 935 of amplifier 820, which is coupled to the gates of transistors 932 and 942. In this example, the resistance of resistor Rb is used to set the voltage difference between the gates of transistors 932 and 934, and between the gates of transistors 942 and 944. Capacitor Cb helps ensure that this voltage difference is kept approximately constant under different adaptive biases.

[0061] In this example, the error amplifier 820 also includes a capacitor Cm coupled between the output 130 and the drain of the transistor 944. The capacitor Cm acts as a Miller compensation capacitor for stability and to enhance the loop bandwidth during transient response.

[0062] In this example, output buffer 830 includes transistors 950, 952, 954, and 956. The gate of transistor 954 is coupled to input 832 of output buffer 830, and the source of transistor 954 is coupled to output 834 of output buffer 830. As discussed further below, transistor 954 is configured as a source follower to provide low output impedance to buffer 830.

[0063] Transistors 950 and 952 are coupled in a current mirror configuration, wherein the gate of transistor 950 is coupled to the gate of transistor 952 and the drain of transistor 950. The sources of transistors 950 and 952 are coupled to ground. The drain of transistor 952 is coupled to the drain of transistor 954. As discussed further below, transistor 950 receives a bias current that is mirrored at the drain of transistor 952.

[0064] The gate of transistor 956 is coupled to the drain of transistor 954, the drain of transistor 956 is coupled to the output 834 of buffer 830, and the source of transistor 956 is coupled to ground. In this example, transistors 956 and 954 are coupled in a super-source follower configuration to further reduce (i.e., attenuate) the output impedance of buffer 830. The super-source follower configuration reduces the output impedance to 1 / (gm1*gm2*ro1), where gm1 is the transconductance of transistor 954, gm2 is the transconductance of transistor 956, and ro1 is the impedance of transistor 954. It should be understood that transistors 952 and 956 may be omitted in some implementations. For implementations where transistors 952 and 956 are omitted, the output impedance of buffer 830 is approximately 1 / gm1.

[0065] exist Figure 9 In the example, Figure 7 The transistor 410 includes a first transistor 410-1 coupled between the power supply rail 112 and the drain of transistor 914, a second transistor 410-2 coupled between the power supply rail 112 and the sources of input transistors 920 and 922, a third transistor 410-3 coupled between the power supply rail 112 and the drain of transistor 950, and a fourth transistor 410-4 coupled between the power supply rail 112 and the source of transistor 954. In this example, the first transistor 410-1 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to transistor 914; the second transistor 410-2 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to the sources of input transistors 920 and 922; the third transistor 410-3 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to transistor 950; and the fourth transistor 410-4 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to the source of transistor 954. However, it should be understood that each of transistors 410-1 through 410-4 could be implemented using a different type of transistor in other implementations. The gate of each of transistors 410-1 to 410-4 is coupled to the gate of transfer device 115 to sense the load current from the gate voltage of transfer device 115 and adjust the corresponding bias current based on the sensed load current. Thus, transistors 410-1 to 410-4 provide adaptive current bias for amplifier circuit 120.

[0066] exist Figure 9 In the example, Figure 7The transistor 710 shown includes a first transistor 710-1 coupled between the power supply rail 112 and node 916 of the bias generation circuit 915, a second transistor 710-2 coupled between the power supply rail 112 and the sources of input transistors 920 and 922, a third transistor 710-3 coupled between the power supply rail 112 and the drain of transistor 950, and a fourth transistor 710-4 coupled between the power supply rail 112 and the source of transistor 954. Figure 9 In the example, the first transistor 710-1 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to node 916 of bias generation circuit 915; the second transistor 710-2 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to the sources of input transistors 920 and 922; the third transistor 710-3 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to the drain of transistor 950; and the fourth transistor 410-4 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to the source of transistor 954. However, it should be understood that each of transistors 710-1 through 710-4 could be implemented using a different type of transistor in other implementations. In this example, voltage biasing circuit 725 is coupled to the gate of each of transistors 710-1 to 710-4 to bias the gates of transistors 710-1 to 710-4.

[0067] A feedback capacitor 615 is coupled between the output 130 and the gate of each of the transistors 710-1 to 710-4. Therefore, the gate of each of the transistors 710-1 to 710-4 is capacitively coupled to the output 130 via the feedback capacitor 615. This capacitive coupling reduces the output voltage V during voltage downscaling. out The transient voltage drop is coupled to the gates of transistors 710-1 to 710-4. In response to the transient voltage drop, each of transistors 710-1 to 710-4 increases (i.e., increases) its corresponding bias current. Therefore, in this example, transistors 710-1 to 710-4 provide dynamic current bias for amplifier circuit 120.

[0068] Figure 10 An example of a chip 1010 including an LDO regulator 110 according to certain aspects of this disclosure is shown. The LDO regulator 110 can be used... Figures 6 to 9 Any of the exemplary implementations shown can be used. Chip 1010 includes a power rail 112, a circuit block 170, a power pad 1030, a reference circuit 1040, and a second circuit block 1070. In the following discussion, circuit block 170 is referred to as the first circuit block 170.

[0069] In this example, the power supply pad 1030 is coupled to an external power supply 1020 (i.e., an off-chip power supply). Power supply 1020 may include a battery, a power management integrated circuit (PMIC), and / or another power source. For an example where power supply 1020 includes a PMIC, the PMIC may include components configured to convert the voltage from the battery to the supply voltage V. DD A voltage regulator (not shown). The power supply pad 1030 can be coupled to the power supply 1020 via a metal line 1025 (e.g., on a printed circuit board).

[0070] Power rail 112 is coupled to power pad 1030. In some respects, power rail 112 is configured to receive a supply voltage V from power supply 1020 via power pad 1030. DD The power supply rail 112 may include one or more metal layers on the chip 1010. The power supply rail 112 may also include one or more vias and / or one or more other metal interconnect structures for coupling one or more metal layers.

[0071] In this example, the input 105 of the LDO regulator 110 is coupled to the power supply rail 112, and the output 130 of the LDO regulator 110 is coupled to the first circuit block 170. As described above, the LDO regulator 110 receives the supply voltage V at input 105. DD And at output 130, based on the supply voltage V DD Generates regulated output voltage V out Output voltage V out The first circuit block 170 is supplied to power the first circuit module 170. The circuit block 170 may include pad drivers, logic circuits (e.g., combinational logic and / or sequential logic), processors, memory, and / or other types of circuits.

[0072] Reference circuit 1040 is coupled to amplifier circuit 120 in LDO regulator 110. Figure 10 The first input 122 (not shown in the diagram). The reference circuit 1040 is configured to generate a reference voltage V. ref And the reference voltage V ref The output is given to the first input 122 of the amplifier circuit 120. As described above, the LDO regulator 100 is based on the reference voltage and the feedback voltage V. fb This is used to adjust the voltage at output 130. The reference circuit 1040 can be implemented using a voltage divider, a bandgap reference circuit, or any combination thereof.

[0073] In this example, the second circuit block 1070 is coupled to the power supply rail 112 and receives the supply voltage V from the power supply rail 112. DDTherefore, in this example, the first circuit block 170 and the second circuit block 1070 are powered by different voltages. More specifically, the first circuit block 170 is powered by the regulated output voltage V of the LDO regulator 110. out Power is supplied, and the second circuit 1070 is supplied with power voltage V from power rail 112. DD Power supply. In this example, LDO regulator 110 allows the first circuit block 170 to be supplied with a voltage V different from the supply voltage V on power rail 112. DD It is powered by the voltage.

[0074] Figure 11 A method 1100 for operating a voltage regulator according to certain aspects is shown. The voltage regulator (e.g., LDO regulator 110) includes a transfer device (e.g., transfer device 115) coupled between the input and output of the voltage regulator and an amplifier circuit (e.g., amplifier circuit 120) coupled to the gate of the transfer device.

[0075] In block 1110, a transient voltage drop at the output of the voltage regulator is detected via a capacitor. This capacitor may correspond to feedback capacitor 615. The transient voltage drop may have a duration between 10 nanoseconds and 1 microsecond.

[0076] In block 1120, a bias current is added to the amplifier circuit based on the detected transient voltage drop. In one example, the voltage regulator may include a transistor (e.g., transistor 710) coupled between a power supply rail (e.g., power supply rail 112) and the amplifier circuit. In this example, the bias current added to the amplifier circuit may include capacitively coupling the transient voltage drop to the gate of the transistor via a capacitor. In one example, the transistor may include a PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0077] An implementation example is described in the following numbered clauses:

[0078] 1. A voltage regulator, comprising:

[0079] A transmission device is coupled between the input and the output of the voltage regulator;

[0080] An amplifier circuit has a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transmission device.

[0081] A first current source is coupled between the power supply rail and the amplifier circuit; and

[0082] A capacitor is coupled between the first current source and the output of the voltage regulator.

[0083] 2. The voltage regulator according to Clause 1, wherein the first current source includes a transistor coupled between the power supply rail and the amplification circuit, wherein the capacitor is coupled between the gate of the transistor and the output of the voltage regulator.

[0084] 3. The voltage regulator according to Clause 2, wherein the transistor includes a p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0085] 4. The voltage regulator according to clause 2 or 3 further includes a voltage biasing circuit coupled to the gate of the transistor.

[0086] 5. The voltage regulator according to any one of clauses 1 to 4 further includes a second current source coupled between the power supply rail and the amplification circuit, wherein the second current source is coupled to the gate of the transmission device.

[0087] 6. The voltage regulator according to Clause 5, wherein:

[0088] The first current source includes a first transistor coupled between the power supply rail and the amplification circuit, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator; and

[0089] The second current source includes a second transistor coupled between the power supply rail and the amplifier circuit, wherein the gate of the second transistor is coupled to the gate of the transmission device.

[0090] 7. The voltage regulator according to Clause 6, wherein:

[0091] The first transistor includes a first p-type field-effect transistor (PFET), the first PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit; and

[0092] The second transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0093] 8. The voltage regulator according to clause 6 or 7 further includes a voltage biasing circuit coupled to the gate of the first transistor.

[0094] 9. The voltage regulator according to any one of clauses 1 to 8, wherein the amplification circuit comprises:

[0095] An amplifier having a first input configured to receive the reference voltage, a second input coupled to the output of the voltage regulator via the feedback path, and an output; and

[0096] A buffer having an input coupled to the output of the amplifier and an output coupled to the gate of the transmission device.

[0097] 10. The voltage regulator according to Clause 9, wherein the first current source comprises:

[0098] A first transistor is coupled between the power supply rail and the amplifier, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator; and

[0099] A second transistor is coupled between the power supply rail and the buffer, wherein the capacitor is coupled between the gate of the second transistor and the output of the voltage regulator.

[0100] 11. The voltage regulator according to Clause 10, wherein:

[0101] The first transistor includes a first p-type field-effect transistor (PFET), the first PFET having a source coupled to the power supply rail and a drain coupled to the amplifier; and

[0102] The second transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the buffer.

[0103] 12. The voltage regulator according to clause 10 or 11 further includes a voltage biasing circuit coupled to the gate of the first transistor and the gate of the second transistor.

[0104] 13. The voltage regulator according to any one of clauses 9 to 12 further includes a second current source coupled between the power supply rail and the amplification circuit, wherein the second current source is coupled to the gate of the transmission device.

[0105] 14. The voltage regulator according to Clause 13, wherein the second current source comprises:

[0106] A third transistor is coupled between the power supply rail and the amplifier, wherein the gate of the third transistor is coupled to the gate of the transmission device; and

[0107] A fourth transistor is coupled between the power supply rail and the buffer, wherein the gate of the third transistor is coupled to the gate of the transmission device.

[0108] 15. The voltage regulator according to any one of clauses 9 to 14, wherein the amplifier comprises a cascaded amplifier.

[0109] 16. The voltage regulator according to any one of clauses 9 to 15 further includes a bias generation circuit, wherein the bias generation circuit comprises:

[0110] A resistor is coupled between a first node and a second node, wherein the first node is coupled to the bias input of the amplifier;

[0111] A capacitor is coupled between the first node and the second node; and

[0112] A bias transistor having a drain coupled to the second node, a gate coupled to the drain, and a source coupled to ground.

[0113] 17. The voltage regulator according to Clause 16, wherein the first current source comprises:

[0114] A first transistor is coupled between the power supply rail and the first node of the bias generation circuit, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator;

[0115] A second transistor is coupled between the power supply rail and the amplifier, wherein the capacitor is coupled between the gate of the second transistor and the output of the voltage regulator; and

[0116] A third transistor is coupled between the power supply rail and the buffer, wherein the capacitor is coupled between the gate of the third transistor and the output of the voltage regulator.

[0117] 18. The voltage regulator according to Clause 17 further includes a voltage biasing circuit coupled to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor.

[0118] 19. A voltage regulator according to any one of clauses 9 to 18, wherein the buffer includes a source follower.

[0119] 20. A method of operating a voltage regulator, wherein the voltage regulator includes a transfer device coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplification circuit coupled to the gate of the transfer device, the method comprising:

[0120] The transient voltage drop at the output of the voltage regulator is detected via a capacitor; and

[0121] The bias current to the amplifier circuit is increased based on the detected transient voltage drop.

[0122] 21. The method according to Clause 20, wherein:

[0123] The voltage regulator includes a transistor coupled between the power supply rail and the amplifier circuit; and

[0124] The bias current added to the amplifier circuit based on the transient voltage drop includes coupling the transient voltage drop capacitance to the gate of the transistor via the capacitor.

[0125] 22. The method according to Clause 21, wherein the transistor includes a first p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0126] 23. The method according to any one of clauses 20 to 22 further includes:

[0127] Detecting the gate voltage of the transmission device; and

[0128] The bias current of the amplifier circuit is adjusted based on the detected gate voltage.

[0129] 24. The method described according to Clause 23, wherein:

[0130] The voltage regulator includes a first transistor coupled between the power supply rail and the amplifier circuit;

[0131] The bias current added to the amplifier circuit based on the transient voltage drop includes coupling the transient voltage drop capacitance to the gate of the first transistor via the capacitor;

[0132] The voltage regulator includes a second transistor coupled between the power supply rail and the amplifier circuit; and

[0133] Adjusting the bias current of the amplifier circuit based on the detected gate voltage includes coupling the gate of the second transistor to the gate of the transmission device.

[0134] 25. A chip, comprising:

[0135] solder pads;

[0136] The power supply rail is coupled to the pad;

[0137] The reference circuit is configured to generate a reference voltage; and

[0138] Voltage regulator, including:

[0139] A transmission device is coupled between the input and the output of the voltage regulator, wherein the input of the voltage regulator is coupled to the power supply rail;

[0140] An amplifier circuit has a first input, a second input, and an output, wherein the first input is coupled to the reference circuit, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transmission device.

[0141] A first current source is coupled between the power supply rail and the amplifier circuit; and

[0142] A capacitor is coupled between the first current source and the output of the voltage regulator.

[0143] 26. The chip according to Clause 25, wherein the first current source includes a transistor coupled between the power supply rail and the amplification circuit, wherein the capacitor is coupled between the gate of the transistor and the output of the voltage regulator.

[0144] 27. The chip according to Clause 26 further includes a voltage biasing circuit coupled to the gate of the transistor.

[0145] 28. The chip according to any one of clauses 25 to 27 further includes a second current source coupled between the power supply rail and the amplification circuit, wherein the second current source is coupled to the gate of the transmission device.

[0146] 29. The chip as described in Clause 28, wherein:

[0147] The first current source includes a first transistor coupled between the power supply rail and the amplification circuit, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator; and

[0148] The second current source includes a second transistor coupled between the power supply rail and the amplifier circuit, wherein the gate of the second transistor is coupled to the gate of the transmission device.

[0149] 30. The chip as described in Clause 29, wherein:

[0150] The first transistor includes a first p-type field-effect transistor (PFET), the first PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit; and

[0151] The second transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0152] Any references to elements in this document using names such as "first," "second," etc., do not generally restrict the number or order of these elements. Rather, these names are used in this document as a convenient way to distinguish two or more elements or instances of elements. Therefore, references to the first element and the second element do not imply that only two elements can be used, or that the first element must precede the second element.

[0153] In this disclosure, the term “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “approximate” as used herein means within 10% of the value or property (i.e., between 90% and 110% of the value or property).

[0154] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and other variations may be applied without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A voltage regulator comprising: a pass device coupled between an input of the voltage regulator and an output of the voltage regulator; an amplification circuit having a first input configured to receive a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output coupled to a gate of the pass device; a first current source coupled between a supply rail and the amplification circuit, wherein the first current source comprises a first transistor coupled between the supply rail and the amplification circuit, a drain of the first transistor directly coupled to the amplification circuit, wherein a capacitor is coupled between a gate of the first transistor and the output of the voltage regulator; and a second current source coupled between the supply rail and the amplification circuit, wherein the second current source comprises a second transistor coupled between the supply rail and the amplification circuit, wherein a gate of the second transistor is coupled to the gate of the pass device and a drain of the second transistor is directly coupled to the amplification circuit.

2. The voltage regulator of claim 1, wherein the first transistor comprises a p-type field effect transistor (PFET) having a source coupled to the supply rail.

3. The voltage regulator of claim 1, further comprising a voltage bias circuit coupled to the gate of the first transistor.

4. The voltage regulator of claim 1, wherein the amplification circuit comprises: an amplifier having a first input configured to receive the reference voltage, a second input coupled to the output of the voltage regulator via the feedback path, and an output; and a buffer having an input coupled to the output of the amplifier and an output coupled to the gate of the pass device.

5. The voltage regulator of claim 4, wherein the first current source further comprises: a third transistor coupled between the supply rail and the buffer, wherein the capacitor is coupled between a gate of the third transistor and the output of the voltage regulator.

6. The voltage regulator of claim 5, wherein: the first transistor comprises a first p-type field effect transistor (PFET) having a source coupled to the supply rail and a drain coupled to the amplifier; and the third transistor comprises a second PFET having a source coupled to the supply rail and a drain coupled to the buffer.

7. The voltage regulator of claim 5, further comprising a voltage bias circuit coupled to the gate of the first transistor and the gate of the third transistor.

8. The voltage regulator of claim 5, wherein the second current source further comprises: a fourth transistor coupled between the supply rail and the buffer, wherein a gate of the fourth transistor is coupled to the gate of the pass device. ​ ​ ​ 9. The voltage regulator of claim 4, wherein the amplifier comprises a cascode amplifier.

10. The voltage regulator of claim 4, further comprising a bias generation circuit, wherein the bias generation circuit comprises: a resistor coupled between a first node and a second node, wherein the first node is coupled to a bias input of the amplifier; a capacitor coupled between the first node and the second node; and a bias transistor having a drain coupled to the second node, a gate coupled to the drain, and a source coupled to ground.

11. The voltage regulator of claim 4, wherein the buffer comprises a source follower.

12. A method of operating the voltage regulator of claim 1, the method comprising: detecting a transient voltage drop at the output of the voltage regulator via the capacitor; increasing a bias current to the amplification circuit based on the detected transient voltage drop; detecting a gate voltage of the pass device; and adjusting the bias current to the amplification circuit based on the detected gate voltage.

13. The method of claim 12, wherein the first transistor comprises a first p-type field effect transistor (PFET), the first PFET having a source coupled to the supply rail.

14. A chip comprising: a pad; a supply rail coupled to the pad; a reference circuit configured to generate a reference voltage; and the voltage regulator of claim 1. ​ ​ ​

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