Test device and method for a battery management system

Abstract

The application relates to the technical field of battery testing, and particularly provides a battery management system testing device and method, which adopts a modular cascading architecture, a single testing module integrates multiple testing circuits, different-stage battery testing is adapted through a cascading mapping interface, high-precision source tables are greatly reduced, and hardware cost is reduced. A precision resistance network is arranged, a same-source voltage division link is formed by first resistors in series, and common-mode error is eliminated; a relay integrates normally-closed / normally-open contacts, realizes constant conduction of a reference path, and realizes controlled conduction of a voltage regulation / shunt branch. Single-channel independent precise control is realized through I2C+GPIO, a common branch is designed to simplify the circuit, and high precision, high expansibility and operation convenience are considered. Therefore, the problems of high cost caused by the fact that each stage of battery needs an independent source table and poor precision caused by error accumulation in the related art are solved.

Description

Technical Field

[0001] This invention relates to the field of battery testing technology, and in particular to a testing apparatus and method for a battery management system. Background Technology

[0002] As a core component of a power battery system, the battery management system (BMS) requires high-precision detection and verification of individual cell voltage, charging and discharging current, equalization function, and overvoltage and undervoltage protection functions. Therefore, it places high demands on the accuracy, scalability, and automation of BMS testing equipment.

[0003] Existing BMS testing equipment mostly adopts an architecture where each battery level corresponds to an independent source meter channel. Each battery level requires an independent high-precision VI source meter and voltage divider circuit, resulting in high hardware costs, large size, and difficulty in flexibly adapting to the testing of BMS chips with different numbers of levels. At the same time, traditional testing equipment often uses a single resistor network structure, which cannot simultaneously achieve precise voltage measurement, overvoltage and undervoltage simulation, and low resistance measurement of the equalization loop on the same hardware platform. Switching between test modes requires manual modification of hardware wiring, which is cumbersome and inconsistent.

[0004] In summary, traditional BMS testing devices suffer from high hardware costs, poor scalability, and limited measurement accuracy, making it impossible to simultaneously meet the demands of high-precision testing and low-cost, highly versatile industrial mass production testing. Summary of the Invention

[0005] The present invention provides a testing device and method for a battery management system, which at least solves the problems of high cost caused by requiring an independent source meter for each battery level and poor accuracy caused by error accumulation.

[0006] This invention provides a battery management system (BMS) testing device, comprising: at least one test module; the test module includes a multi-level BMS test circuit, the BMS test circuit including a core interface circuit, a precision resistor network circuit, and a relay drive and control circuit; the core interface circuit includes a test machine VI channel interface, an I2C control interface, a cascade mapping interface, and a GPIO control interface; the test machine VI channel interface is used to connect to the source meter of an external test device; the I2C control interface is used to communicate between a host computer and the GPIO control interface to send host computer commands to the GPIO control interface for circuit control; the cascade mapping interface is used to connect multiple test modules in series to adapt to BMS testing of batteries with different levels; the GPIO control interface includes a first pin corresponding to the test machine VI channel, the first pin being connected to the test... The relays on the test machine VI channel are connected; the precision resistor network circuit corresponds one-to-one with multiple test machine VI channels. The precision resistor network includes a precision voltage divider resistor network, a high and low voltage adjustment resistor network, and a high current measurement resistor network. The precision voltage divider resistor network includes multiple low-temperature drift first resistors corresponding to the test machine VI channels. The high and low voltage adjustment resistor network consists of multiple second resistors corresponding to the test machine VI channels. The high current measurement resistor network includes multiple shunt resistors corresponding to the test machine VI channels and an external power resistor. The relay drive and control circuit is equipped with multiple relays corresponding one-to-one with the test machine VI channels. The relays include normally closed contacts and normally open contacts. The control terminal of the relay is connected to the corresponding first pin. The normally closed contacts are connected in series in the test machine VI channels. The normally open contacts are connected in series with the second resistors and shunt resistors, and in parallel with the first resistors.

[0007] As an optional solution, the test machine's VI channels include M channels from VI_CH0 to VI_CHm-1, with VI_CH0 to VI_CHn-1 being N core battery-level test channels and VI_CHn to VI_CHm-1 being MN expansion channels. The I2C control interface includes an SCK1 clock pin and an SDA1 data pin, which are connected to the host computer. The SCK1 clock pin and SDA1 data pin are also equipped with pull-up resistors. The first pin includes GPB1_0 to GPB1_n-1, which are connected to the control terminals of the corresponding relays.

[0008] As an optional solution, the precision voltage divider resistor network includes N low-temperature drift first resistors VI_R0 with a resistance value exceeding 1KΩ and an accuracy of <0.1%; the N first resistors VI_R0 are connected in series to form an N-level battery basic precision voltage divider link; the high and low voltage adjustment resistor network consists of N second resistors VI_R1~VI_Rn-1 with a resistance value exceeding 4KΩ, and the second resistors VI_R1~VI_Rn-1 are connected in parallel with the first resistor VI_R0 of the corresponding tester VI channel; the high current measurement resistor network includes shunt resistors VI_RS1~VI_RSn and power resistors built into the test module; the shunt resistors are connected in series with the corresponding power resistors and then connected in parallel with the first resistor VI_R0 of the corresponding tester VI channel.

[0009] As an optional solution, the relay drive and control circuit includes N relays, and the control pins of the N relays are VI_FS0~VI_FSn-1 respectively; the control pins VI_FS0~VI_FSn-1 are connected to the first pins GPB1_0~GPB1_n-1 respectively.

[0010] As an optional solution, the GPIO control interface also includes second pins GPB2_0~GPB2_n-1, each corresponding to one of the VI channels of the test machine, and third pins GPA1_1~GPA1_n-1, each corresponding to one of the VI channels of the test machine. The second pins GPB2_0~GPB2_n-1 are connected to normally open contacts, and the third pin is adapted to dual-level. The third pins GPA1_1~GPA1_n-1 are connected to the digital pins of the BMS chip for interfacing with the digital signal terminals of the BMS chip. The first, second, and third pins are all reserved for expansion functions to adapt to the digital interface requirements of BMS chips of different specifications.

[0011] As an optional solution, it also includes: the BMS chip docking circuit is equipped with a dedicated docking socket, which is connected to the Cell pin of the BMS chip and the corresponding VI channel of the test machine; the power supply circuit adopts a three-way independent isolated power supply architecture, namely a high-voltage test power supply for powering the test VI channel, a low-voltage control power supply for powering the GPIO control interface, and a relay drive power supply for powering the relay.

[0012] As an optional solution, a dedicated connector includes N Cell pins Cell0 to Celln-1, which are connected one-to-one with the VI channels VI_CH0 to VI_CHn-1 of the test machine; each Cell pin is equipped with a current limiting circuit and a filtering circuit.

[0013] As an optional solution, the power supply and grounding circuit also features a layered grounding system with DGND digital ground pins and analog ground pins, where the digital ground and analog ground share a common ground at a single point within the test module.

[0014] This invention also provides a testing method for a battery management system, applicable to a testing device for a battery management system according to any one of the above-mentioned embodiments, comprising: stacking a corresponding number of test modules in series according to the number of battery levels of the BMS chip under test; connecting the test device's test machine VI channel interface to an external high-precision source meter and the I2C control interface to a host computer; connecting the test device to three independent isolated power supplies and completing power-on initialization; the host computer issuing a calibration command through the I2C control interface; switching the external source meter to a forced voltage output mode; and, based on the first resistance of the precision voltage divider resistor network within the test module, sequentially measuring the base circuit current and the adjustment resistance and shunt current of each branch. The loop current of the resistors is calculated, the actual resistance values ​​of each resistor are stored, and the precision resistor network is self-calibrated. The host computer independently controls the on / off of the relays of each tester VI channel through the GPIO control interface, switches the topology of the precision resistor network, and performs resistance measurement tests in voltage measurement mode, overvoltage warning mode, undervoltage warning mode, and equalization mode. In each mode, a single external source meter provides the same test voltage to multiple tester VI channels. The feedback signals and test data of the BMS chip in each test mode are collected in real time, compared with the preset test accuracy threshold and functional threshold, and the performance of the BMS chip is determined to be qualified, generating a test report.

[0015] As an optional solution, the voltage measurement mode test includes: controlling the normally open contacts of the relays of all VI channels of the test machine to open and the normally closed contacts to close, retaining only the first low-temperature drift resistor to form a series same-source voltage divider link; adjusting the output voltage of the external source meter, setting the single-stage voltage Vcell=(V+-V-) / n according to the number of battery stages n, and achieving the same-source voltage supply through a single source meter to eliminate common-mode error; triggering the BMS chip ADC voltage scan, collecting the Cell voltage value reported by the BMS chip for each stage, and using the same-source noise characteristics to achieve noise self-cancellation within the scan cycle; comparing the measured value with the nominal value to verify that the measurement error is ≤±200uV, and repeating the verification at typical operating points such as 3.0V, 3.7V, and 4.2V to determine whether the ADC accuracy and common-mode rejection ratio are qualified;

[0016] The overvoltage warning mode test includes: closing the normally open contacts of all VI channels of the test machine to form a basic voltage divider network with the first resistor in parallel; setting the external source meter voltage so that the basic voltage of each channel is the nominal value of a fully charged battery; disconnecting the normally open contacts of the target channel one by one, so that the target channel retains only the voltage divider of the first resistor, raising the voltage of the target channel to the overvoltage threshold range, collecting the overvoltage warning signal of the BMS chip, and verifying the overvoltage protection trigger function; if it is necessary to search for the overvoltage threshold, keep the resistor network configuration unchanged, adjust the external source meter voltage to determine the overvoltage threshold.

[0017] The undervoltage warning mode test includes: controlling all normally open contacts of the VI channels of the test machine to open, leaving only the first resistor to form a basic voltage divider network, setting the external source meter voltage so that the basic voltage of each channel is the nominal value of a fully charged battery; closing the normally open contacts of the target channel one by one, so that the second resistor is connected in parallel with the first resistor, reducing the voltage of the target channel to the undervoltage threshold range, collecting the undervoltage warning signal of the BMS chip, and verifying the undervoltage protection trigger function. If it is necessary to search for the undervoltage threshold, the resistor network configuration remains unchanged and the external source meter voltage is adjusted to complete the task.

[0018] The resistance measurement test in equalization mode includes: controlling the normally open contacts of all VI channels of the tester to close, so that the shunt resistor, external power resistor and the first resistor are connected in parallel to form a large current shunt network, and the basic background current of the circuit is collected; controlling the equalization switch of the BMS chip under test to turn on one by one, so that the target channel forms a parallel circuit of the first resistor, shunt resistor, external power resistor and R_dson, and the circuit current after conduction is collected. Based on the basic background current, the current after conduction and the output voltage of the source meter, the actual resistance value of R_dson is calculated, realizing high-precision measurement of small resistance and avoiding the anti-interference problem of small voltage measurement.

[0019] The battery management system testing device provided in this invention adopts a modular, cascadeable architecture. A single test module integrates multiple test circuits, and a cascaded mapping interface adapts to testing batteries of different levels, significantly reducing the need for high-precision source meters and lowering hardware costs. A precision resistor network is set up, with the first resistor connected in series to form a common-source voltage divider link, eliminating common-mode errors. Relays integrate normally closed / normally open contacts, ensuring the reference path is always on and the voltage regulation / shunt branch is controlled to conduct. I2C+GPIO enables independent and precise control of each channel, and the shared branch design simplifies the circuit, balancing high testing accuracy, high scalability, and ease of operation. This solves the problems of high cost caused by requiring an independent source meter for each battery level and poor accuracy due to error accumulation in related technologies. Attached Figure Description

[0020] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the embodiments will be briefly introduced below.

[0021] Figure 1 This is a schematic diagram of the overall architecture and control connection of a BMS testing device in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the precision resistor network and relay topology in an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of the multi-module cascade ground and power supply topology in an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the topology of the cascaded mapping interface and the VI channel of the test machine in an embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram of the shunt resistor and relay control circuit in an embodiment of the present invention.

[0026] Figure 6 This is a schematic diagram of the precision resistor network and the first pin control circuit in an embodiment of the present invention.

[0027] Figure 7 This is a schematic diagram of the digital signal interface of the BMS chip and the control circuit of the third pin in an embodiment of the present invention.

[0028] Figure 8 This is a schematic diagram of the I2C-GPIO extended control drive circuit in an embodiment of the present invention.

[0029] Figure 9 This is a schematic diagram of the second pin and the relay control drive circuit in an embodiment of the present invention.

[0030] Figure 10 This is a schematic diagram of the circuit connecting the Cell pin of the BMS chip to the VI channel of the test machine in an embodiment of the present invention. Detailed Implementation

[0031] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0032] like Figures 1 to 3 As shown, a battery management system testing device according to this embodiment includes at least one testing module; the testing module includes a multi-level battery management system (BMS) testing circuit, and the BMS testing circuit includes a core interface circuit, a precision resistor network circuit, and a relay drive and control circuit.

[0033] The core interface circuit includes a tester VI channel interface, an I2C control interface, a cascade mapping interface, and a GPIO control interface. The tester VI channel interface is used to connect to the source meter of an external test device (Tester) to power multiple VI test channels through a single source meter, reducing the number of high-precision source meters used and lowering the cost of test hardware. The I2C control interface is used to communicate with the host computer and the GPIO control interface to send host computer commands to the GPIO control interface for circuit control. The cascade mapping interface is used to connect multiple test modules in series to adapt to BMS testing of batteries with different levels, improving hardware reusability. The GPIO control interface includes a first pin corresponding to the tester VI channel, which is connected to a relay set on the tester VI channel.

[0034] The precision resistor network circuit corresponds one-to-one with multiple tester VI channels. The precision resistor network includes a precision voltage divider resistor network, a high and low voltage adjustment resistor network, and a high current measurement resistor network. The precision voltage divider resistor network includes multiple low-temperature drift first resistors corresponding to the tester VI channels. These first resistors are connected in series to form a common-source voltage divider link to eliminate common-mode error and ensure the accuracy of the BMS test voltage. The high and low voltage adjustment resistor network consists of multiple second resistors corresponding to the tester VI channels. The high current measurement resistor network includes multiple shunt resistors corresponding to the tester VI channels and external power resistors.

[0035] like Figure 1 As shown, each precision resistor network corresponds to one Cell channel (Cell_1~Cell_MAX), realizing the test signal output of a single-stage battery. IIC (I2C) controls the relay switch to select the resistor through the relay drive and control circuit and the GPIO control interface, demonstrating the core control logic of the host computer issuing commands via I2C to control the relay's on / off state to switch the resistor network topology. The BMS_Cell pin is used to connect the test signals of each Cell channel to the corresponding Cell pins of the BMS chip, achieving precise docking between the test device and the BMS chip.

[0036] Specifically, such as Figure 2 As shown, Figure 2 Each precision resistor network includes a 1KΩ, <0.1% accuracy low-temperature drift first resistor. Multiple first resistors are connected in series to form the basic precision voltage divider link of an N-level battery. A 5KΩ, 1% accuracy second resistor is connected in parallel with the first resistor of the corresponding channel for single-stage voltage adjustment to simulate overvoltage / undervoltage test scenarios. A 42Ω, 1% accuracy power resistor is connected in series with the built-in shunt resistor and then in parallel with the first resistor for R_dson small resistance measurement in equalization mode. The relay drive and control circuit includes normally closed and normally open contacts of the relay. The normally closed contacts are connected in series with the first resistor main path by default. The normally open contacts are connected in series with the second resistor and the shunt resistor and then in parallel with the first resistor. The tester controls the on / off state via I2C to realize the switching of the resistor network topology. The middle BMS_Cell pin inputs the test signals of each Cell channel to the BMS chip.

[0037] The relay drive and control circuit is equipped with multiple relays that correspond one-to-one with the VI channels of the test machine. The relays include normally closed contacts and normally open contacts. The control terminal of the relay is connected to the corresponding first pin. The normally closed contacts are connected in series in the first resistor main path of the VI channel of the test machine to ensure that the reference voltage divider path is turned on by default. The normally open contacts are connected in series with the second resistor and the shunt resistor, and in parallel with the first resistor to realize the controlled conduction of the voltage regulation / shunt branch and simplify the test mode switching.

[0038] like Figure 3 As shown, Figure 3 The tester circuit connection involves connecting the power supplies end-to-end to form a continuous test link, adapting to the BMS testing requirements of batteries with different charge levels. The Cell_1 to Cell_MAX channels and grounding structure are essentially layered grounding with DGND digital ground pins and analog ground pins. The digital and analog grounds share a common ground point within the test module. Figure 3 The Cell_1 terminal is grounded at a single point, and all channels share a common ground, eliminating ground bounce interference and ensuring grounding consistency after multiple modules are cascaded. The ring topology with the power supply connected end to end is also a three-way independent isolated power supply architecture. The high-voltage test power supply supplies power to the test VI channel and provides the total voltage to the series precision resistor network, realizing that a single source meter supplies power to multiple VI channels from the same source, eliminating common-mode error from the hardware level.

[0039] The core of the testing device provided in this embodiment is to abandon the redundant architecture of traditional BMS testing systems, which use a single high-precision VI channel for each primary battery. Instead, it addresses the pain points of traditional testing devices—high cost, susceptibility to accuracy interference, and poor scalability—through modular cascading, multiple VI channels sharing a single source meter, integrated precision resistor networks, and separate relay contact control. The overall device uses test modules as basic units, integrating core interface circuits, precision resistor network circuits, and relay drive and control circuits. Each module is controlled by instructions, and the execution logic of resistor network switching and VI channel signal output forms a linkage, enabling high-precision, low-cost testing of BMS for different battery levels, while ensuring testing flexibility and scalability.

[0040] The aforementioned test module can be a single unit or multiple units. A single test module integrates multiple independent BMS test circuits, enabling simultaneous testing of multiple battery levels. The feature of powering multiple VI channels with a single external source meter significantly reduces the number of high-precision source meters required, meaning that only one VI source meter is needed for the multi-level test circuits of a single test module, directly reducing the procurement and maintenance costs of core test equipment.

[0041] The communication connection between the host computer and the GPIO control interface uses the I2C control interface as a communication bridge between the host computer and the test device, enabling the host computer to send control commands to the GPIO control interface, and the GPIO control interface to execute circuit control actions after receiving the commands.

[0042] Using the I2C control interface as the communication bridge between the host computer and the testing device, the host computer can realize the on / off control of all relays and the feedback of equipment status through a single communication link. There is no need to arrange a separate control line for each VI channel of the testing machine, which simplifies the control link and reduces the operational complexity.

[0043] The first pin of the GPIO control interface corresponds one-to-one with the VI channel and relay of the test machine, realizing independent control of the relay of a single VI channel of the test machine. It can perform voltage regulation / high current measurement test on a single battery level, simulate the fault scenario of a single battery, meet the test requirements of single-level fault identification of BMS chip, and greatly improve test flexibility.

[0044] The precision voltage divider resistor network uses a low-temperature drift first resistor connected in series to form a common source voltage divider link. The test voltage of all VI channels is obtained by voltage division from the same source meter and the same resistor network, which completely eliminates common mode error from the hardware level and ensures the basic accuracy of voltage measurement.

[0045] The high-current resistance measurement network adopts a design with built-in shunt resistor and external power resistor. The external power resistor can be replaced with different resistance values ​​according to the test requirements to adapt to the measurement of R_dson small resistances of different current levels, thereby improving the test adaptability of the device.

[0046] The normally closed contacts of the relay are closed by default, ensuring that no additional resistors are involved in the reference voltage divider link. This avoids errors introduced by topological changes in the resistor network during non-testing conditions and ensures the stability of test accuracy.

[0047] Each VI channel's corresponding relay integrates both normally closed and normally open contacts, which can be achieved using one single-pole double-throw relay or two single-pole single-throw relays. The two relays work together to switch the topology of the resistor network, and are not independent relays.

[0048] The relay achieves topology switching of the resistor network through the division of labor between normally closed and normally open contacts. No external resistor load is required. The test mode can be switched by simply issuing on / off commands from the host computer, which simplifies the test operation process and improves test efficiency.

[0049] The normally open contact is connected in series with the second resistor and the shunt resistor, and in parallel with the first resistor: This means that the second resistor and the shunt resistor are a common branch connected in parallel to the first resistor. The overall controllable conduction / disconnection of this branch is achieved by opening and closing the normally open contact, which simplifies the circuit control logic.

[0050] The second resistor and the shunt resistor are designed as a shared parallel branch, and the branch on / off control is achieved through a normally open contact. This reduces the use of hardware components such as relays and control pins, simplifies the circuit structure, and further reduces hardware costs.

[0051] Each core hardware module corresponds one-to-one with the VI channel of the test machine, forming multiple independent BMS test circuits. A failure of a single BMS test circuit only affects the test of the corresponding battery level and will not cause the entire device to fail, thus achieving fault isolation and improving the reliability of the equipment.

[0052] As an optional solution, the tester's VI channels include M channels from VI_CH0 to VI_CHm-1, with VI_CH0 to VI_CHn-1 being N core battery-level test channels and VI_CHn to VI_CHm-1 being MN expansion channels to accommodate future functional expansions. All tester VI channel inputs are connected to an external single-channel high-precision source meter. The I2C control interface includes an SCK1 clock pin and an SDA1 data pin, which connect to the host computer. Pull-up resistors are also provided for the SCK1 clock pin and SDA1 data pin to ensure the stability of the I2C communication signal. The first pin includes GPB1_0 to GPB1_n-1, which are connected to the control terminals of the corresponding relays.

[0053] like Figures 4 to 10 As shown, taking N=8 as an example, the test machine VI channel includes 9 channels from VI_CH0 to VI_CH8. VI_CH0 to VI_CH7 are 8 core battery-level test channels, and VI_CH8 is an expansion channel. The SCK1 clock pin and SDA1 data pin are also equipped with pull-up resistors R80. The first pin includes GPB1_0 to GPB1_7, which are connected to the control terminals of the corresponding relays.

[0054] The other end of the pull-up resistor is connected to a 5V DC power supply to ensure the high-level stability of the I2C communication signal and avoid signal distortion. One end of the SCK1 and SDA1 pins is bidirectionally connected to the host computer's I2C communication port, and the other end is connected to the communication end of the GPIO control interface to realize the stable issuance of host computer commands.

[0055] The cascaded mapping interface enables the series connection of multiple test modules, which can be flexibly adapted to BMS testing of batteries with different levels such as 8 / 16 / 24 / 32. There is no need to reconstruct the hardware circuit, the hardware expansion operation is simple, and the adaptability is strong.

[0056] The tester's VI channel interface has a reserved VI_CH8 expansion channel. The first pin of the GPIO control interface is a standardized pin design, which can expand the number of channels and add control functions according to actual test needs, and adapt to the test needs of different BMS chips.

[0057] The output of the first pin of each channel is directly connected to the control terminal of the corresponding relay, receives the host computer instructions forwarded by the I2C interface, and independently controls the on / off action of the corresponding relay.

[0058] As an optional solution, the precision voltage divider resistor network includes N low-temperature drift first resistors VI_R0 with a resistance value exceeding 1KΩ and an accuracy of <0.1%. The N first resistors VI_R0 are connected in series to form the basic precision voltage divider link of the N-level battery, so as to achieve equal voltage division of the N-level battery with an inter-level error of <0.1%. The two ends of the series link are connected to the V+ and V- terminals of the external high voltage source meter, respectively, to achieve equal voltage division.

[0059] The high and low voltage adjustment resistor network consists of N second resistors VI_R1~VI_Rn-1 with resistances exceeding 4KΩ. These second resistors VI_R1~VI_Rn-1 are connected in parallel with the first resistor VI_R0 of the corresponding tester channel VI to achieve independent single-stage voltage adjustment, simulating overvoltage / undervoltage test scenarios. One end of each second resistor is connected in parallel with the two ends of the first resistor VI_R0 of the corresponding core tester channel VI, and the other end is connected to the normally open contact of the corresponding relay, forming a voltage regulation branch.

[0060] The high-current resistance measurement network includes shunt resistors VI_RS1~VI_RSn and power resistors built into the test module. The shunt resistors are connected in series with the corresponding power resistors and then in parallel with the first resistor VI_R0 of the corresponding tester channel VI to provide a high-current background and adapt to the low resistance measurement requirements of R_dson in the equalization mode.

[0061] like Figures 4 to 10 As shown, the precision voltage divider resistor network includes eight 1000Ω, low-temperature drift first resistors VI_R0 with an accuracy of <0.1%; the eight first resistors VI_R0 are connected in series to form an eight-level battery basic precision voltage divider link; the high and low voltage adjustment resistor network consists of eight 5000Ω second resistors VI_R1~VI_R7, which are connected in parallel with the first resistors VI_R0 of the corresponding VI channel of the test machine.

[0062] The high-current resistance measurement network includes shunt resistors VI_RS1~VI_RS8 and power resistors R73~R77 built into the test module; the shunt resistors are connected in series with the corresponding power resistors and then connected in parallel with the first resistor VI_R0 of the corresponding tester channel VI.

[0063] The first resistor is a high-precision, low-temperature drift resistor with a drift rate of <0.1%, and it serves as an independent reference resistor for each VI channel of the tester. The inter-stage voltage divider error is <0.1%. Combined with the single-source meter's same-source power supply, external power frequency interference and power supply noise are interference from the same source and in the same phase. Noise can be self-cancelled within the BMS chip voltage scan cycle, eliminating the need for additional anti-interference circuits and ensuring high-precision testing requirements of <±200uV.

[0064] As an optional solution, the relay drive and control circuit includes N relays, and the control pins of the N relays are VI_FS0~VI_FSn-1 respectively. The control pins VI_FS0~VI_FSn-1 are directly connected to the first pins GPB1_0~GPB1_n-1 through the drive circuit logic to achieve precise independent control of the relays and avoid interference between channels.

[0065] like Figures 4 to 10 As shown, the relay drive and control circuit includes 8 relays, and the control pins of the 8 relays are VI_FS0~VI_FS7 respectively; the control pins VI_FS0~VI_FS7 are connected to the first pins GPB1_0~GPB1_7 respectively.

[0066] The relays and tester VI channels are matched one-to-one, forming N independent control pin-relay-resistor network links. This enables independent switching of the single-channel resistor network, significantly improving testing flexibility. Clearly defining the identification and connection relationships of the relay control pins makes the hardware topology of the control link clearer, reducing signal crossover in circuit design and lowering the probability of hardware failure.

[0067] The control pin is directly connected to the first pin, which shortens the transmission path of the control signal, improves the on / off response speed of the relay, reduces the time for switching test modes, and improves the overall test efficiency.

[0068] As an optional solution, the GPIO control interface also includes second pins GPB2_0~GPB2_n-1, each corresponding to one of the VI channels of the test machine, and third pins GPA1_1~GPA1_n-1, each corresponding to one of the VI channels of the test machine. The second pins GPB2_0~GPB2_n-1 are connected to normally open contacts, and the third pin is adapted to dual-level. The third pins GPA1_1~GPA1_n-1 are connected to the digital pins of the BMS chip for interfacing with the digital signal terminals of the BMS chip. The first, second, and third pins are all reserved for expansion functions to adapt to the digital interface requirements of BMS chips of different specifications.

[0069] like Figures 4 to 10 As shown, the GPIO control interface also includes second pins GPB2_0~GPB2_7, which correspond one-to-one with the VI channels of the test machine, and third pins GPA1_1~GPA1_7, which correspond one-to-one with the VI channels of the test machine.

[0070] The second pin independently controls the normally open contact, separating the control link of the normally closed / normally open relay contacts, avoiding operational interference caused by single-pin control, and improving the accuracy of relay contact switching. The third pin is compatible with 3.3V / 5V dual-level, allowing direct connection to the digital pins of BMS chips with different level standards without the need for additional level conversion circuits, simplifying testing operations and improving the device's compatibility with different BMS chips.

[0071] The second pin, GPB2_0~GPB2_7, is connected to the normally open contact, and the third pin is adapted to 3.3V / 5V dual level. The third pin, GPA1_1~GPA1_7, is connected to the digital pins of the BMS chip to interface with the digital signal terminal of the BMS chip. The first, second, and third pins are all reserved for expansion functions to adapt to the digital interface requirements of BMS chips of different specifications.

[0072] As an optional solution, it also includes: the BMS chip docking circuit is equipped with a dedicated docking socket, which is connected to the Cell pin of the BMS chip and the corresponding VI channel of the test machine; the power supply circuit adopts a three-way independent isolated power supply architecture, namely a high-voltage test power supply for powering the test VI channel, a low-voltage control power supply for powering the GPIO control interface, and a relay drive power supply for powering the relay.

[0073] A dedicated connector enables rapid docking between the BMS chip and the test device, simplifying the testing process while ensuring pin connection accuracy. Three independent isolated power supplies completely eliminate noise crosstalk between different power sources, ensuring test stability and further improving test accuracy. The three power supplies are functionally zoned, each matching the operating voltage / current requirements of different hardware modules, resulting in higher power utilization efficiency and avoiding overload issues caused by a single power supply, thus improving the device's operational reliability.

[0074] As an optional solution, a dedicated connector includes N Cell pins Cell0 to Celln-1, which are connected one-to-one with the VI channels VI_CH0 to VI_CHn-1 of the test machine; each Cell pin is equipped with a current limiting circuit and a filtering circuit.

[0075] like Figure 10 As shown, the dedicated docking socket U128 includes 8 Cell pins Cell0~Cell7, which are connected one-to-one with the VI channels VI_CH0~VI_CH7 of the test machine.

[0076] Additionally, the Cell pins can be configured with current-limiting and filtering circuits. The current-limiting circuit effectively limits the maximum current in the test loop, preventing overcurrent damage to the BMS chip due to abnormal test voltage and ensuring the safety of the chip under test. The filtering circuit removes noise and interference from the test signal, making the voltage / current signal transmitted to the BMS chip cleaner, reducing measurement errors caused by signal interference, and further improving test accuracy.

[0077] As an optional solution, the power supply and grounding circuit also features a layered grounding system with DGND digital ground pins and analog ground pins, where the digital ground and analog ground share a common ground at a single point within the test module.

[0078] In the power supply and grounding circuits, DGND digital ground pins and analog ground pins are set respectively. The digital ground pins provide a grounding terminal for digital circuits such as GPIO control interface, I2C control interface, and relay drive circuit, while the analog ground pins provide a grounding terminal for analog circuits such as the test instrument VI channel, precision resistor network circuit, and BMS chip docking circuit.

[0079] On the hardware circuit board of the test module, a dedicated common ground point is set up. The digital ground pin and the analog ground pin are connected to this common ground point through independent low-impedance wires to realize a single point common ground within the module. When multiple modules are cascaded, the common ground points of all modules are interconnected.

[0080] The separate design of digital and analog grounds effectively prevents switching noise from digital circuits from entering the analog circuit link, reduces distortion of analog test signals, and ensures the accuracy of voltage / current measurements. The single-point common ground design completely eliminates grounding loops on the circuit board, avoids ground bounce interference caused by ground loops, makes the grounding potential more stable, and further improves the anti-interference capability of test signals.

[0081] When multiple modules are cascaded, their common grounding points are interconnected to ensure that the grounding potential of all cascaded modules is consistent, avoiding cascade errors caused by grounding potential differences and ensuring the accuracy and stability of multi-stage battery testing.

[0082] As an optional solution, it also includes an expansion slot interface and a storage module interface. The expansion slot interface is used to connect an external trapezoidal resistor network to adapt to measurement scenarios with higher currents; the storage module interface is used to save the self-calibrated resistance value data.

[0083] This embodiment also provides a test method for a battery management system, applicable to the test apparatus for the battery management system described above, comprising:

[0084] Step S101: Based on the number of battery levels of the BMS chip to be tested, stack the corresponding number of test modules in series, connect the test machine VI channel interface of the test device to an external high-precision source meter, connect the I2C control interface to the host computer, connect the test device to three independent isolated power supplies and complete the power-on initialization.

[0085] Based on different BMS chips and different battery levels (such as 8 levels, 16 levels, 24 levels, etc.), multiple test modules can be connected in series through a cascade mapping interface to quickly adapt to the testing requirements of BMS with different levels.

[0086] In step S102, the host computer sends a calibration command through the I2C control interface, switches the external source meter to forced voltage output mode, and measures the basic circuit current and the circuit current of each branch adjustment resistor and shunt resistor in sequence based on the first resistor of the precision voltage divider resistor network in the test module. The actual resistance value of each resistor is calculated and stored, and the precision resistor network is self-calibrated.

[0087] Before the formal test, the forced voltage output of the source meter, combined with the first resistor of the precision voltage divider network and the low-temperature drift high-precision reference resistor, was used to measure and store the actual resistance values ​​of the adjustment resistors and shunt resistors of each branch.

[0088] In step S103, the host computer independently controls the relay on / off of each tester VI channel through the GPIO control interface, switches the topology of the precision resistor network, and performs resistance measurement tests in voltage measurement mode, overvoltage warning mode, undervoltage warning mode, and equalization mode. In each mode, a single external source meter provides the same test voltage to multiple tester VI channels.

[0089] By controlling the normally closed / normally open contact state of each VI channel relay via GPIO, it is possible to quickly switch between different test modes. Normally closed contact closed: only the first resistor works, used for base voltage measurement; normally open contact closed: the second resistor / shunt resistor is connected in parallel, used for overvoltage / undervoltage warning simulation and equalization mode resistance measurement.

[0090] Step S104: Real-time acquisition of feedback signals and test data from the BMS chip under each test mode; comparison with preset test accuracy thresholds and functional thresholds; determination of whether the various performance parameters of the BMS chip are qualified; and generation of test report.

[0091] Specifically, the voltage measurement mode test includes: Step 1, resistor network reference configuration. The host computer sends a command through the GPIO control interface to control the normally open contacts of the relays of all tester VI channels to remain open and the normally closed contacts to remain closed, so that all channels retain only the low-temperature drift first resistor of the precision voltage divider resistor network to form a series same source voltage divider link. The voltage divider resistor of each tester VI channel is an independent first resistor, ensuring that the inter-stage voltage divider error is <0.1%.

[0092] Step 2: Supply the same source voltage. Adjust the output voltage of the external high-precision source meter. According to the number of battery levels n of the BMS chip under test, make the total voltage difference of the test device meet the single-level battery test voltage Vcell=(V+-V-) / n. Provide accurate same source test voltage for all VI channels through a single source meter to eliminate common-mode error from the hardware level.

[0093] Step 3, ADC voltage scanning and acquisition: Trigger the ADC voltage scanning function inside the BMS chip, so that the BMS chip can acquire the voltage of all Cell pins one by one. The test device synchronously acquires the measured value of each Cell voltage reported by the BMS chip, and utilizes the noise in phase characteristic of the same power supply to achieve noise self-cancellation within the scanning cycle of the BMS chip, without the need for additional anti-interference operation.

[0094] Step 4, Accuracy and Common-Mode Rejection Ratio Verification: Compare the voltage measurement value reported by the BMS chip with the actual nominal value set by the source meter to verify whether the voltage measurement error of each level is ≤ ±200uV; By adjusting the output voltage of the source meter to switch multiple sets of typical Vcell operating points (such as 3.0V, 3.7V, 4.2V), repeat steps 3-4 to verify the ADC measurement accuracy and common-mode rejection ratio of the BMS chip across the entire voltage operating range.

[0095] Step 5 Result Judgment: If the voltage measurement error of all VI channels is ≤±200uV at all voltage operating points, the voltage measurement performance of the BMS chip Vcell is deemed qualified; if the error of any channel or any voltage point exceeds the standard, the performance is deemed unqualified and the faulty channel is recorded.

[0096] The above overvoltage warning mode test includes: controlling the normally open contacts of all VI channels of the test machine to close, so that the second resistor and the first resistor are connected in parallel to form a basic voltage divider network, and setting the external source meter voltage so that the basic voltage of each channel is the nominal value of a fully charged battery; disconnecting the normally open contacts of the target channel one by one, so that the target channel retains only the voltage divider of the first resistor, raising the voltage of the target channel to the overvoltage threshold range, collecting the overvoltage warning signal of the BMS chip, and verifying the overvoltage protection trigger function; if it is necessary to search for the overvoltage threshold, the resistor network configuration remains unchanged, and the external source meter voltage is adjusted to determine the overvoltage threshold.

[0097] The above-mentioned undervoltage warning mode test includes: controlling all normally open contacts of the VI channels of the test machine to open, leaving only the first resistor to form a basic voltage divider network, setting the external source meter voltage so that the basic voltage of each channel is the nominal value of a fully charged battery; closing the normally open contacts of the target channel one by one, so that the second resistor is connected in parallel with the first resistor, reducing the voltage of the target channel to the undervoltage threshold range, collecting the undervoltage warning signal of the BMS chip, and verifying the undervoltage protection trigger function. If it is necessary to search for the undervoltage threshold, the resistor network configuration remains unchanged and the external source meter voltage is adjusted to complete the task.

[0098] The resistance measurement test in the above equalization mode includes: controlling the normally open contacts of all tester VI channels to close, so that the shunt resistor, external power resistor and the first resistor are connected in parallel to form a large current shunt network, and collecting the basic background current of the circuit; controlling the equalization switch of the BMS chip under test to turn on one by one, so that the target channel forms a parallel circuit of the first resistor, shunt resistor, external power resistor and R_dson, collecting the circuit current after turning on, and calculating the actual resistance value of R_dson based on the basic background current, the current after turning on and the source meter output voltage, realizing high-precision measurement of small resistance and avoiding the anti-interference problem of small voltage measurement.

[0099] It should be noted that the term "comprising" and its variations used in the embodiments of the present invention are open-ended, meaning "including but not limited to". The terms "first", "second", etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features.

[0100] The appearance of the term "embodiment" in various places in this specification does not necessarily mean the same embodiment, nor does it imply that it is independent of or alternative to other embodiments. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other.

Claims

1. A testing device for a battery management system, characterized in that, include: At least one test module; The test module includes a multi-level battery management system (BMS) test circuit, which includes a core interface circuit, a precision resistor network circuit, and a relay drive and control circuit. The core interface circuit includes the test machine VI channel interface, I2C control interface, cascaded mapping interface and GPIO control interface; The VI channel interface of the test machine is used to connect the source meter of external test equipment; the I2C control interface is used to communicate with the host computer and the GPIO control interface to send host computer commands to the GPIO control interface for circuit control; the cascade mapping interface is used to connect multiple test modules in series to adapt to BMS testing of batteries with different levels; the GPIO control interface includes a first pin corresponding to the VI channel of the test machine, and the first pin is connected to the relay set on the VI channel of the test machine. The precision resistor network circuit corresponds one-to-one with multiple tester VI channels. The precision resistor network includes a precision voltage divider resistor network, a high and low voltage adjustment resistor network, and a high current measurement resistor network. The precision voltage divider resistor network includes multiple low temperature drift first resistors corresponding to the tester VI channels. The high and low voltage adjustment resistor network consists of multiple second resistors corresponding to the tester VI channels. The high current measurement resistor network includes multiple shunt resistors corresponding to the tester VI channels and external power resistors. The relay drive and control circuit is equipped with multiple relays that correspond one-to-one with the VI channel of the test machine. The relays include normally closed contacts and normally open contacts. The control terminal of the relay is connected to the corresponding first pin. The normally closed contacts are connected in series in the VI channel of the test machine, and the normally open contacts are connected in series with the second resistor and the shunt resistor, and in parallel with the first resistor.

2. The testing apparatus for the battery management system according to claim 1, characterized in that, The test machine VI channel includes M channels from VI_CH0 to VI_CHm-1, N core battery-level test channels from VI_CH0 to VI_CHn-1, and MN extended channels from VI_CHn to VI_CHm-1. The I2C control interface includes an SCK1 clock pin and an SDA1 data pin. It connects to the host computer through the SCK1 clock pin and the SDA1 data pin. The SCK1 clock pin and the SDA1 data pin are also equipped with pull-up resistors. The first pin includes GPB1_0 to GPB1_n-1, which are connected to the control terminal of the corresponding relay.

3. The testing apparatus for the battery management system according to claim 1, characterized in that, The precision voltage divider resistor network includes N low-temperature drift first resistors VI_R0 with a resistance value exceeding 1KΩ and an accuracy of <0.1%; the N first resistors VI_R0 are connected in series to form an N-level battery basic precision voltage divider link; The high and low voltage adjustment resistor network consists of N second resistors VI_R1~VI_Rn-1 with a resistance value exceeding 4KΩ. The second resistors VI_R1~VI_Rn-1 are connected in parallel with the first resistor VI_R0 of the corresponding tester channel VI. The high-current resistance measurement network includes shunt resistors VI_RS1~VI_RSn and power resistors built into the test module; the shunt resistors are connected in series with the corresponding power resistors and then in parallel with the first resistor VI_R0 of the corresponding tester channel VI.

4. The testing apparatus for the battery management system according to claim 1, characterized in that, The relay drive and control circuit includes N relays, and the control pins of the N relays are VI_FS0~VI_FSn-1 respectively; The control pins VI_FS0 to VI_FSn-1 are connected to the first pins GPB1_0 to GPB1_n-1 respectively.

5. The testing apparatus for the battery management system according to claim 1, characterized in that, The GPIO control interface also includes second pins GPB2_0~GPB2_n-1, which correspond one-to-one with the VI channels of the test machine, and third pins GPA1_1~GPA1_n-1, which correspond one-to-one with the VI channels of the test machine. The second pin, GPB2_0 to GPB2_n-1, is connected to the normally open contact, and the third pin is adapted to dual-level. The third pin, GPA1_1 to GPA1_n-1, is connected to the digital pins of the BMS chip and is used to interface with the digital signal terminal of the BMS chip. The first, second, and third pins are all reserved for expansion functions to adapt to the digital interface requirements of BMS chips of different specifications.

6. The testing apparatus for the battery management system according to claim 1, characterized in that, Also includes: The BMS chip interface circuit is equipped with a dedicated interface socket, which connects to the Cell pin of the BMS chip and the corresponding VI channel of the test machine. The power supply circuit adopts a three-way independent power supply architecture. The three independent power supplies are a high-voltage test power supply for powering the test VI channel, a low-voltage control power supply for powering the GPIO control interface, and a relay drive power supply for powering the relay.

7. The testing apparatus for the battery management system according to claim 6, characterized in that, A dedicated docking socket includes N Cell pins Cell0~Celln-1, which are connected one-to-one with the VI channels VI_CH0~VI_CHn-1 of the test machine; Each Cell pin is equipped with a current-limiting circuit and a filtering circuit.

8. The testing apparatus for the battery management system according to claim 6, characterized in that, The power supply and grounding circuit is also equipped with DGND digital ground pins and analog ground pins with layered grounding. The digital ground and analog ground share a common ground at a single point inside the test module.

9. The testing apparatus for the battery management system according to any one of claims 1 to 8, characterized in that, It also includes an expansion slot interface and a storage module interface. The expansion slot interface is used to connect an external ladder resistor network to adapt to measurement scenarios with higher current. The storage module interface is used to save the resistance value data after self-calibration.

10. A test method for a battery management system, characterized in that, A testing apparatus for a battery management system as described in any one of claims 1 to 9, comprising: Based on the number of battery levels of the BMS chip to be tested, a corresponding number of test modules are stacked in series. The VI channel interface of the test device is connected to an external high-precision source meter, and the I2C control interface is connected to the host computer. Three independent isolated power supplies are connected to the test device and the power-on initialization is completed. The host computer sends a calibration command through the I2C control interface, switches the external source meter to forced voltage output mode, and measures the basic circuit current and the circuit current of each branch adjustment resistor and shunt resistor in turn based on the first resistor of the precision voltage divider resistor network in the test module. The actual resistance value of each resistor is calculated and stored, and the precision resistor network is self-calibrated. The host computer independently controls the relay on / off of each tester VI channel through the GPIO control interface, switches the topology of the precision resistor network, and performs resistance measurement tests in voltage measurement mode, overvoltage warning mode, undervoltage warning mode, and equalization mode. In each mode, a single external source meter provides the same test voltage to multiple tester VI channels. The system collects feedback signals and test data from the BMS chip in real time under various test modes, compares them with preset test accuracy thresholds and functional thresholds, determines whether the various performance parameters of the BMS chip are qualified, and generates a test report.

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