Display device, display panel and manufacturing method thereof

Abstract

A display device, a display panel and a manufacturing method thereof. The display panel comprises a substrate (SU), a driving layer (PN) and a light-emitting layer (OL). The driving layer is arranged on the substrate and comprises a plurality of circuit units (CU), a row wire bundle (LR) and a column wire bundle (LC). The circuit unit comprises a plurality of pixel circuits (PC). The row wire bundle comprises a row wire (LRa). The column wire bundle comprises a column wire (LCa). Circuit units in the same row are connected by a row wire bundle. Circuit units in the same column are connected by a column wire bundle. The orthogonal projection of the row wire bundle and the column wire bundle on the substrate separates a plurality of transparent regions (TRE). The region of the driving layer corresponding to the transparent region is a transparent structure. The light-emitting layer is arranged on the driving layer and comprises a plurality of device units (DC) arranged in an array and corresponding to the transparent regions. The device unit comprises a plurality of light-emitting devices (OLED). The light-emitting device comprises a first electrode (ANO), a light-emitting functional layer (EL) and a second electrode (CAT). The first electrode and the second electrode are transparent structures.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device, a display panel, and a method for manufacturing the display panel. Background Technology

[0002] Organic electroluminescent displays have gained widespread application due to their advantages such as low driving voltage, high luminous efficiency, short response time, and high contrast. Dual-sided displays are a hot research topic. Currently, dual-sided displays are typically achieved by bonding two display panels together, but this increases the thickness and weight of the display device.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a display device, a display panel, and a method for manufacturing the display panel.

[0005] According to one aspect of this disclosure, a display panel is provided, comprising:

[0006] Substrate;

[0007] A driving layer, disposed on one side of the substrate, includes an array of multiple circuit units, multiple routing bundles, and multiple column routing bundles. Each circuit unit includes multiple pixel circuits. Each routing bundle includes multiple routing lines spaced apart along the column direction, and each column routing bundle includes multiple column routing lines spaced apart along the row direction. Circuit units in the same row are connected by a routing bundle, and circuit units in the same column are connected by a column routing bundle. The orthographic projections of the routing bundles and column routing bundles on the substrate intersect to separate multiple transparent regions. The region of the driving layer corresponding to the transparent regions is a transparent structure.

[0008] A light-emitting layer is disposed on the surface of the driving layer away from the substrate, and includes a plurality of device units arranged in an array, the device units corresponding to the transparent area; the device unit includes a plurality of light-emitting devices arranged at intervals, each light-emitting device being connected to a pixel circuit; the light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode stacked sequentially in the direction away from the substrate, the first electrode and the second electrode being transparent structures.

[0009] In one exemplary embodiment of this disclosure, the light-emitting layer further includes a pixel definition layer separating each of the light-emitting devices, the pixel definition layer having an opening defining each of the light-emitting devices;

[0010] The walking wire harness is recessed in the region between two adjacent circuit units to form a row of recesses, the orthographic projection of the row of recesses on the substrate being at least a part of the transparent area; the orthographic projection of one of the openings on the substrate and the orthographic projection of one of the row of recesses on the substrate may at most partially overlap.

[0011] In one exemplary embodiment of this disclosure, the light-emitting layer further includes a pixel definition layer separating each of the light-emitting devices, the pixel definition layer having an opening defining each of the light-emitting devices;

[0012] The column wiring harness is recessed in the region between two adjacent circuit units to form a column recess, and the orthographic projection of the column recess on the substrate is at least a part of the transparent area; the orthographic projection of an opening on the substrate and the orthographic projection of a column recess on the substrate may partially overlap.

[0013] In one exemplary embodiment of this disclosure, the light-emitting layer further includes a pixel definition layer separating each of the light-emitting devices, the pixel definition layer having an opening defining each of the light-emitting devices;

[0014] The walking wire harness is recessed in opposite directions in the area between two adjacent circuit units to form a row of recesses. The orthographic projection of the row of recesses on the substrate is at least a part of the transparent area. The orthographic projection of one of the openings on the substrate and the orthographic projection of one of the row of recesses on the substrate may coincide in at most parts.

[0015] The column wiring harness is recessed in the region between two adjacent circuit units to form a column recess, and the orthographic projection of the column recess on the substrate is at least a part of the transparent area; the orthographic projection of an opening on the substrate and the orthographic projection of a column recess on the substrate may partially coincide.

[0016] In one exemplary embodiment of this disclosure, the same device unit includes three light-emitting devices with different emitting colors, and the first electrodes of the three light-emitting devices are of different sizes.

[0017] In one exemplary embodiment of this disclosure, the light-emitting devices of the same device unit include a first light-emitting device that emits green light, a second light-emitting device that emits red light, and a third light-emitting device that emits blue light;

[0018] The area of ​​the first electrode of the third light-emitting device is larger than the area of ​​the first electrode of the first light-emitting device, and the area of ​​the first electrode of the first light-emitting device is larger than the area of ​​the first electrode of the second light-emitting device.

[0019] In one exemplary embodiment of this disclosure, the orthographic projection of the opening corresponding to the first light-emitting device on the substrate coincides with the orthographic projection of the column of recesses on the substrate in at most a portion.

[0020] The orthographic projection of the opening corresponding to the second light-emitting device on the substrate coincides with the orthographic projection of one of the row recesses on the substrate in most parts.

[0021] The orthographic projection of the opening corresponding to the third light-emitting device on the substrate coincides with the orthographic projection of the row recess on the substrate in at most a portion, and also coincides with the orthographic projection of the column recess on the substrate in at most a portion.

[0022] In one exemplary embodiment of this disclosure, in the first electrode of the device unit corresponding to the same transparent region, at least one of the first electrodes has its orthographic projection on the substrate coincides with the orthographic projection of a routing harness on the substrate; at least one of the first electrodes has its orthographic projection on the substrate coincides with the orthographic projection of a routing harness on the substrate.

[0023] In one exemplary embodiment of this disclosure, in the orthographic projection of the transparent region and its corresponding device unit onto the substrate:

[0024] The transparent area includes a first sub-area and a second sub-area. The first sub-area extends along a first direction different from the row direction and the column direction. The second sub-area is located on one side of the first sub-area and extends along a second direction intersecting the first direction to connect with the first sub-area. The second direction is different from the row direction and the column direction.

[0025] The first electrode of the first light-emitting device and the first electrode of the second light-emitting device are projected onto the driving layer on the same side of the first sub-region and distributed on both sides of the second sub-region along the first direction; the first electrode of the third light-emitting device is projected onto the driving layer on the side of the first sub-region away from the second sub-region.

[0026] In one exemplary embodiment of this disclosure, the wiring harness includes a plurality of wiring lines, and the wiring lines include scan lines;

[0027] The column wiring harness includes multiple column wirings, and the column wirings include data lines.

[0028] In one exemplary embodiment of this disclosure, the pixel circuits connected to different light-emitting devices of the same device unit are located in different circuit units.

[0029] In one exemplary embodiment of this disclosure, pixel circuits connected to different light-emitting devices of the same device unit are located in the same row of circuit units.

[0030] In one exemplary embodiment of this disclosure, the first electrode of each light-emitting device in any of the device units is connected to a pixel circuit via a connection portion;

[0031] The first electrode of the first light-emitting device is connected to a pixel circuit through a first connection portion; the first electrode of the second light-emitting device is connected to a pixel circuit through a second connection portion; and the first electrode of the third light-emitting device is connected to a pixel circuit through a third connection portion.

[0032] The pixel circuits connected to the first connecting part and the second connecting part are located in the same circuit unit, and the pixel circuits connected to the third connecting part are located in different circuit units in the same row;

[0033] The length of the first connecting part in its extending direction is less than the length of the second connecting part in its extending direction, and the length of the second connecting part in its extending direction is less than the length of the third connecting part in its extending direction.

[0034] In one exemplary embodiment of this disclosure, the driver layer includes:

[0035] An active layer is disposed on one side of the substrate;

[0036] A first gate insulating layer covers the active layer and the substrate;

[0037] A gate is disposed on the surface of the first gate insulating layer opposite to the substrate;

[0038] A second gate insulating layer covers the gate and the first gate insulating layer;

[0039] An interlayer dielectric layer covers the second gate insulating layer;

[0040] A source / drain layer is disposed on the surface of the interlayer dielectric layer opposite to the substrate;

[0041] A planarization layer covering the source / drain layer and the interlayer dielectric layer;

[0042] The display panel also includes:

[0043] An encapsulation layer that covers the light-emitting layer;

[0044] A touch layer is disposed on the surface of the encapsulation layer opposite to the substrate.

[0045] In one exemplary embodiment of this disclosure, the first electrode includes a first transparent conductive layer, a conductive metal layer, and a second transparent conductive layer sequentially stacked in a direction away from the substrate, wherein the resistivity of the conductive metal layer is less than the resistivity of the first transparent conductive layer and the second transparent conductive layer.

[0046] The thickness of the conductive metal layer is not less than 200 Å and not more than 300 Å.

[0047] In one exemplary embodiment of this disclosure, the thickness of both the first transparent conductive layer and the second transparent conductive layer is not less than 80 Å and not greater than 100 Å.

[0048] In one exemplary embodiment of this disclosure, the thickness of the second electrode is not less than 13 nm and not more than 15 nm.

[0049] According to one aspect of this disclosure, a method for manufacturing a display panel is provided, comprising:

[0050] A driving layer is formed on one side of the substrate. The driving layer includes multiple circuit units, multiple routing bundles, and multiple column routing bundles arranged in an array. Each circuit unit includes multiple pixel circuits. Each routing bundle includes multiple routing lines spaced apart along the column direction, and each column routing bundle includes multiple column routing lines spaced apart along the row direction. Circuit units in the same row are connected by a routing bundle, and circuit units in the same column are connected by a column routing bundle. The orthographic projections of the routing bundles and the column routing bundles on the substrate intersect to separate multiple transparent regions. The region of the driving layer corresponding to the transparent regions is a transparent structure.

[0051] A light-emitting layer comprising an array of multiple device units is formed on the surface of the driving layer facing away from the substrate. The device units correspond to the transparent area. Each device unit includes multiple spaced-apart light-emitting devices, and each light-emitting device is connected to a pixel circuit. Each light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially in the direction facing away from the substrate. The first electrode and the second electrode are transparent structures.

[0052] According to one aspect of this disclosure, a display device is provided, comprising the display panel described in any of the preceding claims.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0055] Figure 1This is a cross-sectional view of one embodiment of the display panel of this disclosure.

[0056] Figure 2 This is a schematic diagram of the pixel circuit in one embodiment of the display panel of this disclosure.

[0057] Figure 3 This is a layout of the pixel circuitry in one embodiment of the display panel of this disclosure.

[0058] Figure 4 This is a layout of the pixel circuit and the first electrode in one embodiment of the display panel of this disclosure.

[0059] Figures 5-8 These are partial top views of a portion of the film layer of a pixel circuit in one embodiment of the display panel of this disclosure.

[0060] Figure 9 This is a partial schematic diagram of the driving layer in one embodiment of the display panel of this disclosure.

[0061] Figure 10 This is a partial schematic diagram of the driving layer and opening of one embodiment of the display panel of this disclosure.

[0062] Figure 11 This is a partial schematic diagram of the driving layer, opening, and first electrode of one embodiment of the display panel of this disclosure.

[0063] Figure 12 This is a partial schematic diagram showing the connection between the first electrode and the pixel circuit in one embodiment of the display panel of this disclosure.

[0064] Figure 13 This is a partial schematic diagram of the driving layer, opening, first electrode, and second electrode of one embodiment of the display panel of this disclosure.

[0065] Figure 14-17 These are partial top views of some film layers in one embodiment of the display panel of this disclosure.

[0066] Figure 18 This is a graph showing the test results of the thickness of the first electrode and the light transmittance of the display panel in one embodiment of the present disclosure. Detailed Implementation

[0067] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0068] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0069] A transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region is the area through which the current primarily flows.

[0070] The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0071] In this document, "row direction" and "column direction" refer to two intersecting directions. For example, the row direction can be the horizontal direction as shown in the attached diagram, and the column direction can be the vertical direction as shown in the attached diagram, with the two being perpendicular to each other. However, this should not be considered a limitation on the row and column directions; the row direction is not necessarily horizontal, and the column direction is not necessarily vertical. Those skilled in the art will understand that if the display panel undergoes positional changes such as rotation, the actual orientation of the row and column directions can change.

[0072] This disclosure provides a display panel, such as... Figure 1 As shown, the display panel may include a substrate SU, a driving layer PN, and a light-emitting layer OL, wherein:

[0073] The driving layer PN is disposed on one side of the substrate SU and includes multiple circuit units CU, multiple routing bundles LR, and multiple column routing bundles LC arranged in an array. The circuit unit CU includes multiple pixel circuits PC, the routing bundle LR includes multiple routing lines spaced apart along the column direction Y, and the column routing bundle LC includes column routing lines spaced apart along the row direction X. The circuit units CU in the same row are connected by a routing bundle LR, and the circuit units CU in the same column are connected by a column routing bundle LC. The orthographic projections of the routing bundle LR and the column routing bundle LC on the substrate SU intersect to separate multiple transparent regions TRA. The area of ​​the driving layer PN corresponding to the transparent region TRA is a transparent structure.

[0074] The light-emitting layer OL is disposed on the surface of the driving layer PN away from the substrate SU, and includes multiple device units DC arranged in an array, with each device unit DC corresponding to the transparent region TRA; each device unit DC includes multiple light-emitting devices OLED arranged at intervals, and each light-emitting device OLED is connected to a pixel circuit PC; each light-emitting device OLED includes a first electrode ANO, a light-emitting functional layer EL, and a second electrode CAT stacked sequentially in the direction away from the substrate SU, with the first electrode ANO and the second electrode CAT being transparent structures.

[0075] The display panel of this embodiment can have both the first electrode ANO and the second electrode CAT of the light-emitting device OLED set to a transparent structure, so that the light-emitting device OLED can emit light in both directions, thereby realizing double-sided display; wherein, the light-emitting device OLED can emit light in the direction away from the substrate SU for front display, and the light-emitting device OLED can emit light in the direction closer to the substrate SU for back display.

[0076] Meanwhile, since both the first electrode ANO and the second electrode CAT are transparent structures, and the area of ​​the driving layer PN corresponding to the transparent area TRA is also transparent, the display panel has a transparent effect.

[0077] In addition, the pixel circuit PC and the light-emitting device OLED can be distributed according to the circuit unit CU and the device unit DC, and the device unit DC is set to correspond to the transparent area TRA. This can reduce or avoid the light-emitting device OLED being blocked by the pixel circuit PC, the walking wire harness LR and the column walking wire harness LC, thereby improving the brightness of back-emitting light, reducing the brightness difference with front-emitting light, and thus improving the transparency effect.

[0078] The basic structure of the display panel according to the present disclosure will be described in detail below:

[0079] The display panel can be used for bidirectional light emission, i.e., front and rear display, and can achieve transparent display. The display panel may include a substrate SU, a driving layer PN, and a light-emitting layer OL, wherein:

[0080] like Figure 1 As shown, the substrate SU can be a flat plate that serves as a load-bearing element, and its shape can be rectangular or other shapes. The material of the substrate SU can include transparent rigid materials such as glass, or flexible materials such as polyimide (PI). The substrate SU can be a single-layer or multi-layer structure, without special limitations.

[0081] like Figure 1As shown, the driving layer PN can be directly stacked on one side of the substrate SU; alternatively, to prevent impurities in the substrate SU from affecting the driving layer PN, a buffer layer can be provided between the substrate SU and the driving layer PN, with the driving layer PN located on the surface of the buffer layer facing away from the substrate SU. The driving layer PN, the substrate SU, and the film layer between them can form a driving backplate. The driving layer PN includes at least a driving region and a peripheral region. The peripheral region can be an annular region surrounding the driving region or two discontinuous regions separated on both sides of the driving region, as long as it is located outside the driving region.

[0082] The driving layer PN has a driving circuit for driving the light-emitting devices (OLEDs) of the light-emitting layer OL to emit light. The driving circuit may include multiple pixel circuits PCs and peripheral circuits. The pixel circuits PCs are located within the driving area; however, some areas of the pixel circuits PCs may be located in the peripheral area. The number of pixel circuits PCs can be the same as the number of OLEDs, and they are connected one-to-one with each OLED to control independent light emission from each OLED. Alternatively, multiple OLEDs can be connected to the same pixel circuit PC to drive multiple OLEDs to emit light. The peripheral circuits are located in the peripheral area and connected to the pixel circuits PCs. They are used to input driving signals to the pixel circuits PCs to control the OLEDs to emit light. The peripheral circuits may include light-emitting control circuits, gate driving circuits, source driving circuits, and power supply circuits, etc.

[0083] The pixel circuit PC can be a 7T1C, 7T2C, 6T1C, or 6T2C structure, as long as it can drive the OLED light-emitting device to emit light; no special restrictions are placed on its structure here. Here, nTmC indicates that one pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). Of course, one pixel circuit PC can also connect to multiple OLED light-emitting devices simultaneously, driving multiple OLED light-emitting devices to emit light simultaneously or in a time-division manner.

[0084] The following example, using a 7T1C pixel circuit PC, illustrates the structure and driving method of the pixel circuit PC:

[0085] like Figure 2 As shown, the pixel circuit PC may include seven transistors and a storage capacitor, namely, driving transistor DT, first transistors T1 to sixth transistors T6, and storage capacitor Cst, wherein:

[0086] The control terminal of the first transistor T1 can be used to receive the write control signal Scan, the first terminal is used to receive the data signal Vdata, and the second terminal is connected to the first terminal of the driving transistor DT.

[0087] The control terminal of the second transistor T2 is used to receive the write control signal Scan. The first terminal is connected to the second terminal of the driving transistor DT, and the second terminal is connected to the control terminal of the driving transistor DT.

[0088] The control terminal of the third transistor T3 is used to receive the light emission control signal EM, the first terminal is used to receive the first power supply signal VDD, and the second terminal is connected to the first terminal of the driving transistor DT.

[0089] The control terminal of the fourth transistor T4 is used to receive the first reset control signal Reset1, the first terminal is used to receive the first reset signal Vinit1, and the second terminal is connected to the control terminal of the driving transistor DT.

[0090] The control terminal of the fifth transistor T5 is used to receive the second reset control signal Reset2, the first terminal is used to receive the second reset signal Vinit2, and the second terminal is connected to the first terminal of the light-emitting device OLED.

[0091] The control terminal of the sixth transistor T6 is used to receive the light emission control signal EM. The first terminal is connected to the second terminal of the driving transistor DT, and the second terminal is connected to the first terminal of the light-emitting device OLED. The second terminal of the light-emitting device OLED is used to receive the second power supply signal VSS.

[0092] The first plate of the storage capacitor Cst is connected to the first terminal of the third transistor T3 for inputting the first power supply signal VDD, and the second plate is connected to the control terminal of the driving transistor DT.

[0093] The aforementioned driving transistor DT and transistors T1 through T6 are all P-type thin-film transistors; the first power supply signal VDD is a high-level signal, and the second power supply signal VSS is a low-level signal; the light-emitting device OLED is an organic light-emitting diode, with its first terminal being the anode and its second terminal being the cathode. Driving transistor DT and transistors T1 through T6 are all turned on when the voltage is low and turned off when the voltage is high.

[0094] The aforementioned driving method for the pixel circuit PC may include:

[0095] During the reset phase: a first reset signal Reset1 is transmitted to the control terminal of the fourth transistor T4, and a second reset signal Reset2 is transmitted to the control terminal of the fifth transistor T5 to turn on the fourth transistor T4 and the fifth transistor T5; simultaneously, the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned off. The first reset signal Vinit1 is transmitted to the control terminal of the driving transistor DT through the fourth transistor T4, and the second reset signal Vinit2 is transmitted to the first terminal of the OLED light-emitting device through the fifth transistor T5. The first reset signal Vinit1 and the second reset signal Vinit2 can be signals with the same voltage.

[0096] During the data writing phase: the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off, so that the data signal Vdata is transmitted to the control terminal of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2.

[0097] During the light-emitting stage: the light-emitting control signal EM is transmitted to the control terminals of the third transistor T3 and the sixth transistor T6, turning on the third transistor T3 and the sixth transistor T6; at the same time, the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off, so as to transmit the signal at the second terminal of the driving transistor DT to the first terminal of the light-emitting device OLED, so as to control the light-emitting device OLED to emit light.

[0098] The thin-film transistors in the aforementioned driving circuit layer can be top-gate or bottom-gate thin-film transistors. Each thin-film transistor can include an active layer ACT, a gate Ga, a source, and a drain. The gate Ga can be a dual-gate structure, a single-gate structure, or other structures. The active layers ACT, gate Ga, source, and drain of each thin-film transistor are arranged in the same layer, which simplifies the process.

[0099] The following example, using a top-gate thin-film transistor in a pixel circuit PC, illustrates the structure of the driving layer PN:

[0100] like Figure 1 As shown, the driving layer PN may include an active layer ACT, a first gate insulating layer GI1, a gate Ga, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a source / drain layer SD, and a planarization layer PLN, wherein:

[0101] An active layer ACT is disposed on one side of the substrate SU. A first gate insulating layer GI1 covers the active layer ACT and the substrate SU. A gate electrode Ga is disposed on the surface of the first gate insulating layer GI1 facing away from the substrate SU and directly opposite the active layer ACT. A second gate insulating layer GI2 covers the gate electrode Ga and the first gate insulating layer GI1. An interlayer dielectric layer ILD covers the second gate insulating layer GI2. A source / drain layer SD is disposed on the surface of the interlayer dielectric layer ILD facing away from the substrate SU and includes a source and a drain electrode, which are connected to the two ends of the active layer ACT through contact holes. A planarization layer PLN covers the source / drain layer SD and the interlayer dielectric layer ILD. Of course, the driving circuit layer may also include other film layers, as long as they can drive the OLED light-emitting device to emit light, which will not be described in detail here.

[0102] In addition, the driving layer PN may also include a first plate Cst1 and a second plate Cst2 of the storage capacitor Cst. The first plate Cst1 may be disposed in the same layer as the gate Ga, and the second plate Cst2 may be disposed on the surface of the second gate insulating layer GI2 away from the substrate SU and opposite to the first plate Cst1. The interlayer dielectric layer ILD covers the second plate Cst2.

[0103] The following is a combination Figures 3-8 ,right Figure 2 The layout of the 7T1C pixel circuit PC is illustrated by example:

[0104] like Figures 3-8 As shown, the driving layer PN may include a semiconductor layer 001, a first conductive layer 002, a second conductive layer 003, and a third conductive layer 004, wherein:

[0105] like Figure 3 and Figure 5 As shown, semiconductor layer 001 includes an active layer ACT of each transistor (driving transistor DT, first transistor T1 to sixth transistor T6).

[0106] like Figure 3 and Figure 6 As shown, the first conductive layer 002 includes the gate of each transistor, scan line GAL, light emission control line EML, first reset line REL1, second reset line REL2, and the first plate Cst1 of the storage capacitor Cst, which may be located in the first conductive layer 002, wherein:

[0107] The scan line GAL extends along the row direction X and overlaps with the active layer ACT of the first transistor T1 and the second transistor T2. The overlapping area is the gate of the first transistor T1 and the second transistor T2. The scan line GAL can input the write control signal Scan to the first transistor T1 and the second transistor T2.

[0108] The light emission control line EML can extend along the row direction X and overlap with the active layer ACT of the third transistor T3 and the sixth transistor T6. The overlapping area is the gate of the third transistor T3 and the sixth transistor T6. The light emission control signal EM can be input to the third transistor T3 and the sixth transistor T6 through the light emission control line EML.

[0109] The first reset line REL1 can extend along the row direction X and overlap with the active layer ACT of the fourth transistor T4. The overlapping area is the gate of the fourth transistor T4. The first reset control signal Reset1 can be input to the fourth transistor T4 through the first reset line REL1 to turn on the fourth transistor T4.

[0110] The second reset line REL2 can extend along the row direction X and overlap with the active layer ACT of the fifth transistor T5. The overlapping area is the gate of the fifth transistor T5. The second reset control signal Reset2 can be input to the fifth transistor T5 through the second reset line REL2 to turn on the fifth transistor T5. The first reset control signal Reset1 and the second reset control signal Reset2 can be transmitted simultaneously or at different times.

[0111] The first plate Cst1 of the storage capacitor Cst is reused as the gate of the driving transistor DT, thereby connecting the first plate Cst1 to the gate of the driving transistor DT.

[0112] like Figure 3 and Figure 7 As shown, the second conductive layer 003 may include a first reset signal line VIL1, a second reset signal line VIL2, and a second electrode Cst2 of the storage capacitor Cst, wherein:

[0113] The first reset signal line VIL1 and the second reset signal line VIL2 can extend along the row direction X. The first reset signal line VIL1 is used to transmit the first reset signal Vinit1 to the fourth transistor T4, and the second reset signal line VIL2 is used to transmit the second reset signal Vinit2 to the fifth transistor T5.

[0114] The second electrode Cst2 is positioned opposite the first electrode Cst1, meaning that their orthogonal projections on the substrate SU at least partially overlap, in order to form a storage capacitor Cst.

[0115] like Figure 3 and Figure 8 As shown, the third conductive layer 004 may include a data line DAL, a power line VDL, and spaced-apart first conductive portions SD1, second conductive portions SD2, third conductive portions SD3, and fourth conductive portions SD4, wherein:

[0116] The first conductive part SD1 can be connected to the first reset signal line VIL1 and the fourth transistor T4; the second conductive part SD2 can be connected to the fourth transistor T4, the driving transistor DT, and the storage capacitor Cst; the third conductive part SD3 can be connected to the second reset signal line VIL2 and the fifth transistor T5; the fourth conductive part SD4 can be connected to the sixth transistor T6 for connection to the first electrode ANO of an OLED light-emitting device, such as... Figure 4 As shown.

[0117] like Figure 3 and Figure 7 As shown, in order to ensure that the second transistor T2 and the fourth transistor T4 can be connected to the first plate Cst1 of the storage capacitor Cst and the gate of the driving transistor DT, a through hole H can be formed in the second substrate Cst2. The second conductive part S2 is used to connect the second transistor T2 and the fourth transistor T4 to the first plate Cst1 and the gate of the driving transistor DT through the contact hole passing through the through hole H.

[0118] The data line DAL and the power line VDL can extend along the column direction Y and be spaced apart along the row direction X. The data line DAL can be connected to the first transistor T1; the power line VDL can be connected to the third transistor T3 and the second plate Cst2 to transmit the first power signal VDD.

[0119] like Figure 9 As shown, for the entire driving layer PN, the pixel circuit PC array is distributed such that pixel circuit PCs in the same row can share the first reset signal line VIL1, the second reset signal line VIL2, the light emission control line EML, and the scan line GAL extending along the row direction X. Pixel circuit PCs in the same column can share the data line DAL and the power line VDL. Of course, there can also be shared traces between different rows and different columns.

[0120] like Figure 1 As shown, the light-emitting layer OL is disposed on one side of the driving layer PN. For example, the light-emitting layer OL is disposed on the surface of the planarization layer PLN facing away from the substrate SU. The light-emitting layer OL may include multiple arrayed light-emitting devices OLED, each of which can emit light under the drive of the pixel circuit PC.

[0121] In some embodiments of this disclosure, the light-emitting device OLED is an organic light-emitting diode, which may include a first electrode ANO, a light-emitting functional layer EL, and a second electrode CAT sequentially stacked along a direction away from the substrate SU, wherein:

[0122] The first electrode ANO can be disposed on the surface of the planarization layer PLN facing away from the substrate SU, and connected to a pixel circuit PC through a contact hole. For example, Figure 2 and Figure 4 As shown, the first electrode ANO can be connected to the sixth transistor T6.

[0123] like Figure 4 As shown, in some embodiments of this disclosure, the first electrode ANO can be connected to the pixel circuit PC through a connecting part C. The connecting part C and the first electrode ANO are an integral structure. The connecting part C can extend outward from the edge of the first electrode ANO along a straight line, curve, or broken line, as long as it can extend above the pixel circuit PC and be connected to the pixel circuit PC through a contact hole. For example, one end of the connecting part C is connected to the first electrode ANO, and the other end is connected to the sixth transistor T6 through a contact hole.

[0124] The first electrode ANO can be a single-layer or multi-layer structure, and it can serve as the anode of an OLED light-emitting device. For example, such as Figure 1 As shown, the first electrode ANO may include a first transparent conductive layer TA1, a conductive metal layer MET, and a second transparent conductive layer TA2, sequentially stacked in a direction away from the substrate SU. The resistivity of the conductive metal layer MET is less than the resistivity of the first transparent conductive layer TA1 and the second transparent conductive layer TA2. For example, the materials of the first transparent conductive layer TA1 and the second transparent conductive layer TA2 may be transparent conductive materials such as indium tin oxide (ITO), and the material of the conductive metal layer MET may be silver (Ag) or the like.

[0125] like Figure 1 As shown, the light-emitting functional layer EL is disposed on the surface of the first electrode ANO away from the substrate SU, and may include a hole injection layer, a hole transport layer, a composite light-emitting layer OL, an electron transport layer and an electron injection layer stacked sequentially along the direction away from the substrate SU. In addition, an electron blocking layer may be disposed between the hole transport layer and the composite light-emitting layer OL.

[0126] like Figure 1 As shown, the second electrode CAT covers the light-emitting functional layer EL and can extend to the peripheral area. The second electrode CAT can be connected to the power signal terminal to receive the second power signal VSS. The first electrode ANO and the second electrode CAT work together to make the light-emitting device OLED emit light. The specific light-emitting principle of organic light-emitting diodes will not be detailed here. The material of the second electrode CAT can be magnesium (Mg), silver alloy, or other materials.

[0127] like Figure 1As shown, to facilitate defining the extent of each OLED light-emitting device, the light-emitting layer OL may further include a pixel definition layer PDL, which is disposed on the surface of the driving layer PN away from the substrate SU, along with the first electrode ANO. PDL has multiple openings APE that expose each first electrode ANO in a one-to-one correspondence. The shape of the openings APE can be a polygon such as a quadrilateral, pentagon, or hexagon, or a circle or ellipse; no specific shape is specified here. The light-emitting functional layers EL are stacked on the area of ​​the first electrode ANO located within the openings APE. The light-emitting functional layers EL of each OLED are independently spaced. The emission colors of different light-emitting functional layers EL can be the same or different. The second electrode CAT simultaneously covers each light-emitting functional layer EL, allowing each OLED to share the same second electrode CAT. The multiple openings APE define each OLED, and the boundary of any OLED is the boundary of its corresponding opening APE.

[0128] like Figure 4 As shown, the pixel definition layer PDL can cover the connection part C, so that the light-emitting functional layer EL is not superimposed on the connection part C, and the connection part C does not emit light. This avoids the problem that the contact hole position cannot emit light and the light-emitting area is reduced when the first electrode ANO is directly connected to the pixel circuit PC without using the connection part C.

[0129] OLEDs include various types of OLEDs that emit different colors of light, such as ROLED (red light), GOLED (green light), and BOLED (blue light).

[0130] like Figure 1 As shown, in some embodiments of this disclosure, the display panel may further include a TFE encapsulation layer, which may cover the surface of the light-emitting layer OL facing away from the substrate SU and cover all light-emitting devices OLED, thereby protecting the light-emitting layer OL and preventing external water and oxygen from corroding the light-emitting devices OLED. At the same time, the boundary of the TFE encapsulation layer extends into the peripheral area but does not exceed the peripheral area, which can also protect the peripheral circuits of the peripheral area.

[0131] For example, thin-film encapsulation (TFE) can be used to achieve encapsulation. The encapsulation layer TFE may include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers the surface of the light-emitting layer OL away from the substrate SU. The organic layer may be disposed on the surface of the first inorganic layer away from the substrate SU, and the boundary of the organic layer is defined inside the boundary of the first inorganic layer. The second inorganic layer covers the organic layer and the first inorganic layer that is not covered by the organic layer. The second inorganic layer can block the intrusion of water and oxygen, and the flexible organic layer can achieve planarization.

[0132] like Figure 1 As shown, in some embodiments of this disclosure, the display panel may further include a touch layer TSP, which may be disposed on the surface of the encapsulation layer TFE away from the substrate SU, and can be used in the manner of FMLOC (Flexible Multi-Layer On Cell) for sensing touch operations. The touch layer TSP may adopt a self-capacitive or mutual-capacitive touch structure, and its specific structure is not particularly limited here, as long as it can realize the touch function.

[0133] In addition, such as Figure 1 As shown, in some embodiments of this disclosure, the display panel may further include a transparent cover plate (COV), which may be disposed on the surface of the touch layer TSP facing away from the substrate SU, serving a protective function. When performing touch operations, the user can touch the transparent cover plate (COV). The transparent cover plate (COV) can be bonded to the surface of the touch layer TSP facing away from the substrate SU using optical adhesive or other adhesives. The transparent cover plate (COV) can be UTG (Ultra Thin Glass) or other transparent film layers, as long as it serves both protective and light-transmitting functions.

[0134] It should be noted that, in order to ensure the effect of transparent display, the touch layer TSP and the transparent cover COV of this disclosure are stacked sequentially on the encapsulation layer TFE, without setting a circular polarizing layer.

[0135] The following detailed explanation of the methods for improving light transmittance, in conjunction with the above-described implementation methods, is provided:

[0136] like Figures 9-12 As shown, to improve transmittance, the distribution of the pixel circuit PC and the light-emitting device OLED can be adjusted. The pixel circuit PC can be divided into multiple circuit units CU, and each circuit unit CU can include multiple pixel circuit PCs. Each circuit unit CU can be arranged in an array along the row direction X and the column direction Y, with a certain distance between adjacent circuit units CU. Simultaneously, the light-emitting device OLED can be divided into multiple device units DC, and each device unit DC can be arranged in an array along the row direction X and the column direction Y, with a certain distance between adjacent device units DC. Within the same circuit unit CU, the pixel circuit PCs can be distributed at intervals along the row direction X; the distance between two adjacent circuit units CU is greater than the distance between two adjacent pixel circuit PCs within the same circuit unit CU.

[0137] like Figure 11As shown, each device unit DC may include multiple light-emitting devices (OLEDs). Placing each device unit DC in an area outside the corresponding circuit unit CU can reduce the occlusion of the light-emitting devices OLED by the pixel circuit PC, which is beneficial to improving the rear display effect. That is, the orthogonal projection of the device unit DC on the substrate SU is at least partially located outside the orthogonal projection of the circuit unit CU on the substrate SU.

[0138] like Figures 9-12 As shown, the orthographic projections of the LR routing harness and the LC routing harness on the substrate SU intersect, together with the circuit unit CU, separating multiple transparent regions TRA. The driving layer PN has a transparent structure corresponding to the transparent regions TRA. In each device unit DC, one device unit DC is correspondingly set with one transparent region TRA, that is, the orthographic projection of one device unit DC on the driving backplate at least partially coincides with one transparent region TRA. In the direction perpendicular to the substrate SU, the device unit DC and the circuit unit CU can be staggered, and the device unit DC is also staggered with the LR routing harness and the LC routing harness, reducing the occlusion of the pixel circuit PC on the light-emitting device OLED, which is beneficial to improving the brightness of the back display.

[0139] The area of ​​the display panel corresponding to the transparent area TRA does not have pixel circuit PC and traces. This is equivalent to removing conductive materials that easily block light, resulting in higher light transmittance in this area. For example, the area of ​​the driving layer PN corresponding to the transparent area TRA may include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a planarization layer PLN, a pixel definition layer PDL, etc., which are stacked together.

[0140] like Figures 9-12 As shown, based on the above concept, in detail, the drive layer PN may also include multiple routing harnesses LR and multiple column routing harnesses LC, wherein:

[0141] The travel harness LR can extend along the row direction X and be distributed at intervals along the column direction Y, and a travel harness LR can include multiple travel lines distributed at intervals along the column direction Y.

[0142] A column wiring harness (LC) can extend along the column direction Y and be spaced along the row direction X. A column wiring harness (LC) can include column wirings spaced along the row direction X.

[0143] Circuit units (CUs) in the same row can be connected via a single routing harness (LR), while pixel circuits (PCs) in the same row can be connected via multiple routing lines. Similarly, circuit units (CUs) in the same column can be connected via a single column routing harness (LC), while pixel circuits (PCs) in the same column can be connected via multiple column routing lines. For example, the routing lines of each routing harness (LR) may include scan lines, etc.; the column routing lines of each column routing harness (LC) may include data lines, etc. Both the routing harness (LR) and the column routing harness (LC) are connected to peripheral circuits, allowing drive signals to be transmitted to the pixel circuits (PCs) via these peripheral circuits, thus driving the OLED light-emitting device to emit light.

[0144] In some embodiments of this disclosure, such as Figures 9-12 As shown, the routing lines of a routing harness LR may include a first reset signal line VIL1, a second reset signal line VIL2, an illumination control line EML, and a scan line GAL, all connected to the same row circuit unit CU. The column routing lines of a column routing harness LC may include a data line DAL and a power line VDL, both connected to the same column circuit unit CU.

[0145] To facilitate wiring, the pixel circuit PCs connected to different light-emitting OLEDs in the same device unit DC can be located in different circuit units CU; furthermore, the pixel circuit PCs connected to different light-emitting OLEDs in the same device unit DC can be located in the same row of circuit units CU.

[0146] Figures 14-17 It shows the basis of the above Figures 3-9 A schematic diagram of each membrane layer. Figure 14 The pattern of semiconductor layer 001 is shown. Figure 15 The pattern of the first conductive layer 002 is shown. Figure 16 The pattern of the second conductive layer 003 is shown. Figure 17 The pattern of the third conductive layer 004 is shown.

[0147] like Figure 4 , Figure 11 and 16As shown, in some embodiments of this disclosure, for the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 of the same circuit unit CU, in the third conductive layer 004, the second electrode plate Cst2 of the first pixel circuit PC1 has a through hole H1, the second electrode plate Cst2 of the second pixel circuit PC2 has a through hole H2, and the second electrode plate Cst2 of the third pixel circuit PC3 has a through hole H3. The first light-emitting device ROLED connected to the first pixel circuit PC1 emits red light, the second light-emitting device GOLED connected to the second pixel circuit PC2 emits green light, and the third light-emitting device BOLED connected to the third pixel circuit PC3 emits blue light. Since the turn-on voltage of the second light-emitting device (GOLED) differs from that of the first light-emitting device (ROLED) and the third light-emitting device (BOLED), the storage capacitor Cst of the second pixel circuit PC2 can be different from the storage capacitor Cst connecting the first pixel circuit PC1 and the third pixel circuit PC3. This difference can be achieved by differentiating the facing areas of the first electrode plate Cst1 and the second electrode plate Cst2. For example, the size of the via H2 can be different from that of vias H1 and H3, so that the brightness of the second light-emitting device (GOLED) matches the brightness of the first light-emitting device (ROLED) and the third light-emitting device (BOLED), thereby improving the uniformity of the brightness of the displayed image. Alternatively, the size of H2 can be the same as that of vias H1 and H3, while reducing the area of ​​the second electrode plate Cst2 where the via H2 is located, or the relative position of the second electrode plate Cst2 and the first electrode plate Cst1 can be moved, as long as the facing area of ​​the first electrode plate Cst1 and the second electrode plate Cst2 is reduced.

[0148] For example, the turn-on voltage of the second light-emitting device (GOLED) is higher than that of the first light-emitting device (ROLED) and the third light-emitting device (BOLED). To charge the storage capacitor Cst of the second pixel circuit PC2 faster and match its charging time with that of the first pixel circuit PC1 and the third pixel circuit PC3, the storage capacitor Cst of the second pixel circuit PC2 can be reduced. Therefore, the via H2 can be larger than vias H1 and H3, meaning the area of ​​the orthogonal projection of via H2 onto the substrate SU is larger than the areas of the orthogonal projections of vias H1 and H3 onto the substrate SU. This makes the storage capacitor Cst of the second pixel circuit PC2 smaller than that of the first pixel circuit PC1 and the third pixel circuit PC3, thereby shortening the charging time of the storage capacitor Cst of the second pixel circuit PC2. This helps to make the turn-on time and timing of the light-emitting devices (OLEDs) more consistent, improving image uniformity.

[0149] like Figure 11 and Figure 12As shown, in some embodiments of this disclosure, the pixel circuits of the same circuit unit CU may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 distributed along the row direction X.

[0150] The OLEDs in the same device unit DC can include a first OLED, a second OLED, and a third OLED. The first electrode ANO of the first OLED is designated as first electrode ANO1, the first electrode ANO of the second OLED is designated as first electrode ANO2, and the first electrode ANO of the third OLED is designated as first electrode ANO1.

[0151] For the same device unit DC, the first electrode ANO2 of GOLED can be connected to a first pixel circuit PC1, the first electrode ANO2 of GOLED can be connected to a second pixel circuit PC2, and the first electrode ANO1 of BOLED can be connected to a third pixel circuit PC3. Figure 11 and Figure 12 Only the first electrode ANO of each OLED is shown, and the light-emitting functional layer EL and the second electrode CAT are not shown.

[0152] like Figure 11 As shown, the first pixel circuit PC1 and the second pixel circuit PC2, which are connected to the first light-emitting device ROLED and the second light-emitting device GOLED, can be located in the same circuit unit CU, while the third pixel circuit PC3, which is connected to the third light-emitting device BOLED, can be located in another circuit unit CU. The two circuit units CU are arranged adjacent to each other in the row direction X.

[0153] Of course, in other embodiments of this disclosure, the pixel circuit PC connected to different light-emitting devices OLEDs in the same device unit DC can also be located in the same circuit unit CU.

[0154] Furthermore, for the circuit unit CU with three pixel circuits PC, the routing harness LR connecting it includes the same routing lines as the routing harness LR connecting one pixel circuit PC. Each routing harness LR may include a first reset signal line VIL1, a second reset signal line VIL2, an emission control line EML, and a scan line GAL. Meanwhile, since the three pixel circuits PC are distributed along the row direction, the column routing harness LC includes three sets of column routing lines. Each set of column routing lines includes a data line DAL and a power line VDL, and the same set of column routing lines is connected to the same pixel circuit PC.

[0155] like Figure 11As shown, in some embodiments of this disclosure, in the light-emitting devices (OLEDs) of the same device unit DC, the sizes of the first electrodes ANO of the first light-emitting device ROLED, the second light-emitting device GOLED, and the third light-emitting device BOLED can be different, and the sizes of the openings APE of these three OLEDs are also different. The area of ​​the first electrode ANO3 of the third light-emitting device BOLED is larger than the area of ​​the first electrode ANO2 of the second light-emitting device GOLED, and the area of ​​the first electrode ANO2 of the second light-emitting device GOLED is smaller than the area of ​​the first electrode ANO1 of the first light-emitting device ROLED. The area of ​​the first electrode ANO refers to the area of ​​its orthographic projection on the substrate SU.

[0156] Correspondingly, such as Figure 10 and Figure 11 As shown, the aperture APE defining the first light-emitting device ROLED can be defined as the first aperture APE1, the aperture APE defining the second light-emitting device GOLED can be defined as the second aperture APE2, and the aperture APE defining the third light-emitting device BOLED can be defined as the third aperture APE3. The first aperture APE1 is smaller than the second aperture APE2, and the third aperture APE3 is larger than the first aperture APE1. The size of the aperture APE refers to the area of ​​its orthographic projection on the substrate SU.

[0157] In the orthographic projection of a transparent region TRA and its corresponding device cell DC onto the substrate SU:

[0158] The transparent area TRA may include a first sub-area TRA1 and a second sub-area TRA2. The first sub-area TRA1 extends along a first direction different from the row direction X and the column direction Y. The second sub-area TRA2 is located on one side of the first sub-area TRA1 and extends along a second direction intersecting the first direction until it connects with the first sub-area TRA1. The second direction is different from the row direction X and the column direction Y; for example, the first direction is perpendicular to the second direction.

[0159] The orthographic projections of the first electrode ANO1 of the first light-emitting device ROLED and the first electrode ANO2 of the second light-emitting device GOLED on the substrate SU are located on the same side of the first sub-region TRA1, and are distributed along the first direction on both sides of the second sub-region TRA2. The orthographic projection of the first electrode ANO3 of the third light-emitting device BOLED on the driving layer PN is located on the side of the first sub-region TRA1 away from the second sub-region TRA2.

[0160] It should be noted that since the light-emitting device OLED is defined by the aperture APE, the distribution pattern of the light-emitting device OLED is also the distribution pattern of the aperture APE.

[0161] To ensure the light emission range of the OLED, the size of the aperture APE and the first electrode ANO of the OLED are limited and cannot be too small. Therefore, in order to avoid reducing the shading of the OLED by the LR and LC wiring harnesses by shrinking the aperture APE and the first electrode ANO, the LR and LC wiring harnesses can be bent in the region between two adjacent device units DC. This can reduce the shading of the OLED and avoid shrinking the OLED.

[0162] like Figure 9 As shown, the area between two adjacent circuit units CU, where the routing harness LR is located, is recessed towards each other along a direction parallel to the substrate SU, forming a row recess LTa. The orthographic projection of the row recess LTa onto the substrate SU is at least a part of the transparent area TRA, thus increasing the transparent area TRA. The orthographic projection of the row recess LTa onto the substrate SU at most partially coincides with the orthographic projection of an opening APE onto the substrate SU. For example, the orthographic projection of the row recess LTa onto the substrate SU may not coincide with the orthographic projection of an opening APE onto the substrate SU. Due to the presence of the row recess LTa, the routing harness LR will at least not obstruct the light-emitting device OLED. Of course, the orthographic projection of the row recess LTa onto the substrate SU and the orthographic projection of an opening APE onto the substrate SU can also partially coincide, but the area of ​​the non-coincident area is not less than 90% of the area of ​​the orthographic projection of the opening APE onto the substrate SU. This avoids obstructing the light emission of the OLED.

[0163] For example, the line of the line harness LR that is closest to the transparent area TRA may include alternating straight line segments x1 and line recesses LRa along the line direction. The straight line segments x1 may extend in a straight line along the line direction. The line recesses LRa may include a bottom line segment x3 and a sloping line segment x2 connecting the two ends of the bottom line segment x3. The bottom line segment x3 is connected by two adjacent straight line segments x1 through the sloping line segments x2 at both ends. The sloping line segment x2 and the straight line segment x1 form a certain angle, which is an obtuse angle or an acute angle. Figure 9 The horizontal flat segment x1, horizontal ramp segment x2, and horizontal bottom segment x3 are only shown in the first reset signal line VIL1. The second reset line REL2 can also adopt this segmentation method, which will not be described in detail here.

[0164] Furthermore, within the same wiring harness LR, other wiring harnesses may also bend to avoid the recessed area LRa formed by the bending of the wiring harness closest to the transparent area TRA. For example: Figure 9As shown, the second reset signal line VIL2 and the light emission control line EML can be recessed in the same direction as the first reset signal line REL2. The depth of the recess in the second reset signal line VIL2 is the same as the horizontal recess LTa, so that the distance between the second reset signal line VIL2 and the second reset line REL2 remains unchanged. The recess in the light emission control line EML can form a horizontal recess LTa1, and the depth of the horizontal recess LTa1 is less than that of the horizontal recess LTa. At the same time, the first reset signal line VIL1, the first reset line REL1, and the scan line GAL bend in the same direction to form recesses, and the direction of the recess is opposite to that of the second reset line REL2. The recessed area of ​​the first reset signal line VIL1 can form another horizontal recess LTa, and the recess in the scan line GAL can form a horizontal recess LTa2. The depth of the recess in the first reset line REL1 is the same as the depth of the horizontal recess LTa of the first reset signal line VIL1, and the depth of the horizontal recess LTa2 is less than the depth of the horizontal recess LTa.

[0165] The depth of the indentation mentioned above refers to the distance between the bottom row segment x3 and the straight row segment x1 in the column direction Y.

[0166] The column wiring harness LC can be recessed in the region between two adjacent circuit units CU along a direction parallel to the substrate SU, forming a column recess LCa. The orthographic projection of the column recess LCa onto the substrate SU is at least a part of the transparent area TRA, thus increasing the transparent area TRA. The orthographic projection of the column recess LCa onto the substrate SU at most partially coincides with the orthographic projection of an opening APE onto the substrate SU. For example, the orthographic projection of the column recess LCa onto the substrate SU may not coincide with the orthographic projection of an opening APE onto the substrate SU. Due to the presence of the column recess LCa, the column wiring harness LC will at least not obstruct the light-emitting device OLED. Of course, the orthographic projection of the column recess LCa onto the substrate SU and the orthographic projection of an opening APE onto the substrate SU can also partially coincide, but the area of ​​the non-coincident area is not less than 90% of the area of ​​the orthographic projection of the opening APE onto the substrate SU. This avoids obstructing the light emission of the OLED.

[0167] For example, the column wiring harness LC whose closest column wiring is to the transparent area TRA may include alternating column straight segments y1 and column recesses LCa along the column direction. The column straight segments y1 may extend in a straight line along the column direction. The column recesses LCa may include a column bottom segment y3 and a ramp segment y2 connecting the two ends of the column bottom segment y3. The column bottom segment y3 is connected by two adjacent column straight segments y1 through the column ramp segments y2 at both ends. The column ramp segments y2 and the column straight segments y1 form a certain angle, which is an obtuse angle or an acute angle. Figure 9 The column flat segment y1, column ramp segment y2, and column bottom segment y3 are shown only in the power line VDL of the first pixel circuit PC1. The data line DAL can also adopt this segmentation method, which will not be described in detail here.

[0168] Furthermore, within the same column of traces LC, to avoid the column recess LCa formed by the bend of the column trace closest to the transparent area TRA, other column traces may also bend accordingly. For example: Figure 9 As shown, in the same circuit unit CU:

[0169] In the same pixel circuit PC, the data line DAL and power line VDL are recessed in the same direction and to the same depth. Specifically, the data line DAL of the first pixel circuit PC1 can be recessed in the same direction as its power line VDL. The depth of the recess in the data line DAL of the first pixel circuit PC1 is the same as the column recess LCA, ensuring that the distance between the data line DAL and its power line VDL remains constant. That is, the recess in the data line DAL of the first pixel circuit PC1 forms a column recess LCA1, and the depth of the column recess LCA1 is equal to that of the column recess LCA. Simultaneously, the data line DAL and power line VDL of the second pixel circuit PC2 and the data line DAL and power line VDL of the third pixel circuit PC3 are recessed in the same direction, but in the opposite direction to the recess direction of the data line DAL and power line VDL of the first pixel circuit PC1. The data line DAL of the second pixel circuit PC2 is recessed to form another column recess LCa of the column wiring harness LC where it is located (in the opposite direction to the LCa recess formed by the power line VDL of the first pixel circuit PC1). The data line of the second pixel circuit PC2 can be recessed to form a column recess LCa2. The depth of the column recess LCa2 is less than the depth of the column recess LCa1 and the column recess LCa.

[0170] Of course, the recessed direction of the data line DAL and power line VDL of the second pixel circuit PC2 can also be replaced with... Figure 9 The data line DAL and power line VDL of the same pixel circuit PC can also be recessed in opposite directions. The recess depth of the data line DAL and power line VDL of the same pixel circuit PC can also be different.

[0171] The depth of the indentation mentioned above refers to the distance between the bottom segment y3 and the straight segment y1 in the row direction X.

[0172] In some embodiments of this disclosure, such as Figures 9-11 As shown, the row recess LCa and column recess LCa described above can be set simultaneously, and there are two routing harnesses LR and two column routing harnesses LC around the same transparent area TRA.

[0173] Of course, in other embodiments of this disclosure, only one of the row recess LTa and the column recess LCa may be provided.

[0174] In some embodiments of this disclosure, such as Figure 10As shown, the orthographic projection of the aperture APE corresponding to the first light-emitting device ROLED onto the substrate SU can coincide with at most a portion of the orthographic projection of a column recess LCa onto the substrate SU. The orthographic projection of the aperture APE corresponding to the second light-emitting device GOLED onto the substrate SU can coincide with at most a portion of the orthographic projection of a row recess LRa onto the substrate SU. The orthographic projection of the aperture APE corresponding to the third light-emitting device BOLED onto the substrate SU can coincide with at most a portion of the orthographic projection of a row recess LRa onto the substrate SU, and also with at most a portion of the orthographic projection of a column recess LCa onto the substrate SU.

[0175] The following explains the occlusion relationship between the light-emitting device OLED and the LR and LC wiring harnesses:

[0176] like Figure 11 As shown, the first electrode ANO of each light-emitting device OLED may be slightly larger than the opening APE that defines the light-emitting device OLED. Therefore, in the first electrode ANO of the device unit DC corresponding to the same transparent area, the orthographic projection of at least one first electrode ANO on the substrate SU coincides with the orthographic projection of a line harness LR on the substrate SU; the orthographic projection of at least one first electrode ANO on the substrate SU coincides with the orthographic projection of a line harness LC on the substrate SU.

[0177] In some embodiments of this disclosure, such as Figure 11 As shown, for the same device unit DC:

[0178] A portion of the first electrode ANO1 of the first light-emitting device ROLED covers the second reset control line REL2, but does not cover the second reset signal line VIL2, and a portion of the boundary of the first electrode ANO1 extends in the same direction as the second reset control line REL2.

[0179] A portion of the first electrode ANO2 of the second light-emitting device GOLED covers the nearest power line VDL, but does not cover the data line DAL adjacent to the power line VDL, and a portion of the boundary of the first electrode ANO2 is in the same direction as the extension of the power line VDL.

[0180] A portion of the first electrode ANO3 of the third light-emitting device BOLED covers the second reset control line REL2 of another routing harness LR (opposite to the second reset control line REL2 covered by the first electrode ANO of the first light-emitting device ROLED), but does not cover the second reset signal line VIL2, and a portion of the boundary of the first electrode ANO3 is in the same direction of extension as the second reset control line REL2; at the same time, a portion of the first electrode ANO3 of the third light-emitting device BOLED covers the nearest data line DAL, but does not cover the power line VDL adjacent to the data line DAL, and a portion of the boundary of the first electrode ANO3 is in the same direction of extension as the data line DAL.

[0181] Furthermore, the first electrode ANO of each OLED light-emitting device in any device unit DC is connected to the pixel circuit PC through the connection part C. In the direction perpendicular to the substrate SU, the connection part C overlaps with the walking line bundle LR and the column walking line bundle LC. Thus, through the connection part C, the first electrode ANO can be connected to the pixel circuit PC while corresponding to the transparent area TRA.

[0182] like Figure 12 As shown, in some embodiments of this disclosure, for Figure 12 The device unit DC shown includes a first light-emitting device ROLED, a second light-emitting device GOLED, and a third light-emitting device BOLED. There are also three corresponding connection parts C, namely a first connection part C1, a second connection part C2, and a third connection part C3. The first electrode ANO1 can be connected to the first pixel circuit PC1 through the first connection part C1, the first electrode ANO2 can be connected to the second pixel circuit PC2 through the second connection part C2, and the first electrode ANO3 can be connected to the third pixel circuit PC3 through the third connection part C3. The first pixel circuit PC1 and the second pixel circuit PC2 are located in the same circuit unit PC, and the third pixel circuit PC3 is located in another circuit unit CU.

[0183] like Figure 12As shown, the pixel circuits PC connected to the first connecting part C1 and the second connecting part C2 are located in the same circuit unit PC, and the pixel circuits PC connected to the third connecting part C3 are located in different circuit units CU in the same row. The length of the first connecting part C1 in its extension direction is less than the length of the second connecting part C2 in its extension direction, and the length of the second connecting part C2 in its extension direction is less than the length of the third connecting part C3 in its extension direction. This allows for the connection of the pixel circuit PC and the first electrode ANO while preventing excessively long connecting parts C in the connecting parts C of the OLED light-emitting devices connected to the same device unit DC. This reduces wiring difficulty, maximizes the utilization of the space available for connecting parts C, and helps to minimize the length differences between connecting parts C, thereby improving the uniformity of the display effect.

[0184] The first connection portion C1 and the second reset signal line VIL2 and the light emission control line EML may have overlapping regions on the substrate SU, but the projections of the first connection portion C1 and the second reset control line REL2 on the substrate SU do not overlap, because the projections of the first electrode ANO1 and the second reset control line REL2 on the substrate SU overlap, and the first connection portion C1 is located outside the first electrode ANO1.

[0185] The first connecting portion C1 may include a first segment connected to the first electrode ANO1 and a second segment connected to the first pixel circuit PC1, the first segment and the second segment being connected; the first segment may extend in a direction different from the row direction X and the column direction Y, for example, extending in the second direction mentioned above, and the second segment may extend in the row direction X. The first segment has an overlapping area with the projection of the second reset signal line VIL2 and the light emission control line EML on the substrate SU; the second segment has an overlapping area with the projection of the light emission control line EML on the substrate SU, but no overlapping area with the projection of the second reset signal line VIL2 on the substrate SU.

[0186] The second connection portion C2 and the second reset control line REL2, the second reset signal line VIL2, the light emission control line EML, the data line DAL of the first pixel circuit PC1, and the power supply line VDL have an overlapping area on the substrate SU.

[0187] The second connection portion C2 may include a first segment connected to the first electrode ANO2 and a second segment connected to the second pixel circuit PC2, with the first and second segments connected together. The first segment may extend in a direction different from the row direction X and the column direction Y, for example, along the second direction mentioned above, and the second segment may extend along the column direction Y. The first segment has an overlapping area with the projections of the data line DAL and the power line VDL on the substrate SU; the second segment has an overlapping area with the projections of the second reset control line REL2, the second reset signal line VIL2, and the light emission control line EML on the substrate SU, and the second segment of the second connection portion C2 is located between the data line DAL of the first pixel circuit PC1 and the power line VDL of the second pixel circuit PC2.

[0188] The third connection portion C3 overlaps with the orthogonal projections of the second reset control line REL2, the second reset signal line VIL2, the light emission control line EML, the data line DAL of the third pixel circuit PC3, and the power supply line VDL on the substrate SU. The third pixel circuit PC3 is the third pixel circuit PC3 connected to the third connection portion C3, and its connection to the first pixel circuit PC1 and the second pixel circuit PC2, which are connected to the first connection portion C1 and the second connection portion C2, are located in two adjacent circuit units CU.

[0189] The third connection portion C3 may include a first segment connected to the first electrode ANO3 and a second segment connected to the third pixel circuit PC3, with the first and second segments connected. The first segment may extend in a direction different from the row direction X and the column direction Y, for example, extending in the first direction mentioned above, and the second segment may extend in the column direction Y. The first segment has an overlapping area with the projection of the power line VDL on the substrate SU. However, since the edge of the first electrode ANO3 overlaps with the orthographic projection of the data line DAL of the connected third pixel circuit PC3 on the substrate SU, the first segment of the third connection portion C3 is located on the side of the data line DAL away from the first electrode ANO3, so that the first segment does not overlap with the orthographic projection of the data line DAL on the substrate SU. The second segment has an overlapping area with the projections of the second reset control line REL2, the second reset signal line VIL2, and the light emission control line EML on the substrate SU, and the second segment of the third connection portion C3 is located between the power line VDL of the connected third pixel circuit PC3 and the data line DAL of the adjacent second pixel circuit PC2.

[0190] For the display panel disclosed herein, in order to improve light transmittance, the brightness of the back display can also be increased by adjusting the thickness of the first electrode ANO of the OLED, while ensuring the electrical performance of the first electrode ANO to avoid affecting the normal operation of the OLED. For example:

[0191] like Figure 1As shown, in some embodiments of this disclosure, the first electrode ANO may include a first transparent conductive layer TA1, a conductive metal layer MET, and a second transparent conductive layer TA2. The materials of the first transparent conductive layer TA1 and the second transparent conductive layer TA2 are indium tin oxide (ITO), and the material of the conductive metal layer MET is silver. The thickness of the conductive metal layer MET is not less than 200 Å and not more than 300 Å. The thicknesses of both the first transparent conductive layer TA1 and the second transparent conductive layer TA2 are not less than 80 Å and not more than 100 Å.

[0192] In addition, the material of the second electrode CAT can be a magnesium-silver alloy with a thickness of not less than 13 nm and not more than 15 nm.

[0193] To further improve light transmittance, such as Figure 13 As shown, in some embodiments of this disclosure, the second electrode CAT can be a continuous, solid-layer structure, allowing each OLED to share the same second electrode CAT. A light-transmitting hole HCAT can be formed in the area of ​​the second electrode CAT other than the opening APE. The opening APE must still be covered by the second electrode CAT to ensure that the OLED can emit light normally. The light-transmitting hole HCAT can improve the light transmittance of the display panel and enhance the transparent display effect. The number of light-transmitting holes HCAT can be multiple; the specific number and shape are not specifically limited here, as long as they do not affect the light emission of the OLED.

[0194] It should be noted that since all OLEDs share the same second electrode CAT, the light-transmitting aperture HCAT should not cut off the second electrode CAT corresponding to different OLEDs. The second electrode CAT should still be a conductive whole structure, only partially hollowed out, so that the second power signal VSS can be input to each OLED simultaneously through the external circuit via the second electrode CAT.

[0195] like Figure 18 As shown, Figure 18 The graph shows the variation trend of transmittance of conductive metal layers (MET) of different thicknesses under different wavelengths of light. The horizontal axis represents the wavelength of light, and the vertical axis represents the transmittance. According to... Figure 16 The experimental results show that a conductive metal layer (MET) with a thickness of around 200 Å can maintain very good transmissivity and reflectivity.

[0196] Furthermore, both the planarization layer (PLN) and the pixel definition layer (PDL) can be made of resin or other materials with high light transmittance (not less than 86%). Experiments have been conducted to verify that, within the material and thickness range of the first electrode (ANO) and the second electrode (CAT), the first electrode (ANO) has a reflectance of approximately 53% and a light transmittance of approximately 40%. The brightness of the front display can reach 40%-45%, and the brightness of the back display can reach 60%. The color gamut of both the front and back displays can reach 99%.

[0197] This disclosure also provides a method for manufacturing a display panel, which can be any of the display panels described in the above embodiments, the structure of which will not be detailed here. The manufacturing method may include steps S110 and S120, wherein:

[0198] Step S110: A driving layer is formed on one side of the substrate. The driving layer includes multiple circuit units, multiple routing bundles, and multiple column routing bundles arranged in an array. Each circuit unit includes multiple pixel circuits. Each routing bundle includes multiple routing lines spaced apart along the column direction, and each column routing bundle includes multiple column routing lines spaced apart along the row direction. The circuit units in the same row are connected by a routing bundle, and the circuit units in the same column are connected by a column routing bundle. The orthographic projections of the routing bundles and the column routing bundles on the substrate intersect to separate multiple transparent areas. The region of the driving layer corresponding to the transparent areas is a transparent structure.

[0199] Step S120: A light-emitting layer comprising an array of multiple device units is formed on the surface of the driving layer away from the substrate. The device units correspond to the transparent area. Each device unit comprises multiple spaced light-emitting devices, and each light-emitting device is connected to a pixel circuit. Each light-emitting device comprises a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially in the direction away from the substrate. The first electrode and the second electrode are transparent structures.

[0200] Since the details of the structures involved in each step of the above manufacturing method have been described in detail in the above-described implementation of the display panel, their details and beneficial effects will not be described in detail here.

[0201] It should be noted that although the various steps of the manufacturing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0202] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. The specific structure and beneficial effects of this display panel have been described in detail in the embodiments of the display panel above, and will not be repeated here. The display device of this disclosure can be used in electronic devices with image display functions such as mobile phones, tablet computers, and televisions, and will not be listed individually here.

[0203] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising: Substrate; A driving layer is disposed on one side of the substrate and includes multiple circuit units, multiple routing harnesses and multiple column routing harnesses arranged in an array. The circuit unit includes multiple pixel circuits; the routing harness includes multiple routing lines spaced apart along the column direction, and the column routing harness includes multiple column routing lines spaced apart along the row direction; the circuit units in the same row are connected by one routing harness, and the circuit units in the same column are connected by one column routing harness; the orthographic projections of the routing harness and the column routing harness on the substrate intersect to separate multiple transparent areas, and the area of ​​the driving layer corresponding to the transparent area is a transparent structure; the distance between two adjacent pixel circuits in the same circuit unit is less than the distance between two adjacent circuit units; A light-emitting layer is disposed on the surface of the driving layer opposite to the substrate, and includes a plurality of device units arranged in an array, the device units corresponding to the transparent area; each device unit includes a plurality of spaced-apart light-emitting devices, each light-emitting device being connected to a pixel circuit; each light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially in the direction opposite to the substrate, the first electrode and the second electrode being transparent; the pixel circuits connected to different light-emitting devices in the same device unit are located in different circuit units; The routing harness is recessed in the region between two adjacent circuit units to form a row recess, the orthographic projection of the row recess on the substrate being at least a part of the transparent area; and / or, the column routing harness is recessed in the region between two adjacent circuit units to form a column recess, the orthographic projection of the column recess on the substrate being at least a part of the transparent area.

2. The display panel according to claim 1, wherein, The light-emitting layer further includes a pixel definition layer that separates each of the light-emitting devices, the pixel definition layer having an opening that defines each of the light-emitting devices; The orthographic projection of one of the openings on the substrate and the orthographic projection of one of the row recesses on the substrate may partially overlap.

3. The display panel according to claim 1, wherein, The light-emitting layer further includes a pixel definition layer that separates each of the light-emitting devices, the pixel definition layer having an opening that defines each of the light-emitting devices; The orthographic projection of one of the openings on the substrate and the orthographic projection of one of the recesses on the substrate may partially overlap.

4. The display panel according to claim 1, wherein, The light-emitting layer further includes a pixel definition layer that separates each of the light-emitting devices, the pixel definition layer having an opening that defines each of the light-emitting devices; The walking wire harness is recessed in opposite directions in the area between two adjacent circuit units to form a row of recesses. The orthographic projection of the row of recesses on the substrate is at least a part of the transparent area. The orthographic projection of one of the openings on the substrate and the orthographic projection of one of the row of recesses on the substrate may coincide in at most parts. The column wiring harness is recessed in the region between two adjacent circuit units to form a column recess, and the orthographic projection of the column recess on the substrate is at least a part of the transparent area; the orthographic projection of an opening on the substrate and the orthographic projection of a column recess on the substrate may partially coincide.

5. The display panel according to claim 4, wherein, The same device unit includes three light-emitting devices with different emitting colors, and the first electrodes of the three light-emitting devices are of different sizes.

6. The display panel according to claim 5, wherein, The light-emitting devices of the same device unit include a first light-emitting device that emits green light, a second light-emitting device that emits red light, and a third light-emitting device that emits blue light; The area of ​​the first electrode of the third light-emitting device is larger than the area of ​​the first electrode of the first light-emitting device, and the area of ​​the first electrode of the first light-emitting device is larger than the area of ​​the first electrode of the second light-emitting device.

7. The display panel according to claim 6, wherein, The orthographic projection of the opening corresponding to the first light-emitting device on the substrate coincides with the orthographic projection of one of the column of recesses on the substrate in multiple parts. The orthographic projection of the opening corresponding to the second light-emitting device on the substrate coincides with the orthographic projection of one of the row recesses on the substrate in most parts. The orthographic projection of the opening corresponding to the third light-emitting device on the substrate coincides with the orthographic projection of the row recess on the substrate in at most a portion, and also coincides with the orthographic projection of the column recess on the substrate in at most a portion.

8. The display panel according to claim 1, wherein, In the first electrode of the device unit corresponding to the same transparent region, the orthographic projection of at least one of the first electrodes on the substrate coincides with the orthographic projection of a routing harness on the substrate; the orthographic projection of at least one of the first electrodes on the substrate coincides with the orthographic projection of a routing harness on the substrate.

9. The display panel according to claim 6, wherein, In the orthographic projection of the transparent region and its corresponding device unit onto the substrate: The transparent area includes a first sub-area and a second sub-area. The first sub-area extends along a first direction different from the row direction and the column direction. The second sub-area is located on one side of the first sub-area and extends along a second direction intersecting the first direction to connect with the first sub-area. The second direction is different from the row direction and the column direction. The first electrode of the first light-emitting device and the first electrode of the second light-emitting device are projected onto the driving layer on the same side of the first sub-region and distributed on both sides of the second sub-region along the first direction; the first electrode of the third light-emitting device is projected onto the driving layer on the side of the first sub-region away from the second sub-region.

10. The display panel according to claim 1, wherein, The wiring harness includes multiple wiring lines, and the wiring lines include scan lines; The column wiring harness includes multiple column wirings, and the column wirings include data lines.

11. The display panel according to claim 6, wherein, The pixel circuits connected to different light-emitting devices in the same device unit are located in the same row of circuit units.

12. The display panel according to claim 11, wherein, The first electrode of each light-emitting device in any of the device units is connected to a pixel circuit via a connection portion; The first electrode of the first light-emitting device is connected to a pixel circuit through a first connection portion; the first electrode of the second light-emitting device is connected to a pixel circuit through a second connection portion; and the first electrode of the third light-emitting device is connected to a pixel circuit through a third connection portion. The pixel circuits connected to the first connecting part and the second connecting part are located in the same circuit unit, and the pixel circuits connected to the third connecting part are located in different circuit units in the same row; The length of the first connecting part in its extending direction is less than the length of the second connecting part in its extending direction, and the length of the second connecting part in its extending direction is less than the length of the third connecting part in its extending direction.

13. The display panel according to any one of claims 1-12, wherein, The driving layer includes: An active layer is disposed on one side of the substrate; A first gate insulating layer covers the active layer and the substrate; A gate is disposed on the surface of the first gate insulating layer opposite to the substrate; A second gate insulating layer covers the gate and the first gate insulating layer; An interlayer dielectric layer covers the second gate insulating layer; A source / drain layer is disposed on the surface of the interlayer dielectric layer opposite to the substrate; A planarization layer covering the source / drain layer and the interlayer dielectric layer; The display panel also includes: An encapsulation layer that covers the light-emitting layer; A touch layer is disposed on the surface of the encapsulation layer opposite to the substrate.

14. The display panel according to any one of claims 1-12, wherein, The first electrode includes a first transparent conductive layer, a conductive metal layer, and a second transparent conductive layer stacked sequentially in a direction away from the substrate, wherein the resistivity of the conductive metal layer is less than the resistivity of the first transparent conductive layer and the second transparent conductive layer. The thickness of the conductive metal layer is not less than 200 Å and not more than 300 Å.

15. The display panel according to claim 14, wherein, The thickness of both the first transparent conductive layer and the second transparent conductive layer is not less than 80 Å and not greater than 100 Å.

16. The display panel according to claim 1, wherein, The thickness of the second electrode is not less than 13 nm and not more than 15 nm.

17. A method for manufacturing a display panel, comprising: A driving layer is formed on one side of the substrate, the driving layer including multiple circuit units, multiple routing bundles and multiple column routing bundles distributed in an array; The circuit unit includes multiple pixel circuits; the routing harness includes multiple routing lines spaced apart along the column direction, and the column routing harness includes multiple column routing lines spaced apart along the row direction; the circuit units in the same row are connected by one routing harness, and the circuit units in the same column are connected by one column routing harness; the orthographic projections of the routing harness and the column routing harness on the substrate intersect to separate multiple transparent areas, and the area of ​​the driving layer corresponding to the transparent area is a transparent structure; A light-emitting layer comprising an array of multiple device units is formed on the surface of the driving layer facing away from the substrate. The device units correspond to the transparent area. Each device unit includes multiple spaced-apart light-emitting devices, and each light-emitting device is connected to a pixel circuit. Each light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially in the direction facing away from the substrate. The first electrode and the second electrode are transparent. Pixel circuits connected to different light-emitting devices in the same device unit are located in different circuit units. The routing harness is recessed in the region between two adjacent circuit units to form a row recess, the orthographic projection of the row recess on the substrate being at least a part of the transparent area; and / or, the column routing harness is recessed in the region between two adjacent circuit units to form a column recess, the orthographic projection of the column recess on the substrate being at least a part of the transparent area.

18. A display device comprising the display panel according to any one of claims 1-16.

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