Display panel and display device

Abstract

The present invention discloses a display panel and a display device, relating to the field of display technology, wherein a non-display area includes a scan drive circuit, which includes at least a plurality of cascaded shift register units; the output end of each shift register unit is connected to at least one scan line in the display area; the non-display area also includes a first clock signal line and a second clock signal line, and the shift register unit is electrically connected to the first clock signal line and the second clock signal line, respectively; the display panel includes a substrate, a transistor layer arranged on the substrate, a first auxiliary conductive layer and a second auxiliary conductive layer, the first clock signal line and the second clock signal line are located in the second auxiliary conductive layer, and are electrically connected to the transistor layer through the first auxiliary conductive layer, respectively; the first auxiliary conductive layer includes a conductive block, and the first clock signal line and the second clock signal line overlap with the conductive block in a direction perpendicular to the plane where the substrate is located, so as to reduce the load difference between the first clock signal line and the second clock signal line.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] From the CRT (cathode ray tube) era to the LCD (liquid crystal display) era, and now to the OLED (organic light-emitting diode) and LED display eras, the display industry has undergone decades of rapid development and is now closely related to our lives. From traditional mobile phones, tablets, TVs, and PCs to today's smart wearable devices, VR, in-car displays, and other electronic devices, display technology is indispensable.

[0003] With the development of display technology, users have higher and higher requirements for display products. How to reduce the display abnormality caused by the load difference of signal lines has become one of the technical problems that need to be solved urgently at this stage. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and a display device, which aim to reduce the load difference between the first clock signal line and the second clock signal line to avoid abnormal stripes.

[0005] In a first aspect, the present invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area;

[0006] The non-display area includes a scan driving circuit, and the scan driving circuit at least includes a plurality of cascaded shift register units;

[0007] The display area includes a plurality of scan lines, and the output end of the shift register unit of each stage is connected to at least one of the scan lines;

[0008] The non-display area further includes a first clock signal line and a second clock signal line, and the shift register unit is electrically connected to the first clock signal line and the second clock signal line respectively;

[0009] The display panel includes a substrate, a transistor layer arranged on the substrate, a first auxiliary conductive layer and a second auxiliary conductive layer, the first auxiliary conductive layer is located on the side of the transistor layer facing away from the substrate, and the second auxiliary conductive layer is located on the side of the first auxiliary conductive layer facing away from the substrate; the first clock signal line and the second clock signal line are located in the second auxiliary conductive layer, and are electrically connected to the transistor layer through the first auxiliary conductive layer respectively; the first auxiliary conductive layer includes a conductive block, and the first clock signal line and the second clock signal line overlap with the conductive block along a direction perpendicular to the plane of the substrate.

[0010] In a second aspect, based on the same inventive concept, the present invention provides a display device, comprising the display panel provided in the first aspect of the present invention.

[0011] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0012] In the display panel and display device provided by the present invention, a scan drive circuit is provided in the non-display area, and the cascaded shift register unit in the scan drive circuit is electrically connected to the scan line in the display area for providing a scan signal to the scan line. The non-display area is also provided with a first clock signal line and a second clock signal line, and the shift register unit is electrically connected to the first clock signal line and the second clock signal line, respectively, to obtain the clock signal through the first clock signal line and the second clock signal line. Under the control of the signal provided by the first clock signal line and the second clock signal line to the shift register unit, the pixel rows in the display area are turned on row by row. If the load difference between the first clock signal line and the second clock signal line is large, the difference between the clock signals transmitted by the first clock signal line and the second clock signal line will also be large, which may cause abnormal horizontal stripes to appear between different pixel rows. To this end, an embodiment of the present invention sets the first clock signal line and the second clock signal line on the second auxiliary conductive layer, and sets the first clock signal line and the second clock signal line to be electrically connected to the conductive blocks on the first auxiliary conductive layer to reduce the difference in coupling capacitance between the first clock signal line and the second clock signal line and other film layers, thereby helping to reduce the difference in driving ability of the signals on the first clock signal line and the second clock signal line to the scanning line, helping to avoid the problem of abnormal horizontal stripes display between different display rows on the display panel, and helping to improve the overall display effect of the display panel and the display device.

[0013] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0014] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0016] Figure 1 FIG2 is a top view of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 Shown Figure 1 An AA' cross-sectional view of the panel is shown in FIG.

[0018] Figure 3 Shown is a schematic diagram of a film layer corresponding to the first clock signal line and the second clock signal line in the non-display area;

[0019] Figure 4 FIG2 is a schematic diagram showing a connection between a shift register unit and a first clock signal line and a second clock signal line in a scan driving circuit;

[0020] Figure 5 FIG2 is another top view of a display panel provided by an embodiment of the present invention;

[0021] Figure 6 Shown is a top view of the relationship between the clock signal line and the conductive block;

[0022] Figure 7 FIG2 is a schematic diagram showing a layout of a shift register unit and a conductive block provided by an embodiment of the present invention;

[0023] Figure 8 FIG2 is a circuit diagram of a single shift register unit provided by an embodiment of the present invention;

[0024] Figure 9 FIG2 is a top view of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention.

[0026] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0027] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0028] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0029] It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention may be combined with each other unless there is any contradiction.

[0030] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0031] Figure 1 FIG2 shows a top view of a display panel provided by an embodiment of the present invention. This embodiment illustrates the arrangement of sub-pixels P in the display panel but does not limit the actual pixel arrangement. In other embodiments of the present invention, the display panel may also adopt other pixel arrangements. Furthermore, this embodiment uses rectangular sub-pixels as an example and does not limit the actual shape and size of the sub-pixels. Figure 1 The number of scan lines shown is for illustration only and does not limit the number of scan lines actually included in the display panel and the number of shift register units corresponding to the scan lines.

[0032] Figure 2 Shown Figure 1 An AA' cross-sectional view of the display panel in the embodiment illustrates a film layer structure of the display panel, which only reflects a relative position relationship among the substrate 00, the transistor layer 10, the first auxiliary conductive layer S1 and the second auxiliary conductive layer S2, and does not limit the actual number of film layers and film layer sizes contained in the display panel.

[0033] Figure 3 FIG. 1 is a schematic diagram of a film layer corresponding to the first clock signal line L1 and the second clock signal line L2 in the non-display area NA. Figure 4 FIG. 1 is a schematic diagram showing a connection between a shift register unit in a scan driving circuit and a first clock signal line L1 and a second clock signal line L2 .

[0034] Please refer to Figures 1 to 4 , an embodiment of the present invention provides a display panel, comprising: a display area AA and a non-display area NA at least partially surrounding the display area AA;

[0035] The non-display area NA includes a scan driving circuit, which includes at least a plurality of cascaded shift register units VSR;

[0036] The display area AA includes a plurality of scan lines X, and the output end of the shift register unit VSR of each stage is connected to at least one scan line X;

[0037] The non-display area NA further includes a first clock signal line L1 and a second clock signal line L2, and the shift register unit VSR is electrically connected to the first clock signal line L1 and the second clock signal line L2 respectively;

[0038] The display panel includes a substrate 00, a transistor layer 10 arranged on the substrate 00, a first auxiliary conductive layer S1 and a second auxiliary conductive layer S2, the first auxiliary conductive layer S1 is located on the side of the transistor layer 10 facing away from the substrate 00, and the second auxiliary conductive layer S2 is located on the side of the first auxiliary conductive layer S1 facing away from the substrate 00; the first clock signal line L1 and the second clock signal line L2 are located in the second auxiliary conductive layer S2, and are respectively electrically connected to the transistor layer 10 through the first auxiliary conductive layer S1; the first auxiliary conductive layer S1 includes a conductive block 90, and the first clock signal line L1 and the second clock signal line L2 overlap with the conductive block 90 along a direction perpendicular to the plane of the substrate 00.

[0039] It should be noted that Figure 1 The method of setting the shift register unit VSR in the non-display area NA on one side of the extension direction of the scan line X is only illustrated. In some other embodiments of the present invention, the shift register unit VSR can also be set on both sides of the extension direction of the scan line X. For example, please refer to Figure 5 , Figure 5 FIG. 2 shows another top view of a display panel provided by an embodiment of the present invention. In this embodiment, the two ends of the same scan line X are electrically connected to different shift register units VSR, respectively. The two shift register units VSR simultaneously drive the same scan line X, which is beneficial for improving the overall driving capability of the display panel.

[0040] In the related art, when the first clock signal line L1 and the second clock signal line L2 are introduced into the non-display area NA, the circuit structure overlapping with the first clock signal line L1 and the second clock signal line L2 along the direction perpendicular to the plane where the substrate 00 is located is different, resulting in different sizes of coupling capacitances formed between the first clock signal line L1 and the second clock signal line L2 and other conductive film layers, which in turn leads to different load differences between the first clock signal line L1 and the second clock signal line L2, and ultimately a large difference in the driving capability of the scan line X. For example, the difference in the scanning signals provided to the odd-numbered rows of pixels and the even-numbered rows of pixels is large, resulting in a large difference in the display brightness of the odd-numbered rows of pixels and the even-numbered rows of pixels on the display panel, resulting in the problem of displaying odd-even horizontal stripes.

[0041] To address the above-mentioned technical problems, the present invention provides a display panel 100. A scan driver circuit is provided in the non-display area NA. A cascaded shift register unit VSR in the scan driver circuit is electrically connected to a scan line X in the display area AA, thereby providing a scan signal to the scan line X. The non-display area NA is also provided with a first clock signal line L1 and a second clock signal line L2. The shift register unit VSR is electrically connected to the first clock signal line L1 and the second clock signal line L2, respectively, and receives clock signals from the first clock signal line L1 and the second clock signal line L2. Under the control of signals provided to the shift register unit by the first clock signal line L1 and the second clock signal line L2, pixel rows in the display area AA are turned on row by row. If the load difference between the first clock signal line L1 and the second clock signal line L2 is large, the difference in the clock signals transmitted by the first clock signal line L1 and the second clock signal line L2 will also be large, potentially causing abnormal horizontal stripes between different pixel rows. To this end, in an embodiment of the present invention, both the first clock signal line L1 and the second clock signal line L2 are disposed on the second auxiliary conductive layer S2, and both the first clock signal line L1 and the second clock signal line L2 are electrically connected to the conductive block 90 on the first auxiliary conductive layer S1, so as to reduce the difference in coupling capacitance between the first clock signal line L1 and the second clock signal line L2 and other film layers, thereby facilitating reduction in the difference in driving capability of the signals on the first clock signal line L1 and the second clock signal line L2 to the scan line X, thereby facilitating avoidance of the problem of abnormal horizontal stripes displayed between different display rows on the display panel, and thereby improving the overall display effect of the display panel and the display device.

[0042] Optionally, continue to refer to Figure 2 The display panel provided in this embodiment may be a display panel using organic light-emitting diode display technology, i.e., an OLED (Organic Light-Emitting Diode) display panel. The basic structure of the light-emitting functional layer of the OLED display panel includes an anode RE, a light-emitting material layer 50, and a cathode (not shown in the figure), wherein the light-emitting material layer 50 is located between the anode RE and the cathode in a direction perpendicular to the substrate 00. When the power supply supplies an appropriate voltage, the holes of the anode and the electrons of the cathode will combine in the light-emitting material layer to generate bright light. Compared with thin-film field-effect transistor liquid crystal displays, OLED display devices have the characteristics of high visibility and high brightness, and are more power-saving, light in weight, and thin in thickness. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode display technology, such as a MicroLED display panel, or a MiniLED display panel, etc.

[0043] Figure 2Only the OLED display panel is used for illustration. Optionally, the display panel includes a substrate 00 and a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, a gate metal layer MG, a third metal layer M3, and a fourth metal layer M4 arranged on one side of the substrate 00, and also includes a semiconductor layer poly and an oxide layer IGZO. Among them, the first metal layer M1 and the gate metal layer MG are used to set the gate of the transistor; the capacitor metal layer is used to form a capacitor structure with the first metal layer M1 or the second metal layer M2. The source electrode and the drain electrode of the transistor T0 in the display panel may be located in the second metal layer M2, and the semiconductor layer poly includes a source region and a drain region, and the source region and the drain region are formed by doping N-type impurity ions or P-type impurity ions. The source electrodes of some transistors are electrically connected to the source region of the semiconductor layer poly through contact holes, and the drain electrodes of the transistors are electrically connected to the drain region of the semiconductor layer poly through contact holes. It should be noted that, Figure 2 The embodiment is described by taking the display panel including both low-temperature polysilicon transistors and oxide transistors as an example, but does not limit the actual film layer structure of the display panel. In some other embodiments of the present invention, the display panel may also include only low-temperature polysilicon transistors, or only oxide transistors.

[0044] When the display panel includes a FIAA wiring structure, a third metal layer M3 and a fourth metal layer M4 may be provided in the display panel for providing the FIAA wiring. In the embodiment of the present invention, when introducing the conductive block 90, the conductive block is provided in the third metal layer M3, and the first clock signal line L1 and the second clock signal line L2 are provided in the fourth metal layer M4. The existing third metal layer M3 and fourth metal layer in the panel can be reused without adding additional film layers, thereby simplifying the film layer structure of the display panel.

[0045] Figure 6 The diagram shows a top view of the relationship between the clock signal line and the conductive block. This embodiment illustrates the top view relationship between the first clock signal line L1 and the second clock signal line L2 and the conductive block located on the side thereof facing the substrate 00.

[0046] Please refer to Figure 3 and Figure 6 In an optional embodiment of the present invention, in the non-display area NA, the conductive blocks include first conductive blocks 91 and second conductive blocks 92 alternately arranged along a first direction D1, the first conductive blocks 91 and the second conductive blocks 92 are insulated, and the first direction D1 is the extension direction of the first clock signal line L1 and the second clock signal line L2; each first conductive block 91 is electrically connected to the first clock signal line L1 through a different first conductive hole K1, and each second conductive block 92 is electrically connected to the second clock signal line L2 through a different second conductive hole K2.

[0047] In this embodiment, the first clock signal line L1 and the second clock signal line L2 are arranged on the same layer, and the first conductive block 91 and the second conductive block 92 are arranged on the same layer and insulated from each other. The first clock signal line L1 is electrically connected to the first conductive block 91, and is electrically connected to different shift register units VSR through the first conductive block 91. The second clock signal line L2 is electrically connected to the second conductive block 92, and is electrically connected to different shift register units VSR through the second conductive block 92. The transistors in the shift register unit VSR are located in the transistor layer 10 of the display panel, that is, along the direction perpendicular to the plane where the substrate 00 is located, the film layer where the first conductive block 91 and the second conductive block 92 are located is located between the film layer where the first clock signal line L1 and the second clock signal line L2 are located and the shift register unit VSR. The first conductive block 91 and the second conductive block 92 can isolate the first clock signal line L1 and the second clock signal line L2 from the shift register unit VSR, reducing the interference of the signal of the shift register unit VSR on the first clock signal line L1 and the second clock signal line L2, thereby helping to reduce the load difference between the first clock signal line L1 and the second clock signal line L2 caused by the influence of the signal of the shift register unit VSR, and helping to improve the problem of display horizontal stripes between different pixel rows.

[0048] Continue to refer Figure 3 and Figure 6 In an optional embodiment of the present invention, along a direction perpendicular to the plane of the substrate 00, the first clock signal line L1 overlaps with both the first conductive block 91 and the second conductive block 92, and the second clock signal line L2 overlaps with both the first conductive block 91 and the second conductive block 92. It should be noted that in order to clearly illustrate the structure of the first conductive block 91 and the second conductive block 92, this embodiment does not show other film layer structures on the display panel. In order to clearly distinguish the first conductive block 91 and the second conductive block 92, this embodiment does not show the structure of the first conductive block 91 and the second conductive block 92. Figure 6 The first conductive blocks 91 and the second conductive blocks 92 are filled differently, but it should be clear that the first conductive blocks 91 and the second conductive blocks 92 are located in the same film layer of the display panel.

[0049] Specifically, along a direction perpendicular to the plane of the substrate 00, the first clock signal line L1 and the second clock signal line L2 are arranged relative to the first conductive block 91 and the second conductive block 92. When the first clock signal line L1 is arranged to overlap both the first conductive block 91 and the second conductive block 92, a coupling capacitor is formed between the first clock signal line L1 and the first conductive block 91 and the second conductive block 92 it overlaps with. When the second clock signal line L2 is arranged to overlap both the first conductive block 91 and the second conductive block 92, a coupling capacitor is formed between the second clock signal line L2 and the first conductive block 91 and the second conductive block 92 it overlaps with. If the first clock signal line L1 and the second clock signal line L2 overlap with different types of conductive blocks, the difference in coupling capacitance formed with the conductive blocks may be significant, resulting in a significant difference in load on the first clock signal line L1 and the second clock signal line L2, which may affect the display quality of the display panel. Therefore, in this embodiment, the first and second signal lines are arranged to overlap both the first and second conductive blocks 91 and 92, which helps reduce the difference in coupling capacitance formed between the first and second signal lines and the conductive blocks.

[0050] In this embodiment, the arrangement direction of the first conductive block 91 and the second conductive block 92 is consistent with the extension direction of the first clock signal line L1 and the second clock signal line L2, and both extend along the first direction D1. Optionally, along the direction perpendicular to the plane of the substrate 00, the total number of first conductive blocks 91 and second conductive blocks 92 overlapping with the first clock signal line L1 is the same as the total number of first conductive blocks and second conductive blocks 92 overlapping with the second clock signal line L2, so as to further reduce the difference in coupling capacitance between the first clock signal line L1 and the second clock signal line L2.

[0051] Continue to refer Figure 6 In an optional embodiment of the present invention, the edges of the first clock signal line L1 and the second clock signal line L2 that are opposite to each other along the second direction D2 are both located between the edges of the first conductive block 91 and the second conductive block 92 that are opposite to each other along the second direction D2, and the second direction D2 intersects with the first direction D1.

[0052] In this embodiment, the first conductive block 91 and the second conductive block 92 are arranged along the first direction D1, the first clock signal line L1 and the second clock signal line L2 extend along the first direction D1, and the first conductive block 91 and the second conductive block 92 both include two opposite sides along the second direction D2. When the first clock signal line L1 and the second clock signal line L2 overlap with the first conductive block 91 and the second conductive block 92 along a direction perpendicular to the plane where the substrate 00 is located, the embodiment of the present invention further defines that the orthographic projection of the first clock signal line L1 and the second clock signal line L2 on the plane where the substrate 00 is located is located between the two opposite sides of the first conductive block 91 and the second conductive block 92 along the second direction D2. This is conducive to better controlling the overlapping area of ​​the first clock signal line L1 and the second clock signal line L2 with the first conductive block 91 and the second conductive block 92 respectively, thereby better controlling the load of the first clock signal line L1 and the second clock signal line L2 and reducing the load difference between the two.

[0053] Continue to refer Figure 6 In an optional embodiment of the present invention, the first conductive block 91 and the second conductive block 92 have the same shape and size. This embodiment is described using the example of a rectangular structure for the first conductive block 91 and the second conductive block 92, but does not limit the actual structure of the first conductive block 91 and the second conductive block 92. Thus, the first conductive block 91 and the second conductive block 92 can be formed using the same specifications and dimensions, which helps simplify the manufacturing process of the first conductive block 91 and the second conductive block 92. In addition, when the shapes and sizes of the first conductive block 91 and the second conductive block 92 are set to be the same, the coupling capacitance formed by the overlap between the first clock signal line L1 and the first conductive block 91 and the second conductive block 92 and the coupling capacitance formed by the overlap between the second clock signal line L2 and the first conductive block 91 and the second conductive block 92 will be more consistent, thereby further reducing the difference in coupling capacitance between the first clock signal line L1 and the second clock signal line L2, thereby reducing the load difference between the two, improving the consistency of the scan signal output by the shift register unit VSR to the scan line X, and improving the overall display effect of the display panel.

[0054] Optionally, in the display panel provided by an embodiment of the present invention, the line widths of the first clock signal line L1 and the second clock signal line L2 are equal along the second direction D2. Since the first clock signal line L1 and the second clock signal line L2 are located in the same film layer and are made of the same material, and the shapes and sizes of the first conductive block 91 and the second conductive block 92 are set to be the same, and the first clock signal line L1 and the second clock signal line L2 are set within the range defined by two opposing sides of the first conductive block 91 and the second conductive block 92 along the second direction D2, this is more conducive to reducing the coupling capacitance difference and load difference between the first clock signal line L1 and the second clock signal line L2, and is more conducive to improving the overall display effect of the display panel.

[0055] Figure 7 FIG. 1 is a schematic diagram showing a layout of the shift register unit VSR and the conductive block 90 provided in an embodiment of the present invention. Figure 8 The figure shows a circuit diagram of a single shift register unit VSR provided by an embodiment of the present invention. This embodiment is described by taking the shift register unit VSR as an example including 8 transistors and two capacitors, but does not limit the actual structure of the shift register unit VSR. In some other embodiments of the present invention, the shift register unit VSR can also be embodied as other circuit structures. In this embodiment, the shift register unit VSR includes 8 transistors M1 to M8, and the corresponding connected signal terminals include the first clock signal terminal CK, the second clock signal terminal XCK, the input terminal IN, the first voltage terminal VGH, the second voltage terminal VGL, and the output terminal OUT. The two capacitors are capacitors C1 and C2. Optionally, the first clock signal terminal CK is electrically connected to the first clock signal line L1, and the second clock signal terminal XCK is electrically connected to the second clock signal line L2. Figure 8 The layout of each device is illustrated correspondingly in the embodiment.

[0056] Please refer to Figure 7 and Figure 8 This embodiment shows two shift registers arranged along the first direction D1, and shows a complete first conductive block 91 and a partial structure of two second conductive blocks 92 located on both sides of the first conductive block 91 along the first direction D1. It can be seen that the areas of the two second conductive blocks 92 located on both sides of the first conductive block 91 are half of the area of ​​the entire second conductive block 92, and the entire structure of the second conductive block 92 is not shown, only half of it is shown. For the relative position relationship between the second conductive block 92 and the two adjacent shift registers, please refer to Figure 8 The positional relationship between the first conductive block 91 and two adjacent shift registers.

[0057] Please refer to Figure 7In an optional embodiment of the present invention, along a direction perpendicular to the plane of the substrate 00, the same first conductive block 91 partially overlaps with two shift register units VSR arranged adjacent to each other along the first direction D1, and the same second conductive block 92 partially overlaps with two shift register units VSR arranged adjacent to each other along the first direction D1.

[0058] Specifically, when the embodiment of the present invention introduces the first conductive block 91 and the second conductive block 92, the first conductive block 91 partially overlaps with two adjacent shift register units VSR, for example Figure 8 In the illustrated embodiment, the first conductive block 91 overlaps with the lower half of the upper shift register unit VSR and the upper half of the upper shift register unit VSR. In this partial area, both the upper shift register unit VSR and the lower shift register unit VSR are connected to the second clock signal line via the second clock signal terminal XCK. Using the same first conductive block 91 for connection facilitates reducing the number of first conductive blocks 91 in the display panel. Similarly, when the second conductive block 92 overlaps with two adjacent shift register units VSR, both shift register units VSR corresponding to the same second conductive block 92 need to be connected to the first clock signal terminal CK, and then connected to the first clock signal line via the first clock signal terminal CK. In this case, the same second conductive block 92 can be used to achieve electrical connection to the first clock signal terminals CK of the two adjacent shift register units VSR, which also facilitates reducing the number of second conductive blocks 92 in the display panel and simplifying the display panel manufacturing process.

[0059] Continue to refer Figure 7 and Figure 8 In an optional embodiment of the present invention, in at least some of the shift register units VSR, along a direction perpendicular to the plane of the substrate 00 , the same shift register unit VSR partially overlaps with the adjacent first conductive block 91 and second conductive block 92 .

[0060] Specifically, the same shift register unit VSR must be electrically connected to the first clock signal line L1 through the first clock signal end, and also needs to be electrically connected to the second clock signal line L2 through the second clock signal end. When the same shift register unit VSR is electrically connected to the adjacent first conductive block 91 and the second conductive block 92, the electrical connection with one of the first clock signal line L1 and the second clock signal line L2 can be achieved through the first conductive block 91, and the electrical connection with the other of the first clock signal line L1 and the second clock signal line L2 can be achieved through the second conductive block 92. Therefore, it is possible to achieve electrical connection between the shift register unit VSR and the first clock signal line L1 and the second clock signal line L2, and to isolate the influence of the shift register unit VSR on the load of the first clock signal line L1 and the second clock signal line L2 through the first conductive block 91 and the second conductive block 92, which is beneficial to improving the overall display effect of the display panel.

[0061] Continue to refer Figure 7 and Figure 8 In an optional embodiment of the present invention, the shift register unit VSR includes multiple transistors. Along a direction perpendicular to the plane of the substrate 00, the number of transistors overlapping with the same first conductive block 91 is m, and the number of transistors overlapping with the same second conductive block 92 is n, where m=n.

[0062] This embodiment is explained by taking the example of the same shift register unit VSR including 8 transistors. When the number of transistors overlapping the same first conductive block 91 and the same second conductive block 92 with the shift register unit VSR is set to be the same, the influence of the transistors on the electrical signals of the first conductive block 91 and the second conductive block 92 is more consistent, so that the influence of the first conductive block 91 and the second conductive block 92 on the first clock signal line L1 and the second clock signal line L2 will be more consistent, which is conducive to avoiding the problem of large load difference between the first clock signal line L1 and the second clock signal line L2 due to the influence of different electrical signals. Therefore, it is more conducive to reducing the load difference between the first clock signal line L1 and the second clock signal line L2, and is more conducive to avoiding the problem of display horizontal stripes between different pixel rows, which is conducive to improving the display effect of the display panel.

[0063] Continue to refer Figure 4 , and make appropriate reference Figure 7In an optional embodiment of the present invention, adjacent first conductive blocks 91 and second conductive blocks 92 correspond to the N-th, N+1-th, and N+2-th shift register units VSR. Along a direction perpendicular to the plane of the substrate 00, the first conductive block 91 overlaps with s transistors in the N-th shift register unit VSR and overlaps with p transistors in the N+1-th shift register unit VSR; the second conductive block 92 overlaps with s transistors in the N+1-th shift register unit VSR and overlaps with p transistors in the N+2-th shift register unit VSR; wherein N≥1, s≥1, and p≥1.

[0064] The positions of the s transistors overlapping with the first conductive block 91 in the N-stage shift register unit VSR are the same as the positions of the s transistors overlapping with the second conductive block 92 in the N+1-stage shift register unit VSR;

[0065] The positions of the p transistors overlapping the first conductive block 91 in the (N+1) stage shift register unit VSR are the same as the positions of the p transistors overlapping the second conductive block 92 in the (N+2) stage shift register unit VSR.

[0066] Specifically, the same first conductive block 91 can be divided into a first part overlapping with the N-th shift register unit VSR and a second part overlapping with the N+1-th shift register unit VSR, and the same second conductive block 92 can be divided into a third part overlapping with the N+1-th shift register unit VSR and a fourth part overlapping with the N+2-th shift register unit VSR, wherein the first part overlaps with the s transistors in the N-th shift register unit VSR, and the third part overlaps with the s transistors in the N+1-th shift register unit VSR. The positions of the s transistors corresponding to the first part in the shift register unit VSR are the same as the positions of the s transistors corresponding to the third part in the shift register unit VSR. The shift register units VSR at the same position have the same effect on the first conductive block 91 and the second conductive block 92. Similarly, the second part overlaps with the p transistors in the N+1-th shift register unit VSR, and the fourth part overlaps with the p transistors in the N+2-th shift register unit VSR. The positions of the p transistors corresponding to the second part in the shift register unit VSR are the same as the positions of the p transistors corresponding to the fourth part in the shift register unit VSR. The shift register units VSR at the same position have the same effect on the first conductive block 91 and the second conductive block 92. Such a setting is more conducive to improving the film response of the shift register unit VSR to the first conductive block 91 and the second conductive block 92. For example, the coupling capacitance between the first conductive block and the second conductive block and the shift register unit VSR tends to be consistent, and then the coupling capacitance formed by the first clock signal line L1 and the first conductive block and the second conductive block is consistent with the coupling capacitance formed by the second clock signal line L2 and the first conductive block and the second conductive block, and then the load of the first clock signal line L1 and the second clock signal line L2 tends to be consistent, which is more conducive to avoiding the problem of display horizontal stripes caused by the large difference in load between the first clock signal line L1 and the second clock signal line L2, and is therefore more conducive to improving the display effect of the display panel.

[0067] Based on the same inventive concept, the present invention further provides a display device, referring to FIG. Figure 9 FIG2 is a top view of a display device provided by an embodiment of the present invention. The display device 200 includes the display panel 100 in any of the above embodiments.

[0068] The display device 200 provided in the embodiment of the present invention can be any electronic device with a display function, such as a touch screen display, a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention. For details, please refer to the detailed description of the display panel 100 in the above embodiments, and will not be repeated in this embodiment.

[0069] It is understandable that Figure 9 The rounded rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of the present invention, the display device 200 may also be rectangular, circular, elliptical or any other feasible shape, and the present invention does not specifically limit this.

[0070] It can be seen from the above embodiments that the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0071] In the display panel and display device provided by the present invention, a scan drive circuit is provided in the non-display area, and the cascaded shift register unit in the scan drive circuit is electrically connected to the scan line in the display area for providing a scan signal to the scan line. The non-display area is also provided with a first clock signal line and a second clock signal line, and the shift register unit is electrically connected to the first clock signal line and the second clock signal line, respectively, to obtain the clock signal through the first clock signal line and the second clock signal line. Under the control of the signal provided by the first clock signal line and the second clock signal line to the shift register unit, the pixel rows in the display area are turned on row by row. If the load difference between the first clock signal line and the second clock signal line is large, the difference between the clock signals transmitted by the first clock signal line and the second clock signal line will also be large, which may cause abnormal horizontal stripes to appear between different pixel rows. To this end, an embodiment of the present invention sets the first clock signal line and the second clock signal line on the second auxiliary conductive layer, and sets the first clock signal line and the second clock signal line to be electrically connected to the conductive blocks on the first auxiliary conductive layer to reduce the difference in coupling capacitance between the first clock signal line and the second clock signal line and other film layers, thereby helping to reduce the difference in driving ability of the signals on the first clock signal line and the second clock signal line to the scanning line, helping to avoid the problem of abnormal horizontal stripes display between different display rows on the display panel, and helping to improve the overall display effect of the display panel and the display device.

[0072] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area at least partially surrounding the display area; The non-display area includes a scan driving circuit, and the scan driving circuit at least includes a plurality of cascaded shift register units; The display area includes a plurality of scan lines, and the output end of the shift register unit of each stage is connected to at least one of the scan lines; The non-display area further includes a first clock signal line and a second clock signal line, and the shift register unit is electrically connected to the first clock signal line and the second clock signal line respectively; The display panel includes a substrate, a transistor layer arranged on the substrate, a first auxiliary conductive layer and a second auxiliary conductive layer, the first auxiliary conductive layer is located on the side of the transistor layer facing away from the substrate, and the second auxiliary conductive layer is located on the side of the first auxiliary conductive layer facing away from the substrate; the transistor in the shift register unit is located in the transistor layer of the display panel, the first clock signal line and the second clock signal line are located in the second auxiliary conductive layer, and are electrically connected to the transistor layer through the first auxiliary conductive layer respectively; the first auxiliary conductive layer includes a conductive block, and the first clock signal line and the second clock signal line overlap with the conductive block along a direction perpendicular to the plane of the substrate.

2. The display panel according to claim 1, wherein: In the non-display area, the conductive blocks include first conductive blocks and second conductive blocks alternately arranged along a first direction, the first conductive blocks and the second conductive blocks are insulated, and the first direction is an extension direction of the first clock signal line and the second clock signal line; Each of the first conductive blocks is electrically connected to the first clock signal line through a different first conductive via, and each of the second conductive blocks is electrically connected to the second clock signal line through a different second conductive via.

3. The display panel according to claim 2, wherein: Along a direction perpendicular to the plane of the substrate, the first clock signal line overlaps both the first conductive block and the second conductive block, and the second clock signal line overlaps both the first conductive block and the second conductive block.

4. The display panel according to claim 2, wherein: The edges of the first clock signal line and the second clock signal line that are opposite to each other along the second direction are both located between the edges of the first conductive block and the second conductive block that are opposite to each other along the second direction, and the second direction intersects the first direction.

5. The display panel according to claim 2, wherein: The first conductive block and the second conductive block have the same shape and size.

6. The display panel according to claim 2, wherein: Along a direction perpendicular to the plane of the substrate, the same first conductive block partially overlaps with two adjacent shift register units arranged along the first direction, and the same second conductive block partially overlaps with two adjacent shift register units arranged along the first direction.

7. The display panel according to claim 6, wherein: In at least some of the shift register units, along a direction perpendicular to the plane where the substrate is located, the same shift register unit partially overlaps with the adjacent first conductive block and the adjacent second conductive block.

8. The display panel according to claim 6, wherein: The shift register unit includes multiple transistors. Along a direction perpendicular to the plane of the substrate, the number of transistors overlapping with the same first conductive block is m, and the number of transistors overlapping with the same second conductive block is n, where m=n.

9. The display panel according to claim 8, wherein: Adjacent first and second conductive blocks correspond to the Nth, N+1th, and N+2th stage shift register units, and along a direction perpendicular to the plane of the substrate, the first conductive block overlaps with s transistors in the Nth stage shift register unit and overlaps with p transistors in the N+1th stage shift register unit; the second conductive block overlaps with s transistors in the N+1th stage shift register unit and overlaps with p transistors in the N+2th stage shift register unit; wherein N≥1, s≥1, and p≥1; The positions of the s transistors overlapping with the first conductive block in the N-stage shift register unit are the same as the positions of the s transistors overlapping with the second conductive block in the N+1-stage shift register unit; The positions of the p transistors overlapping with the first conductive block in the (N+1) stage shift register unit are the same as the positions of the p transistors overlapping with the second conductive block in the (N+2) stage shift register unit.

10. A display device, characterized in that: The display panel comprises any one of claims 1 to 9.

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