Mainboard of multi-path server, server and power-on control method

Abstract

The disclosure provides a motherboard of a multi-path server, a server and a power-on control method. The motherboard of the multi-path server comprises: N groups of processors, each group of processors comprising M processors; a power module configured to provide power to the N groups of processors; a timing manager connected with the power module and the N groups of processors, wherein the timing manager is configured to control the power module to supply power to the N groups of processors; and any two processors of the N*M processors are connected with each other through at least one bus. All processors are interconnected through the bus, so that the processors can communicate without additional chips, reducing communication delay caused by the chips, and the chips do not need to be considered during the power-on process of the server, so that the power-on process is simpler and easier to implement.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of computer technology, and more particularly to a motherboard for a multi-channel server, a server, and a power-on control method. Background Technology

[0002] As users demand increasingly higher server performance, multi-processor servers are becoming more and more common. Multi-processor servers offer advantages over traditional single-processor servers in terms of both computing performance and reliability. Multi-processor servers typically refer to servers with four, eight, or more processors, meaning that communication between these processors has a significant impact on server performance.

[0003] A typical multi-processor server consists of multiple motherboard substrates. The processors on different motherboard substrates usually need to communicate with each other using a co-operative chip (CC). This not only increases the communication latency between processors, but also makes it difficult for the server to power on. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a motherboard, server, and power-on control method for a multi-channel server. It provides a structure for a multi-channel server that does not require a CC chip, which can not only reduce communication latency between different processors, but also make the power-on process of the server simple and easy to implement.

[0005] In a first aspect, at least one embodiment of this disclosure provides a motherboard for a multi-processor server, comprising: N groups of processors, each group of processors comprising M processors, wherein N is an integer greater than or equal to 4 and M is an integer greater than or equal to 1; a power supply module configured to provide power to the N groups of processors; and a timing manager connected to the power supply and the N groups of processors, wherein the timing manager is configured to control the power supply module to supply power to the N groups of processors; wherein any two processors among the N*M processors are interconnected via at least one bus.

[0006] In at least one embodiment provided according to the first aspect, the motherboard of the multi-way server further includes: N motherboard substrates, wherein any two motherboard substrates among the N motherboard substrates are separate, some motherboard substrates among the N motherboard substrates are separate, or all motherboard substrates among the N motherboard substrates belong to the same circuit board; wherein each motherboard substrate among the N motherboard substrates is provided with a group of processors among N processors.

[0007] In at least one embodiment provided according to the first aspect, the timing manager includes a first timing management module and N second timing management modules, wherein the first timing management module is connected to the N second timing management modules; the N second timing management modules correspond to N groups of processors respectively, wherein each of the N second timing management modules is connected to M corresponding processors.

[0008] In at least one embodiment provided according to the first aspect, each of the N motherboard substrates is further provided with one of the N second timing management modules, and the first timing management module is disposed outside the N motherboard substrates.

[0009] In at least one embodiment provided according to the first aspect, the motherboard of the multi-way server further includes: a clock module connected to N*M processors, configured to receive a first clock signal from a first processor among the N*M processors, expand the first clock signal into N*M-1 second clock signals, and send the N*M-1 second clock signals to the N*M-1 processors other than the first processor, wherein the first clock signal and the second clock signal are synchronized in time.

[0010] In at least one embodiment provided according to the first aspect, when all the motherboard substrates in the N motherboard substrates belong to the same circuit board, the bus between any two processors among the N*M processors is implemented by wiring; when there are discrete motherboard substrates in the N motherboard substrates, the processors on the discrete motherboard substrates are interconnected by detachable cables.

[0011] In at least one embodiment provided according to the first aspect, the motherboard of the multi-way server further includes: N*M first DIP switches, each connected to N*M processors, wherein each of the N*M first DIP switches is configured to set a corresponding processor number.

[0012] In at least one embodiment provided according to the first aspect, the motherboard of the multi-way server further includes: N second DIP switches, respectively disposed on N motherboard substrates, wherein each of the N second DIP switches is configured to set the number of a corresponding motherboard substrate.

[0013] In at least one embodiment provided according to the first aspect, the motherboard of the multi-channel server further includes N sideband signal interfaces and N timing signal interfaces, wherein the N sideband signal interfaces are respectively disposed on N motherboard substrates, and the N timing signal interfaces are respectively disposed on N motherboard substrates, wherein each of the N sideband signal interfaces is connected to a first timing management module via a cable or trace, the N timing signal interfaces are connected to the first timing management module via a cable or trace, and each of the N timing signal interfaces is connected to a corresponding second timing management module via a trace.

[0014] In at least one embodiment provided according to the first aspect, the motherboard of the multi-way server further includes: N*M voltage regulation modules connected to the power module and the timing manager, and respectively connected to N*M processors, configured to convert the voltage output by the power module into the voltage required by the processor according to the control of the timing manager.

[0015] In at least one embodiment provided according to the first aspect, the motherboard of the multi-way server further includes: N*M first crystal oscillators, each connected to N*M processors; and N*M second crystal oscillators, each connected to N*M processors; wherein the frequency of the N*M first crystal oscillators is higher than the frequency of the N*M second crystal oscillators.

[0016] In at least one embodiment provided according to the first aspect, at least one bus employs an inter-chip global memory interconnect (xGMI) bus, a compute fast link (CXL) bus, a super-path interconnect (UPI) bus, or an external memory interface (xHMI) bus.

[0017] In at least one embodiment provided according to the first aspect, any one of the N*M processors further includes an external device interface that supports a high-speed PCIe bus for peripheral component interconnection and supports at least one of the following: Serial Advanced Technology Attachment (SATA) bus, xHMI bus, xGMI bus, CXL bus, UPI bus, external 10 Gigabit Ethernet (XGBE) bus, and graphics output protocol (GOP) bus.

[0018] In a second aspect, at least one embodiment of this disclosure provides a multi-way server, including: a motherboard of a multi-way server as described in any of the first aspects.

[0019] Thirdly, at least one embodiment of this disclosure provides a power-on control method, applied to a motherboard of a multi-processor server as described in any of the first aspects or to a multi-processor server as described in the second aspect. The method includes: a timing manager receiving sleep state signals sent by N*M processors; in response to determining that the N*M processors have entered sleep state, the timing manager sending a normal voltage control signal to a power module, the normal voltage control signal instructing the power module to output a normal operating voltage to the N*M processors; the timing manager receiving a first power supply normal signal sent by the N*M processors, the first power supply normal signal indicating that the power supply to the processor is at a normal operating voltage; the timing manager sending a second power supply normal signal to the N*M processors, the second power supply normal signal instructing the processor to confirm the power supply status; in response to receiving the confirmation signal, the timing manager sending a power reset signal to the power module, the power reset signal instructing the power module to reset, and the confirmation signal instructing the processor to confirm that the power supply status is normal; and the timing manager receiving reset completion signals sent by the N*M processors to complete the power-on process.

[0020] In at least one embodiment provided according to the third aspect, before receiving the sleep state signal sent by N*M processors, the method further includes: in response to power-on, a timing manager sends a wake-up voltage control signal to a power module, the wake-up voltage control signal being used to instruct the power module to output a wake-up voltage to the N*M processors, wherein the wake-up voltage causes the N*M processors to enter a logical wake-up state of abnormal operation.

[0021] In at least one embodiment provided according to the third aspect, the timing manager receives sleep state signals sent by N*M processors, including: N second timing management modules receiving sleep state signals sent by each of the corresponding M processors; after each of the N second timing management modules receives the M sleep state signals, the N second timing management modules send a signal indicating that the processor is in a sleep state to a first timing management module; after the first timing management module receives the signal indicating that the processor is in a sleep state sent by each of the N second timing management modules, the first timing management module determines that the N*M processors have entered a sleep state.

[0022] In at least one embodiment provided according to the third aspect, the timing manager sends a normal voltage control signal to the power module, including: sending a first indication signal of normal operating voltage from a first timing management module to N second timing management modules; in response to the first indication signal, each of the N second timing management modules sends M first enable signals to the power module, the first enable signals indicating that the power module outputs a normal operating voltage, and each of the M first enable signals corresponds to a processor.

[0023] In at least one embodiment provided according to the third aspect, the timing manager sends a wake-up voltage control signal to the power module, including: a first timing management module sending a second indication signal of the wake-up voltage to N second timing management modules; in response to the second indication signal, each of the N second timing management modules sends M second enable signals to the power module, the second enable signals indicating that the power module outputs a wake-up voltage, and each of the M second enable signals corresponding to a processor.

[0024] This disclosure provides a motherboard for a multi-processor server, the server itself, and a power-on control method. The motherboard of the multi-processor server includes: N groups of processors, each group comprising M processors, where N is an integer greater than or equal to 4, and M is an integer greater than or equal to 1; a power supply module configured to provide power to the N groups of processors; and a timing manager connected to the power supply and the N groups of processors, wherein the timing manager is configured to control the power supply module to supply power to the N groups of processors; wherein any two processors among the N*M processors are interconnected via at least one bus. This bus interconnection eliminates the need for an additional CC chip for communication between processors, reducing communication latency caused by the CC chip. Furthermore, the power-on process is simplified and easier to implement as the CC chip is not considered during server power-on. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 A block diagram of an interface for a processor provided in at least one embodiment of the present disclosure is shown;

[0027] Figure 2 A schematic diagram of a motherboard 200 of a dual-socket server provided in at least one embodiment of the present disclosure is shown;

[0028] Figure 3a and Figure 3b A schematic diagram of a motherboard for a multi-way server provided in at least one embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic diagram showing the connection relationship of processors within the motherboard of a multi-way server provided in at least one embodiment of the present disclosure is shown;

[0030] Figure 5A schematic diagram of the processor and clock module on the motherboard of a multi-channel server provided in at least one embodiment of the present disclosure is shown;

[0031] Figure 6 A schematic diagram of a motherboard for a multi-way server provided in at least one embodiment of the present disclosure is shown;

[0032] Figure 7 A flowchart of a power-on control method provided in at least one embodiment is shown;

[0033] Figures 8a-8d The power-on process of the processor in the motherboard of an eight-way server provided in at least one embodiment of the present disclosure is illustrated. Specific Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “coupled,” “connected,” or “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0036] This disclosure discloses a motherboard for a multi-processor server, the server itself, and a power-on control method. The motherboard of the multi-processor server includes: N groups of processors, each group comprising M processors, where N is an integer greater than or equal to 4, and M is an integer greater than or equal to 1; a power supply module configured to provide power to the N groups of processors; and a timing manager connected to the power supply and the N groups of processors, wherein the timing manager is configured to control the power supply module to supply power to the N groups of processors. Any two processors among the N*M processors are interconnected via at least one bus, where the at least one bus is an Inter-Chip Global Memory Interconnect (xGMI) bus, a Compute Fast Link (CXL) bus, a Hyper-Interconnect (UPI) bus, or an External Memory Interface (xHMI) bus. This bus interconnection eliminates the need for an additional CC chip for communication between processors, reducing communication latency caused by the CC chip. Furthermore, the power-on process is simplified and easier to implement as the CC chip is not considered during server power-on.

[0037] The embodiments and examples of this disclosure will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the same reference numerals in the drawings denote the same components, parts, or elements.

[0038] Figure 1 A block diagram of an interface for a processor 100 provided in at least one embodiment of the present disclosure is shown.

[0039] For example, in some examples, processor 100 may include eight interfaces: interface G0, interface G1, interface G2, interface G3, interface G4, interface G5, interface P6, and interface P7. These eight interfaces can all be differential bus interfaces, such as supporting PCIe (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), XGBE (10 Gigabit Ethernet), etc., with each interface supporting at least one type of bus. The interfaces of processor 100 may also support xGMI (Socket / Inter-Chip Global Memory Interconnect), UPI (Ultra Path Interconnect), CXL (Compute Express Link), and other buses that can be used for connections between processors. Optionally, the interfaces of processor 100 may also be general-purpose external device interfaces, such as general-purpose external memory interfaces.

[0040] For example, interfaces G0-G3 support PCIe and xGMI buses; interfaces G4 and G5 support PCIe, SATA, and xGMI buses; interface P6 supports PCIe and SATA buses; and interface P7 supports PCIe, SATA, and XGBE buses. Interfaces supporting xGMI buses can be used to interconnect processors for communication. Interfaces supporting PCIe buses can be used to connect PCIe devices; for example, interface P6 can connect PCIe Gen 5 devices and is compatible with PCIe Gen 4-Gen 1 devices. Interfaces supporting SATA buses can be used to connect SATA devices, such as SATA hard drives. Interfaces supporting XGBE buses can be used to connect Ethernet.

[0041] like Figure 1 As shown, processor 100 has six interfaces for interconnection between processors. All interfaces can connect to PCIe devices, and four interfaces can connect to SATA devices, along with one Ethernet interface. The six xGMI interfaces ensure sufficient connectivity when processor 100 needs to connect to other processors. Furthermore, the placement of the interfaces within processor 100 can be configured, providing more options for external cabling and motherboard routing, increasing product flexibility and adaptability to various scenarios. For example, the eight interfaces of processor 100 can be evenly distributed across its four edges, or evenly distributed across its two edges, or all eight interfaces can be located on one edge. For instance, four interfaces could be on the left edge and the other four on the right edge, or four interfaces could be on the north / top edge and the other four on the south / bottom edge.

[0042] Figure 1 Arrows indicate the directions "south" and "north" in the diagram. Understandably, the directions in the diagram are only for illustrative purposes to indicate where the processor is located. Figure 1 The direction indicated in the text does not represent or limit the direction in which the processor 100 is used. It is still understandable that... Figure 1 The positions of the eight interfaces in the processor 100 are for illustrative purposes only and do not limit their actual locations.

[0043] Figure 2 A schematic diagram of a motherboard 200 of a dual-socket server provided in at least one embodiment of the present disclosure is shown.

[0044] For example, the motherboard 200 of a dual-socket server includes a motherboard substrate 201, a first processor socket 204, a second processor socket 205, memory interfaces 206, 207, 208, and 209, processor interfaces 210, 211, 212, 213, 214, 215, and 216, a high-speed processor 217, 220, 221, 222, 223, 224, 225, and 226, and a high-speed processor 227. The processor interfaces are represented by solid lines in the diagram. The diagram also includes dashed lines filled with diagonal stripes, representing the first processor 202 and the second processor 203. For example, the first processor 202 is located inside the first processor socket 204 in the diagram; this does not mean that the first processor 202 is a component of the first processor socket 204, but rather illustrates the relative positional relationship between the first processor 202 and the first processor socket 204. For example, in practical applications, the first processor 202 is "inserted" into the first processor socket 204, which securely connects the first processor 202 to the motherboard 201. The proportions of the first processor 202 and the first processor socket 204 in the diagram do not represent an actual proportional relationship. The relationship between the second processor 203 and the second processor socket 205 is the same as that between the first processor 202 and the first processor socket 204, and will not be repeated here. The first processor 202 and the second processor 203 are the same processor, for example, both using... Figure 1 The processor 100 is included in the present disclosure. In the embodiments of this disclosure, the processor may be a Central Processing Unit (CPU), such as an x86 architecture CPU. Processor sockets are used to house the processors; a first processor socket 204 is used to house a first processor 202, and a second processor socket 205 is used to house a second processor 203. The first processor 202 and the second processor 203 are not soldered or otherwise fixedly connected to the motherboard substrate 201; that is, the first processor 202 and the second processor 203 can be removed from the processor sockets or the processors can be replaced. It is understood that the embodiments of this disclosure do not limit the shape, size, and appearance of the first processor socket 204 and the second processor socket 205.

[0045] Memory interfaces 206 and 207 are connected to the first processor socket 204, and memory interfaces 208 and 209 are connected to the second processor socket 205. Processor interfaces 210-217 are connected to the first processor socket 204, and processor interfaces 220-217 are connected to the second processor socket 205. Memory interfaces 206-207 and processor interfaces 210-217 can be connected to the first processor 202 via the first processor socket 204. Memory interfaces 208-209 and processor interfaces 220-227 can be connected to the second processor 203 via the second processor socket 205. Memory interfaces 206-209 can be connected to the first processor socket 204 and the second processor socket 205 via traces in the motherboard substrate 201. Similarly, processor interfaces 210-217 and 220-227 can be connected to the first processor socket 204 and the second processor socket 205 via traces in the motherboard substrate 201. Alternatively, memory interfaces 206-209, processor interfaces 210-217, and processor interfaces 220-227 can also be located on the processor socket or connected to the processor socket via a detachable cable.

[0046] Each of memory interfaces 206-209 can connect to a group of memory, such as 6 or 12 memory modules as a group. Optionally, memory interfaces 206-209 can connect to 6 or 12 dual in-line memory module slots.

[0047] Each of processor interfaces 210-217 and 220-227 supports a high-speed PCIe bus for peripheral component interconnect. Each of these interfaces also supports at least one of the following: Serial Advanced Technology Attachment (SATA) bus, external memory interface (xHMI) bus, and 10 Gigabit Ethernet (XGBE) bus. In other words, each processor interface supports more than two buses, as detailed below. Figure 1 The interface settings for the processor.

[0048] The structure of the motherboard for a dual-socket server has been described above. The motherboard for a multi-socket server, according to at least one embodiment of this disclosure, will now be described with reference to the accompanying drawings.

[0049] In some embodiments, the motherboard of a multi-processor server includes: N groups of processors, each group of processors including M processors, where N is an integer greater than or equal to 4 and M is an integer greater than or equal to 1; a power supply module configured to provide power to the N groups of processors; and a timing manager connected to the power supply and the N groups of processors, wherein the timing manager is configured to control the power supply module to supply power to the N groups of processors; wherein any two processors among the N*M processors are interconnected via at least one bus, and the at least one bus adopts a global memory interconnect (xGMI) bus, a compute fast link (CXL) bus, a superpath interconnect (UPI) bus, or an external memory interface (xHMI) bus.

[0050] Multi-socket server motherboards can accommodate two or more processors, such as 2, 4, 8, 16, 32, or even more. As previously discussed, dual-socket server motherboards typically house both processors on the same motherboard substrate. However, with the increasing number of processors, using a single motherboard substrate for multiple processors results in a very large motherboard area. This places higher demands on motherboard design and manufacturing, and excessively large motherboards are not conducive to practical applications.

[0051] The multi-processor servers provided in the embodiments of this disclosure mainly target three-way servers, four-way servers, eight-way servers, sixteen-way servers, and thirty-two-way servers, that is, the number of processors in the multi-processor server is an integer greater than or equal to 3. For example, N equals 3, 4, 5, 6, 8, 16, etc., and M equals 1, 2, 4, etc. For example, an eight-way server can have 4 groups of processors, in which case M equals 2 and N equals 4. A four-way server can have 4 groups of processors, in which case M equals 1 and N equals 4. Furthermore, N equals 3 and M equals 1, indicating a total of 3 groups of processors, with each group having 1 processor.

[0052] In this embodiment, the processors are grouped, which facilitates motherboard layout design and better management of processor power-on processes. For example, the connection method of the processor interfaces can be standardized, such as... Figure 4 .

[0053] In some embodiments, the grouping of processors may correspond to motherboard substrates. For example, the motherboard of a multi-processor server further includes: N motherboard substrates, wherein any two motherboard substrates among the N motherboard substrates are separate, some motherboard substrates among the N motherboard substrates are separate, or all motherboard substrates among the N motherboard substrates belong to the same circuit board; wherein each of the N motherboard substrates is provided with a group of processors among the N processors.

[0054] In this embodiment, the motherboard substrate can be independent or only part of a circuit board. For example, if N motherboard substrates belong to the same circuit board, all processors can be interconnected using traces on the circuit board. If the N motherboard substrates are independent, i.e., discrete, processors on different motherboard substrates need to be connected via cables, while processors on the same motherboard substrate can be connected via traces. Similarly, if some of the N motherboard substrates belong to the same circuit board and others belong to other circuit boards, processors on the same circuit board can be connected via traces, while processors on different circuit boards need to be connected via cables. For example, an eight-way server motherboard can include four motherboard substrates, each with two processors. A four-way server motherboard can include two motherboard substrates, each with two processors. Thus, both the eight-way server motherboard and the four-way server motherboard can use, for example... Figure 2 The motherboard of the dual-socket server in this embodiment is used as the motherboard substrate. Similarly, the motherboard of the eight-socket server can be implemented using the motherboard of the four-socket server. For example, the motherboard of the eight-socket server can also include two motherboard substrates, each with four processors, while the motherboard of the four-socket server can include only one motherboard substrate, each with four processors. In this case, the motherboard of the eight-socket server can be implemented using two four-socket server motherboards. Optionally, the motherboard of the multi-socket server can also be implemented using the motherboard of the single-socket server, for example, by splicing multiple motherboards of single-socket servers and connecting them according to the needs of the multi-socket server. The motherboard of the single-socket server is not described in this document. It is understood that the single-socket server can adopt existing architectures and is not limited here.

[0055] In this embodiment, the power supply module is connected to N motherboard substrates to power N*M processors. The power supply module can be located outside the N motherboard substrates; for example, a separate motherboard substrate may be used to house other components besides the processors. Alternatively, the power supply module can be located on one of the N motherboard substrates. The power supply module provides a power interface, allowing external power cables to be connected to it. Similarly, the timing manager can also be located outside the N motherboard substrates, for example, on the same dedicated motherboard substrate as the power supply module. The timing manager can also be located on one of the N motherboard substrates.

[0056] Optionally, any two processors among the N*M processors are interconnected via at least one bus. To achieve interconnection between any two processors, at least one bus connection is required; that is, each processor needs to provide an interface for interconnection. For example... Figure 1In a processor interface, when four processors need to be interconnected, any two processors can be interconnected via one or two buses. When eight processors need to be interconnected, only one bus can be used. With a processor having many interfaces, more buses can be selected for interconnection, thereby improving communication performance between processors.

[0057] Figure 3a and Figure 3b A schematic diagram of a motherboard for a multi-way server provided in at least one embodiment of the present disclosure is shown.

[0058] exist Figure 3a The following description uses a multi-processor server motherboard 300, which includes two motherboard substrates and four processors, as an example. Figure 3a As shown, the motherboard 300 of the multi-processor server includes a motherboard substrate 310, a motherboard substrate 320, processors 311, 312, 321, and 322, a power module 330, and a timing manager 330. Processors 311 and 312 are mounted on the motherboard substrate 310, and processors 321 and 322 are mounted on the motherboard substrate 320. The power module 330 is connected to the motherboard substrates 310 and 320. The timing manager 340 is connected to the processors 311, 312, 321, 322, and the power module 330. The power module 330 supplies power to the timing manager 340, processors 311, 312, 321, and 322, as well as external devices. Any two processors among processors 311, 312, 321, and 322 are connected via one or two buses; the connection method can be found in [reference needed]. Figure 4 The description.

[0059] Figure 4 A schematic diagram showing the connection relationship of processors within the motherboard of a multi-way server provided in at least one embodiment of the present disclosure is shown.

[0060] To more clearly illustrate the connection methods between processors, Figure 4 Only the motherboard substrate and processor are shown; other components or interfaces are not shown. This does not mean that other components or interfaces are not present. Furthermore, for ease of understanding, Figure 4 The motherboard of the multi-way server in the text only includes four processors. Understandably, eight-way servers, sixteen-way servers, and servers with more processors can also use this configuration. Figure 4 The processor connection method is shown.

[0061] For example, in Figure 4In the multi-processor server, the motherboard 400 includes a motherboard substrate 410 and a motherboard substrate 420. Motherboard substrate 410 has processors 411 and 412. Motherboard substrate 420 has processors 421 and 422. Both motherboard substrate 410 and motherboard substrate 420 can adopt... Figure 2 The motherboard 200 of the dual-socket server shown is implemented. Motherboard substrate 410 and motherboard substrate 420 can be on the same plane, i.e., motherboard substrate 410 and motherboard substrate 420 are the same circuit board. Motherboard substrate 410 and motherboard substrate 420 can also be on different planes, for example, motherboard substrate 410 and motherboard substrate 420 are stacked, and motherboard substrate 410 and motherboard substrate 420 belong to different layers. Interface G2 of processor 411 is connected to interface G0 of processor 421; interface G0 of processor 411 is connected to interface G2 of processor 412; interface G5 of processor 411 is connected to interface G4 of processor 422; interface G0 of processor 412 is connected to interface G2 of processor 422; interface G4 of processor 412 is connected to interface G5 of processor 421; and interface G2 of processor 421 is connected to interface G0 of processor 422. Figure 4 There are no connected interfaces available for connecting external devices, such as PCIe devices, SATA devices, network devices, etc. Besides... Figure 4 In addition to the connection methods in the diagram, two processors can be interconnected using any numbered interface, such as interface G1, interface G4, etc. As long as an interface supports the xHMI bus, it can be used as the interface for processor interconnection.

[0062] Figure 4 The processors 411 and 412 on the motherboard substrate 410 can be connected by wiring, and the processors 411 on the motherboard substrate 410 and 421 on the motherboard substrate 420 can be connected by cables.

[0063] Figure 4 Any two processors can be connected via a single bus (or a set of buses), for example, processors 411 and 412, or processors 421 and 422, can all be connected via a single bus. Optionally, any two processors can also be connected via two buses. When a large number of external devices are not required, the data communication performance between processors can be improved by increasing the number of buses used for the processor interconnect. Optionally, at least one bus of the processor interconnect can be an inter-chip global memory interconnect (xGMI) bus, a compute fast link (CXL) bus, a super-path interconnect (UPI) bus, or an external memory interface (xHMI) bus.

[0064] The motherboard of the multi-processor server provided in at least one embodiment of the present disclosure interconnects the processors in the motherboard via an xHMI bus, eliminating the need for an additional CC chip. This reduces latency caused by communication between processors via a CC chip and also lowers costs.

[0065] Optionally, any one of the N*M processors also includes an external device interface that supports a high-speed PCIe bus for peripheral component interconnection and at least one of the following: Serial Advanced Technology Attachment (SATA) bus, external memory interface (xHMI) bus, external 10 Gigabit Ethernet (XGBE) bus, and graphics output protocol (GOP) bus. For example, processor 311 also includes five external device interfaces, which also support the xHMI bus, etc.

[0066] Optionally, the timing manager includes a first timing management module and N second timing management modules, wherein the first timing management module is connected to the N second timing management modules; the N second timing management modules correspond to N groups of processors, and each of the N second timing management modules is connected to M corresponding processors. In this embodiment, the first timing management module and the second timing management module can be implemented using a Complex Programmable Logic Device (CPLD).

[0067] Optionally, each of the N motherboard substrates is further provided with one of the N second timing management modules, while the first timing management module is located outside the N motherboard substrates.

[0068] For example, Figure 3b The timing manager 340 includes a first timing management module 341, a second timing management module 342, and a second timing management module 343. The first timing management module 341 is located outside the motherboard substrate 310 and motherboard substrate 320, the second timing management module 342 is located on the motherboard substrate 310, and the second timing management module 343 is located on the motherboard substrate 320. The second timing management module 342 is connected to processors 311 and 312, and the second timing management module 343 is connected to processors 321 and 322. All three timing management modules are connected to the power module 330.

[0069] Optionally, the motherboard of the multi-processor server also includes a power button interface, connected to a first timing management module and N second timing management modules. The power button interface is connected to a power button. When the power button is triggered (e.g., pressed), a power-on signal is sent to the first timing management module and the N second timing management modules via the power button interface. For example, the power button interface is respectively connected to... Figure 3b The first timing management module 341, the second timing management module 342, and the second timing management module 343 are connected.

[0070] Optionally, the motherboard of the multi-processor server also includes: N*M voltage regulation modules, connected to the power supply module and timing manager, and each connected to N*M processors, configured to convert the voltage output by the power supply module into the voltage required by the processors under the control of the timing manager. For example, Figure 3b The motherboard substrate 310 is provided with two voltage regulation modules, which are respectively connected to processor 311, processor 312, power module 330 and second timing management module 342; the motherboard substrate 320 is also provided with two voltage regulation modules, which are respectively connected to processor 321, processor 322, power module 330 and second timing management module 343.

[0071] Optionally, the motherboard of the multi-processor server also includes: N*M first DIP switches, each connected to one of the N*M processors, wherein each of the N*M first DIP switches is configured to set the number of a corresponding processor. The motherboard of the multi-processor server also includes: N second DIP switches, each disposed on one of the N motherboard substrates, wherein each of the N second DIP switches is configured to set the number of a corresponding motherboard substrate. For example, motherboard substrate 310 has a total of 3 DIP switches; the second DIP switches are used to set the number of motherboard substrate 310, and the two first DIP switches are connected to processors 311 and 312 respectively, and are used to set the numbers of processors 311 and 312 respectively. Through the DIP switches, the timing manager can distinguish the source of the signal, such as which motherboard substrate and which processor it comes from.

[0072] Optionally, the motherboard of the multi-processor server also includes N sideband signal interfaces and N timing signal interfaces. The N sideband signal interfaces are respectively disposed on N motherboard substrates, and the N timing signal interfaces are also disposed on N motherboard substrates. Each of the N sideband signal interfaces is connected to a first timing management module via a cable or trace, and each of the N timing signal interfaces is connected to the first timing management module via a cable or trace. Furthermore, each of the N timing signal interfaces is connected to a corresponding second timing management module via a trace. For example, motherboard substrate 320 has one sideband signal interface and one timing signal interface, both of which are connected to the first timing management module 341 via traces or cables. The sideband signal interfaces are used to transmit signals that do not require real-time transmission, such as the serial number information of each processor. The timing signal interfaces are used to transmit timing signals for processor power-on, which have high timeliness requirements.

[0073] Optionally, each of the N motherboard substrates may also include a USB (Universal Serial Bus) interface / slot, a network interface, and low-speed external interfaces. Low-speed interfaces may include, for example, an M.2 interface, an interface for a Baseboard Management Controller (BMC), or a 350 Ethernet interface.

[0074] Optionally, the motherboard of the multi-processor server further includes a clock module connected to N*M processors, configured to receive a first clock signal from a first processor among the N*M processors, expand the first clock signal into N*M-1 second clock signals, and send the N*M-1 second clock signals to the other N*M-1 processors besides the first processor, wherein the first clock signal and the second clock signals are synchronized in time. In some embodiments, the first clock signal is generated by the first processor. For example, the first processor receives an initial clock signal from an external source, and generates first clock signals with different frequencies / periods based on the initial clock signal. For instance, the first processor is connected to a 48MHz crystal oscillator, and generates a 100MHz clock signal based on the 48MHz clock signal and outputs it to the clock module, thereby the clock module outputs, for example, seven 100MHz clock signals.

[0075] Figure 5 A schematic diagram of the processor and clock module on the motherboard of a multi-channel server provided in at least one embodiment of the present disclosure is shown.

[0076] Figure 5 Continue Figure 3a and Figure 3bTake the processor in the example. To highlight the relationship between the processor and the clock module, Figure 5 Only show Figure 3a and Figure 3b The processor is shown, but other devices are not. Figure 5 In this embodiment, processors 311, 312, 321, and 322 are all connected to the clock module 500. Processor 311 serves as the main processor and has a clock interface through which a first clock signal is input. Processor 311 outputs the first clock signal to the clock module 500. The clock module 500 generates three second clock signals based on the first clock signal and outputs these three second clock signals to processors 312, 321, and 322 respectively. In this embodiment, the first and second clock signals are synchronized clock signals, or can be understood as the same time signal.

[0077] For example, clock module 500 is a clock expansion chip that can expand the input clock signal into multiple clock signals, and the expanded clock signals are synchronized with the input clock signal in time. Therefore, processors 311, 312, 321, and 322 are synchronized in time, eliminating the need for additional time synchronization operations.

[0078] Optionally, the input to processor 311 can also be an initial clock signal. Processor 311 then generates a first clock signal based on the initial clock signal. The initial clock signal may be out of sync with the first clock signal, but the first clock signal and the second clock signal are synchronized in time. In this way, processors 311, 312, 321, and 322 all operate using the first clock signal, thus ensuring time synchronization between processors.

[0079] Optionally, the motherboard of the multi-processor server also includes: N*M first crystal oscillators, each connected to N*M processors; and N*M second crystal oscillators, each connected to N*M processors; wherein the frequency of the N*M first crystal oscillators is higher than the frequency of the N*M second crystal oscillators.

[0080] For example, Figure 5The processor 311 includes crystal oscillator interfaces 501 and 502, and the processor 312 includes crystal oscillator interfaces 503 and 504. Similarly, processors 321 and 322 also include two crystal oscillator interfaces (crystal oscillator interfaces 505, 506, 507, and 508). Crystal oscillator interfaces 501 and 503 are connected to low-frequency crystal oscillators, while crystal oscillator interfaces 502 and 504 are connected to high-frequency crystal oscillators. Crystal oscillator interfaces 501 and 503 are connected to different crystal oscillators. Optionally, crystal oscillator interfaces 501 and 503 can also be connected to the same crystal oscillator. In this embodiment, the low-frequency crystal oscillator can be a 32kHz crystal oscillator, and the high-frequency crystal oscillator can be a 48MHz crystal oscillator.

[0081] Figure 6 A schematic diagram of a motherboard for a multi-way server provided in at least one embodiment of the present disclosure is shown.

[0082] Apart from Figure 3a , Figure 3b and Figure 5 In addition to the components already described, the motherboard substrate 310 also includes DIP switches 610, 611, and 612, a sideband communication interface 601, a timing communication interface 603, two 32KTXAL crystal oscillators, and two 48MXTAL crystal oscillators. The motherboard substrate 320 also includes DIP switches 620, 621, and 622, a sideband communication interface 602, a timing communication interface 604, two 32KTXAL crystal oscillators, and two 48MXTAL crystal oscillators. The sideband communication interface 601, timing communication interface 603, sideband communication interface 602, and timing communication interface 604 are connected to the first timing management module 341. DIP switch 610 is used to set the number of the motherboard substrate 310, DIP switch 620 is used to set the number of the motherboard substrate 320, DIP switch 611 is used to set the number of the processor 311, DIP switch 612 is used to set the number of the processor 312, DIP switch 621 is used to set the number of the processor 321, and DIP switch 622 is used to set the number of the processor 322. For example, DIP switches 611, 612, 621, and 622 can be set to 8 numbers from 000 to 111, which use binary encoding. DIP switches 610 and 620 can be set to 4 numbers from 00 to 11.

[0083] At least one embodiment of this disclosure also provides a multi-way server, including a motherboard of the multi-way server as described in any of the above embodiments. In some implementations, the multi-way server may further include a chassis, within which a power module, a heat dissipation structure, a storage module, a network card, etc., are disposed. The power module is connected to the motherboard of the multi-way server to provide voltage to the motherboard. The storage module may be a PCIe memory, a SATA memory, etc., and can serve as an external device to the motherboard, connected via an interface on the motherboard. The heat dissipation structure can dissipate heat from the motherboard and other components within the chassis, thereby improving the operation of the multi-way server. The network card can be directly inserted into a slot on the motherboard. The outer surface of the chassis may be provided with various interfaces, such as a power interface, a display interface, a storage device interface, a test device interface, a USB interface, audio input and audio output interfaces, etc.

[0084] At least one embodiment of this disclosure also provides a power-on control method, applied to the motherboard of a multi-processor server in any of the above embodiments or the multi-processor server in the above embodiments. The method includes: in response to receiving a power-on signal, N*M processors send a sleep state signal to a timing manager; in response to determining that N*M processors have entered a sleep state, the timing manager controls a power supply module to output a normal operating voltage to the N*M processors; after the N*M processors sense the normal operating voltage, they send a first power supply normal signal to the timing controller, the first power supply normal signal indicating that the processor's power supply is at a normal operating voltage; in response to receiving the first power supply normal signal, the timing manager sends a second power supply normal signal to the N*M processors, the second power supply normal signal indicating that the processor confirms the power supply status; in response to receiving a confirmation signal, the timing manager sends a power reset signal to the power supply module, causing the power supply module to reset, the confirmation signal indicating that the processor confirms that the power supply status is normal; after a preset time period after the power supply module completes the reset, the N*M processors send a reset completion signal to the timing manager to complete the power-on.

[0085] Figure 7 A flowchart of a power-on control method provided in at least one embodiment is shown.

[0086] like Figure 7 As shown, the power-on control method 700 includes the following steps:

[0087] Step S701: The timing manager receives sleep state signals from N*M processors.

[0088] In step S702, in response to determining that N*M processors have entered sleep state, the timing manager sends a normal voltage control signal to the power module. This normal voltage control signal instructs the power module to output normal operating voltage to the N*M processors.

[0089] In step S703, the timing manager receives the first power supply normal signal sent by N*M processors. The first power supply normal signal indicates that the power supply of the processor is at the normal operating voltage.

[0090] Step S704: The timing manager sends a second power supply normal signal to N*M processors, instructing the processors to confirm the power supply status. Step S705: In response to receiving the confirmation signal, the timing manager sends a power reset signal to the power module. The power reset signal instructs the power module to reset, and the confirmation signal instructs the processors to confirm that the power supply status is normal. Step S706: The timing manager receives reset completion signals from the N*M processors to complete the power-on process.

[0091] The following is based on Figure 3b The power-on process of the processor is described using the timing manager 340 in the motherboard 300 of a multi-processor server as an example.

[0092] When the motherboard 300 of the multi-processor server is powered on, the processor and timing manager can receive the power-on signal. For example, the power module 330 of the motherboard 300 is connected to the power supply, but simply connecting the power supply does not mean that the devices on the motherboard 300 have been powered on. In particular, the processor needs to go through a certain process before it can be powered on.

[0093] In some embodiments, after the motherboard is powered on, in response to the power-on of the motherboard of the multi-processor server, the timing manager controls the power module to output wake-up voltages to N*M processors. These wake-up voltages cause the N*M processors to enter a logical wake-up state that is not operating normally. For example, in response to power-on, the timing manager sends a wake-up voltage control signal to the power module, which instructs the power module to output wake-up voltages to the N*M processors, wherein the wake-up voltages cause the N*M processors to enter a logical wake-up state that is not operating normally.

[0094] For example, after the power module 330 of the motherboard 300 is connected to the DC power supply, the timing manager 340 sends a wake-up voltage enable signal to the power module 330, causing the power module 330 to simultaneously provide wake-up voltage to processors 311, 312, 321, and 322. This wake-up voltage can cause processors 311, 312, 321, and 322 to enter an abnormal logical wake-up state, such as a soft shutdown state. The wake-up voltage can be the voltage of the S5 power supply.

[0095] In some embodiments, the timing manager sends a wake-up voltage control signal to the power module, including: a first timing management module sending a wake-up voltage indication signal to N second timing management modules; in response to the wake-up voltage indication signal, each of the N second timing management modules sends M wake-up voltage enable signals to the power module, the wake-up voltage enable signals being used to instruct the power module to output a wake-up voltage, and each of the M wake-up voltage enable signals corresponding to a processor.

[0096] For example, after the motherboard 300 is connected to the DC power line, both the second timing management module 342 and the second timing management module 343 send a wake-up voltage enable signal to the power module 330, so that the power module 330 simultaneously provides wake-up voltage to the processors 311, 312, 321 and 322.

[0097] In some embodiments, after the power module stably outputs the wake-up voltage, the power module sends a wake-up voltage power supply normal signal to the timing manager. For example, the power module 330 determines that the wake-up voltage output is stable, such as 1ms, after the output wake-up voltage has exceeded a preset duration. After the timing manager receives all wake-up voltage power supply normal signals, it sends a logical wake-up signal to all processors, causing the processors to complete logical wake-up. The number of wake-up voltage power supply normal signals is the same as the number of processors. For example, the timing manager 340 simultaneously sends the RSMRST_L signal to processors 311, 312, 321, and 322.

[0098] For example, after the power module 330 stabilizes the output wake-up voltage, it sends a normal power supply signal for the wake-up voltage to the second timing management module 342 and the second timing management module 343. The second timing management module 342 and the second timing management module 343 then transmit this normal power supply signal to the first timing management module 341. After receiving the two normal power supply signals for the wake-up voltage, the first timing management module 341 sends an RSMRST_L signal to the processors 311 and 312 through the second timing management module 342, and sends an RSMRST_L signal to the processors 321 and 322 through the second timing management module 343.

[0099] During step S701, the timing manager 340 receives sleep state signals from N*M processors. In response to receiving a power-on signal, the N*M processors send sleep state signals to the timing manager 340. For example, the power-on signal can be triggered by a power button, similar to the power button on a computer. When the power button is pressed by the user, a rising or falling edge signal is generated, which is the power-on signal. The power button can be connected to the timing manager via a power button interface. The timing manager first receives the power-on signal and then passes it through to the processors. For example, the timing manager 340 receives the power-on signal and then passes it through to processors 311, 312, 321, and 322. For example, when the first timing management module 341 receives the power-on signal, it passes the power-on signal through the second timing management module 342 and the second timing management module 343. Then, the second timing management module 342 passes the power-on signal through the processor 311 and the processor 312, and the second timing management module 343 passes the power-on signal through the processor 321 and the processor 322.

[0100] After receiving the power-on signal, the processor sends a sleep state signal to the timing manager 340. In this embodiment, the sleep state signal can be a high-level signal of SLP_S3 and SLP_S5. For example, after receiving the power-on signal, processors 311, 312, 321, and 322 will respectively send a sleep state signal to the timing manager (e.g., ...). Figure 3a The timing manager 340 in the middle sends a signal to enter sleep mode. Or, as... Figure 3b As shown, processors 311 and 312 send sleep state signals to the second timing management module 342, and processors 321 and 322 send sleep state signals to the second timing management module 343. The second timing management module 343 then sends the sleep state signals of processors 321 and 322 to the first timing management module 341. After receiving all the sleep state signals, the timing manager determines that all processors have entered sleep state. This sleep state can also be called standby state, hibernation state, etc.

[0101] In some embodiments, each of the N*M processors sends a sleep state signal to a second timing management module on its motherboard substrate; after each of the N second timing management modules receives M sleep state signals, it sends a signal indicating that the processor is in a sleep state to a first timing management module; after the first timing management module receives the signal indicating that the processor is in a sleep state from each of the N second timing management modules, it determines that the N*M processors have entered a sleep state. For example, the second timing management module 342 merges two sleep state signals from processors 311 and 312 into one signal and sends it to the first timing management module 341, and the second timing management module 343 merges two sleep state signals from processors 321 and 322 into one signal and sends it to the first timing management module 341.

[0102] In step S702, in response to determining that N*M processors have entered a sleep state, the timing manager sends a normal voltage control signal to the power module. This normal voltage control signal instructs the power module to output a normal operating voltage to the N*M processors. For example, after receiving four sleep state signals from processors 311, 312, 321, and 322, the timing manager 340 controls the power module 330 to output a normal operating voltage to processors 311, 312, 321, and 322. In some implementations, the timing manager outputs an enable signal for the normal operating voltage or sends a normal voltage control signal to the power module, thereby causing the power module to output the normal operating voltage to all processors. In this embodiment, the normal operating voltage is, for example, the voltage of the S0 power supply.

[0103] In some implementations, a first timing management module sends a normal operating voltage indication signal to N second timing management modules. In response to the normal operating voltage indication signal, each of the N second timing management modules sends M normal operating voltage enable signals to the power supply module. These enable signals instruct the power supply module to output a normal operating voltage, and each of the M enable signals corresponds to a processor. In response to the M first enable signals, the power supply module outputs a normal operating voltage to the M processors corresponding to those signals. For example, a first timing management module 341 sends a normal operating voltage indication signal to second timing management modules 342 and 343. The second timing management modules 342 and 343 then send two enable signals to the power supply module 330, indicating the output normal operating voltage, thereby causing the power supply module 330 to output normal voltage to processors 311, 312, 321, and 322.

[0104] In step S703, the timing manager receives first power-on-completion signals from N*M processors. These first power-on-completion signals indicate that the processors are powered at their normal operating voltage. For example, processors 311, 312, 321, and 322 send normal operating voltage power-on-completion signals to the timing manager 340. Alternatively, processors 311 and 312 send normal operating voltage power-on-completion signals to the second timing management module 342, and processors 321 and 322 send normal operating voltage power-on-completion signals to the second timing management module 343. The second power-on-completion signal may be, for example, a "power good" signal.

[0105] In step S704, the timing manager sends a second power-on signal to N*M processors. This second power-on signal instructs the processors to acknowledge the power supply status. For example, after receiving four first power-on signals, the timing manager 340 sends a second power-on signal to processors 311, 312, 321, and 322. Alternatively, after receiving four first power-on signals, the first timing management module 341 sends a second power-on signal to the second timing management module 342 and the second timing management module 343, which then transmit the second power-on signal to processors 311, 312, 321, and 322.

[0106] After receiving the second power supply normal signal, N*M processors will send an acknowledgment signal to the timing manager if the current power supply status is correct.

[0107] In step S705, in response to receiving the acknowledgment signal, the timing manager sends a power reset signal to the power module. The acknowledgment signal indicates to the processor that the power supply status is normal. The power reset signal instructs the power module to reset. For example, after receiving the power reset signal, power module 330 will reset.

[0108] In step S706, the timing manager receives reset completion signals from N*M processors to complete power-on. After sensing the power module reset, the N*M processors send a reset completion signal to the timing manager after a preset duration. For example, if the preset duration is 1ms, then 1ms after the power module 330 resets, processors 311, 312, 321, and 322 send a reset completion signal to the timing manager 340. Alternatively, processors 311, 312, 321, and 322 send a reset completion signal to the first timing management module 341 via the second timing management module 342 and the second timing management module 343. It is understood that a power module reset does not necessarily mean a power outage.

[0109] The above section described the power-on process for processors in a four-way server using the processors and timing manager as examples. Understandably, this method can also be extended to eight-way or more servers. For instance, in an eight-way server, only the number of second timing management modules and the corresponding number of processors increases; however, the power-on process for each processor remains the same as that of a four-way server.

[0110] Figures 8a-8d The power-on process of the processor in the motherboard of an eight-way server provided in at least one embodiment of the present disclosure is illustrated.

[0111] The eight-way server includes eight processors: CPU0, CPU1, CPU2, ..., and CPU7. The main CPLD is the first timing management module, and CPLD0-CPLD3 are the second timing management modules. CPLD0-CPLD3 are mounted on four motherboard substrates, which are not shown in the diagram. The main CPLD is connected to CPLD0-CPLD3. CPLD0 is connected to CPU0 and CPU1, CPLD1 is connected to CPU2 and CPU3, CPLD2 is connected to CPU4 and CPU5, and CPLD3 is connected to CPU6 and CPU7.

[0112] exist Figure 8aIn the process, after the main CPLD is powered on, it sends wake-up voltage indication signals for CPU0 and CPU1 to CPLD0, wake-up voltage indication signals for CPU2 and CPU3 to CPLD1, wake-up voltage indication signals for CPU4 and CPU5 to CPLD2, and wake-up voltage indication signals for CPU6 and CPU7 to CPLD3. Consequently, CPLD0 sends S5 power enable signals for CPU0 and CPU1 to the power module, CPLD1 sends S5 power enable signals for CPU2 and CPU3 to the power module, CPLD2 sends S5 power enable signals for CPU4 and CPU5 to the power module, and CPLD3 sends S5 power enable signals for CPU6 and CPU7 to the power module. After the power module supplies the S5 power voltage to each CPU, it feeds back a PG signal (power good signal) to CPLD0-CPLD3. Each of CPLD0-CPLD3 then sends a CPU_S5_PWRGD signal to the main CPLD, as shown in step 801 of the diagram. After receiving all CPU_S5_PWRGD signals, the main CPLD sends the CPU_RSMRST_L signal to CPLD0-CPLD3, as in step 802. CPLD0-CPLD3 then pass this signal through to their respective connected CPUs to complete the CPU wake-up. The identical steps in the diagram represent the same timing stage with no time difference.

[0113] exist Figure 8b In step 803, the power button triggers a power-on signal PWR_BTN to the main CPLD when the power button is pressed. The main CPLD then sends CPU0 / 1_PWR_BTN to CPLD0, CPU2 / 3_PWR_BTN to CPLD1, CPU4 / 5_PWR_BTN to CPLD2, and CPU6 / 7_PWR_BTN to CPLD3. Upon receiving the power-on signal, CPLDs 0-3 pass it through to the corresponding CPU; for example, CPLD0 sends the PWR_BTN signal to CPU0. After each CPU receives the power-on signal, it sends a sleep state signal. For example, the sleep state signal could be a high-level signal output from SLP_S3_L and SLP_S5_L in the diagram. Step 804: CPLD0 receives CPU0_S5, CPU0_S3, CPU1_S5, and CPU1_S3, and sends CPU0 / 1_S5 and CPU0 / 1_S3 signals to the main CPLD to indicate that CPU0 and CPU1 have entered standby mode. CPLD1-CPLD3 perform the same operation as CPLD1.

[0114] exist Figure 8cIn the process, after the main CPLD determines that all CPUs have entered standby mode, it executes step 805, sending the CPU_S0_EN signal to CPLD0-CPLD3. This signal instructs the power module to output the S0 power supply voltage. CPLD0 outputs CPU0_S0_EN and CPU1_S0_EN (simplified as EN in the diagram) to the power module, causing the power module to output the S0 power supply voltage to CPU0 and CPU1. After the power module stabilizes the output of the S0 power supply voltage, it feeds back the PG signal to CPLD0 to indicate that the voltage is being output normally. After receiving the PG signal, CPLD0 sends the CPU0 / 1_S0_PWRGD signal to the main CPLD (step 806). CPLD1-CPLD3 also perform the same operation as CPLD0.

[0115] After the main CPLD receives the CPU0 / 1_S0_PWRGD, CPU2 / 3_S0_PWRGD, CPU4 / 5_S0_PWRGD, and CPU6 / 7_S0_PWRGD signals, step 807 is executed. The main CPLD transmits the CPU_POWERGOOD signal to each CPU via CPLD0-CPLD3. After confirming that the power supply status is normal, CPU0-CPU7 transmit the CPU_PWRGD_OUT signal to the main CPLD via CPLD0-CPLD3. Then, step 808 is executed, where the main CPLD and CPLD0-CPLD3 send the CPU_PWROK signal to each other, and CPLD0-CPLD3 and their connected CPUs also send this signal to each other (mutual sending is shown as a double arrow in the diagram). Connected CPUs also need to send the CPU_PWROK signal to each other. In the diagram, CPU0 SVI3 VR is the voltage regulation module of CPU0, which regulates the operating voltage of CPU0.

[0116] After mutually confirming that the CPU voltage is normal, the main CPLD sends a reset request to the control power module, for example... Figure 8c RST in the middle.

[0117] After a preset time following the power module reset, each CPU performs... Figure 8d In step 809, each CPU resets and sends a RESET_L signal to each other, and sends the signal to the main CPLD via CPLD0-CPLD3, thereby completing the power-on process.

[0118] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0119] It is important to note that the flowcharts and method descriptions in this application are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the given order. Some steps may be performed in parallel, independently of each other, or in another suitable order. Furthermore, words such as "secondly," "then," "next," etc., are not intended to limit the order of steps; these words are merely used to guide the reader through the description of these methods.

[0120] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that connections, arrangements, or configurations must be made in the manner shown in the block diagrams. It should also be noted that in the apparatuses and methods of this application, components or steps can be disassembled and / or recombined. Such disassembly and / or recombination should be considered equivalent solutions to those in this application.

[0121] The following points need to be noted: (1) The accompanying drawings of the embodiments of this disclosure only involve structures related to the embodiments of this disclosure; other structures can be referred to in general design. (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments. The above description is only an exemplary implementation of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A motherboard for a multi-processor server, characterized in that, include: N groups of processors, wherein each group of processors comprises M processors, where N is an integer greater than or equal to 3 and M is an integer greater than or equal to 1. The power module is configured to provide power to the N groups of processors; A timing manager, connected to the power supply and the N groups of processors, wherein the timing manager is configured to control the power supply module to supply power to the N groups of processors; and A clock module, connected to the N*M processors, is configured to receive a first clock signal from a first processor among the N*M processors, expand the first clock signal into N*M-1 second clock signals, and send the N*M-1 second clock signals to the N*M-1 processors other than the first processor, wherein the first clock signal and the second clock signals are synchronized in time. In this configuration, any two processors among the N*M processors are interconnected via at least one bus.

2. The motherboard of the multi-channel server according to claim 1, characterized in that, The motherboard of the multi-way server also includes: N motherboard substrates, wherein any two motherboard substrates are separate; a portion of the motherboard substrates are separate, while another portion belong to the same circuit board; or, all the motherboard substrates in the N motherboard substrates belong to the same circuit board. Each of the N motherboard substrates is equipped with one of the N sets of processors.

3. The motherboard of the multi-channel server according to claim 2, characterized in that, The timing manager includes a first timing management module and N second timing management modules, wherein the first timing management module is connected to the N second timing management modules; The N second timing management modules correspond to the N groups of processors, and each of the N second timing management modules is connected to the corresponding M processors.

4. The motherboard of the multi-channel server according to claim 3, characterized in that, Each of the N motherboard substrates is further provided with one of the N second timing management modules, and the first timing management module is located outside the N motherboard substrates.

5. The motherboard of the multi-channel server according to claim 3, characterized in that, When all the motherboard substrates of the N motherboard substrates belong to the same circuit board, the bus between any two processors among the N*M processors is implemented by wiring; When there are discrete motherboard substrates among the N motherboard substrates, the processors on the discrete motherboard substrates are interconnected by detachable cables.

6. The motherboard of the multi-channel server according to claim 1, characterized in that, The motherboard of the multi-way server also includes: N*M first DIP switches are respectively connected to the N*M processors, wherein each of the N*M first DIP switches is configured to set the number of a corresponding processor.

7. The motherboard of the multi-channel server according to claim 3, characterized in that, The motherboard of the multi-way server also includes: N second DIP switches are respectively disposed on the N motherboard substrates, wherein each of the N second DIP switches is configured to set the number of the corresponding motherboard substrate.

8. The motherboard of the multi-channel server according to claim 3, characterized in that, The motherboard of the multi-channel server also includes N sideband signal interfaces and N timing signal interfaces. The N sideband signal interfaces are respectively disposed on the N motherboard substrates, and the N timing signal interfaces are respectively disposed on the N motherboard substrates. Each of the N sideband signal interfaces is connected to the first timing management module via a cable or wiring. The N timing signal interfaces are connected to the first timing management module via a cable or wiring. Furthermore, each of the N timing signal interfaces is connected to the corresponding second timing management module via a wiring.

9. The motherboard of the multi-channel server according to claim 1, characterized in that, The motherboard of the multi-way server also includes: N*M voltage regulation modules are connected to the power supply module and the timing manager, and are also connected to the N*M processors. They are configured to convert the voltage output by the power supply module into the voltage required by the processors under the control of the timing manager.

10. The motherboard of the multi-channel server according to claim 1, characterized in that, The motherboard of the multi-way server also includes: N*M first crystal oscillators are respectively connected to the N*M processors; and N*M second crystal oscillators are respectively connected to the N*M processors; The frequencies of the N*M first crystal oscillators are higher than the frequencies of the N*M second crystal oscillators.

11. The motherboard of the multi-channel server according to claim 1, characterized in that, The at least one bus adopts the Global Interconnect for Chip (xGMI) bus, Compute Fast Link (CXL) bus, Hyperpath Interconnect (UPI) bus, or External Memory Interface (xHMI) bus.

12. The motherboard of the multi-channel server according to claim 1, characterized in that, Each of the N*M processors also includes an external device interface. The external device interface supports a high-speed PCIe bus for peripheral component interconnection and at least one of the following: Serial Advanced Technology Accessories (SATA) bus, xHMI bus, xGMI bus, CXL bus, UPI bus, external 10 Gigabit Ethernet (XGBE) bus, and graphics output protocol (GOP) bus.

13. A multi-way server, characterized in that, include: The motherboard of the multi-way server as described in any one of claims 1-12.

14. A power-on control method, applied to the motherboard of a multi-channel server as described in any one of claims 1-12 or applied to a multi-channel server as described in claim 13, the method comprising: The timing manager receives sleep state signals from N*M processors; In response to determining that the N*M processors have entered a sleep state, the timing manager sends a normal voltage control signal to the power module, the normal voltage control signal being used to instruct the power module to output a normal operating voltage to the N*M processors; The timing manager receives a first power supply normal signal from the N*M processors, the first power supply normal signal indicating that the processor's power supply is at the normal operating voltage; The timing manager sends a second power supply normal signal to the N*M processors, and the second power supply normal signal instructs the processors to confirm the power supply status; In response to receiving the confirmation signal, the timing manager sends a power reset signal to the power module, the power reset signal instructing the power module to reset, and the confirmation signal instructs the processor to confirm that there is no abnormality in the power supply status; The timing manager receives reset completion signals from the N*M processors to complete the power-on process.

15. The power-on control method according to claim 14, wherein, Before receiving sleep state signals from N*M processors, the method further includes: In response to power-on, the timing manager sends a wake-up voltage control signal to the power module. The wake-up voltage control signal is used to instruct the power module to output a wake-up voltage to the N*M processors, wherein the wake-up voltage causes the N*M processors to enter a non-normal logical wake-up state.

16. The power-on control method according to claim 14, wherein, The timing manager receives sleep state signals from N*M processors, including: N second timing management modules receive the sleep state signal sent by each of the corresponding M processors; After each of the N second timing management modules receives M sleep state signals, the N second timing management modules send a signal to the first timing management module indicating that the processor is in a sleep state. After the first timing management module receives a signal indicating that the processor is in a sleep state from each of the N second timing management modules, the first timing management module determines that the N*M processors have entered a sleep state.

17. The power-on control method according to claim 14, wherein, The timing manager sends a normal voltage control signal to the power module, including: The first timing management module sends a first indication signal of the normal operating voltage to N second timing management modules: In response to the first indication signal, each of the N second timing management modules sends M first enable signals to the power module. The first enable signals are used to indicate that the power module outputs a normal operating voltage, and each of the M first enable signals corresponds to a processor.

18. The power-on control method according to claim 14, wherein, The timing manager sends a wake-up voltage control signal to the power module, including: The first timing management module sends a second indication signal of the wake-up voltage to N second timing management modules; In response to the second indication signal, each of the N second timing management modules sends M second enable signals to the power module. The second enable signals are used to instruct the power module to output a wake-up voltage, and each of the M second enable signals corresponds to a processor.

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