High voltage device and method of manufacturing the same

Abstract

The present application provides a high voltage device and a manufacturing method thereof. The high voltage device comprises a semiconductor layer, a well region, a drift oxide region, a body region, a gate, a source and a drain, and a field plate. The well region has a first conductivity type and is formed in the semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type and is formed in the semiconductor layer, and the body region is connected with the drift region in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer and are located in the body region and the well region respectively. The field plate is formed on and connected to the drift oxide region. The field plate is a conductor with a temperature coefficient not higher than 4 ohm / ℃.

Description

Technical Field

[0001] This invention relates to a high-voltage component and its manufacturing method, and particularly to a high-voltage component with a low temperature coefficient field plate and its manufacturing method. Background Technology

[0002] Figure 1A and Figure 1B A top view and a cross-sectional view of a known power element 100 are shown respectively. Figure 1B show Figure 1A A cross-sectional view of the AA' section. A power element is defined as one where, during normal operation, the voltage applied to the drain is higher than 5V. Generally, a power element has a drift region 12a between the drain and gate (e.g., ...). Figure 1B (As shown in the dashed box), the drain 19 is separated from the body region 16, and the lateral length of the drift region 12a is adjusted according to the operating voltage it withstands during normal operation. Figure 1A and Figure 1B As shown, the power element 100 includes: a well region 12, an insulating structure 13, a body region 16, a gate 17, a source 18, and a drain 19. The well region 12 is N-type and is formed on the substrate 11. The insulating structure 13 is a local oxidation of silicon (LOCOS) structure, defining an operating region 13a, which serves as the primary operating region for the power element 100 during operation. The range of the operating region 13a is... Figure 1A The bold black dashed box in the image illustrates this. To improve the breakdown voltage of power device 100, the length of drift region 12a in the channel direction can be extended, but this increases the on-resistance and reduces the operating speed. Furthermore, the significant difference in N-type impurity concentration between drift region 12a and drain 19, and the voltage difference between their respective coupling voltages exceeding 5V to several hundred volts, limits the breakdown voltage of power device 100, thus restricting its application range and reducing its performance.

[0003] In view of this, the present invention proposes a power element and a method thereof that can improve the breakdown voltage during non-conducting operation, thereby increasing the withstand voltage of the power element 100, reducing the on-resistance, and integrating a field plate with a low temperature coefficient. Summary of the Invention

[0004] In one viewpoint, the present invention provides a high-voltage device comprising: a semiconductor layer formed on a substrate; a well region having a first conductivity type formed in the semiconductor layer; a drift oxide region formed on the semiconductor layer, wherein the drift oxide region is located on a drift region; a body region having a second conductivity type formed in the semiconductor layer, the body region and the drift region being connected in a channel direction; and a gate formed on the semiconductor layer, a portion of the body region being located directly below the gate and connected to the gate, to provide the high-voltage device with a conduction operation... The device includes a reverse current channel in operation; a source and a drain having the first conductivity type, the source and drain being formed in the semiconductor layer, and the source and drain being located in the body region below the gate and the well region away from the body region, respectively; and in the channel direction, the drift region being located in the well region between the drain and the body region, serving as a drift current channel for the high voltage device in the conduction operation; and a field plate formed and connected to the drift oxide region; wherein the field plate is a conductor with a temperature coefficient not higher than 4 ohms / ℃.

[0005] In another viewpoint, the present invention provides a method for manufacturing a high-voltage device comprising: forming a semiconductor layer on a substrate; forming a well region in the semiconductor layer, the well region having a first conductivity type; forming a drift oxide region on the semiconductor layer, wherein a shallow trench isolation region is located on the drift region; forming a body region in the semiconductor layer, the body region being connected to the drift region in a channel direction, the body region having a second conductivity type; and forming a gate on the semiconductor layer, a portion of the body region being located directly below the gate and connected to the gate, so as to... Provides a reverse current path for the high-voltage element in a conduction operation; forms a source and a drain in the semiconductor layer, with the source and drain located in the body region below the gate and the well region away from the body region, respectively, and in the channel direction, the drift region is located in the well region between the drain and the body region, serving as a drift current path for the high-voltage element in the conduction operation; and forms and connects a field plate to the drift oxide region; wherein the field plate is a conductor with a temperature coefficient not higher than 4 ohms / ℃.

[0006] In one embodiment, the drift oxidation region includes a shallow trench isolation (STI) region, a local oxidation of silicon (LOCOS) region, or a chemical vapor deposition (CVD) oxidation region.

[0007] In one embodiment, the field plate has a length in the channel direction and a width in a width direction, and the ratio of the width to the length is 2:100.

[0008] In one embodiment, the field plate is used as a resistive element.

[0009] In one embodiment, the field plate is used as an electrode in a capacitor element.

[0010] In one embodiment, the field plate is electrically connected to the source or the gate, or electrically floating.

[0011] The advantages of this invention are that it can reduce the on-resistance of high-voltage components and increase the breakdown protection voltage of high-voltage components.

[0012] Another advantage of the present invention is that it can integrate the field plate process of the high voltage component with the electrode process of the external resistor or capacitor component, and form the field plate of the high voltage component and the electrode of the external resistor or capacitor component in a single process step without the need for additional process steps.

[0013] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0014] Figure 1A and Figure 1B The diagram shows a cross-sectional view and a top view of a known high-voltage component 100.

[0015] Figure 2A and Figure 2B A cross-sectional view and a top view of a high-voltage component are shown according to an embodiment of the present invention.

[0016] Figure 3A and Figure 3B A cross-sectional view and a top view of a high-voltage component are shown according to another embodiment of the present invention.

[0017] Figure 4A and Figure 4B A cross-sectional view and a top view of a high-voltage control element are shown in another embodiment of the present invention.

[0018] Figures 5A-5H This is a schematic diagram illustrating a method for manufacturing a high-voltage component according to an embodiment of the present invention.

[0019] Explanation of symbols in the diagram

[0020] 100, 200, 300, 400: High-voltage components

[0021] 11, 21, 31, 41: substrate

[0022] 12, 22, 32, 42: Trap Zone

[0023] 12a, 22a, 32a, 42a: Drift Zones

[0024] 13: Insulation structure

[0025] 13a: Operating Area

[0026] 16, 26, 36, 46: body area

[0027] 17, 27, 37, 47: Gate

[0028] 18, 28, 38, 48: Source Pole

[0029] 19, 29, 39, 49: Drain electrode

[0030] 21', 31', 41': Semiconductor layers

[0031] 21a, 31a, 41a: Upper surface

[0032] 21b, 31b, 41b: Lower surface

[0033] 23, 33, 43: Drift oxidation zone

[0034] 25, 35, 45: Field board

[0035] 261, 281: Shielding

[0036] 271: Conductive layer

[0037] 272: Spacer layer

[0038] 273: Dielectric layer

[0039] 282: Lightly doped region

[0040] L: Length

[0041] W: Width Detailed Implementation

[0042] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. The drawings in this invention are illustrative and are primarily intended to illustrate process steps and the hierarchical relationship between layers; shapes, thicknesses, and widths are not drawn to scale.

[0043] Please refer to Figure 2A and Figure 2B The diagram shows a cross-sectional view and a top view of a high-voltage component 200 according to an embodiment of the present invention. Figure 2A and Figure 2BAs shown, the high-voltage device 200 includes: a semiconductor layer 21', a well region 22, a drift oxide region 23, a field plate 25, a body region 26, a gate 27, a source 28, and a drain 29. The semiconductor layer 21' is formed on the substrate 21, and the semiconductor layer 21' is perpendicular to the vertical direction (e.g., ...). Figure 2A As indicated by the solid arrow in the diagram (hereinafter the same), the substrate 21 has an opposing upper surface 21a and a lower surface 21b. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21, for example, by an epitaxial step, or by using a portion of the substrate 21 as the semiconductor layer 21'. The methods of forming the semiconductor layer 21' are well known to those skilled in the art and will not be described in detail here.

[0044] Please continue reading. Figure 2A and Figure 2B Drift oxide region 23 is formed on semiconductor layer 21' and is located in drift region 22a (e.g. Figure 2A (As shown in the dashed box). The well region 22 has a first conductivity type, is formed in the semiconductor layer 21', and in the vertical direction, the well region 22 is located below and connected to the upper surface 21a. The well region 22 is formed, for example, by at least one ion implantation process step. The body region 26 has a second conductivity type, is formed in the well region 22, and in the vertical direction, the body region 26 is located below and connected to the upper surface 21a. The body region 26 and the drift region 22a are in the channel direction (e.g., Figure 2A and Figure 2B The direction of the dashed arrow in the middle is indicated (the same applies below) connecting above.

[0045] Gate 27 is formed on the upper surface 21a of semiconductor layer 21'. Viewed from the top, gate 27 is approximately along the width direction (e.g., ...). Figure 2B As indicated by the solid arrow in the image (hereinafter the same), it is a rectangle extending upwards, and in the vertical direction, a portion of the body region 26 is located directly below and connected to the gate 27 to provide a reverse current path for the high-voltage component 200 during conduction operation. The gate 27 includes a conductive layer 271, a spacer layer 272, and a dielectric layer 273.

[0046] The source 28 and drain 29 have a first conductivity type. In the vertical direction, the source 28 and drain 29 are formed below the upper surface 21a and connected in the upper surface 21a, and the source 28 and drain 29 are respectively located in the channel direction of the gate 27 (e.g., Figure 2A and Figure 2BAs indicated by the dashed arrow in the diagram (the same applies below), the drift region 22a is located in the body region 26 below the body region 26 and in the well region 22 away from the body region 26. In the channel direction, the drift region 22a is located between the drain 29 and the body region 26, separating the drain 29 and the body region 26, and is located in the well region 22 near the upper surface 21a. It serves as a drift current channel for the high-voltage element 200 during conduction operation. (See cross-sectional view) Figure 2A Viewed vertically, source 28 and drain 29 are located below and connected to the upper surface 21a. Field plate 25 is formed and connected to the drift oxide region 23. Field plate 25 is a conductor with a temperature coefficient not exceeding 4 ohms / ℃.

[0047] In one embodiment, the field plate 25 can be used as a low temperature coefficient resistive element outside the high voltage element 200. This saves the process steps of fabricating additional resistive elements and reduces manufacturing costs.

[0048] In one embodiment, the field plate 25 can be used as an electrode in a capacitor element outside the high-voltage component 200. This eliminates the need for additional fabrication steps for the electrode in the capacitor element, reducing manufacturing costs. The capacitor element is, for example, a metal-insulator-polysilicon (MIP) capacitor.

[0049] In one embodiment, the field plate 25 is electrically connected to the source 28 or the gate 27, or electrically floating.

[0050] In one embodiment, the drift oxidation region 23 is a chemical vapor deposition (CVD) oxidation region.

[0051] In one embodiment, such as Figure 2B As shown, the field plate 25 has a length L in the channel direction and a width W in the width direction, and the ratio of width W to length L is 2:100 or 100:2.

[0052] Compared with the prior art, the high-voltage element according to the present invention further includes a drift oxide region and a field plate. When the high-voltage element is in conduction operation, electrically connecting the field plate to an appropriate voltage can concentrate more carriers, thereby reducing the on-resistance. Furthermore, when the high-voltage element is in conduction or non-conduction operation, the electric field applied by the field plate can prevent the electric field from concentrating on the surface near the drain, and the electric field distribution can expand; thus, the breakdown protection voltage can be improved. In addition, since the field plate of the high-voltage element according to the present invention uses a conductor with a relatively low temperature coefficient, in addition to the above advantages, the field plate can also serve as an external resistive element or an electrode in a capacitor element. This saves the process steps of separately manufacturing resistive elements and electrodes in capacitor elements, reducing manufacturing costs.

[0053] It should be noted that the so-called inversion current channel refers to the region under the gate 27 formed by the voltage applied to the gate 27 during the conduction operation of the high voltage element 200, so that the conduction current can pass through. This is well known to those skilled in the art and will not be described in detail here.

[0054] It should be noted that the so-called drift current channel refers to the region through which the conduction current passes in a drifting manner during the conduction operation of the high voltage component 200. This is well known to those skilled in the art and will not be elaborated here.

[0055] It should be noted that the upper surface 21a does not refer to a completely flat plane, but rather to a surface of the semiconductor layer 21'. In this embodiment, for example, the portion of the upper surface 21a that contacts the drift oxide region 24 has a recessed portion.

[0056] It should be noted that the gate 27 includes a conductive layer 271 with conductivity, a dielectric layer 273 connected to the upper surface, and a spacer layer 272 with electrical insulating properties. The dielectric layer 273 is formed on the body region 26 and the well region 22, and is connected to both regions. The conductive layer 271 serves as the electrical contact of the gate 27, and is formed on and connected to all dielectric layers 273. The spacer layer 272 is formed on both sides of the conductive layer 271 to serve as an electrical insulating layer on both sides of the gate 27. This is well known to those skilled in the art and will not be described in detail here.

[0057] It should be noted that the aforementioned "first conductivity type" and "second conductivity type" refer to the doping of semiconductor composition regions (such as, but not limited to, the aforementioned well region, body region, source and drain regions) with impurities of different conductivity types in high voltage components, so that the semiconductor composition regions become the first or second conductivity type (such as, but not limited to, the first conductivity type being N-type and the second conductivity type being P-type, or vice versa). The first conductivity type and the second conductivity type are conductivity types with opposite electrical properties.

[0058] Furthermore, it should be noted that the so-called high-voltage component refers to a component that, during normal operation, applies a voltage higher than a specific voltage, such as 5V, and the channel distance (length of drift region 22a) between the body region 26 and the drain 29 is adjusted according to the operating voltage during normal operation, thus enabling operation at the aforementioned higher specific voltage. This is well known to those skilled in the art and will not be elaborated upon here.

[0059] Figure 3A and Figure 3B A cross-sectional view and a top view of the high-voltage component 300 are shown according to another embodiment of the present invention. This embodiment and... Figure 2A and Figure 2B The difference in this embodiment is that the drift oxide region 33 is a shallow trench isolation (STI) region. The substrate 31, upper surface 31a, lower surface 31b, semiconductor layer 31', well region 32, drift region 32a, field plate 35, body region 36, gate 37, source 38, and drain 39 in this embodiment are similar to... Figure 2A and Figure 2B The substrate 21, upper surface 21a, lower surface 21b, semiconductor layer 21', well region 22, drift region 22a, field plate 25, body region 26, gate 27, source 28 and drain 29 are described in detail here.

[0060] Figure 4A and Figure 4B A cross-sectional view and a top view of a high-voltage control element 400 are shown in another embodiment of the present invention. This embodiment and... Figure 2A and Figure 2B The difference from the previous embodiment is that the drift oxide region 43 in this embodiment is a local oxidation of silicon (LOCOS) region. The substrate 41, upper surface 41a, lower surface 41b, semiconductor layer 41', well region 42, drift region 42a, field plate 45, body region 46, gate 47, source 48, and drain 49 in this embodiment are similar to... Figure 2A and Figure 2B The substrate 21, upper surface 21a, lower surface 21b, semiconductor layer 21', well region 22, drift region 22a, field plate 25, body region 26, gate 27, source 28 and drain 29 are described in detail here.

[0061] Please refer to Figures 5A-5H This is a schematic diagram illustrating a method for manufacturing a high-voltage component 200 according to an embodiment of the present invention. Figure 5A As shown, a semiconductor layer 21' is first formed on a substrate 21. The semiconductor layer 21' is formed on the substrate 21, for example, through an epitaxial step, or as a portion of the substrate 21. The semiconductor layer 21' is formed in the vertical direction (e.g., Figure 5A As indicated by the solid arrow in the diagram (hereinafter the same), the substrate 21 has an opposing upper surface 21a and a lower surface 21b. The manner in which the semiconductor layer 21' is formed is well known to those skilled in the art and will not be described in detail here. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor substrate.

[0062] Next, please refer to Figure 5BFor example, but not limited to, using multiple ion implantation process steps, a first conductive impurity is doped into the semiconductor layer 21' in the form of accelerated ions to form a well region 22. At this time, the drift oxide region 23 has not yet been formed, and the upper surface 21a has not yet been fully defined. The well region 22 is formed in the semiconductor layer 21', and in the vertical direction, the well region 22 is located below and connected to the upper surface 21a.

[0063] Next, please refer to Figure 5C A body region 26 is formed in the well region 22, and in the vertical direction, the body region 26 is located below and connected to the upper surface 21a. The body region 26 has a second conductivity type. The steps of forming the body region 26 include, for example but not limited to, using a photoresist layer 261 formed by a photolithography process as a shield, and doping the well region 22 with a second conductivity type impurity to form the body region 26. In this embodiment, a second conductivity type impurity can be incorporated into the well region 22 in the form of accelerated ions, for example but not limited to, an ion implantation process. Figure 5C As indicated by the straight dashed arrow, the injection is carried out into the trap region 22 to form the body region 26.

[0064] Next, please refer to Figure 5D Dielectric layer 273 and conductive layer 271 are formed on the upper surface 21a of semiconductor layer 21', respectively, for gate 27, and in the vertical direction (e.g. Figure 5D As indicated by the solid arrow in the image (the same applies below), a portion of the body region 26 is located directly below and connected to the gate 27 to provide a reverse current path for the high-voltage element 200 during conduction operation.

[0065] Please see Figure 5E and Figure 2A For example, after forming the dielectric layer 273 and conductive layer 271 of the gate 27, a lightly doped region 282 is formed to provide a conduction channel below the spacer layer 272 when the high-voltage device 200 is in conduction operation; this is because the body region 26 below the spacer layer 272 cannot form a reverse current channel when the high-voltage device 200 is in conduction operation. A method for forming the lightly doped region 282 is, for example, to dope a first conductivity type impurity into the body region 26 to form the lightly doped region 282. In this embodiment, for example, but not limited to, an ion implantation process can be used to implant the first conductivity type impurity in the form of accelerated ions, such as... Figure 5E As indicated by the dashed arrow pointing vertically, the lightly doped region 282 is injected into the body region 26 to form a lightly doped region 282. Since the impurity concentration of the first conductivity type in the lightly doped region 282 is much lower than that in the source 28, the lightly doped region 282 can be ignored in the region where it overlaps with the source 28, and therefore will be omitted in the following figures.

[0066] Please continue reading. Figure 5E .like Figure 5E As shown, in the vertical direction, a source 28 and a drain 29 are formed below and connected to the upper surface 21a. The source 28 and drain 29 are located in the body region 26 below the gate 27 in the channel direction and in the well region 22 away from the body region 26, respectively. In the channel direction, a drift region 22a is located between the drain 29 and the body region 26, near the well region 22 of the upper surface 21a, serving as a drift current channel for the high-voltage element 200 during conduction. The source 28 and drain 29 have a first conductivity type. The steps of forming the source 28 and drain 29 include, for example but not limited to, using a photoresist layer 281 formed by a photolithography process as a shield, and doping the first conductivity type impurities into the body region 26 and the well region 22, respectively, to form the source 28 and drain 29. In this embodiment, the first conductivity type impurities can be introduced in the form of accelerated ions, for example but not limited to, an ion implantation process. Figure 5G As indicated by the straight dashed arrow, the material is injected into the body region 26 and the well region 22 to form the source 28 and the drain 29.

[0067] Next, as Figure 5F As shown, spacer layers 272 are formed outside the side of conductive layer 271 to form gate 27.

[0068] Next, as Figure 5G As shown, the drift oxide region 23 is formed on the semiconductor layer 21' and is located in the drift region 22a (as shown). Figure 5G (As shown in the dashed box in the middle) and connected to the trap region 22. Among them, the drift oxidation region 23 is, for example, a chemical vapor deposition (CVD) oxidation region.

[0069] Next, as Figure 5G As shown, a field plate 25 is formed and connected to the drift oxide region 23. The field plate 25 is a conductor with a temperature coefficient not exceeding 4 ohms / ℃.

[0070] In one embodiment, the field plate 25 can be used as an electrode in a capacitor element outside the high-voltage component 200. This eliminates the need for additional fabrication steps for the electrode in the capacitor element, reducing manufacturing costs. The capacitor element is, for example, a metal-insulator-polysilicon (MIP) capacitor.

[0071] In one embodiment, the field plate 25 is electrically connected to the source 28 or the gate 27, or electrically floating.

[0072] In one embodiment, such as Figure 2BAs shown, the field plate 25 has a length L in the channel direction and a width W in the width direction, and the ratio of width W to length L is 2:100 or 100:2.

[0073] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. Various equivalent variations can be conceived by those skilled in the art within the same spirit of the invention. For example, other process steps or structures, such as a deep well region, can be added without affecting the main characteristics of the component; furthermore, lithography is not limited to photomask technology and may also include electron beam lithography. All such variations can be derived by analogy from the teachings of the present invention. Furthermore, the described embodiments are not limited to individual application and can be combined, for example, but not limited to using two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent variations. Moreover, any embodiment of the present invention does not necessarily achieve all the objectives or advantages; therefore, no claim should be limited thereto.

Claims

1. A high-voltage component, characterized in that, Include: A semiconductor layer is formed on a substrate; A well region having a first conductivity type is formed in the semiconductor layer; A drift oxide region is formed on the semiconductor layer, wherein the drift oxide region is located on a drift region; A body region having a second conductivity type is formed in the semiconductor layer, and the body region and the drift region are connected in a channel direction; A gate is formed on the semiconductor layer, and a portion of the body region is located directly below the gate and connected to the gate to provide a reverse current path for the high voltage device during a conduction operation; A source and a drain, having the first conductivity type, the source and the drain are formed in the semiconductor layer, and the source and the drain are respectively located in the body region below the gate and in the well region away from the body region. In the channel direction, the drift region is located in the well region between the drain and the body region, serving as a drift current channel for the high-voltage element during the conduction operation; and A plate is formed and connected to the drifting oxidation zone; The field plate is a conductor with a temperature coefficient not exceeding 4 ohm / ℃.

2. The high-voltage component as described in claim 1, wherein, The drift oxidation zone includes a shallow trench isolation zone, a regional oxidation zone, or a chemical vapor deposition oxidation zone.

3. The high-voltage component as described in claim 1, wherein, The plate has a length in the channel direction and a width in the width direction, and the ratio of the width to the length is 2:100 or 100:

2.

4. The high-voltage component as described in claim 1, wherein, The plate is used as a resistive element.

5. The high-voltage component as described in claim 1, wherein, This field plate is used as one of the plates in a capacitor element.

6. The high-voltage component as claimed in claim 1, wherein, The field plate is electrically connected to the source or the gate, or electrically floating.

7. A method for manufacturing a high-voltage component, characterized in that, Include: A semiconductor layer is formed on a substrate; A well region is formed in the semiconductor layer, and the well region has a first conductivity type; A body region is formed in the semiconductor layer, the body region is connected to a drift region in a channel direction, and the body region has a second conductivity type; A gate is formed on the semiconductor layer, and a portion of the body region is located directly below the gate and connected to the gate to provide a reverse current path for the high voltage device during a conduction operation; A source and a drain are formed in the semiconductor layer, and the source and the drain are respectively located in the body region below the gate and in the well region away from the body region. In the channel direction, the drift region is located in the well region between the drain and the body region, and is used as a drift current channel for the high voltage element in the conduction operation. The source and the drain have the first conductivity type. A drift oxide region is formed on the semiconductor layer, wherein the drift oxide region is located on the drift region; and A plate is formed and connected to the drifting oxidation zone; The field plate is a conductor with a temperature coefficient not exceeding 4 ohm / ℃.

8. The high-voltage component manufacturing method as described in claim 7, wherein, The drift oxidation zone includes a shallow trench isolation zone, a regional oxidation zone, or a chemical vapor deposition oxidation zone.

9. The high-voltage component manufacturing method as described in claim 7, wherein, The plate has a length in the channel direction and a width in the width direction, and the ratio of the width to the length is 2:100 or 100:

2.

10. The high-voltage component manufacturing method as described in claim 7, wherein, The plate is used as a resistive element.

11. The method for manufacturing high-voltage components as described in claim 7, wherein, This field plate is used as one of the plates in a capacitor element.

12. The high-voltage component manufacturing method as described in claim 7, wherein, The field plate is electrically connected to the source or the gate, or electrically floating.

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