A radio frequency baseband joint fast AGC control system and method

Abstract

The application discloses a kind of radio frequency baseband joint fast AGC control system and method, the system includes: VGA, frequency converter, ADC, digital signal processing module, DAC, DVGA, detector, filter, threshold comparison unit, control selection unit, DVGA error processing unit and VGA error processing unit;Compared with the difference of prior art digital AGC control structure includes: after ADC, increase digital variable gain amplifier (DVGA), increase the ability of digital domain power control;Error processing module is replaced by control selection unit, VGA error processing unit and DVGA error processing unit, according to the size of error control selection is carried out.The application proposes that system is cooperated by VGA loop and DVGA loop, so that VGA control loop works without entering convergent state, reduce the dependence of control process on physical device delay, while reducing AGC convergence time, so that output digital baseband signal is more flat, and have more flexible control ability, adapt to different burst data structure, and the scope of application is wider.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of wireless network communication, and particularly relates to a radio frequency baseband joint fast AGC control system and method. BACKGROUND

[0002] The current wireless communication receiving end automatic gain control mostly adopts a digital AGC structure. Figure 1 As shown in the figure, the radio frequency input signal is converted into a digital baseband signal after sequentially passing through a variable gain amplifier (VGA) of the digital AGC structure, a frequency converter and an analog-to-digital converter (ADC), and the VGA control quantity is obtained through a digital detection, filtering, threshold comparison and error processing digital signal processing process, and then the VGA control quantity is output through a digital-to-analog converter (DAC) to realize closed-loop automatic gain control. The control process can obtain different control response time and digital baseband signal stability by adjusting the VGA control frequency, bandwidth and step size, etc.

[0003] For a burst communication signal, the automatic gain control process must be completed within the preamble time period of the burst signal, and the signal must be stable in the subsequent data segment, which requires a fast response time, such as a WIFI signal requiring the gain control process to be completed within 5.6us. Figure 1 As shown in the figure, the digital AGC control structure includes analog devices such as VGA, frequency converter, ADC and DAC, and also includes digital processing modules such as detection, filtering and error processing, which are limited by the performance level of each physical device in the gain control loop, such as sampling rate, interface transmission rate, device response time, etc. The overall control delay of the control loop may reach us level or even 10us level, and the control delay determines the upper limit of the loop bandwidth, which leads to the fact that the digital AGC loop structure cannot converge within the required time, and the adaptability is greatly reduced. Although the current method can achieve a fast AGC response time by improving the performance level of the device, the cost is high and the economy is poor. SUMMARY

[0004] Therefore, the present application provides a radio frequency baseband joint fast AGC control system and method, which cooperates the VGA loop and the DVGA loop to make the VGA control loop work without entering the convergence state, reduces the dependence of the control process on the physical device delay, and reduces the AGC convergence time.

[0005] To achieve this purpose, the present application adopts the following technical solution: a radio frequency baseband joint fast AGC control system, the system comprising: VGA, frequency converter, ADC, digital signal processing module and DAC.

[0006] The digital signal processing module includes: DVGA, detector, filter, threshold comparison unit, control selection unit, DVGA error processing unit and VGA error processing unit;

[0007] Along the direction of signal transmission, VGA, inverter, ADC, DVGA, detector, filter, threshold comparison unit, control selection unit, DVGA error processing unit and DVGA are connected in sequence to form DVGA automatic gain control loop.

[0008] Along the direction of signal transmission, VGA, inverter, ADC, DVGA, detector, filter, threshold comparison unit, control selection unit, VGA error processing unit, DAC, and VGA are connected in sequence to form the VGA automatic gain control loop.

[0009] The DVGA also features a digital baseband output.

[0010] A radio frequency baseband combined fast AGC control method, the method being based on the aforementioned radio frequency baseband combined fast AGC control system, comprising:

[0011] S1: Radio frequency input signal S RF (t) G is obtained after passing through VGA VGA (n)·S RF (t), where G VGA (n) represents the amplification of the VGA during the nth control, where n≥1, and t represents time;

[0012] S2: Signal G VGA (n)·S RF (t) After passing through the frequency converter and ADC, the ADC sampled digital signal G is obtained. VGA (n)·S BB (t), this signal is then processed by DVGA to obtain the digital baseband signal G. VGA (n)·G DVGA (n)·S BB (t), S BB (t) represents the digital baseband signal obtained after the radio frequency signal passes through the inverter and ADC, G DVGA (n) represents the amplification of the DVGA during the nth control cycle;

[0013] S3: The digital baseband signal is passed through a detector and a filter to obtain the current signal power estimate P(n);

[0014] S4: The power estimate P(n) is compared with the threshold comparison unit to obtain the current estimation error Err(n). Based on the estimation error Err(n) and the current state, the control selection is performed. If the VGA error processing unit is selected, proceed to S5; if the DVGA error processing unit is selected, proceed to S6.

[0015] S5: VGA error processing unit calculates G VGA (n+1) and outputs to VGA through DAC for control, and sets G DVGA (n+1) to 1, directly outputs control DVGA, and returns to S1.

[0016] S6: DVGA error processing unit calculates G DVGA (n+1) and directly outputs control DVGA, and the VGA error processing unit sets G VGA (n+1) to G VGA (n), outputs to VGA through DAC for control, and returns to S1.

[0017] A radio frequency baseband joint fast AGC control method, in S4, the method for controlling selection according to the estimation error Err(n) and the current state is as follows:

[0018] First, two threshold parameters are set: an entering threshold ETH IN and an exiting threshold ETH OUT , and satisfy ETH IN >ETH OUT .

[0019] Then, it is judged: if the current state is the DVGA error processing state, when |Err(n)|>ETH IN , the VGA error processing state is entered, otherwise the current state is maintained; if the current state is the VGA error processing state, when |Err(n)|<ETH OUT , the DVGA error processing state is entered, otherwise the current state is maintained.

[0020] The radio frequency baseband joint fast AGC control system provided by the application provides a new fast AGC architecture, the system cooperates the VGA loop and the DVGA loop, so that the VGA control loop does not need to enter the convergence state when working, reduces the dependence of the control process on the physical device delay, and reduces the AGC convergence time, secondly, the system uses the DVGA to realize higher-precision control results, so that the output digital baseband signal is more stable; in the method, the VGA and the DVGA control selection are not judged by the absolute value of |Err(n)|, but are judged according to the setting of the two control states of the VGA and the DVGA, ETH IN and ETH OUTA set of entry and exit thresholds not only constrains the control range of the DVGA and reduces the requirements for the dynamic range of the ADC, but also prevents the unstable state of frequent switching between the two control modes, thus improving the stability of the control process.

[0021] The system and method disclosed in this application have more flexible control capabilities, can adapt to different burst data structures, and have a wider range of applications. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a digital AGC system in the prior art;

[0023] Figure 2 This is a schematic diagram of the radio frequency baseband combined fast AGC control system structure in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the state transition of the control selection unit in the embodiments of this application;

[0025] Figure 4 This is a diagram showing the power variation of the original received signal during simulated burst transmission in an embodiment of this application.

[0026] Figure 5 This is a graph showing the change in received signal power after simulating burst transmission RF baseband combined with AGC in an embodiment of this application;

[0027] Figure 6 These are the VGA and DVGA control quantities in the simulated burst transmission RF baseband combined AGC in the embodiments of this application; Detailed Implementation

[0028] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

[0029] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0030] One such Figure 2 The radio frequency baseband combined fast AGC control system shown includes: VGA, inverter, ADC, digital signal processing module and DAC; the digital signal processing module includes: DVGA, detector, filter, threshold comparison unit, control selection unit, DVGA error processing unit and VGA error processing unit.

[0031] The system comprises two automatic gain control loops of VGA and DVGA, wherein the VGA automatic gain control loop is connected in sequence along the direction of signal transmission of VGA, frequency converter, ADC, DVGA, detector, filter, threshold comparison unit, control selection unit, VGA error processing unit, DAC and VGA; and the DVGA automatic gain control loop is connected in sequence along the direction of signal transmission of VGA, frequency converter, ADC, DVGA, detector, filter, threshold comparison unit, control selection unit, VGA error processing unit, DAC and VGA.

[0032] The difference between the radio frequency baseband joint AGC control structure and the digital AGC control structure in the prior art is that a digital variable gain amplifier (DVGA) is added after the ADC to increase the ability of digital domain power control; the error processing module is replaced by a control selection unit, a VGA error processing unit and a DVGA error processing unit to control selection according to the size of the error. The VGA error processing unit is affected by the control delay of the physical device, while the DVGA error processing unit is only affected by the digital processing delay, and has a faster response speed. The VGA error processing module and the DVGA error processing module are mutually exclusive, and the control selection module is used to determine which error processing module is currently enabled.

[0033] The control process of the radio frequency baseband joint fast AGC control system is as follows:

[0034] S1: a radio frequency input signal S RF (t) is obtained after passing through the VGA VGA (n)·S RF (t), wherein G VGA (n) represents the gain of the VGA at the n-th control, n≥1, and t represents time;

[0035] S2: the signal G VGA (n)·S RF (t) is obtained after passing through the frequency converter and the ADC VGA (n)·S BB (t), and the signal is obtained as a digital baseband signal G VGA (n)·G DVGA (n)·S BB (t), S BB (t) represents the signal obtained after the radio frequency signal passes through the frequency converter and the ADC, G DVGA (n) represents the gain of the DVGA at the n-th control;

[0036] S3: the current signal power estimation value P(n) is obtained after the digital baseband signal passes through the detector and the filter;

[0037] S4: The power estimate P(n) is compared with the threshold to obtain the current estimation error Err(n). Based on the estimation error and the current state, the control selection is performed. If the VGA error processing unit is selected, proceed to S5; if the DVGA error processing unit is selected, proceed to S6.

[0038] As an example, the above-mentioned comprehensive judgment based on the current control state and the absolute value of Err(n) includes two threshold parameters: the entry threshold ETH. IN and the breakout threshold ETH OUT And satisfy ETH IN ETH OUT If the current state is DVGA error processing state, when |Err(n)|>ETH IN When |Err(n)| is in VGA error processing state, it enters the VGA error processing state; otherwise, it remains in the current state. If the current state is VGA error processing state, when |Err(n)| <ETH OUT When the error occurs, exit the VGA error processing state and enter the DVGA error processing state; otherwise, remain in the current state.

[0039] S5: The VGA error processing unit calculates G based on Err(n). VGA (n+1), and output to VGA via DAC for control, while simultaneously G DVGA (n+1) is set to 1, and the DVGA is directly output to control it. If the control process has not ended, it returns to S1 to continue control. If the control process has ended, no further operation is performed and the program ends.

[0040] S6: The DVGA error processing unit calculates G based on Err(n). DVGA (n+1), directly output control of DVGA, while the VGA error processing unit will... VGA (n+1) takes the value G VGA (n) is output to VGA via DAC for control. If the control process has not ended, it returns to S1 to continue control. If the control process has ended, no further operation is performed and the program ends.

[0041] Example

[0042] In this embodiment, the burst communication signal bandwidth is set to 10MHz, the ADC sampling rate to 40MHz, the single burst transmission time to 1ms, and the AGC convergence time to 10us is required. The simulated burst transmission signal, with a detection window of 1us, yields the raw received signal power without power control as follows: Figure 4 As shown, the noise floor is nearly 1000 times lower than the strongest signal power. Both VGA and DVGA error processing loops use logarithmic adjustment loops, with update coefficients of 1 / 2 and 1 / 4 respectively.IN and ETH OUT are set to 6dB and 2dB respectively, the signal power convergence results are shown in Figure 5 , 5 power samples can achieve AGC convergence, and the AGC convergence time is about 5us. The control amount of VGA and DVGA in the control process is shown in Figure 6 . Small range signal fluctuation (<6dB) is directly processed by DVGA, and the VGA control amount is unchanged; large range power fluctuation is jointly processed by VGA and DVGA, and DVGA mainly absorbs power fluctuation below 2dB. The joint processing of VGA and DVGA shortens the stabilization time of the burst signal as a whole, and ensures the reliable reception of the signal.

Claims

1. A radio frequency baseband joint fast AGC control system, characterized in that, The system comprises a VGA, a frequency converter, an ADC, a digital signal processing module and a DAC; The digital signal processing module comprises a DVGA, a detector, a filter, a threshold comparison unit, a control selection unit, a DVGA error processing unit and a VGA error processing unit; In the direction of signal transmission, the VGA, the frequency converter, the ADC, the DVGA, the detector, the filter, the threshold comparison unit, the control selection unit, the DVGA error processing unit and the DVGA are sequentially connected to form a DVGA automatic gain control loop; In the direction of signal transmission, the VGA, the frequency converter, the ADC, the DVGA, the detector, the filter, the threshold comparison unit, the control selection unit, the VGA error processing unit, the DAC and the VGA are sequentially connected to form a VGA automatic gain control loop; The DVGA is further provided with a digital baseband output end.

2. A radio frequency baseband joint fast AGC control method, characterized in that, The method is based on the radio frequency baseband joint fast AGC control system of claim 1 and comprises: S1: a radio frequency input signal S RF (t) after passing through a VGA VGA (n) · S RF (t), where G VGA (n) represents the gain of the VGA at the nth control, n ≥ 1, and t represents time; S2: signal G VGA (n) · S RF (t) ADC sampling digital signal G obtained after passing through the frequency converter and the ADC VGA (n) · S BB (t), the digital baseband signal G obtained after passing through the DVGA again VGA (n) · G DVGA (n) · S BB (t), S BB (t) represents the digital baseband signal obtained after the radio frequency signal passes through the frequency converter and the ADC, G DVGA (n) represents the amplification amount of the DVGA at the n-th control S3: a current signal power estimation value P(n) is obtained after the digital baseband signal passes through the detector and the filter; S4: a current estimation error Err(n) is obtained after the power estimation value P(n) passes through the threshold comparison unit, and control selection is performed according to the estimation error Err(n) and the current state, if the VGA error processing unit is selected, S5 is entered, and if the DVGA error processing unit is selected, S6 is entered; S5: VGA error processing unit according to Err(n) to obtain G VGA (n+1), and output to the VGA through the DAC for control, while G DVGA (n+1) is set to 1, directly output control DVGA, return to S1; S6: The VGA error processing unit calculates G according to Err(n) DVGA (n+1), directly outputs control DVGA, and the VGA error processing unit takes G VGA (n+1) as G VGA (n), outputs to the VGA through the DAC for control, and returns to S1.

3. The method of claim 2, wherein the method further comprises: In the S4, the method of performing control selection according to the estimation error Err(n) and the current state is as follows: In the S4, the method of performing control selection according to the estimation error Err(n) and the current state is as follows: First, two threshold parameters are set: an entry threshold ETH IN and an exit threshold ETH OUT , and satisfy ETH IN >ETH OUT ; then, a judgment is made: if the current state is the DVGA error processing state, when |Err(n)|>ETH IN , the VGA error processing state is entered, otherwise the current state is maintained; if the current state is the VGA error processing state, when |Err(n)|<ETH OUT , the VGA error processing state is exited and the DVGA error processing state is entered, otherwise the current state is maintained.

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