Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device, the display substrate comprising a display area (100) and a frame area (300), the frame area (300) comprising a circuit area (310) and a partition area (320), the circuit area (310) comprising a third gate driving circuit, a second gate driving circuit (GOA-2) and a first gate driving circuit (GOA-1) arranged in sequence along a direction away from the display area (100), the partition area (320) comprising a power supply line, the power supply line comprising a first branch (VSS-1) and a second branch (VSS-2); the second branch (VSS-2) of the power supply line and the first branch (VSS-1) of the power supply line have an overlapping area in orthographic projection on a substrate, the second branch (VSS-2) of the power supply line and the first gate driving circuit (GOA-1) have an overlapping area in orthographic projection on the substrate, and the first branch (VSS-1) of the power supply line and the first gate driving circuit (GOA-1) do not have an overlapping area in orthographic projection on the substrate.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the substrate, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, including a display area and a frame area located on at least one side of the display area. The frame area includes a circuit area and a partition area sequentially disposed along a direction away from the display area. The circuit area includes a third gate driving circuit, a second gate driving circuit, and a first gate driving circuit sequentially disposed along a direction away from the display area. The partition area includes a power line, which includes a first branch and a second branch. In a plane perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on a substrate. The first semiconductor layer includes an active layer of a plurality of polysilicon transistors. The first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode of a storage capacitor. The second conductive layer includes an active layer of a plurality of polysilicon transistors and a first electrode of a storage capacitor. The first conductive layer includes a second electrode of a storage capacitor; the second semiconductor layer includes an active layer of multiple oxide transistors; the third conductive layer includes gate electrodes of multiple oxide transistors; the fourth conductive layer includes first and second electrodes of multiple polysilicon transistors, first and second electrodes of multiple oxide transistors, and a first branch of the power line; the fifth conductive layer includes a second branch of the power line. The orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first branch of the power line on the substrate, and also overlaps with the orthographic projection of the first gate driving circuit on the substrate. The orthographic projection of the first branch of the power line on the substrate does not overlap with the orthographic projection of the first gate driving circuit on the substrate.

[0005] In an exemplary embodiment, the orthographic projection of the second branch of the power line on the substrate does not overlap with the orthographic projection of the second gate driving circuit on the substrate.

[0006] In an exemplary embodiment, the second branch of the power line includes a plurality of spaced-apart venting openings, the orthographic projections of the plurality of venting openings on the substrate overlapping the orthographic projections of the first branch of the power line and the first gate driving circuit on the substrate.

[0007] In an exemplary embodiment, the area of ​​the vent opening projected onto the substrate is 5% to 15% of the area of ​​the second branch of the power line projected onto the substrate.

[0008] In an exemplary embodiment, the first gate driving circuit and the second gate driving circuit respectively include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, a second capacitor, and a third capacitor.

[0009] The gate electrode of the first transistor, the first electrode of the second transistor, and the gate electrode of the third transistor are all electrically connected to the first clock signal line. The first electrode of the first transistor is electrically connected to the input terminal. The second electrode of the first transistor is electrically connected to the gate electrode of the second transistor, the gate electrode of the eighth transistor, the first electrode of the twelfth transistor, and the first electrode of the thirteenth transistor.

[0010] The second terminal of the second transistor is electrically connected to the second terminal of the third transistor, the gate electrode of the fifth transistor, and the first terminal of the eleventh transistor;

[0011] The first electrode of the third transistor, the first electrode of the tenth transistor, the gate electrode of the eleventh transistor, and the gate electrode of the twelfth transistor are all electrically connected to the second low-voltage line.

[0012] The gate electrode of the fourth transistor is electrically connected to the second electrode of the twelfth transistor, the gate electrode of the tenth transistor, and the first plate of the third capacitor. The second electrode of the fourth transistor, the first electrode of the sixth transistor, and the gate electrode of the seventh transistor are all electrically connected to the second clock signal line.

[0013] The first terminal of the fifth transistor, the first terminal of the eighth transistor, the first terminal of the ninth transistor, the second terminal of the thirteenth transistor, and the second plate of the second capacitor are all electrically connected to the first high-voltage line. The second terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor and the second plate of the third capacitor.

[0014] The gate electrode of the sixth transistor is electrically connected to the first plate of the first capacitor and the second electrode of the eleventh transistor, and the second electrode of the sixth transistor is electrically connected to the second plate of the first capacitor and the first electrode of the seventh transistor.

[0015] The second terminal of the seventh transistor is electrically connected to the second terminal of the eighth transistor, the gate electrode of the ninth transistor, and the first plate of the second capacitor; the second terminals of the ninth transistor and the tenth transistor are both electrically connected to the output terminal; the gate electrode of the thirteenth transistor is electrically connected to the third clock signal line.

[0016] In an exemplary embodiment, the first high-voltage line includes a first branch and a second branch, and the second low-voltage line includes a first branch, a second branch, a third branch, and a fourth branch;

[0017] The first branch of the first high-voltage line, the first branch of the second low-voltage line, and the second branch of the second low-voltage line are disposed in the same layer as the fourth conductive layer; the second branch of the first high-voltage line, the third branch of the second low-voltage line, and the fourth branch of the second low-voltage line are disposed in the same layer as the fifth conductive layer.

[0018] In an exemplary embodiment, the first conductive layer includes a first connection electrode, and the fourth conductive layer includes a third connection electrode, a fourth connection electrode, and a fifth connection electrode.

[0019] The first connecting electrode is connected to the gate electrode of the second transistor and the gate electrode of the eighth transistor to form an integral structure; the third connecting electrode is connected to the first electrode of the thirteenth transistor to form an integral structure; the fourth connecting electrode is connected to the second electrode of the first transistor to form an integral structure; and the fifth connecting electrode is connected to the first electrode of the twelfth transistor to form an integral structure.

[0020] The first connecting electrode is connected to the third connecting electrode, the fourth connecting electrode, and the fifth connecting electrode through vias.

[0021] In an exemplary embodiment, in the first gate driving circuit, the third connection electrode is L-shaped.

[0022] In an exemplary embodiment, the third clock signal line is disposed on the same layer as the fourth conductive layer, and the third clock signal line includes a first protrusion, which is connected to the gate electrode of the thirteenth transistor through a via.

[0023] The active layer of the thirteenth transistor includes a channel region. In the first gate drive circuit, the via connecting the first bump to the gate electrode of the thirteenth transistor and the via connecting the first connection electrode to the third connection electrode are respectively located on both sides of the channel region of the thirteenth transistor.

[0024] In an exemplary embodiment, in the second gate drive circuit, the third connection electrode is shaped like the letter "1".

[0025] In an exemplary embodiment, the third clock signal line is disposed on the same layer as the fourth conductive layer, and the third clock signal line includes a first protrusion, which is connected to the gate electrode of the thirteenth transistor through a via.

[0026] The active layer of the thirteenth transistor includes a channel region. In the second gate drive circuit, the via connecting the first bump to the gate electrode of the thirteenth transistor and the via connecting the first connection electrode to the third connection electrode are located on the same side of the channel region of the thirteenth transistor.

[0027] In an exemplary embodiment, the ninth transistor includes a plurality of gate electrodes arranged in parallel at intervals, the tenth transistor includes a plurality of gate electrodes arranged in parallel at intervals, the number of gate electrodes of the ninth transistor in the second gate driving circuit is greater than the number of gate electrodes of the ninth transistor in the first gate driving circuit, and the number of gate electrodes of the tenth transistor in the second gate driving circuit is less than the number of gate electrodes of the tenth transistor in the first gate driving circuit.

[0028] In an exemplary embodiment, in the second gate driving circuit, the length of each gate electrode of the ninth transistor along the first direction is between 30% and 40% of the width of the second gate driving circuit along the first direction, and the width of each gate electrode of the ninth transistor along the second direction is between 2% and 3% of the width of the second gate driving circuit along the first direction.

[0029] In an exemplary embodiment, the border area includes a plurality of straight-line extension areas and a corner area disposed between the plurality of straight-line extension areas. The circuit area also includes a plurality of virtual gate driving circuit groups, each of the virtual gate driving circuit groups including at least one virtual gate driving circuit. The plurality of virtual gate driving circuit groups are distributed around the display area in the corner area.

[0030] In an exemplary embodiment, the distance between two adjacent virtual gate drive circuit groups is between 1 / 6 and 1 / 3 of the length of the corner region.

[0031] In an exemplary embodiment, the display substrate further includes a first planarization layer disposed between the fourth conductive layer and the fifth conductive layer, wherein the first planarization layer above the first gate driving circuit and the first planarization layer above the second gate driving circuit are continuously disposed.

[0032] This disclosure also provides a display device, including a display substrate as described in any of the preceding embodiments.

[0033] This disclosure also provides a method for fabricating a display substrate. The display substrate includes a display area and a border area located on at least one side of the display area. The border area includes a circuit area and a partition area sequentially arranged along a direction away from the display area. The circuit area includes a third gate driving circuit, a second gate driving circuit, and a first gate driving circuit sequentially arranged along a direction away from the display area. The partition area includes a power line, which includes a first branch and a second branch. The fabrication method includes: sequentially forming a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer on a substrate. The first semiconductor layer includes an active layer of a plurality of polysilicon transistors. The first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode of a storage capacitor. The second conductive layer... The system includes a second electrode plate for a storage capacitor, a second semiconductor layer comprising an active layer of multiple oxide transistors, a third conductive layer comprising gate electrodes of multiple oxide transistors, a fourth conductive layer comprising first and second electrodes of multiple polysilicon transistors, first and second electrodes of multiple oxide transistors, and a first branch of the power line, and a fifth conductive layer comprising a second branch of the power line. The orthographic projection of the second branch of the power line onto the substrate overlaps with the orthographic projection of the first branch of the power line onto the substrate, and also overlaps with the orthographic projection of the first gate driving circuit onto the substrate. Conversely, the orthographic projection of the first branch of the power line onto the substrate does not overlap with the orthographic projection of the first gate driving circuit onto the substrate.

[0034] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0035] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0036] Figure 1 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0037] Figure 2 This is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure;

[0038] Figure 3a This is a schematic diagram of the planar structure of a border region according to an embodiment of the present disclosure;

[0039] Figure 3b for Figure 3a Sectional view along the middle AA direction;

[0040] Figure 3c This is a schematic diagram of the planar structure of another border region according to an embodiment of the present disclosure;

[0041] Figure 4 This is a schematic diagram of a scanning control circuit according to an embodiment of the present disclosure;

[0042] Figure 5 This is an equivalent circuit diagram of a scanning control circuit according to an embodiment of the present disclosure;

[0043] Figure 6 for Figure 5 The driving timing diagram of the scan control circuit shown is as follows;

[0044] Figure 7 This is a schematic diagram of the planar structure of the partition region and the first gate driving circuit region in a display substrate according to an embodiment of the present disclosure;

[0045] Figure 8 This is a schematic diagram of the planar structure of the second gate driving circuit region in a display substrate according to an embodiment of the present disclosure;

[0046] Figure 9a for Figure 7 A planar schematic diagram of the display substrate after the formation of the first semiconductor layer;

[0047] Figure 9b for Figure 8 A planar schematic diagram of the display substrate after the formation of the first semiconductor layer;

[0048] Figure 10a for Figure 7 A planar schematic diagram of the display substrate after the first conductive layer has been formed;

[0049] Figure 10b for Figure 8 A planar schematic diagram of the display substrate after the first conductive layer has been formed;

[0050] Figure 11a for Figure 7 A planar schematic diagram of the display substrate after the formation of the second conductive layer;

[0051] Figure 11b for Figure 8 A planar schematic diagram of the display substrate after the formation of the second conductive layer;

[0052] Figure 12a for Figure 7 A schematic diagram of the display substrate after the formation of the third conductive layer;

[0053] Figure 13a for Figure 7A planar schematic diagram of the display substrate after the fourth insulating layer has been formed;

[0054] Figure 13b for Figure 8 A planar schematic diagram of the display substrate after the fourth insulating layer has been formed;

[0055] Figure 14a for Figure 7 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0056] Figure 14b for Figure 8 A planar schematic diagram of the display substrate after the fourth conductive layer has been formed. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0058] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0059] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0060] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0061] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0062] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0063] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0064] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0065] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0066] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0067] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0068] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one pixel driving circuit, which is connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a GOA circuit and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to light-emitting signal lines E1, E2, E3, ..., Eo. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a GOA circuit and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0069] In some exemplary embodiments, the shape of the sub-pixel Pxij can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0070] In some exemplary embodiments, a pixel unit within a display area may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0071] In some example implementations, the timing controller, data driver, scan driver, and light-emitting driver can be located in a non-display area. Specifically, the scan driver and light-emitting driver can be located on opposite sides of the display area, for example, on the left and right sides of the display area; the timing controller and data driver can be located on one side of the display area, for example, on the lower side of the display area. However, this embodiment is not limited to this.

[0072] In some exemplary embodiments, the sub-pixel Pxij includes a pixel circuit. The pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. However, this embodiment is not limited to this. For example, the pixel circuit can include N-type transistors and P-type transistors. The N-type transistor can be, for example, an oxide thin-film transistor, and the P-type transistor can be, for example, a low-temperature polycrystalline silicon thin-film transistor. The active layer of the low-temperature polycrystalline silicon thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polycrystalline silicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors on a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can utilize the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0073] LTPO display technology combines the advantages of LTPS and IGZO, and is suitable for both high-frequency and low-frequency displays, making it an increasingly popular technology in display panels. However, LTPO display panels typically require three sets of GOA circuits for driving, compared to the two sets of GOA circuits in LTPS products, resulting in larger left and right bezels. To improve the competitiveness of LTPO products and reduce their left and right bezels, it is necessary to provide a bezel design suitable for LTPO display panels.

[0074] Figure 2 This is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure. Figure 2 As shown, in an exemplary embodiment, the display substrate may include a display area 100 and an edge area located outside the display area 100. The edge area may include a bonding area 200 located on one side of the display area 100 and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may include a plurality of sub-pixels arranged in a matrix. The bonding area 200 may include at least an isolation dam and a bonding circuit that connects the signal lines of the plurality of sub-pixels to an external driving device. The border area 300 may include at least an isolation dam, a gate driver on array (GOA) circuit that transmits scan signals and light emission signals to the circuit units of the plurality of sub-pixels, and power lines that transmit voltage signals to the plurality of sub-pixels. The bonding area 200 and the isolation dam of the border area 300 form a ring structure surrounding the display area 100.

[0075] Figure 3a This is a schematic diagram of the planar structure of the bezel area of ​​a display substrate according to an embodiment of the present disclosure. Figure 2 Enlarged view of region C in the middle. Figure 3b for Figure 3a Cross-sectional view along direction AA (where, Figure 3b The third gate drive circuit is not shown in the image. Figure 3c This is a schematic diagram of the planar structure of another border region according to an embodiment of this disclosure. For example... Figure 3a , Figure 3b and Figure 3c As shown, in a plane parallel to the display substrate, the display substrate may include a display area 100 and a border area 300 located on at least one side of the display area 100. The border area 300 may include a circuit area 310, a partition area 320 and a cutting area 330 arranged sequentially along the direction away from the display area.

[0076] In an exemplary embodiment, the display area 100 may include a plurality of circuit units and a plurality of light-emitting devices. Each circuit unit is provided with a pixel driving circuit. The plurality of light-emitting devices are connected to the pixel driving circuits in the plurality of circuit units respectively. The pixel driving circuit is configured to output current to the connected light-emitting devices so that the light-emitting devices emit light of corresponding brightness.

[0077] In an exemplary embodiment, the circuit area 310 may include at least a gate driving device, which may be connected to the pixel driving circuit of a plurality of circuit units in the display area 100 to output scanning signals and light emission control signals to the display area.

[0078] In an exemplary embodiment, the partition region 320 may include at least a power line, an isolation dam, and a crack dam. The power line may extend in a direction parallel to the edge of the display area and be connected to a second power line VSS of the circuit unit in the display area. The isolation dam may extend in a direction parallel to the edge of the display area. The isolation dam is configured to block the organic layer in the encapsulation layer to prevent the organic layer from flowing to the cutting area. The crack dam is configured to prevent the cutting process from affecting the film structure of the display substrate.

[0079] In an exemplary embodiment, the cutting area 330 may include at least a cutting groove, which is configured to allow the cutting device to cut along the cutting groove after all film layers have been prepared.

[0080] In an exemplary embodiment, the gate driving device may include multiple cascaded Gate Driver On Array (GOA) circuits. The GOA circuits convert clock signals into turn-on / turn-off voltages and output them to the display area respectively. Each GOA circuit is typically connected to the scan signal line and the light emission signal line in a circuit unit. By having each GOA circuit output the turn-on voltage in turn in sequence, the line-by-line scanning of multiple unit rows in the display area can be achieved.

[0081] Figure 4 This is a schematic diagram of the GOA circuit according to at least one embodiment of the present disclosure. Figure 4 As shown, the GOA circuit provided in this embodiment includes: an output sub-circuit 11, a second node control sub-circuit 12, a third node control sub-circuit 13, a second output node control sub-circuit 14, a first output node control sub-circuit 15, a first isolation sub-circuit 16, and a second isolation sub-circuit 17.

[0082] The output sub-circuit 11 is electrically connected to the first output node N1, the second output node N4, the first high voltage line VGH, the second low voltage line VGL, and the output terminal OUT, respectively. It is used to write the low voltage signal provided by the second low voltage line VGL to the output terminal OUT under the control of the potential of the first output node N1, and to write the high voltage signal provided by the first high voltage line VGH to the output terminal OUT under the control of the potential of the second output node N4.

[0083] The second node control sub-circuit 12 is electrically connected to the first clock signal line CK, the second low voltage line VGL, the first output node N1, and the second node N2, respectively. It is used to write the low voltage signal provided by the second low voltage line VGL into the second node N2 under the control of the first clock signal provided by the first clock signal line CK, and to write the first clock signal provided by the first clock signal line CK into the second node N2 under the control of the potential of the first output node N1.

[0084] The third node control sub-circuit 13 is electrically connected to the third node N3, the second isolation node N02, and the second clock signal line CB, respectively. It is used to write the second clock signal into the third node N3 under the control of the potential of the second isolation node N02, and to adjust the potential of the third node N3 according to the potential of the second isolation node N02.

[0085] The second output node control sub-circuit 14 is electrically connected to the second clock signal line CB, the third node N3, the second output node N4, the first high voltage line VGH, and the first output node N1, respectively. Under the control of the second clock signal, it controls the connection between the third node N3 and the second output node N4. Under the control of the potential of the first output node N1, it writes the high voltage signal provided by the first high voltage line VGH into the second output node N4 and maintains the potential of the second output node N4.

[0086] The first output node control sub-circuit 15 is electrically connected to the first clock signal line CK, the input terminal IN, the second clock signal line CB, the first high voltage line VGH, the second isolation node N02, and the first isolation node N01, respectively. It is used to write the input signal provided by the input terminal IN into the first isolation node N01 under the control of the first clock signal, and to write the high voltage signal into the first isolation node N01 under the control of the potential of the second clock signal and the second isolation node N02.

[0087] The first isolation sub-circuit 16 is electrically connected to the second low voltage line VGL, the first output node N1 and the first isolation node N01 respectively, and is used to control the connection between the first output node N1 and the first isolation node N01 under the control of the second low voltage provided by the second low voltage line VGL.

[0088] The second isolation sub-circuit 17 is electrically connected to the second low voltage line VGL, the second node N2, and the second isolation node N02, respectively, and is used to control the connection between the second node N2 and the second isolation node N02 under the control of the second low voltage provided by the second low voltage line VGL.

[0089] The shift register unit provided in this disclosure, by adding a first isolation sub-circuit 16 and a second isolation sub-circuit 17, can prevent the potential of the first output node N1 from being too low and affecting the potential of the first isolation node N01, and prevent the potential of the second isolation node N02 from being too low and affecting the potential of the second node N2.

[0090] When the shift register unit provided in this disclosure is in operation, the second node control sub-circuit 12, under the control of the first clock signal, writes a low voltage signal into the second node N2, and under the control of the potential of the first output node N1, writes the first clock signal into the second node N2; the second isolation sub-circuit 17, under the control of the second low voltage, controls the connection between the second node N2 and the second isolation node N02; the third node control sub-circuit 13, under the control of the potential of the second isolation node N02, writes the second clock signal into the third node N3, and adjusts the potential of the third node N3 according to the potential of the second node N2; the second output node control sub-circuit 14, under the control of the second clock signal... The first output node control sub-circuit 15 controls the connection between the third node N3 and the second output node N4. Under the control of the potential of the first output node N1, the high voltage signal provided by the first high voltage line VGH is written into the second output node N4, and the potential of the second output node N4 is maintained. Under the control of the first clock signal, the first output node control sub-circuit 15 writes the input signal provided by the input terminal IN into the first isolation node N01, and under the control of the second clock signal and the potential of the second isolation node N02, writes the high voltage signal into the first isolation node N01. Under the control of the second low voltage, the first isolation sub-circuit 16 controls the connection between the first output node N1 and the first isolation node N01.

[0091] In some exemplary implementations, such as Figure 5 As shown, the output sub-circuit 11 includes a ninth transistor T9 and a tenth transistor T10.

[0092] In this configuration, the gate electrode of the ninth transistor T9 is electrically connected to the second output node N4, the first terminal of the ninth transistor T9 is electrically connected to the first high-voltage line VGH, and the second terminal of the ninth transistor T9 is electrically connected to the output terminal OUT.

[0093] The gate electrode of the tenth transistor T10 is electrically connected to the first output node N1, the first terminal of the tenth transistor T10 is electrically connected to the output terminal OUT, and the second terminal of the tenth transistor T10 is electrically connected to the second low voltage line VGL.

[0094] In some exemplary embodiments, the second node control sub-circuit 12 may include a third transistor T3 and a second transistor T2.

[0095] Among them, the gate electrode of the third transistor T3 is electrically connected to the first clock signal line CK, the first electrode of the third transistor T3 is electrically connected to the second low voltage line VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2.

[0096] The gate electrode of the second transistor T2 is electrically connected to the first isolation node N01, the first terminal of the second transistor T2 is electrically connected to the first clock signal line CK, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0097] In some exemplary implementations, such as Figure 5 As shown, the third node control sub-circuit 13 includes a sixth transistor T6 and a first capacitor C1.

[0098] Among them, the gate electrode of the sixth transistor T6 is electrically connected to the second isolation node N02, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3.

[0099] The first plate of the first capacitor C1 is electrically connected to the second isolation node N02, and the second plate of the first capacitor C1 is electrically connected to the third node N3.

[0100] In some exemplary embodiments, the second output node control sub-circuit 14 includes a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a second capacitor C2.

[0101] Among them, the gate electrode of the seventh transistor T7 is electrically connected to the second clock signal line CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the second output node N4.

[0102] The gate electrode of the eighth transistor T8 is electrically connected to the first isolation node N01, the first terminal of the eighth transistor T8 is electrically connected to the first high voltage line VGH, and the second terminal of the eighth transistor T8 is electrically connected to the second output node N4.

[0103] The gate electrode of the thirteenth transistor T13 is electrically connected to the third clock signal line NCX, the first terminal of the thirteenth transistor T13 is electrically connected to the first isolation node N01, and the second terminal of the thirteenth transistor T13 is electrically connected to the first high voltage line VGH.

[0104] The first plate of the second capacitor C2 is electrically connected to the second output node N4, and the second plate of the second capacitor C2 is electrically connected to the first high voltage line VGH.

[0105] In some exemplary implementations, such as Figure 5 As shown, the first output node control sub-circuit 15 includes a first transistor T1, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0106] Among them, the gate electrode of the first transistor T1 is electrically connected to the first clock signal line CK, the first terminal of the first transistor T1 is electrically connected to the input terminal IN, and the second terminal of the first transistor T1 is electrically connected to the first isolation node N01.

[0107] The gate electrode of the fourth transistor T4 is electrically connected to the first output node N1, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal line CB.

[0108] The gate electrode of the fifth transistor T5 is electrically connected to the second node N2, the first terminal of the fifth transistor T5 is electrically connected to the first high voltage line VGH, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the fourth transistor T4 (i.e., the seventh node N7).

[0109] The first plate of the third capacitor C3 is electrically connected to the first output node N1, and the second plate of the third capacitor C3 is electrically connected to the seventh node N7.

[0110] In some exemplary embodiments, the first isolation sub-circuit 16 includes a twelfth transistor T12.

[0111] The gate electrode of the twelfth transistor T12 is electrically connected to the second low-voltage line VGL, the first terminal of the twelfth transistor T12 is electrically connected to the first isolation node N01, and the second terminal of the twelfth transistor T12 is electrically connected to the first output node N1.

[0112] In some exemplary implementations, such as Figure 5 As shown, the second isolation sub-circuit 17 includes an eleventh transistor T11.

[0113] The gate electrode of the eleventh transistor T11 is electrically connected to the second low-voltage line VGL, the first terminal of the eleventh transistor T11 is electrically connected to the second node N2, and the second terminal of the eleventh transistor T11 is electrically connected to the second isolation node N02.

[0114] Figure 5 This is an equivalent circuit diagram of a GOA circuit according to at least one embodiment of the present disclosure. Figure 5As shown, the GOA circuit provided in this exemplary embodiment includes: an output sub-circuit 11, a second node control sub-circuit 12, a third node control sub-circuit 13, a second output node control sub-circuit 14, a first output node control sub-circuit 15, a first isolation sub-circuit 16, and a second isolation sub-circuit 17. Specifically, the output sub-circuit 11 includes a ninth transistor T9 and a tenth transistor T10; the second node control sub-circuit 12 may include a third transistor T3 and a second transistor T2; the third node control sub-circuit 13 includes a sixth transistor T6 and a first capacitor C1; the second output node control sub-circuit 14 includes a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a second capacitor C2; the first output node control sub-circuit 15 includes a first transistor T1, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3; the first isolation sub-circuit 16 includes a twelfth transistor T12; and the second isolation sub-circuit 17 includes an eleventh transistor T11.

[0115] Specifically, the gate electrode of the ninth transistor T9 is electrically connected to the second output node N4, the first terminal of the ninth transistor T9 is electrically connected to the first high-voltage line VGH, and the second terminal of the ninth transistor T9 is electrically connected to the output terminal OUT. The gate electrode of the tenth transistor T10 is electrically connected to the first output node N1, the first terminal of the tenth transistor T10 is electrically connected to the output terminal OUT, and the second terminal of the tenth transistor T10 is electrically connected to the second low-voltage line VGL. The gate electrode of the second transistor T2 is electrically connected to the first isolation node N01, the first terminal of the second transistor T2 is electrically connected to the first clock signal line CK, and the second terminal of the second transistor T2 is electrically connected to the second node N2. The gate electrode of the third transistor T3 is electrically connected to the first clock signal line CK, the first terminal of the third transistor T3 is electrically connected to the second low-voltage line VGL, and the second terminal of the third transistor T3 is electrically connected to the second node N2. The gate electrode of the sixth transistor T6 is electrically connected to the second isolation node N02, the first terminal of the sixth transistor T6 is electrically connected to the second clock signal line CB, and the second terminal of the sixth transistor T6 is electrically connected to the third node N3. The first plate of the first capacitor C1 is electrically connected to the second isolation node N02, and the second plate of the first capacitor C1 is electrically connected to the third node N3. The gate electrode of the seventh transistor T7 is electrically connected to the second clock signal line CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the second output node N4. The gate electrode of the eighth transistor T8 is electrically connected to the first isolation node N01, the first electrode of the eighth transistor T8 is electrically connected to the first high-voltage line VGH, and the second electrode of the eighth transistor T8 is electrically connected to the second output node N4. The gate electrode of the thirteenth transistor T13 is electrically connected to the third clock signal line NCX, the first electrode of the thirteenth transistor T13 is electrically connected to the first isolation node N01, and the second electrode of the thirteenth transistor T13 is electrically connected to the first high-voltage line VGH. The first plate of the second capacitor C2 is electrically connected to the second output node N4, and the second plate of the second capacitor C2 is electrically connected to the first high-voltage line VGH. The gate electrode of the first transistor T1 is electrically connected to the first clock signal line CK, the first terminal of the first transistor T1 is electrically connected to the input terminal IN, and the second terminal of the first transistor T1 is electrically connected to the first isolation node N01. The gate electrode of the fourth transistor T4 is electrically connected to the first output node N1, and the second terminal of the fourth transistor T4 is electrically connected to the second clock signal line CB. The gate electrode of the fifth transistor T5 is electrically connected to the second node N2, the first terminal of the fifth transistor T5 is electrically connected to the first high voltage line VGH, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the fourth transistor T4 (i.e., the seventh node N7). The first plate of the third capacitor C3 is electrically connected to the first output node N1, and the second plate of the third capacitor C3 is electrically connected to the seventh node N7.The gate electrode of the twelfth transistor T12 is electrically connected to the second low-voltage line VGL, the first terminal of the twelfth transistor T12 is electrically connected to the first isolation node N01, and the second terminal of the twelfth transistor T12 is electrically connected to the first output node N1. The gate electrode of the eleventh transistor T11 is electrically connected to the second low-voltage line VGL, the first terminal of the eleventh transistor T11 is electrically connected to the second node N2, and the second terminal of the eleventh transistor T11 is electrically connected to the second isolation node N02.

[0116] In this exemplary embodiment, the first output node N1, the second node N2, the third node N3, the second output node N4, the first isolation node N01, the second isolation node N02, and the seventh node N7 are junctions representing related electrical connections in the circuit diagram. In other words, these nodes are equivalent to junctions of related electrical connections in the circuit diagram.

[0117] In some exemplary embodiments, the first transistor T1 to the thirteenth transistor T13 in the GOA circuit can all be P-type thin-film transistors, such as low-temperature polysilicon (LTPS) thin-film transistors. Alternatively, embodiments of this disclosure can select either bottom-gate or top-gate thin-film transistors, as long as the switching function can be achieved. This embodiment is not limited in this respect.

[0118] The technical solution of this embodiment will be further explained below through the working process of the GOA circuit. The working process of the first-stage GOA circuit will be used as an example for explanation. The input terminal IN of the first-stage GOA circuit is connected to the initial signal line STV. Figure 6 for Figure 5 The diagram shows a timing sequence of a GOA circuit. Figure 5 and Figure 6 As shown, the GOA circuit of this exemplary embodiment includes 13 transistor units (e.g., first transistor T1 to thirteenth transistor T13), 3 capacitor units (i.e., first capacitor C1 to third capacitor C3), 4 input terminals (i.e., input terminal IN, first clock signal line CK, second clock signal line CB, and third clock signal line NCX), 1 output terminal (i.e., output terminal OUT), and 2 power supply terminals (i.e., first high voltage line VGH and second low voltage line VGL). In some examples, the first high voltage line VGH continuously provides a high-level signal; the second low voltage line VGL continuously provides a low-level signal.

[0119] The following example illustrates the operation of the GOA circuit by demonstrating how it provides a scan signal or reset signal to the N-type transistor of the pixel circuit. The operation of the GOA circuit provided in this exemplary embodiment includes the following stages.

[0120] The operation of the shift register unit provided in this disclosure includes:

[0121] In the first stage t1, the input terminal IN provides a low voltage, the second clock signal line CB provides a high voltage, the first clock signal line CK provides a low voltage, and the third clock signal line NCX provides a high voltage. T1 and T3 are both turned on. The low voltage provided by the input terminal IN is written to the first isolation node N01. T2 is turned on. The second node N2 is written with a low voltage. T8 is turned on. The second output node N4 is written with a high voltage. T9 is turned off. T10 is turned on. The output terminal OUT outputs a low voltage.

[0122] In the second stage t2, the input terminal IN is provided with a low voltage, the second clock signal line CB is provided with a low voltage, the first clock signal line CK is provided with a high voltage, and the third clock signal line NCX is provided with a low voltage. T1 is turned off, T3 is turned off, the first isolation node N01 maintains a low voltage, T2 is turned on, the potential of the second node N2 becomes a high voltage, T8 and T13 are both turned on, the second output node N4 is written with a high voltage, T9 is turned off, T10 is turned on, and the output terminal OUT outputs a low voltage.

[0123] In the third stage t3, the input terminal IN provides a low voltage, the second clock signal line CB provides a high voltage, the first clock signal line CK provides a low voltage, and the third clock signal line NCX provides a low voltage. T1 and T3 are both turned on, the low voltage provided by the input terminal IN is written to N01, T2 is turned on, the second node N2 is written with a low voltage, T8 and T13 are both turned on, the second output node N4 is written with a high voltage, T9 is turned off, T10 is turned on, and the output terminal OUT outputs a low voltage.

[0124] In the fourth stage t4, the input terminal IN is provided with a low voltage, the second clock signal line CB is provided with a low voltage, the first clock signal line CK is provided with a high voltage, the third clock signal line NCX is provided with a low voltage, T1 is turned off, T3 is turned off, the first isolation node N01 maintains a low voltage, T2 is turned on, the potential of the second node N2 becomes a high voltage, T8 and T13 are both turned on, N4 is written with a high voltage, T9 is turned off, T10 is turned on, and the output terminal OUT outputs a low voltage.

[0125] In the fifth stage t5, the input terminal IN is provided with a high voltage, the second clock signal line CB is provided with a high voltage, the first clock signal line CK is provided with a low voltage, the third clock signal line NCX is provided with a low voltage, T1 is turned on, the high voltage provided by the input terminal IN is written to N1, T3 is turned on, VGL is written to N2, T6 is turned on, the potential of the third node N3 is a high voltage, T4 is turned off, T7 is turned off, T8 is turned off, T9 is turned off, T10 is turned off, and the potential of the light control signal output by the output terminal OUT is maintained at a low voltage.

[0126] In the sixth stage t6, the input terminal IN is provided with a high voltage, the second clock signal line CB is provided with a low voltage, the first clock signal line CK is provided with a high voltage, the third clock signal line NCX is provided with a low voltage, T1 is turned off, T3 is turned off, T2 is turned off, the potential of the second node N2 is maintained at a low voltage, T6 is turned on, T7 is turned on, the potential of N4 is low voltage, T4 and T5 are turned on, the potential of the first output node N1 is high voltage, T9 is turned on, T10 is turned off, and the output terminal OUT outputs the first high voltage provided by the first high voltage line VGH;

[0127] In the seventh stage t7, the input terminal IN is provided with a high voltage, the second clock signal line CB is provided with a high voltage, the first clock signal line CK is provided with a low voltage, the third clock signal line NCX is provided with a low voltage, T1, T3 and T13 are all turned on, the potential of the first output node N1 is high voltage, the potential of N2 is low voltage, T6 is turned on, T5 is turned on, T4 is turned off, the potential of the third node N3 is high voltage, T7 is turned off, T8 is turned off, the potential of the second output node N4 is maintained at low voltage, T9 is turned on, T10 is turned off, and the output terminal OUT outputs the first high voltage provided by the first high voltage line VGH;

[0128] In the eighth stage t8, the input terminal IN provides a low voltage, the second clock signal line CB provides a low voltage, the first clock signal line CK provides a high voltage, the third clock signal line NCX provides a high voltage, T1, T3 and T13 are all turned off, the potential of the first output node N1 is maintained at a high voltage, T2 is turned off, the potential of N2 is maintained at a low voltage, T6 is turned on, T7 is turned on, the potential of the second output node N4 is a low voltage, T9 is turned on, T10 is turned off, and the output terminal OUT outputs the first high voltage provided by the first high voltage line VGH.

[0129] After stage 8 t8, the input terminal IN provides a low voltage, and the circuit operation state can be referred to as the first stage t1 to the fourth stage t4 mentioned above. The output terminal OUT outputs a low voltage until the input terminal IN inputs a high-level signal, and then it starts again from the fifth stage t5.

[0130] In some exemplary embodiments, the output signal of the GOA circuit provided in this embodiment can be provided as a gate drive signal (e.g., a scan signal, a reset signal, or a light emission control signal) to the pixel drive circuit of the display area. In some examples, the GOA circuit of this embodiment can be applied to a low-temperature polycrystalline oxide display substrate and can provide a gate drive signal to the N-type transistor in the pixel circuit of the display area. However, this embodiment is not limited thereto.

[0131] In some exemplary embodiments, the first clock signal input at the first clock signal terminal CK and the second clock signal input at the second clock signal terminal CB are both pulse signals, and the pulse widths of the first and second clock signals can be approximately the same. The duty cycle of the first and second clock signals can be greater than 1 / 2, for example, approximately 1 / 3. In this embodiment, the duty cycle refers to the proportion of the high-level duration within a pulse cycle (including the high-level duration and the low-level duration) in the entire pulse cycle.

[0132] In some exemplary embodiments, the second low-voltage line VGL can continuously provide a low-level signal, and the first high-voltage line VGH can continuously provide a high-level signal. However, this embodiment is not limited to this.

[0133] This disclosure provides a display substrate, including a display area and a border area located on at least one side of the display area, as shown in FIG3. Figure 7 , Figure 8 , Figures 9a to 14b As shown, the border area includes a circuit area 310 and an isolation area 320 arranged sequentially along the direction away from the display area. The circuit area 310 includes a third gate driving circuit (not shown in the figure), a second gate driving circuit GOA2 and a first gate driving circuit GOA1 arranged sequentially along the direction away from the display area. The isolation area includes a power line VSS and an isolation dam disposed on the power line VSS. The power line VSS includes a first branch VSS-1 and a second branch VSS-2.

[0134] In a plane perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on a substrate. The first semiconductor layer includes an active layer of multiple polysilicon transistors. The first conductive layer includes the gate electrode of multiple polysilicon transistors and the first electrode of a storage capacitor. The second conductive layer includes the second electrode of the storage capacitor. The second semiconductor layer includes an active layer of multiple oxide transistors. The third conductive layer includes the gate electrode of multiple oxide transistors. The fourth conductive layer includes the first and second electrodes of multiple polysilicon transistors, the first and second electrodes of multiple oxide transistors, and a first branch VSS-1 of a power line. The fifth conductive layer includes a second branch VSS-2 of the power line.

[0135] The orthographic projection of the second branch VSS-2 of the power line on the substrate overlaps with the orthographic projection of the first branch VSS-1 of the power line on the substrate (thus forming a double-layer trace), and the orthographic projection of the second branch VSS-2 of the power line on the substrate overlaps with the orthographic projection of the first gate drive circuit GOA-1 on the substrate.

[0136] In the original LTPO GOA bezel design, the power line VSS is only located in the partition area 320, requiring a bezel size of approximately 1.2 mm and a lateral space of 626 μm for a single-sided GOA circuit. The display substrate of this disclosure extends the power line VSS from the partition area 320 to the circuit area 310, allowing a portion of the second branch VSS-2 of the power line to overlap with the first gate drive circuit GOA-1, thus reducing the width of the bezel area and achieving a narrow bezel design. For example, a display substrate prepared according to an embodiment of this disclosure requires only 481 μm of lateral space for a single-sided GOA circuit, reducing the bezel size from the original 1.2 mm to 0.985 mm, significantly reducing the left and right bezels of the display panel.

[0137] In some exemplary embodiments, the orthographic projection of the first branch VSS-1 of the power line on the substrate does not overlap with the orthographic projection of the first gate drive circuit GOA-1 on the substrate.

[0138] In some exemplary embodiments, the orthographic projection of the second branch VSS-2 of the power line on the substrate does not overlap with the orthographic projection of the second gate drive circuit GOA-2 on the substrate.

[0139] In some exemplary embodiments, the second branch VSS-2 of the power line includes a plurality of spaced venting openings VSS-K, and the orthographic projection of the plurality of venting openings VSS-K on the substrate overlaps with the orthographic projection of the first branch VSS-1 of the power line and the first gate drive circuit GOA-1 on the substrate.

[0140] This embodiment of the invention designs multiple venting openings to form venting paths, allowing gas components in the first planarization layer to evaporate through these venting paths during the manufacturing process, thereby preventing the gas components in the first planarization layer from damaging the organic light-emitting layer in the pixel.

[0141] In some exemplary embodiments, the area of ​​the orthographic projection of the venting opening VSS-K onto the substrate is 5% to 15% of the area of ​​the orthographic projection (including the cut-out portion and the uncut portion) of the second branch VSS-2 of the power line onto the substrate. For example, the area of ​​the orthographic projection of the venting opening VSS-K onto the substrate is 10% of the area of ​​the orthographic projection of the second branch VSS-2 of the power line onto the substrate.

[0142] In some exemplary embodiments, the width d1 of the exhaust opening VSS-K along the first direction X is 5% to 15% of the width d3 of the partition region 320 along the first direction X, and the width d2 of the exhaust opening VSS-K along the second direction Y is 5% to 15% of the width d3 of the partition region 320 along the first direction X.

[0143] For example, the width d3 of the partition area 320 along the first direction X can be 121um, the width d1 of the exhaust opening VSS-K along the first direction X can be 15um, and the width d2 of the exhaust opening VSS-K along the second direction Y can be 15um.

[0144] In some exemplary embodiments, the shape of the exhaust opening VSS-K can be any shape such as rectangle, triangle, trapezoid, pentagon or hexagon.

[0145] In some exemplary embodiments, the first gate drive circuit GOA-1 and the second gate drive circuit GOA-2 may respectively include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0146] The gate electrode of the first transistor T1, the first electrode of the second transistor T2, and the gate electrode of the third transistor T3 are all electrically connected to the first clock signal line CK. The first electrode of the first transistor T1 is electrically connected to the input terminal. The second electrode of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2, the gate electrode of the eighth transistor T8, the first electrode of the twelfth transistor T12, and the first electrode of the thirteenth transistor T13.

[0147] The second terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3, the gate electrode of the fifth transistor T5, and the first terminal of the eleventh transistor T11.

[0148] The first electrode of the third transistor T3, the first electrode of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the gate electrode of the twelfth transistor T12 are all electrically connected to the second low-voltage line VGL.

[0149] The gate electrode of the fourth transistor T4 is electrically connected to the second electrode of the twelfth transistor T12, the gate electrode of the tenth transistor T10, and the first plate of the third capacitor C3. The second electrode of the fourth transistor T4, the first electrode of the sixth transistor T6, and the gate electrode of the seventh transistor T7 are all electrically connected to the second clock signal line CB.

[0150] The first terminal of the fifth transistor T5, the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, the second terminal of the thirteenth transistor T13, and the second plate of the second capacitor C2 are all electrically connected to the first high voltage line VGH. The second terminal of the fifth transistor T5 is electrically connected to the first terminal of the fourth transistor T4 and the second plate of the third capacitor C3.

[0151] The gate electrode of the sixth transistor T6 is electrically connected to the first plate of the first capacitor C1 and the second electrode of the eleventh transistor T11. The second electrode of the sixth transistor T6 is electrically connected to the second plate of the first capacitor C1 and the first electrode of the seventh transistor T7.

[0152] The second terminal of the seventh transistor T7 is electrically connected to the second terminal of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the first plate of the second capacitor C2; the second terminal of the ninth transistor T9 and the second terminal of the tenth transistor T10 are both electrically connected to the output terminal; the gate electrode of the thirteenth transistor T13 is electrically connected to the third clock signal line NCK.

[0153] In some exemplary embodiments, the first high-voltage line VGH includes a first branch VGH1 and a second branch VGH2, and the second low-voltage line VGL includes a first branch VGL1, a second branch VGL2, a third branch VGL3, and a fourth branch VGL4.

[0154] The first branch VGH1 of the first high-voltage line, the first branch VGL1 of the second low-voltage line, and the second branch VGL2 of the second low-voltage line are disposed in the same layer as the fourth conductive layer; the second branch VGH2 of the first high-voltage line, the third branch VGL3 of the second low-voltage line, and the fourth branch VGL4 of the second low-voltage line are disposed in the same layer as the fifth conductive layer.

[0155] In some exemplary embodiments, the first conductive layer includes a first connection electrode 101, and the fourth conductive layer includes a third connection electrode 401, a fourth connection electrode 402, and a fifth connection electrode 403.

[0156] The first connecting electrode 101 is connected to the gate electrode of the second transistor T2 and the gate electrode of the eighth transistor T8 to form an integral structure; the third connecting electrode 401 is connected to the first electrode of the thirteenth transistor T13 to form an integral structure; the fourth connecting electrode 402 is connected to the second electrode of the first transistor T1 to form an integral structure; and the fifth connecting electrode 403 is connected to the first electrode of the twelfth transistor T12 to form an integral structure.

[0157] The first connecting electrode 101 is connected to the third connecting electrode 401, the fourth connecting electrode 402 and the fifth connecting electrode 403 through vias.

[0158] In some exemplary embodiments, in the first gate drive circuit GOA-1, the third connection electrode 401 is L-shaped.

[0159] In some exemplary embodiments, the third clock signal line NCK is disposed on the same layer as the fourth conductive layer. The third clock signal line NCK includes a first protrusion NCK-1, which is connected to the gate electrode of the thirteenth transistor T13 through a via.

[0160] In some exemplary embodiments, the active layer of the thirteenth transistor T13 includes a channel region. In the first gate drive circuit GOA-1, the via connecting the first bump NCK-1 to the gate electrode of the thirteenth transistor T13 and the via connecting the first connection electrode 101 to the third connection electrode 401 are respectively located on both sides of the channel region of the thirteenth transistor T13.

[0161] The display substrate of this disclosure reduces the bezel size by designing the layout of the GOA circuit so that the width of the GOA circuit along the first direction X is narrowed.

[0162] In some exemplary embodiments, in the second gate drive circuit GOA-2, the third connection electrode 401 is shaped like the letter "1".

[0163] In some exemplary embodiments, the active layer of the thirteenth transistor T13 includes a channel region. In the second gate drive circuit GOA-2, the via connecting the first bump NCK-1 to the gate electrode of the thirteenth transistor T13 and the via connecting the first connection electrode 101 to the third connection electrode 401 are located on the same side of the channel region of the thirteenth transistor T13.

[0164] In some exemplary embodiments, the ninth transistor T9 includes a plurality of gate electrodes G9 arranged in parallel at intervals, and the tenth transistor T10 includes a plurality of gate electrodes G10 arranged in parallel at intervals. The number of gate electrodes G9 of the ninth transistor T9 in the second gate driving circuit GOA-2 is greater than the number of gate electrodes G9 of the ninth transistor T9 in the first gate driving circuit GOA-1. The number of gate electrodes G10 of the tenth transistor T10 in the second gate driving circuit GOA-2 is less than the number of gate electrodes G10 of the tenth transistor T10 in the first gate driving circuit GOA-1.

[0165] In some exemplary embodiments, in the second gate drive circuit GOA-2, the number of gate electrodes G9 of the ninth transistor T9 is 6, and the number of gate electrodes G10 of the tenth transistor T10 is 2.

[0166] In some exemplary embodiments, in the first gate drive circuit GOA-1, the number of gate electrodes G9 of the ninth transistor T9 is 4, and the number of gate electrodes G10 of the tenth transistor T10 is 4.

[0167] In some exemplary embodiments, in the second gate drive circuit GOA-2, the length of each gate electrode G9 of the ninth transistor T9 along the first direction X is between 30% and 40% of the width of the second gate drive circuit GOA-2 along the first direction X, and the width of each gate electrode G9 of the ninth transistor T9 along the second direction Y is between 2% and 3% of the width of the second gate drive circuit GOA-2 along the first direction X.

[0168] In some exemplary embodiments, in the second gate drive circuit GOA-2, the length of each gate electrode G10 of the tenth transistor T10 along the first direction X is between 30% and 40% of the width of the second gate drive circuit GOA-2 along the first direction X, and the width of each gate electrode G10 of the tenth transistor T10 along the second direction Y is between 2% and 3% of the width of the second gate drive circuit GOA-2 along the first direction X.

[0169] The display substrate of this disclosure reduces the size of the GOA circuit while satisfying the driving and operation requirements.

[0170] In some exemplary embodiments, in the second gate drive circuit GOA-2, the length of each gate electrode G9 of the ninth transistor T9 along the first direction X can be between 16 and 160 micrometers, for example, it can be 45.4 micrometers; the width of each gate electrode G9 of the ninth transistor T9 along the second direction Y can be between 3 and 5 micrometers, for example, it can be 3.3 micrometers.

[0171] In some exemplary embodiments, in the second gate drive circuit GOA-2, the length of each gate electrode G10 of the tenth transistor T10 along the first direction X can be between 16 and 160 micrometers, for example, it can be 45.2 micrometers; the width of each gate electrode G10 of the tenth transistor T10 along the second direction Y can be between 3 and 5 micrometers, for example, it can be 3.3 micrometers.

[0172] In some exemplary implementations, such as Figure 3b As shown, the display substrate also includes a first planarization layer, which is disposed between the fourth conductive layer and the fifth conductive layer. The first planarization layer above the first gate driving circuit GOA-1 and the first planarization layer above the second gate driving circuit GOA-2 are continuously disposed.

[0173] In some exemplary implementations, such as Figure 3cAs shown, the border area 300 includes multiple straight-line extension areas 300a and corner areas 300b disposed between the multiple straight-line extension areas 300a. The circuit area also includes multiple dummy GOA circuit groups, each dummy GOA circuit group including at least one dummy GOA circuit. The multiple dummy GOA circuit groups are distributed around the display area 100 in the corner area 300b. In the display substrate of this embodiment, the dummy GOA circuits are changed from the original clustered design to a regularly distributed design, which improves the uniformity of the GOA circuits.

[0174] In some exemplary embodiments, the distance d2 between two adjacent Dummy GOA circuit groups is between 1 / 6 and 1 / 3 of the corner length d1. Exemplarily, the distance d2 between two adjacent Dummy GOA circuit groups is at most 1 / 4 of the corner length d1.

[0175] In some exemplary embodiments, the corner area 300b may be arc-shaped.

[0176] The remaining structure of the GOA circuit in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0177] The structure of a display substrate is illustrated below using an example of its fabrication process. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using one or more of spraying and spin coating; and etching can be performed using one or more of dry and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0178] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0179] The fabrication process of the display substrate in this exemplary embodiment includes the following steps:

[0180] (1) Provide a substrate.

[0181] In some exemplary embodiments, the substrate can be a rigid substrate or a flexible substrate. A rigid substrate may include one or more of glass and metal foil. A flexible substrate may include one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0182] (2) Forming a first semiconductor layer pattern. In some exemplary embodiments, forming the first semiconductor layer pattern includes: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film using a patterning process to form the first semiconductor layer pattern, such as... Figure 9a or Figure 9b As shown. The first semiconductor layer pattern includes at least an active layer for a plurality of transistors (e.g., transistors T1 to T13) in the GOA circuit. The active layer may include at least one channel region and a plurality of doped regions. The channel region may be undoped and has semiconductor properties. The doped regions are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor thin film may be polycrystalline silicon.

[0183] In some exemplary embodiments, the first semiconductor layer includes at least: an active layer 110 of a first transistor T1, an active layer 120 of a second transistor T2, an active layer 130 of a third transistor T3, an active layer 140 of a fourth transistor T4, an active layer 150 of a fifth transistor T5, an active layer 160 of a sixth transistor T6, an active layer 170 of a seventh transistor T7, an active layer 180 of an eighth transistor T8, an active layer 190 of a ninth transistor T9, an active layer 1100 of a tenth transistor T10, an active layer 1110 of an eleventh transistor T11, an active layer 1120 of a twelfth transistor T12, and an active layer 1130 of a thirteenth transistor T13.

[0184] In some exemplary embodiments, the active layer 110 of the first transistor T1, the active layer 120 of the second transistor T2, the active layer 130 of the third transistor T3, the active layer 150 of the fifth transistor T5, the active layer 170 of the seventh transistor T7, the active layer 180 of the eighth transistor T8, the active layer 190 of the ninth transistor T9, the active layer 1100 of the tenth transistor T10, the active layer 1110 of the eleventh transistor T11, and the active layer 1120 of the twelfth transistor T12 may extend along the second direction Y. The active layer 140 of the fourth transistor T4, the active layer 160 of the sixth transistor T6, and the active layer 1130 of the thirteenth transistor T13 may extend along the first direction X. However, this embodiment is not limited in this respect.

[0185] In some exemplary embodiments, the active layer 130 of the third transistor T3 is located in the second direction Y between the active layer 110 of the first transistor T1 and the active layer 1120 of the twelfth transistor T12. The active layers 120 of the second transistor T2 and 1110 of the eleventh transistor T11 are adjacent in the second direction Y. The active layer 180 of the eighth transistor T8 is located in the second direction Y between the active layer 170 of the seventh transistor T7 and the active layer 150 of the fifth transistor T5. The active layers of the ninth transistor T9 and the tenth transistor T10 are arranged sequentially in the second direction Y. The active layer 160 of the sixth transistor T6 is located in the first direction X between the active layer 120 of the second transistor T2 and the active layer 180 of the eighth transistor T8. The active layer 1130 of the thirteenth transistor T13 is located in the first direction X on the side of the active layer 150 of the fifth transistor T5 away from the active layer 1100 of the tenth transistor T10.

[0186] In some exemplary embodiments, the active layer of each transistor includes a channel region and first partitions 11-1 to 113-1 and second partitions 11-2 to 113-2 located on both sides of the channel region. The second partition 19-2 of the active layer of the ninth transistor T9 and the second partition 110-2 of the active layer of the tenth transistor T10 can be an interconnected integral structure. The first partition 15-1 of the active layer of the fifth transistor T5, the first partition 18-1 of the active layer of the eighth transistor T8, and the first partition 113-1 of the active layer of the thirteenth transistor T13 can be an interconnected integral structure.

[0187] In some exemplary embodiments, the orthographic projections of the active layer 150 of the fifth transistor T5, the active layer 180 of the eighth transistor T8, and the active layer 1120 of the twelfth transistor T12 onto the substrate can be L-shaped. The orthographic projections of the active layer 110 of the first transistor T1, the active layer 120 of the second transistor T2, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the active layer 160 of the sixth transistor, and the active layer 170 of the seventh transistor T7 onto the substrate can be dumbbell-shaped. The active layer 190 of the ninth transistor T9 and the active layer 1100 of the tenth transistor T10 can be rectangular. However, this embodiment is not limited in this respect.

[0188] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polycrystalline silicon. The channel region may be undoped and have semiconductor properties. The first and second partitions may be located on opposite sides of the channel region and are doped with impurities, thus becoming conductive. The impurities may vary depending on the type of transistor.

[0189] (3) Forming a first conductive layer pattern. In some exemplary embodiments, forming the first conductive layer pattern includes: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the first insulating layer, such as... Figure 10a and Figure 10b As shown. In some examples, the first conductive layer pattern may include: the gate electrodes of a plurality of transistors (e.g., transistors T1 to T13) of the GOA circuit, and the first electrodes of a plurality of capacitors (e.g., first capacitor C1 to third capacitor C3) of the GOA circuit.

[0190] In some exemplary embodiments, the first conductive layer may include: the gate electrode G1 of the first transistor T1, the gate electrode G2 of the second transistor T2, the gate electrode G3 of the third transistor T3, the gate electrode G4 of the fourth transistor T4, the gate electrode G5 of the fifth transistor T5, the gate electrode G6 of the sixth transistor T6, the gate electrode G7 of the seventh transistor T7, the gate electrode G8 of the eighth transistor T8, the gate electrode G9 of the ninth transistor T9, the gate electrode G10 of the tenth transistor T10, the gate electrode G11 of the eleventh transistor T11, the gate electrode G12 of the twelfth transistor T12, the gate electrode G13 of the thirteenth transistor T13, the first terminal C1a of the first capacitor C1, the first terminal C2a of the second capacitor C2, and the first terminal C3a of the third capacitor C3.

[0191] In some exemplary embodiments, the first conductive layer may further include a first connection electrode 101. The first connection electrode 101, the gate electrode G2 of the second transistor T2, and the gate electrode G8 of the eighth transistor may be an integral structure.

[0192] In some exemplary embodiments, the gate electrode G11 of the eleventh transistor T11 and the gate electrode G12 of the twelfth transistor T12 can be a single integrated structure. The gate electrode G4 of the fourth transistor T4, the first terminal C3a of the third capacitor C3, and the gate electrode G10 of the tenth transistor T10 can be a single integrated structure. The gate electrode G6 of the sixth transistor T6 and the first terminal C1a of the first capacitor C1 can be a single integrated structure. The gate electrode G9 of the ninth transistor T9 and the first terminal C2a of the second capacitor C2 can be a single integrated structure. However, this embodiment is not limited to these embodiments.

[0193] In some exemplary embodiments, the ninth transistor T9 and the tenth transistor T10 may be multi-gate transistors to prevent and reduce leakage current. However, this embodiment is not limited to this.

[0194] In some exemplary embodiments, the ninth transistor T9 includes a plurality of gate electrodes G9 arranged in parallel at intervals, and the tenth transistor T10 includes a plurality of gate electrodes G10 arranged in parallel at intervals. The number of gate electrodes G9 of the ninth transistor T9 in the second gate driving circuit GOA-2 is greater than the number of gate electrodes G9 of the ninth transistor T9 in the first gate driving circuit GOA-1. The number of gate electrodes G10 of the tenth transistor T10 in the second gate driving circuit GOA-2 is less than the number of gate electrodes G10 of the tenth transistor T10 in the first gate driving circuit GOA-1.

[0195] In some exemplary embodiments, in the second gate drive circuit GOA-2, the number of gate electrodes G9 of the ninth transistor T9 is 6, and the number of gate electrodes G10 of the tenth transistor T10 is 2.

[0196] In some exemplary embodiments, in the first gate drive circuit GOA-1, the number of gate electrodes G9 of the ninth transistor T9 is 4, and the number of gate electrodes G10 of the tenth transistor T10 is 4.

[0197] (4) Forming a second conductive layer pattern. In some exemplary embodiments, forming a second conductive layer pattern includes: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the second insulating layer, such as... Figure 11a and Figure 11b As shown. In some examples, the second conductive layer pattern may include the second terminals of multiple capacitors (e.g., first capacitor C1 to third capacitor C3) of the GOA circuit.

[0198] In some exemplary embodiments, the second conductive layer may include: the second terminal C1b of the first capacitor C1, the second terminal C2b of the second capacitor C2, and the second terminal C3b of the third capacitor C3. However, this embodiment is not limited thereto.

[0199] In some exemplary embodiments, the projection of the second electrode C1b of the first capacitor C1 onto the substrate overlaps with the projection of the first electrode C1a onto the substrate. Similarly, the projection of the second electrode C2b of the second capacitor C2 onto the substrate overlaps with the projection of the first electrode C2a onto the substrate. Likewise, the projection of the second electrode C3b of the third capacitor C3 onto the substrate overlaps with the projection of the first electrode C3a onto the substrate.

[0200] (5) Forming a third conductive layer pattern. In some exemplary embodiments, forming a third conductive layer pattern includes: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a third insulating layer covering the second conductive layer; and a third conductive layer pattern disposed on the third insulating layer, such as... Figure 12a As shown. In some examples, in the GOA-1 circuit, the third conductive layer pattern may include: a second connection electrode 301. The second connection electrode 301 is configured to be connected to a subsequently formed sixth connection electrode 404 via a subsequently formed fourth via E1, and to the second electrodes D10-1 and D10-2 of a subsequently formed tenth transistor T10 via a subsequently formed fourth via E2.

[0201] (6) Forming a fourth insulating layer pattern. In some exemplary embodiments, forming the fourth insulating layer pattern includes: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the second conductive layer, such as... Figure 13a and Figure 13b As shown. In some examples, multiple vias are formed on the fourth insulating layer. The multiple vias include at least: multiple first vias F1 to F28, multiple second vias K1 to K13, multiple third vias D1 to D4, and fourth vias E1 to E2. The fourth, third, second, and first insulating layers within the multiple first vias F1 to F28 are etched away, exposing the surface of the first semiconductor layer. The fourth, third, and second insulating layers within the multiple second vias K1 to K13 are etched away, exposing the surface of the first conductive layer. The fourth and third insulating layers within the multiple third vias D1 to D4 are etched away, exposing the surface of the second conductive layer. The fourth insulating layer within the fourth vias E1 to E2 is etched away, exposing the surface of the third conductive layer.

[0202] (7) Forming a fourth conductive layer pattern. In some exemplary embodiments, forming a fourth conductive layer pattern includes: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer pattern on a fourth insulating layer, such as... Figure 14a and Figure 14b As shown. In some examples, the fourth conductive layer pattern may include: first terminals S1 to S13 and second terminals D1 to D13 of multiple transistors (e.g., first transistor T1 to thirteenth transistor T13) of the GOA circuit, multiple clock signal lines (e.g., first clock signal line CK, second clock signal line CB, and third clock signal line NCX) and multiple power supply lines (e.g., initial signal line STV, first high voltage line VGH1, and second low voltage lines VGL1 to VGL2).

[0203] In some exemplary embodiments, the first terminal S3 and the second low-voltage line VGL1 of the third transistor T3 can be an integral structure. The first terminal S1 and the initial signal line STV of the first transistor T1 can be an integral structure. The second terminal D2 of the second transistor T2, the second terminal D3 of the third transistor T3, and the first terminal S11 of the eleventh transistor T11 can be an integral structure. The second terminal D4 of the fourth transistor T4 and the second terminal D5 of the fifth transistor T5 can be an integral structure. The first terminals S10-1 and S10-2 of the tenth transistor T10 and the second low-voltage line VGL2 can be an integral structure. The first terminal S5 of the fifth transistor T5, the first terminal S8 of the eighth transistor T8, the first terminals S9-1 to S9-2 of the ninth transistor T9, the first terminal S13 of the thirteenth transistor T13, and the first high-voltage line VGH1 can be an integral structure. The second terminal D8 of the eighth transistor T8 and the first terminal S7 of the seventh transistor T7 can be an integral structure. The second terminal D6 of the sixth transistor T6 and the second terminal D7 of the seventh transistor T7 can be an integral structure.

[0204] In some exemplary embodiments, in the GOA-1 and GOA-2 circuits, the fourth conductive layer pattern may further include: a third connection electrode 401, a fourth connection electrode 402, a fifth connection electrode 403, and a sixth connection electrode 404. The third connection electrode 401 is integrally formed with the second electrode D13 of the thirteenth transistor T13, the fourth connection electrode 402 is integrally formed with the second electrode D1 of the first transistor T1, and the fifth connection electrode 403 is integrally formed with the first electrode S12 of the twelfth transistor T12. The first connection electrode 101 is connected to the third connection electrode 401 through the second via K5, to the fourth connection electrode 402 through the second via K2, and to the fifth connection electrode 403 through the second via K7.

[0205] In some exemplary embodiments, in the GOA-1 circuit, the sixth connection electrode 404 and the second electrodes D9-1 to D9-3 of the ninth transistor are integrally structured. The second connection electrode 301 is connected to the sixth connection electrode 404 through the fourth via E1 and to the second electrodes D10-1 to D10-2 of the tenth transistor through the fourth via E2.

[0206] In some exemplary embodiments, in the GOA-2 circuit, the sixth connection electrode 404 is integrated with the second electrodes D9-1 to D9-3 of the ninth transistor and the second electrodes D10-1 to D10-2 of the tenth transistor. However, this embodiment is not limited to this.

[0207] (7) Forming a fifth conductive layer pattern. In some exemplary embodiments, forming the fifth conductive layer pattern includes: sequentially depositing a first planarization film and a fifth conductive film on a substrate on which the aforementioned pattern is formed; patterning the first planarization film and the fifth conductive film using a patterning process; and forming the first planarization layer and the fifth conductive layer pattern on the fourth conductive layer, such as... Figure 7 and Figure 8 As shown. In some examples, the fifth conductive layer pattern may include: a second branch VSS-2 of the second power line, a first high voltage line VGH2, second low voltage lines VGL3 to VGL4, and a plurality of initial signal lines (e.g., a first initial signal line ESTV for providing an initial signal for the first gate drive circuit GOA-1, a second initial signal line GSTV_N for providing an initial signal for the second gate drive circuit GOA-2, and a third initial signal line GSTV_P for providing an initial signal for the third gate drive circuit GOA-3).

[0208] In some exemplary embodiments, the second branch VSS-2 of the second power line may be located above the isolation region 320 and the GOA-1 circuit. The second branch VSS-2 of the second power line includes a plurality of venting openings for forming venting paths through which gas components in the first planarization layer can evaporate during the process, thereby preventing the gas components in the first planarization layer from damaging the organic light-emitting layer in the pixel.

[0209] In some exemplary embodiments, the first high voltage line VGH2, the second low voltage lines VGL3 to VGL4, and a plurality of initial signal lines (e.g., the first initial signal line ESTV, the second initial signal line GSTV_N, and the third initial signal line GSTV_P) may be located above the GOA-2 circuit.

[0210] In some exemplary embodiments, pixel circuits can be formed in the display area while the GOA circuit is formed in the non-display area. For example, the first semiconductor layer in the display area may include the active layer of the transistors of the pixel circuit, the first conductive layer in the display area may include the gate electrode of the transistors of the pixel circuit and the first electrode of the storage capacitor, the second conductive layer in the display area may include at least the second electrode of the storage capacitor of the pixel circuit, and the third conductive layer in the display area may include at least the first and second electrodes of the transistors of the pixel circuit. After forming the first conductive layer, a second semiconductor layer can be formed in the display area, and an insulating layer is disposed between the second semiconductor layer and the first conductive layer. The material of the second semiconductor thin film can be a metal oxide, such as IGZO. However, this embodiment does not limit the location of the second semiconductor layer.

[0211] In some exemplary embodiments, after forming the fifth conductive layer, patterns such as a second planarization layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer can be sequentially formed in the display area. In some examples, a second planarization film is coated on a substrate with the aforementioned patterns, and a second planarization layer pattern is formed by masking, exposing, and developing the second planarization film. Subsequently, an anode film is deposited on the substrate of the display area with the aforementioned patterns, and the anode film is patterned using a patterning process to form an anode pattern on the second planarization layer. Then, a pixel definition film is coated on the substrate with the aforementioned patterns, and a pixel definition layer (PDL) pattern is formed by masking, exposing, and developing processes. The pixel definition layer is formed in each sub-pixel of the display area, and the pixel definition layer in each sub-pixel forms a pixel opening that exposes the anode. Subsequently, an organic light-emitting layer is formed within the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned using a patterning process to form a cathode pattern. Subsequently, an encapsulation layer is formed on the cathode, which may include a stacked structure of inorganic / organic / inorganic materials.

[0212] In some exemplary embodiments, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first planarization layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The first and second insulating layers are referred to as gate insulation (GI) layers, the third insulating layer as interlayer insulation (ILD) layers, and the fourth insulating layer as passivation layers. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. However, this embodiment is not limited in this respect. For example, the anode can be made of a reflective material such as a metal, and the cathode can be made of a transparent conductive material.

[0213] The structure and its fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0214] This disclosure also provides a display device, including the display substrate described above. In some exemplary embodiments, the display substrate may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. However, this embodiment is not limited thereto.

[0215] This disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and a frame area located on at least one side of the display area, the frame area including a circuit area and a partition area sequentially arranged along a direction away from the display area, the circuit area including a third gate driving circuit, a second gate driving circuit and a first gate driving circuit sequentially arranged along a direction away from the display area, the partition area including a power line, the power line including a first branch and a second branch, the fabrication method including:

[0216] A first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer are sequentially formed on a substrate. The first semiconductor layer includes an active layer of multiple polysilicon transistors. The first conductive layer includes gate electrodes of multiple polysilicon transistors and a first electrode of a storage capacitor. The second conductive layer includes a second electrode of the storage capacitor. The second semiconductor layer includes an active layer of multiple oxide transistors. The third conductive layer includes gate electrodes of multiple oxide transistors. The fourth conductive layer includes first and second electrodes of multiple polysilicon transistors, first and second electrodes of multiple oxide transistors, and a first branch of the power line. The fifth conductive layer includes a second branch of the power line. The orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first branch of the power line on the substrate. The orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first gate driving circuit on the substrate. The orthographic projection of the first branch of the power line on the substrate does not overlap with the orthographic projection of the first gate driving circuit on the substrate.

[0217] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising a display area and a frame area located on at least one side of the display area, the frame area comprising a circuit area and a partition area arranged sequentially along a direction away from the display area, the circuit area comprising a third gate driving circuit, a second gate driving circuit and a first gate driving circuit arranged sequentially along a direction away from the display area, the partition area comprising a power line, the power line comprising a first branch and a second branch; In a plane perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on a substrate. The first semiconductor layer includes an active layer of multiple polysilicon transistors. The first conductive layer includes gate electrodes of multiple polysilicon transistors and a first electrode of a storage capacitor. The second conductive layer includes a second electrode of a storage capacitor. The second semiconductor layer includes an active layer of multiple oxide transistors. The third conductive layer includes gate electrodes of multiple oxide transistors. The fourth conductive layer includes first and second electrodes of multiple polysilicon transistors, first and second electrodes of multiple oxide transistors, and a first branch of the power line. The fifth conductive layer includes a second branch of the power line. The orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first branch of the power line on the substrate, and the orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first gate driving circuit on the substrate. The orthographic projection of the first branch of the power line on the substrate does not overlap with the orthographic projection of the first gate driving circuit on the substrate.

2. The display substrate according to claim 1, wherein, The orthographic projection of the second branch of the power line on the substrate does not overlap with the orthographic projection of the second gate drive circuit on the substrate.

3. The display substrate according to claim 1, wherein, The second branch of the power line includes a plurality of spaced-apart venting openings, and the orthographic projection of the plurality of venting openings on the substrate overlaps with the orthographic projection of the first branch of the power line and the first gate driving circuit on the substrate.

4. The display substrate according to claim 3, wherein, The area of ​​the vent opening projected onto the substrate is 5% to 15% of the area of ​​the second branch of the power line projected onto the substrate.

5. The display substrate according to claim 1, wherein, The first gate driving circuit and the second gate driving circuit respectively include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, a second capacitor, and a third capacitor; The gate electrode of the first transistor, the first electrode of the second transistor, and the gate electrode of the third transistor are all electrically connected to the first clock signal line. The first electrode of the first transistor is electrically connected to the input terminal. The second electrode of the first transistor is electrically connected to the gate electrode of the second transistor, the gate electrode of the eighth transistor, the first electrode of the twelfth transistor, and the first electrode of the thirteenth transistor. The second terminal of the second transistor is electrically connected to the second terminal of the third transistor, the gate electrode of the fifth transistor, and the first terminal of the eleventh transistor; The first electrode of the third transistor, the first electrode of the tenth transistor, the gate electrode of the eleventh transistor, and the gate electrode of the twelfth transistor are all electrically connected to the second low-voltage line. The gate electrode of the fourth transistor is electrically connected to the second electrode of the twelfth transistor, the gate electrode of the tenth transistor, and the first plate of the third capacitor. The second electrode of the fourth transistor, the first electrode of the sixth transistor, and the gate electrode of the seventh transistor are all electrically connected to the second clock signal line. The first terminal of the fifth transistor, the first terminal of the eighth transistor, the first terminal of the ninth transistor, the second terminal of the thirteenth transistor, and the second plate of the second capacitor are all electrically connected to the first high-voltage line. The second terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor and the second plate of the third capacitor. The gate electrode of the sixth transistor is electrically connected to the first plate of the first capacitor and the second electrode of the eleventh transistor, and the second electrode of the sixth transistor is electrically connected to the second plate of the first capacitor and the first electrode of the seventh transistor. The second terminal of the seventh transistor is electrically connected to the second terminal of the eighth transistor, the gate electrode of the ninth transistor, and the first plate of the second capacitor; the second terminals of the ninth transistor and the tenth transistor are both electrically connected to the output terminal; the gate electrode of the thirteenth transistor is electrically connected to the third clock signal line.

6. The display substrate according to claim 5, wherein, The first high-voltage line includes a first branch and a second branch, and the second low-voltage line includes a first branch, a second branch, a third branch, and a fourth branch; The first branch of the first high-voltage line, the first branch of the second low-voltage line, and the second branch of the second low-voltage line are disposed in the same layer as the fourth conductive layer; the second branch of the first high-voltage line, the third branch of the second low-voltage line, and the fourth branch of the second low-voltage line are disposed in the same layer as the fifth conductive layer.

7. The display substrate according to claim 5, wherein, The first conductive layer includes a first connecting electrode, and the fourth conductive layer includes a third connecting electrode, a fourth connecting electrode, and a fifth connecting electrode; The first connecting electrode is connected to the gate electrode of the second transistor and the gate electrode of the eighth transistor to form an integral structure; the third connecting electrode is connected to the first electrode of the thirteenth transistor to form an integral structure; the fourth connecting electrode is connected to the second electrode of the first transistor to form an integral structure; and the fifth connecting electrode is connected to the first electrode of the twelfth transistor to form an integral structure. The first connecting electrode is connected to the third connecting electrode, the fourth connecting electrode, and the fifth connecting electrode through vias.

8. The display substrate according to claim 7, wherein, In the first gate drive circuit, the third connecting electrode is L-shaped.

9. The display substrate according to claim 8, wherein, The third clock signal line is disposed on the same layer as the fourth conductive layer. The third clock signal line includes a first protrusion, which is connected to the gate electrode of the thirteenth transistor through a via. The active layer of the thirteenth transistor includes a channel region. In the first gate drive circuit, the via connecting the first bump to the gate electrode of the thirteenth transistor and the via connecting the first connection electrode to the third connection electrode are respectively located on both sides of the channel region of the thirteenth transistor.

10. The display substrate according to claim 7, wherein in the second gate driving circuit, the third connecting electrode is in the shape of an "1".

11. The display substrate according to claim 10, wherein, The third clock signal line is disposed on the same layer as the fourth conductive layer. The third clock signal line includes a first protrusion, which is connected to the gate electrode of the thirteenth transistor through a via. The active layer of the thirteenth transistor includes a channel region. In the second gate drive circuit, the via connecting the first bump to the gate electrode of the thirteenth transistor and the via connecting the first connection electrode to the third connection electrode are located on the same side of the channel region of the thirteenth transistor.

12. The display substrate according to claim 11, wherein, The ninth transistor includes a plurality of gate electrodes arranged in parallel at intervals, and the tenth transistor includes a plurality of gate electrodes arranged in parallel at intervals. The number of gate electrodes of the ninth transistor in the second gate driving circuit is greater than the number of gate electrodes of the ninth transistor in the first gate driving circuit; the number of gate electrodes of the tenth transistor in the second gate driving circuit is less than the number of gate electrodes of the tenth transistor in the first gate driving circuit.

13. The display substrate according to claim 12, wherein, In the second gate driving circuit, the length of each gate electrode of the ninth transistor along the first direction is between 30% and 40% of the width of the second gate driving circuit along the first direction, and the width of each gate electrode of the ninth transistor along the second direction is between 2% and 3% of the width of the second gate driving circuit along the first direction.

14. The display substrate according to claim 12, wherein, The border area includes multiple straight-line extension areas and corner areas disposed between the multiple straight-line extension areas. The circuit area also includes multiple virtual gate driving circuit groups, each of which includes at least one virtual gate driving circuit. The multiple virtual gate driving circuit groups are distributed around the display area in the corner areas.

15. The display substrate according to claim 14, wherein, The distance between two adjacent virtual gate drive circuit groups is between 1 / 6 and 1 / 3 of the length of the corner region.

16. The display substrate according to claim 1, further comprising a first planarization layer disposed between the fourth conductive layer and the fifth conductive layer, wherein the first planarization layer above the first gate driving circuit and the first planarization layer above the second gate driving circuit are continuously disposed.

17. A display device comprising a display substrate as described in any one of claims 1 to 16.

18. A method for fabricating a display substrate, the display substrate comprising a display area and a border area located on at least one side of the display area, the border area comprising a circuit area and a partition area sequentially disposed along a direction away from the display area, the circuit area comprising a third gate driving circuit, a second gate driving circuit, and a first gate driving circuit sequentially disposed along a direction away from the display area, the partition area comprising a power line and an isolation dam disposed on the power line, the power line comprising a first branch and a second branch, the fabrication method comprising: A first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer are sequentially formed on a substrate. The first semiconductor layer includes an active layer of multiple polysilicon transistors. The first conductive layer includes gate electrodes of multiple polysilicon transistors and a first electrode of a storage capacitor. The second conductive layer includes a second electrode of a storage capacitor. The second semiconductor layer includes an active layer of multiple oxide transistors. The third conductive layer includes gate electrodes of multiple oxide transistors. The fourth conductive layer includes first and second electrodes of multiple polysilicon transistors, first and second electrodes of multiple oxide transistors, and a first branch of the power line. The fifth conductive layer includes a second branch of the power line. The orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first branch of the power line on the substrate, and the orthographic projection of the second branch of the power line on the substrate overlaps with the orthographic projection of the first gate driving circuit on the substrate. The orthographic projection of the first branch of the power line on the substrate does not overlap with the orthographic projection of the first gate driving circuit on the substrate.

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