Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate, a shielding signal line and at least one first adapter. The substrate comprises a display area and a peripheral area surrounding the display area; the shielding signal line is located on one side of the substrate and in the peripheral area, and is arranged around the display area. The side of the shielding signal line facing the display area comprises at least one avoiding slot. The first adapter is located in the same layer as the shielding signal line and in the avoiding slot. The first adapter is used for electrically connecting a gate drive circuit located on the side of the shielding signal line away from the display area with a gate line located in the display area. The array substrate disclosed by the application can avoid the problems of light leakage or flicker at the edge of the liquid crystal display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] During the fabrication of liquid crystal display (LCD) array substrates, shielding electrodes are typically placed around the display area to shield against external electric fields, preventing image quality issues such as edge light leakage. Currently, some products place the shielding signal line, which provides the shielding signal to the shielding electrodes, between the gate drive circuit and the gate line, and on the same film layer as the gate line. The gate drive circuit needs to cross the shielding signal line via a connection to the source / drain metal layer. Then, holes are drilled in the film layer between the shielding signal line and the display area to connect the source / drain metal layer lines to the gate line, thus completing the connection between the gate drive circuit and the gate line. Products using this approach still experience edge light leakage or flickering issues after prolonged use. Summary of the Invention

[0003] The present invention provides an array substrate, a display panel, and a display device to solve the problem of light leakage at the edge of a liquid crystal display panel.

[0004] A first aspect of the present invention provides an array substrate, comprising:

[0005] Substrate; the substrate includes a display area and a peripheral area surrounding the display area;

[0006] A shielded signal line is located on one side of the substrate; the shielded signal line is located in the peripheral area and is disposed around the display area; the side of the shielded signal line facing the display area includes at least one clearance groove;

[0007] At least one first adapter is located on the same layer as the shielded signal line and in a clearance slot; the first adapter is used to electrically connect the gate drive circuit located on the side of the shielded signal line away from the display area to the gate line located within the display area.

[0008] In some embodiments, the shielded signal line includes a plurality of clearance slots, and adjacent clearance slots are spaced a predetermined distance apart; one clearance slot corresponds to a first adapter; each first adapter is located in the corresponding clearance slot.

[0009] In some embodiments, the array substrate further includes: a second adapter portion located on the side of the shielded signal line away from the substrate; one end of the second adapter portion is electrically connected to the first adapter portion, and the other end is electrically connected to the gate drive circuit.

[0010] In some embodiments, the orthographic projection of the second adapter on the substrate overlaps at least partially with the orthographic projection of the shielded signal line on the substrate.

[0011] In some embodiments, the array substrate further includes: a third adapter portion located on the side of the first adapter portion and the second adapter portion away from the substrate; the third adapter portion is used to electrically connect the first adapter portion and the second adapter portion.

[0012] In some embodiments, the array substrate further includes: a shielding electrode located on the side of the shielding signal line away from the substrate; the orthographic projection of the shielding electrode on the substrate is located in the peripheral region, and the area of ​​the orthographic projection of the shielding electrode on the substrate is larger than the area of ​​the orthographic projection of the shielding signal line on the substrate; the shielding electrode is electrically connected to the shielding signal line.

[0013] The shielding electrode and the third adapter are located on the same layer; the shielding electrode includes multiple openings, the third adapter is located in the openings, and the third adapter and the shielding electrode are spaced apart.

[0014] In some embodiments, the array substrate further includes:

[0015] A first conductive layer is located on one side of the substrate; the first conductive layer includes a shielded signal line, a first transition portion, and a gate line;

[0016] The first insulating layer is located on the side of the first conductive layer that is away from the substrate.

[0017] The second conductive layer is located on the side of the first insulating layer that is away from the first conductive layer; the second conductive layer includes a second transition portion.

[0018] The second insulating layer is located on the side of the second conductive layer that is away from the first insulating layer;

[0019] The third conductive layer is located on the side of the second insulating layer opposite to the second conductive layer; the third conductive layer includes a third transition portion and a shielding electrode; the third transition portion is electrically connected to the first transition portion through a first via penetrating the second insulating layer and the first insulating layer, and is electrically connected to the second transition portion through a second via penetrating the second insulating layer; the shielding electrode is electrically connected to the shielded signal line through a third via penetrating the second insulating layer and the first insulating layer.

[0020] In some embodiments, the second conductive layer further includes data lines that intersect with the gate lines; both the gate lines and the data lines extend from the display area to the surrounding area;

[0021] The shielded signal line includes a first portion parallel to the grid line and a second portion parallel to the data line; a clearance slot is provided on the second portion.

[0022] A second aspect of the present invention also provides a display panel comprising an array substrate as described above, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

[0023] A third aspect of the present invention also provides a display device comprising the display panel of any of the above claims.

[0024] The beneficial effects of this invention are as follows:

[0025] This invention provides an array substrate, a display panel, and a display device. The array substrate includes a substrate, a shielded signal line, and at least one first adapter portion. The substrate includes a display area and a peripheral area surrounding the display area. The shielded signal line is located on one side of the substrate and within the peripheral area, surrounding the display area. The side of the shielded signal line facing the display area includes at least one clearance groove. The first adapter portion is located on the same layer as the shielded signal line and is situated within the clearance groove. The first adapter portion is used to electrically connect a gate driving circuit located on the side of the shielded signal line away from the display area to a gate line located within the display area.

[0026] The array substrate provided by the present invention has a clearance groove on the shielded signal line and a first adapter portion is disposed within the clearance groove. Compared with the arrangement method in the related technology, without changing the area of ​​the display area and the surrounding area, and without changing the setting position of the shielded signal line, the distance between the first adapter portion and the display area can be increased from 20μm to 30μm to 30μm to 60μm. This can avoid the problem of edge light leakage or flickering caused by the negative pressure via being too close to the display area during the display process. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a top view of the array substrate structure in related technologies;

[0029] Figure 2 This is a partially enlarged top view of the array substrate structure in related technologies;

[0030] Figure 3 This is one of the schematic cross-sectional views of an array substrate in related technologies;

[0031] Figure 4 This is the second cross-sectional schematic diagram of an array substrate in related technologies;

[0032] Figure 5 This is a timing diagram of the driving signals in related technologies;

[0033] Figure 6 This is one of the enlarged top view schematic diagrams of the array substrate provided in an embodiment of the present invention;

[0034] Figure 7 This is a second partially enlarged top view of the array substrate provided in an embodiment of the present invention;

[0035] Figure 8 One of the cross-sectional schematic diagrams of the array substrate provided in the embodiment of the present invention;

[0036] Figure 9 A second cross-sectional schematic diagram of the array substrate provided in an embodiment of the present invention;

[0037] Figure 10 This is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in the present invention are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of the present invention. The accompanying drawings of the present invention are for illustrative purposes only and do not represent actual proportions.

[0039] Figure 1 This is a top view of the array substrate structure in related technologies; Figure 2 This is a partially enlarged top view of the array substrate structure in related technologies; Figure 3 This is one of the schematic cross-sectional views of an array substrate in related technologies; Figure 4 This is the second cross-sectional schematic diagram of an array substrate in related technologies.

[0040] A liquid crystal display panel includes an array substrate and a counter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the counter substrate. In related technologies, such as... Figure 1As shown, the array substrate includes a display area S1 and a peripheral area S2 surrounding the display area S1. To prevent external electric fields from affecting the signal of the display area S1, a shielding electrode 12 is provided in the peripheral area S2 to surround the display area S1. The shielding electrode 12 inputs a shielding signal through the shielding signal line 11 to shield the external electric field.

[0041] Figure 2 for Figure 1 Enlarged diagram of region A in the middle. Figure 3 for Figure 2 A sectional view along section line BB. Figure 4 for Figure 2 A sectional view along section line CC. (e.g.) Figure 2 and Figure 3 As shown, the shielding electrode 12 is located on the side of the shielding signal line 11 away from the substrate 18. An insulating layer is provided between the shielding electrode 12 and the shielding signal line 11. The shielding electrode 12 and the shielding signal line 11 are connected through a via penetrating the insulating layer.

[0042] In related technologies, such as Figure 2 As shown, the shielding signal line 11 is disposed between the gate driving circuit 13 and the gate line 17 in the display area S1. The gate driving circuit 13 is used to input a gate driving signal to the gate line 17 to drive the thin-film transistors (TFTs) of each pixel unit in the display area S1 to turn on or off. In specific implementations, the gate driving circuit 13 can be a GOA circuit composed of multiple GOA (Gate On Array) units, which is not limited here. In specific implementations, since the shielding signal line 11 and the gate line 17 are usually disposed on the same film layer, such as... Figure 4 As shown, when connecting the gate drive circuit and the gate line, it is necessary to connect the gate drive circuit to the source / drain metal layer (typically including the source and drain of the thin-film transistor) using the traces of the source / drain metal layer, which cross the shielded signal line 11. Since the source / drain metal layer and the gate line are located in different film layers, the gate line is usually located between the substrate 18 and the first insulating layer 19, and the source / drain metal layer is usually located between the first insulating layer 19 and the second insulating layer 20. In related technologies, a first via is opened through the second insulating layer 20 and the first insulating layer 19 to expose the first connection portion 14, wherein the first connection portion 14 is located in the same film layer as the gate line and is electrically connected to the gate line. A second via is opened through the second insulating layer 20 to expose the second connection portion 15, wherein the second connection portion 15 is located in the source / drain metal layer and is electrically connected to the gate drive circuit. Then, the connection between the first connection portion 14 and the second connection portion 15 is made through the third connection portion 16 covering the first and second vias, thereby completing the connection between the gate drive circuit and the gate line.

[0043] Figure 5 This is a timing diagram of the driving signals in related technologies.

[0044] During the environmental reliability test, the test product manufactured using the above method still exhibited issues such as edge light leakage or flickering after prolonged use. For example... Figure 5 As shown, the researchers of this invention further discovered that, taking a 120Hz refresh rate as an example, the display duration T of one frame is approximately 8.3ms. During the display cycle of one frame, the gate drive signal (Gout) is a high voltage signal vgh (voltage approximately 14V) for approximately 23μs. The holding time of the high voltage signal vgh accounts for only 0.72% of the frame duration, while the gate drive signal (Gout) is a low voltage signal vgl (voltage approximately -14V) for approximately 99.73% of the frame duration. The voltage Vcom of the shielded signal line remains at approximately -0.2V. Therefore, during the display process, the gate drive signal remains a low voltage signal for a long time, and the first and second vias can be regarded as negative voltage vias. Because the first and second vias are under negative pressure for a long time during the display process, contaminants in the surrounding frame and liquid crystal molecules of the display panel are prone to move and accumulate towards the location of the vias. This causes changes in the high voltage retention rate (VHR) and anchoring capability of the liquid crystal alignment film. Due to the limitation of the bezel width of the display device, the current design distance between the first and second transition parts and the display area S1 is about 20μm to 30μm. When contaminants accumulate excessively, they can easily affect the normal display of the edge pixels of the display panel, resulting in edge light leakage or flickering.

[0045] In view of this, a first aspect of the present invention provides an array substrate for solving the above-mentioned problems.

[0046] Figure 6 This is one of the enlarged top view schematic diagrams of the array substrate provided in an embodiment of the present invention.

[0047] In embodiments of the present invention, such as Figure 6 As shown, the array substrate includes a substrate 18, a shielded signal line 11, and at least one first adapter portion 14.

[0048] The substrate 18 is located at the bottom of the array substrate and serves a supporting and load-bearing function. The substrate 18 can be a conventional shape such as rectangular or square; however, it can also be irregularly shaped when applied to irregularly shaped displays. The material of the substrate 18 can be a transparent material such as optical glass or optical resin, and is not limited thereto. Figure 1 As shown, the shape and size of the substrate 18 are the same as those of the array substrate, and the substrate 18 includes a display area S1 and a peripheral area S2 surrounding the display area S1.

[0049] The shielded signal line 11 is located on one side of the substrate 18. For example... Figure 1 As shown, the shielded signal line 11 is located within the surrounding area S2 and is arranged around the display area S1. Figure 6 As shown, the shielded signal line 11 includes at least one clearance groove H on the side facing the display area S1.

[0050] At least one first adapter 14. The first adapter 14 is located on the same layer as the shielded signal line 11 and is located in the clearance slot H. The first adapter 14 is used to electrically connect the gate drive circuit located on the side of the shielded signal line 11 away from the display area S1 to the gate line 17 located in the display area S1.

[0051] In this embodiment of the invention, a clearance groove H is provided on the shielded signal line 11, and the first adapter 14 is disposed within the clearance groove H. Compared with the arrangement method in related technologies, without changing the area of ​​the display area S1 and the surrounding area S2, and without changing the setting position of the shielded signal line 11, the distance between the first adapter 14 and the display area S1 can be increased from 20μm~30μm to 30μm~60μm. This avoids the problem of edge light leakage or flickering caused by the negative pressure via being too close to the display area during the display process. Furthermore, the array substrate provided in this embodiment of the invention can be manufactured using existing processes. The clearance groove H can be directly formed by etching while manufacturing the shielded signal line 11, avoiding the problem of increased manufacturing difficulty and cost, and ensuring process stability.

[0052] In some embodiments, such as Figure 6 As shown, the shielded signal line 11 includes multiple clearance slots H, with adjacent clearance slots H spaced a predetermined distance apart. Each clearance slot H corresponds to a first connecting portion 14, and each first connecting portion 14 is located within its corresponding clearance slot H. Since the first connecting portions 14 are typically spaced a certain distance apart, by creating multiple mutually spaced clearance slots H on the shielded signal line 11, with each clearance slot H slightly larger than the first connecting portion 14 to accommodate it, large-area slotting of the shielded signal line 11 can be avoided. This ensures the trace area of ​​the shielded signal line 11, reduces its internal resistance, and guarantees signal transmission efficiency.

[0053] In some embodiments, the size of a clearance slot H on the shielded signal line 11 may be much larger than the size of a first connection portion 14, so that a clearance slot H can accommodate multiple first connection portions 14, thereby reducing the number of clearance slots H, which is not limited here.

[0054] Figure 7 This is a second enlarged top view of the array substrate provided in an embodiment of the present invention.

[0055] In some embodiments, such as Figure 7 As shown, the array substrate also includes a second adapter 15. The second adapter 15 is located on the side of the shielded signal line 11 facing away from the substrate 18. One end of the second adapter 15 is electrically connected to the first adapter 14, and the other end is electrically connected to the gate drive circuit 13, thereby realizing the connection between the gate line 17 and the gate drive circuit 13. Figure 7 As shown, a second connection portion 15 corresponds to a first connection portion 14. The second connection portion 15 is located on the side of the corresponding first connection portion 14 away from the display area S1, and is electrically connected to its corresponding first connection portion 14.

[0056] In some embodiments, such as Figure 7 As shown, the array substrate further includes a third adapter 16. The third adapter 16 is located on the side of the first adapter 14 and the second adapter 15 facing away from the substrate 18, wherein the first adapter 14 and the second adapter 15 are electrically connected through the third adapter 16. In a specific implementation, as... Figure 7 As shown, a third adapter 16 corresponds to a first adapter 14. The orthographic projection of the first adapter 14 on the substrate 18 and the orthographic projection of the second adapter 15 corresponding to the first adapter 14 on the substrate 18 are both located within the orthographic projection of the third adapter 16 corresponding to the first adapter on the substrate 18.

[0057] In some embodiments, such as Figure 7 As shown, the orthographic projection of the second adapter 15 on the substrate 18 at least partially overlaps with the orthographic projection of the shielding signal line 11 on the substrate 18, thereby reducing the distance between the second adapter 15 and the first adapter 14, and thus reducing the size of the third adapter 16. In a specific implementation, the second adapter 15 may also be located on the side of the shielding signal line 11 away from the display area S1, so that the orthographic projection of the second adapter 15 on the substrate 18 does not overlap with the orthographic projection of the shielding signal line 11 on the substrate 18, which is not limited here.

[0058] In some embodiments, such as Figure 7As shown, the array substrate also includes a shielding electrode 12. The shielding electrode 12 is located on the side of the shielding signal line 11 facing away from the substrate 18. The orthographic projection of the shielding electrode 12 on the substrate 18 is located within the peripheral region S2, and the area of ​​the orthographic projection of the shielding electrode 12 on the substrate 18 is larger than the area of ​​the orthographic projection of the shielding signal line 11 on the substrate 18. The shielding signal line 11 is electrically connected to the shielding electrode 12, thereby inputting a shielding signal to the shielding electrode 12 through the shielding signal line 11 to shield the external electric field. In this embodiment of the invention, the area of ​​the orthographic projection of the shielding electrode 12 on the substrate 18 is larger than the area of ​​the orthographic projection of the shielding signal line 11 on the substrate 18, and the shielding electrode 12 has a larger area, resulting in a better electric field shielding effect compared to only providing the shielding signal line 11. In specific implementations, the orthographic projection of the shielding electrode 12 on the substrate 18 can cover the entire peripheral region S2, which is not limited here.

[0059] In some embodiments, the shielding electrode 12 and the third transition portion 16 are located on the same layer. The shielding electrode 12 includes a plurality of openings K, the third transition portion 16 is located in the openings K, and the third transition portion 16 is spaced apart from the shielding electrode 12. In a specific implementation, by setting the orthographic projection of the second transition portion 15 on the substrate 18 to at least partially overlap with the orthographic projection of the shielding signal line 11 on the substrate 18, the distance between the second transition portion 15 and the first transition portion 14 can be reduced, thereby reducing the size of the third transition portion 16, and consequently reducing the size of the openings K, ensuring the coverage area of ​​the shielding electrode 16, and improving the effect of electric field shielding.

[0060] Figure 8 One of the cross-sectional schematic diagrams of the array substrate provided in the embodiment of the present invention; Figure 9 This is a second cross-sectional schematic diagram of the array substrate provided in an embodiment of the present invention.

[0061] In specific implementation, such as Figure 8 As shown, the array substrate provided in this embodiment of the invention includes: a first conductive layer 21, a first insulating layer 19, a second conductive layer 22, a second insulating layer 20, and a third conductive layer 23.

[0062] The first conductive layer 21 is located on one side of the substrate 18. The first conductive layer 21 includes a shielded signal line 11, a first connection portion 14, and a gate line 17. In a specific implementation, the first conductive layer 21 may also include the gate of a thin-film transistor located within the display area S1 and connected to the gate line; this is not limited here. The first conductive layer may be made of conductive materials such as metal; this is not limited here.

[0063] The first insulating layer 19 is located on the side of the first conductive layer 31 facing away from the substrate 18, and is used to provide insulation protection for the first conductive layer 21. The first insulating layer 19 can be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and insulating resin, and is not limited thereto. In specific implementations, the first insulating layer 19 can be a single-layer structure or a composite structure of multiple film layers, and is not limited thereto.

[0064] The second conductive layer 22 is located on the side of the first insulating layer 19 opposite to the first conductive layer 21. The second conductive layer includes a second transition portion 15. In specific embodiments, the second conductive layer 22 may also include a gate drive circuit output signal line 24 for connecting the second transition portion 15 and the gate drive circuit and for outputting a gate drive signal to the second transition portion 15, as well as the source electrode and drain electrode of the thin-film transistor located in the display area S1, etc., which are not limited here. The first conductive layer may be made of conductive materials such as metal, which are not limited here.

[0065] The second insulating layer 20 is located on the side of the second conductive layer 22 opposite to the first insulating layer 19, and is used to provide insulation protection for the second conductive layer 22. The first insulating layer 19 can be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and insulating resin, and is not limited here. In specific implementations, the first insulating layer 19 can be a single-layer structure or a composite structure of multiple film layers, and is not limited here.

[0066] The third conductive layer 23 is located on the side of the second insulating layer 20 opposite to the second conductive layer 22. The third conductive layer 23 includes a third connection portion 16 and a shielding electrode 12. For example... Figure 8 As shown, the third connecting portion 16 is electrically connected to the first connecting portion 14 through a first through-hole H1 penetrating the second insulating layer 20 and the first insulating layer 19, and is electrically connected to the second connecting portion 15 through a second through-hole H2 penetrating the second insulating layer 20. Figure 9 As shown, the shielding electrode 12 is electrically connected to the shielding signal line 11 through a third via H3 that penetrates the second insulating layer 20 and the first insulating layer 19. The orthographic projections of the first via H1, the second via H2, and the third via H3 on the substrate 1 do not overlap.

[0067] In some embodiments, the array substrate further includes data lines 25 that intersect with the gate lines 17. Specifically, the gate lines 17 and data lines 25 may be perpendicular to each other, which is not limited here. The data lines 25 are connected to the source electrodes of the thin-film transistors in the pixel circuit and are used to input display data signals to the pixel circuit. Figure 6 and Figure 7 As shown, both the gate line 17 and the data line 25 extend from the display area S1 to the peripheral area S2 and are connected to the gate driving circuit and the display driving circuit, respectively.

[0068] In specific implementation, such as Figure 1 , Figure 6 and Figure 7 As shown, the shielded signal line 11 includes a first part (not shown in the figure) parallel to the gate line 17 and a second part 112 parallel to the data line 25, and a clearance groove H is provided on the second part 112 of the shielded signal line 11.

[0069] Figure 10 This is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present invention.

[0070] A second aspect of the present invention provides a display panel.

[0071] The display panel can be a liquid crystal display panel, which includes the array substrate 1 provided in any of the above embodiments, the opposing substrate 2 disposed opposite to the array substrate 1, and the liquid crystal layer located between the array substrate 1 and the opposing substrate 2. In specific implementations, the display panel can also be other types of display panels, which are not limited here.

[0072] The display panel provided in this embodiment of the invention includes the array substrate provided in any of the above embodiments, and has the same technical effects as the array substrate in any of the above embodiments in specific implementation, which will not be described in detail here.

[0073] A third aspect of the present invention provides a display device. The display device provided by the present invention includes the display panel provided in any of the above embodiments, and has the same technical effects as the display panel in any of the above embodiments in specific implementations, which will not be elaborated further here.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, characterized in that, include: Substrate; The substrate includes a display area and a peripheral area surrounding the display area; A shielded signal line is located on one side of the substrate; the shielded signal line is located in the peripheral area and is disposed around the display area; the side of the shielded signal line facing the display area includes at least one clearance groove; At least one first adapter is located on the same layer as the shielded signal line and is located in the clearance slot; The first adapter is used to electrically connect the gate driving circuit located on the side of the shielded signal line away from the display area to the gate line located within the display area; wherein, the distance between the first adapter and the display area is 30. ~60 ; The second adapter is located on the side of the shielded signal line away from the substrate; one end of the second adapter is electrically connected to the first adapter, and the other end is electrically connected to the gate drive circuit. The third adapter is located on the side of the first adapter and the second adapter that is away from the substrate; the third adapter is used to electrically connect the first adapter and the second adapter.

2. The array substrate as described in claim 1, characterized in that, The shielded signal line includes a plurality of clearance slots, and adjacent clearance slots are spaced a set distance apart; one of the clearance slots corresponds to one of the first adapters; each of the first adapters is located in the corresponding clearance slot.

3. The array substrate as described in claim 1, characterized in that, The orthographic projection of the second adapter on the substrate overlaps at least partially with the orthographic projection of the shielded signal line on the substrate.

4. The array substrate as described in claim 1, characterized in that, Also includes: A shielding electrode is located on the side of the shielding signal line that is away from the substrate; the orthographic projection of the shielding electrode on the substrate is located in the peripheral area, and the area of ​​the orthographic projection of the shielding electrode on the substrate is larger than the area of ​​the orthographic projection of the shielding signal line on the substrate. The shielding electrode is electrically connected to the shielding signal line; The shielding electrode and the third adapter are located on the same layer; the shielding electrode includes multiple openings, the third adapter is located in the openings, and the third adapter is spaced apart from the shielding electrode.

5. The array substrate as described in claim 4, characterized in that, Also includes: A first conductive layer is located on one side of the substrate; the first conductive layer includes the shielded signal line, the first transition portion, and the gate line; The first insulating layer is located on the side of the first conductive layer that is away from the substrate. The second conductive layer is located on the side of the first insulating layer opposite to the first conductive layer; the second conductive layer includes the second transition portion. The second insulating layer is located on the side of the second conductive layer that is opposite to the first insulating layer; A third conductive layer is located on the side of the second insulating layer opposite to the second conductive layer; the third conductive layer includes the third transition portion and the shielding electrode; the third transition portion is electrically connected to the first transition portion through a first via penetrating the second insulating layer and the first insulating layer, and is electrically connected to the second transition portion through a second via penetrating the second insulating layer; the shielding electrode is electrically connected to the shielded signal line through a third via penetrating the second insulating layer and the first insulating layer.

6. The array substrate as described in claim 5, characterized in that, The second conductive layer also includes data lines that intersect with the gate lines; both the gate lines and the data lines extend from the display area to the peripheral area. The shielded signal line includes a first portion parallel to the grid line and a second portion parallel to the data line; the clearance slot is disposed on the second portion.

7. A display panel, characterized in that, It includes an array substrate as described in any one of claims 1 to 6, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

8. A display device, characterized in that, Includes the display panel as described in claim 7.

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