Dataflow-based computing unit, vector processor and artificial intelligence chip

Abstract

This disclosure provides a dataflow-based computing unit, vector processor, and artificial intelligence chip, relating to the field of artificial intelligence technology. The computing unit includes multiple computing circuits, comprising: a first computing circuit configured to perform a first calculation on a first set of data to obtain a first set of calculation results; a second computing circuit connected in parallel with the first computing circuit and configured to perform a second calculation on a second set of data to obtain a second set of calculation results; and a third computing circuit configured to perform a third calculation on a third set of data flowing to the third computing circuit, where the third set of data includes both the first set of calculation results and the second set of calculation results, to obtain a third set of calculation results, wherein at least one of the durations of the first calculation and the second calculation partially overlaps with the duration of the third calculation.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and in particular to a dataflow-based computing unit, vector processor, and artificial intelligence chip. Background Technology

[0002] With the development of artificial intelligence technology, various AI algorithms have been widely applied across various industries. However, the calculations involved in AI algorithms are typically highly complex and diverse, placing high demands on the computing units used to perform these calculations.

[0003] In related technologies, instruction set-based computing units are typically used to perform calculations in artificial intelligence algorithms. Summary of the Invention

[0004] The inventors noted that in related technologies, the computing speed of the computing unit is relatively low.

[0005] The inventors discovered through analysis that, for multi-step computations with data dependencies (i.e., the data required for the subsequent computation includes the results of the previous computation), in this instruction set-based computing unit, the preceding computation circuit only outputs all the results to the subsequent computation circuit after completing all the necessary preceding computations. The subsequent computation circuit must remain idle until it receives these results from the preceding computation circuit before it can begin executing the next computation. This step-by-step serial computation method results in a low computation speed for the computing unit.

[0006] To address the aforementioned problems, the present disclosure proposes the following solutions.

[0007] According to one aspect of the present disclosure, a data stream-based computing unit is provided, comprising: a first computing circuit configured to perform a first calculation on a first set of data to obtain a first set of calculation results; a second computing circuit connected in parallel with the first computing circuit and configured to perform a second calculation on a second set of data to obtain a second set of calculation results; and a third computing circuit configured to perform a third calculation on the third set of data to obtain a third set of calculation results when a third set of data flowing to the third computing circuit includes both the first set of calculation results and the second set of calculation results, wherein at least one of the duration of the first calculation and the duration of the second calculation partially overlaps with the duration of the third calculation.

[0008] In some embodiments, the first calculation is the same as the second calculation.

[0009] In some embodiments, the plurality of computing circuits further include: a fourth computing circuit configured to perform a fourth calculation on the fourth set of data to obtain a fourth set of calculation results when the fourth set of data flowing to the fourth computing circuit includes the third set of calculation results, wherein the fourth calculation is different from both the first calculation and the third calculation, and the duration of the fourth calculation partially overlaps with the duration of the third calculation.

[0010] In some embodiments, the fourth calculation is the inverse operation of the first calculation.

[0011] In some embodiments, the first calculation is a fixed-point to floating-point conversion calculation, and the fourth calculation is a floating-point to fixed-point conversion calculation.

[0012] In some embodiments, the plurality of computing circuits further include: a fifth computing circuit configured to perform a fifth calculation on the fifth set of data to obtain a fifth set of calculation results when the fifth set of data flowing to the fifth computing circuit includes the second set of calculation results, wherein the fifth calculation is different from the second calculation, and the duration of the fifth calculation partially overlaps with the duration of the second calculation; the fourth computing circuit is further configured to perform the fourth calculation on the fourth set of data when the fourth set of data includes the fifth set of calculation results.

[0013] In some embodiments, the fifth calculation is an exponential function calculation.

[0014] In some embodiments, the computing unit further includes at least one set of switches, each set of switches corresponding one-to-one with at least one of the plurality of computing circuits. Each set of switches includes a first switch connected in parallel with the corresponding computing circuit and a second switch connected in series with the corresponding computing circuit and in parallel with the first switch.

[0015] In some embodiments, the at least one set of switches includes two sets of switches that correspond one-to-one with at least two computing circuits.

[0016] In some embodiments, the fourth computing circuit and the fifth computing circuit correspond one-to-one with two sets of switches. Each set of switches includes a first switch connected in parallel with the corresponding computing circuit and a second switch connected in series with the corresponding computing circuit and in parallel with the first switch.

[0017] According to another aspect of the present disclosure, a vector processor is provided, including the data flow-based computing unit described in any of the above embodiments.

[0018] In some embodiments, the vector processor further includes: a data buffer configured to buffer the first set of data and the second set of data, and in response to a first drive signal corresponding to a computing task, to transfer the first set of data to the first computing circuit and to transfer the second set of data to the second computing circuit; a direct memory access module configured to, in response to a second drive signal corresponding to the computing task, read the first set of data and the second set of data from off-chip memory and to transfer the first set of data and the second set of data to the data buffer; and a control register configured to, in response to a control signal, send the first drive signal and the second drive signal.

[0019] According to another aspect of the present disclosure, an artificial intelligence chip is provided, including the vector processor described in any of the foregoing embodiments.

[0020] According to another aspect of the present disclosure, a data stream-based computation method is provided, comprising: a first computation circuit performing a first computation on a first set of data to obtain a first set of computation results; a second computation circuit connected in parallel with the first computation circuit performing a second computation on a second set of data to obtain a second set of computation results; and, when a third set of data flowing to a third computation circuit includes the first set of computation results and the second set of computation results, the third computation circuit performing a third computation on the third set of data to obtain a third set of computation results, wherein at least one of the duration of the first computation and the duration of the second computation partially overlaps with the duration of the third computation.

[0021] In some embodiments, the first calculation is the same as the second calculation.

[0022] In some embodiments, the calculation method further includes: when the fourth set of data flowing to the fourth calculation circuit includes the third set of calculation results, the fourth calculation circuit performs a fourth calculation on the fourth set of data to obtain a fourth set of calculation results, wherein the fourth calculation is different from both the first calculation and the third calculation, and the duration of the fourth calculation partially overlaps with the duration of the third calculation.

[0023] In some embodiments, the fourth calculation is the inverse operation of the first calculation.

[0024] In some embodiments, the first calculation is a fixed-point to floating-point calculation, and the fourth calculation is a floating-point to fixed-point calculation.

[0025] In some embodiments, the calculation method further includes: when the fifth set of data flowing to the fifth calculation circuit includes the second set of calculation results, the fifth calculation circuit performs a fifth calculation on the fifth set of data to obtain a fifth set of calculation results, wherein the fifth calculation is different from the second calculation, and the duration of the fifth calculation partially overlaps with the duration of the second calculation; when the fourth set of data includes the fifth set of calculation results, the fourth calculation circuit also performs the fourth calculation on the fourth set of data.

[0026] In some embodiments, the fifth calculation is an exponential function calculation.

[0027] In some embodiments, the first computing circuit and the second computing circuit correspond one-to-one with two sets of switches, each set of switches including a first switch and a second switch; the first switch corresponding to the first computing circuit is connected in parallel with the first computing circuit, and the second switch corresponding to the first computing circuit is connected in series with the first computing circuit and in parallel with the first switch corresponding to the first computing circuit; the first switch corresponding to the second computing circuit is connected in parallel with the second computing circuit, and the second switch corresponding to the second computing circuit is connected in series with the second computing circuit and in parallel with the first switch corresponding to the second computing circuit; under a first condition, the third set of data includes the first set of data and the second set of calculation results, and the first condition includes the first switch corresponding to the first computing circuit. Under the first condition, the second switch is turned off and the corresponding second switch is turned off, and the first switch corresponding to the second calculation circuit is turned on and the corresponding second switch is turned off; under the second condition, the third set of data includes the second set of data and the first set of calculation results, and the second condition includes the first switch corresponding to the first calculation circuit being turned off and the corresponding second switch being turned on, and the first switch corresponding to the second calculation circuit being turned on and the corresponding second switch being turned off; under the third condition, the third set of data includes the first set of data and the second set of data, and the third condition includes both the first switch corresponding to the first calculation circuit and the first switch corresponding to the second calculation circuit being turned on, and both the second switch corresponding to the first calculation circuit and the second switch corresponding to the second calculation circuit being turned off.

[0028] In some embodiments, the first computing circuit, the second computing circuit, and the third computing circuit correspond one-to-one with three sets of switches, each set of switches including a first switch and a second switch; the first switch corresponding to the first computing circuit is connected in parallel with the first computing circuit, the second switch corresponding to the first computing circuit is connected in series with the first computing circuit and in parallel with the first switch corresponding to the first computing circuit; the first switch corresponding to the second computing circuit is connected in parallel with the second computing circuit, the second switch corresponding to the second computing circuit is connected in series with the second computing circuit and in parallel with the first switch corresponding to the second computing circuit; the first switch corresponding to the third computing circuit is connected in parallel with the third computing circuit, the second switch corresponding to the third computing circuit is connected in series with the third computing circuit and in parallel with the first switch corresponding to the third computing circuit; under the fourth condition, the fourth set of data includes the first set of data, the fourth condition includes both the first switch corresponding to the first computing circuit and the first switch corresponding to the third computing circuit being turned on, and the first computing circuit... Under the fifth condition, the fourth set of data includes the first set of calculation results, the fifth condition includes the first switch corresponding to the first calculation circuit being off and the corresponding second switch being on, and the first switch corresponding to the third calculation circuit being on and the second switch corresponding to the third calculation circuit being off, and the set of switches corresponding to the second calculation circuit being off; under the sixth condition, the fourth set of data includes the second set of data, the sixth condition includes the first switch corresponding to the second calculation circuit being on and the corresponding second switch being off, and the set of switches corresponding to the first calculation circuit and the set of switches corresponding to the third calculation circuit being off; under the seventh condition, the fourth set of data includes the second set of calculation results, the seventh condition includes the first switch corresponding to the second calculation circuit being off and the corresponding second switch being on, and the set of switches corresponding to the first calculation circuit and the set of switches corresponding to the third calculation circuit being off.

[0029] In this embodiment of the disclosure, the data flow-based computing unit includes a first computing circuit, a second computing circuit, and a third computing circuit. Since at least one of the durations of the first computing circuit performing the first calculation and the second computing circuit performing the second calculation partially overlaps with the duration of the third computing circuit performing the third calculation, the third calculation performed in the subsequent step does not need to wait for the first and second calculations to be fully completed before it can begin. Thus, the third calculation can be performed in parallel with the first or second calculation for a period of time, thereby improving the computing speed of the computing unit.

[0030] Furthermore, during the execution of the first and second calculations, since the third calculation circuit does not need to be idle all the time, the idle time of the computing resources in the computing unit is shortened, and the resource utilization of the computing unit is improved.

[0031] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a data flow-based computing unit according to some embodiments of the present disclosure;

[0034] Figure 2 This is a schematic diagram of the structure of a data flow-based computing unit according to other embodiments of this disclosure;

[0035] Figure 3 This is a schematic diagram of the structure of a data flow-based computing unit according to some embodiments of the present disclosure;

[0036] Figure 4 This is a schematic diagram of the structure of a data flow-based computing unit according to some embodiments of the present disclosure;

[0037] Figure 5 This is a schematic diagram of the structure of a data flow-based vector processor according to some embodiments of the present disclosure;

[0038] Figure 6 This is a data stream-based computing method according to some embodiments of the present disclosure;

[0039] Figure 7 This is a data stream-based computing method according to other embodiments of this disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0042] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0043] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0044] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0046] Figure 1 This is a schematic diagram of the structure of a data flow-based computing unit according to some embodiments of the present disclosure.

[0047] like Figure 1 As shown, the data flow-based computing unit 100 includes a first computing circuit 11, a second computing circuit 12, and a third computing circuit 13. The second computing circuit 12 and the first computing circuit 11 are connected in parallel.

[0048] The first calculation circuit 11 can be configured to perform a first calculation on a first set of data to obtain a first set of calculation results.

[0049] The second calculation circuit 12 can be configured to perform a second calculation on the second set of data to obtain the second set of calculation results.

[0050] For example, the first computing circuit 11 may include an input terminal and an output terminal. Figure 1 (Not shown in the diagram), so that the first calculation circuit 11 can receive the first set of data through the input terminal and output the first set of calculation results through the output terminal. Similarly, the second calculation circuit 12 may also include an input terminal and an output terminal (not shown in the diagram), so that the first calculation circuit 11 can receive the first set of data through the input terminal and output the first set of calculation results through the output terminal. Figure 1 (not shown in the image) so that the second calculation circuit 12 can receive the second set of data through the input terminal and output the second set of calculation results through the output terminal.

[0051] The third calculation circuit 13 can be connected to the output terminals of the first calculation circuit 11 and the second calculation circuit 12 through two data paths, so that the first set of calculation results can flow to the third calculation circuit 13 through one of the two data paths, and the second set of calculation results can flow to the third calculation circuit 13 through the other of the two data paths.

[0052] The third computing circuit 13 can be configured to perform a third calculation on the third set of data to obtain a third set of calculation results, provided that the third set of data flowing to the third computing circuit includes the first set of calculation results and the second set of calculation results. In other embodiments, the third set of data flowing to the third computing circuit 13 may include other data, which will be further described below.

[0053] Here, at least one of the duration of the first calculation and the duration of the second calculation may partially overlap with the duration of the third calculation.

[0054] It should be understood that the first set of calculation results, the second set of calculation results, and the third set of calculation results may each include one or more calculation results.

[0055] In some embodiments, the first calculation and the second calculation may be the same.

[0056] In some embodiments, the duration of the first calculation and the duration of the second calculation may both partially overlap with the duration of the third calculation.

[0057] For example, the first and second calculations are both fixed-point to floating-point conversions, and the third calculation is a floating-point addition. The first calculation circuit 11 receives a first set of data consisting of 10 fixed-point numbers, and the second calculation circuit 12 receives a second set of data consisting of another 10 fixed-point numbers. The first calculation circuit 11 and the second calculation circuit 12 can perform fixed-point to floating-point conversions in parallel. When the third set of data flowing to the third calculation circuit 13 includes a floating-point number output by the first calculation circuit 11 and a floating-point number output by the second calculation circuit 12, the third calculation circuit 13 can perform a floating-point addition calculation on these two floating-point numbers to obtain a floating-point addition result.

[0058] In this case, the duration of the first calculation and the duration of the second calculation partially overlap with the duration of the third calculation. That is, the third calculation circuit 13 does not need to wait for the first calculation circuit 11 and the second calculation circuit 12 to convert all 10 fixed-point numbers they received into 10 floating-point numbers before it starts to perform calculations.

[0059] In the above embodiments, the data flow-based computing unit includes a first computing circuit, a second computing circuit, and a third computing circuit. Since at least one of the durations of the first computing circuit performing the first calculation and the second computing circuit performing the second calculation partially overlaps with the duration of the third computing circuit performing the third calculation, the third calculation performed in the subsequent step does not need to wait for the first and second calculations to be fully completed before it can begin. Thus, at least one of the first and second calculations can be executed in parallel with the third calculation for a period of time, thereby improving the computing speed of the computing unit.

[0060] Furthermore, during the execution of the first and second calculations, since the third calculation circuit does not need to be idle all the time, the idle time of the computing resources in the computing unit is shortened, and the resource utilization of the computing unit is improved.

[0061] Figure 2 This is a schematic diagram of the structure of a data flow-based computing unit according to other embodiments of the present disclosure.

[0062] like Figure 2 As shown, the multiple computing circuits in the data flow-based computing unit 100 may further include a fourth computing circuit 14. For example, the fourth computing circuit 14 may be connected to the third computing circuit 13 via a data path, so that the third set of calculation results output by the third computing circuit 13 may flow to the fourth computing circuit 14 via the data path.

[0063] The fourth calculation circuit 14 can be configured to perform a fourth calculation on the fourth set of data to obtain a fourth set of calculation results when the fourth set of data flowing to the fourth calculation circuit includes the third set of calculation results.

[0064] Here, the duration of the fourth calculation can partially overlap with the duration of the third calculation.

[0065] In some embodiments, the fourth calculation may be different from both the first and third calculations. In this case, the first calculation may be the same as the second calculation.

[0066] In some embodiments, the fourth calculation can be the inverse operation of the first calculation. For example, the first and second calculations can both be fixed-point to floating-point calculations, the third calculation can be floating-point addition, and the fourth calculation can be floating-point to fixed-point calculations.

[0067] In the above embodiments, the data flow-based computing unit may further include a fourth computing circuit to support more complex multi-step calculations. In this case, since the duration of the fourth calculation performed by the fourth computing circuit can partially overlap with the duration of the third calculation performed by the third computing circuit, the fourth calculation performed in the later step does not need to wait for the third calculation performed in the previous step to be completed before it can begin, thereby further improving the computing speed of the computing unit.

[0068] Figure 3 This is a schematic diagram of the structure of a data flow-based computing unit according to some embodiments of the present disclosure.

[0069] like Figure 3 As shown, the multiple computing circuits in the data flow-based computing unit 100 may further include a fifth computing circuit 15.

[0070] The fifth calculation circuit 15 can be configured to perform a fifth calculation on the fifth set of data to obtain a fifth set of calculation results, provided that the fifth set of data flowing to the fifth calculation circuit includes the second set of calculation results output by the second calculation circuit 12. Here, the duration of the fifth calculation partially overlaps with the duration of the second calculation.

[0071] In some embodiments, the fifth calculation may differ from the second calculation. For example, the second calculation may be a fixed-point to floating-point conversion calculation, while the fifth calculation may be an exponential function calculation. Thus, the dataflow-based computing unit can selectively support a wider range of multi-step calculations.

[0072] In some embodiments, the second calculation circuit 12 can be connected to the third calculation circuit 13 and the fifth calculation circuit 15 via a first control switch 31 (e.g., a single-pole double-throw switch). By controlling the first switch 31, the second set of calculation results output by the second calculation circuit 12 can be selectively output to the third calculation circuit 13 or the fifth calculation circuit 15.

[0073] In some embodiments, the fourth computing circuit 14 can be connected to the third computing circuit 13 and the fifth computing circuit 15 via a second control switch 32 (e.g., a single-pole double-throw switch). By controlling the second switch 32, it is possible to select whether the third set of calculation results output by the third computing circuit 13 flows to the fourth computing circuit 14 or whether the fifth set of calculation results output by the fifth computing circuit 15 flows to the fourth computing circuit 14.

[0074] If the fourth set of data flowing to the fourth calculation circuit 14 includes the fifth set of calculation results output by the fifth calculation circuit 15, the fourth calculation circuit 14 can be configured to perform a fourth calculation on the fifth set of calculation results. For example, the second calculation circuit 12 can perform a fixed-point to floating-point conversion to convert a 10-point fixed-point number into 10 floating-point numbers, the fifth calculation circuit 15 can perform an exponential function calculation to obtain an exponential function calculation result in the form of 10 floating-point numbers, and the fourth calculation circuit 14 can perform a floating-point to fixed-point conversion to convert the exponential function calculation result in the form of 10 floating-point numbers into an exponential function calculation result in the form of 10 fixed-point numbers.

[0075] It should be understood that the duration of the fourth calculation may partially overlap with the duration of the fifth calculation.

[0076] It should also be understood that the single-pole double-throw switches 31 and 32 are merely examples. For instance, the second computing circuit 12 can also be connected to a multiplexer that can receive control signals corresponding to the computing task to select which computing circuit to output the second set of computing results to; the fourth computing circuit 14 can also be connected to a multiplexer that can receive control signals corresponding to the computing task to select which set of computing results to flow to the fourth computing circuit 14.

[0077] In some embodiments, the data flow-based computing unit 100 may further include at least one set of switches, which may correspond one-to-one with at least one of a plurality of computing circuits. Each set of switches may include a first switch connected in parallel with the corresponding computing circuit, and a second switch connected in series with the corresponding computing circuit and in parallel with the first switch.

[0078] For example, if the first switch of a certain computing circuit is turned on but the corresponding second switch is turned off, the data will flow to the next computing circuit via the path of the first switch, and will not flow to the current computing circuit. In this case, the computing circuit will neither receive data nor perform calculations.

[0079] For example, if the first switch of a certain computing circuit is off but the corresponding second switch is on, data will flow into the computing circuit instead of into the path where the first switch of the computing circuit is located. In this case, the computing circuit will perform calculations based on the incoming data.

[0080] In this way, different data paths in the data flow-based computing unit can be selected and configured according to actual computing needs, so as to support multiple types of computing and improve the flexibility of the computing unit.

[0081] Figure 4 This is a schematic diagram of the structure of a data flow-based computing unit according to some embodiments of the present disclosure.

[0082] like Figure 4 As shown, at least one set of switches in the data flow-based computing unit 100 may include two sets of switches that correspond one-to-one with at least two computing circuits. Figure 4 Five computing circuits and five corresponding sets of switches 41 are schematically shown. Each set of switches 41 may include a first switch 42 connected in parallel with the corresponding computing circuit and a second switch 43 connected in series with the corresponding computing circuit and in parallel with the first switch 42.

[0083] In some embodiments, the first computing circuit 11 and the second computing circuit 12 can correspond one-to-one with two sets of switches 41. By controlling these two sets of switches 41, the third set of data flowing to the third computing circuit 13 can be different.

[0084] For example, if the first switch 42 corresponding to the first calculation circuit 11 is turned on and the corresponding second switch 43 is turned off, and the first switch 42 corresponding to the second calculation circuit 12 is turned off and the corresponding second switch 43 is turned on, then the third set of data flowing to the third calculation circuit 13 may include the first set of data and the second set of calculation results. The third calculation circuit 13 may also be configured to perform a third calculation on the first set of data and the second set of calculation results.

[0085] For example, if the first switch 42 corresponding to the first calculation circuit 11 is off and the corresponding second switch 43 is on, and the first switch 42 corresponding to the second calculation circuit 12 is on and the corresponding second switch 43 is off, then the third set of data flowing to the third calculation circuit 13 may include the second set of data and the first set of calculation results. The third calculation circuit 13 may also be configured to perform a third calculation on the second set of data and the first set of calculation results.

[0086] For example, if both the first switch 42 corresponding to the first calculation circuit 11 and the first switch 42 corresponding to the second calculation circuit 12 are turned on, and both the second switch 43 corresponding to the first calculation circuit 11 and the second switch 43 corresponding to the second calculation circuit 12 are turned off, then the third set of data flowing to the third calculation circuit 13 may include the first set of data and the second set of data. The third calculation circuit 13 may also be configured to perform a third calculation on the first set of data and the second set of data.

[0087] Thus, the third calculation circuit 13 can perform a third calculation based on different sets of third data.

[0088] In other embodiments, the first computing circuit 11 and the third computing circuit 13 can correspond one-to-one with the two sets of switches 41. Similarly, the second computing circuit 12 and the third computing circuit 13 can correspond one-to-one with the two sets of switches 41.

[0089] For example, if a set of switches 41 corresponding to the first calculation circuit 11 is turned off, and the first switch 42 corresponding to the third calculation circuit 13 is turned on and the corresponding second switch 43 is turned off, then the second set of calculation results of the second calculation circuit 12 can flow out through the path where the first switch 42 corresponding to the third calculation circuit 13 is located.

[0090] In some embodiments, the first computing circuit 11, the second computing circuit 12, and the third computing circuit can correspond one-to-one with three sets of switches 41.

[0091] For example, if the first switch 42 corresponding to the third calculation circuit 13 is on but the corresponding second switch 43 is off, then the third calculation circuit 13 will not receive data or perform calculations. In this case, if the first switch 42 corresponding to the first calculation circuit 11 is off and the corresponding second switch 43 is on, and both the first switch 42 and the second switch 43 corresponding to the second calculation circuit 12 are off, then the first set of calculation results of the first calculation circuit 11 can flow out through the path where the first switch 42 corresponding to the third calculation circuit 13 is located.

[0092] Thus, by controlling a set of switches 41 corresponding to the third calculation circuit 13, the calculation results of the first calculation circuit 11 can be directly output.

[0093] In some embodiments, the fourth computing circuit 14 may also correspond to a set of switches 41. Similarly, for example, if the first switch 42 corresponding to the fourth computing circuit 14 is turned on but the corresponding second switch 43 is turned off, the fourth computing circuit 14 will not receive data or perform calculations. In this case, the third set of calculation results from the third computing circuit 13 can flow out through the path where the first switch 42 corresponding to the fourth computing circuit 14 is located.

[0094] Thus, by controlling a set of switches 41 corresponding to the fourth calculation circuit 14, the calculation results of the third calculation circuit 13 can be directly output.

[0095] In some embodiments, the fifth computing circuit 15 may also correspond to a set of switches 41. Similarly, for example, if the first switch 42 corresponding to the fifth computing circuit 15 is turned on but the corresponding second switch 43 is turned off, the fifth computing circuit 15 will not receive data or perform calculations. In this case, the second set of calculation results of the second computing circuit 12 can flow out through the path where the first switch 42 corresponding to the fifth computing circuit 15 is located.

[0096] Thus, by controlling a set of switches 41 corresponding to the fifth calculation circuit 15, the calculation results of the second calculation circuit 12 can be directly output.

[0097] In some embodiments, when the second computing circuit 12 corresponds to a set of switches 41, the fifth set of data flowing to the fifth computing circuit 15 can be different by controlling the set of switches 41 corresponding to the second computing circuit 12.

[0098] For example, if the first switch 42 corresponding to the second calculation circuit 12 is turned on and the corresponding second switch 43 is turned off, then the fifth set of data flowing to the fifth calculation circuit 15 may include the second set of data. In this case, the fifth calculation circuit 15 can be configured to perform a fifth calculation on the second set of data.

[0099] Thus, the fifth calculation circuit 15 can perform a fifth calculation based on different sets of fifth data.

[0100] In some embodiments, where the first computing circuit 11, the second computing circuit 12, and the third computing circuit correspond one-to-one with three sets of switches 41, the fourth set of data flowing to the fourth computing circuit 14 can be made different by controlling these three sets of switches 41.

[0101] For example, if both the first switch 42 corresponding to the first computing circuit 11 and the first switch 42 corresponding to the third computing circuit 13 are turned on, and the second switch 43 corresponding to the first computing circuit 11, the second switch 43 corresponding to the third computing circuit 13, and a set of switches 41 corresponding to the second computing circuit 12 are all turned off, then the fourth set of data flowing to the fourth computing circuit 14 may include the first set of data. The fourth computing circuit 14 can be configured to perform a fourth calculation on the first set of data.

[0102] For example, if the first switch 42 corresponding to the first calculation circuit 11 is off and the corresponding second switch 43 is on, and the first switch 42 corresponding to the third calculation circuit 13 is on and the second switch 43 corresponding to the third calculation circuit is off, and a set of switches 41 corresponding to the second calculation circuit is off, then the fourth set of data flowing to the fourth calculation circuit 14 may include the first set of calculation results. The fourth calculation circuit 14 can be configured to perform a fourth calculation on the first set of calculation results.

[0103] For example, if the first switch 42 corresponding to the second calculation circuit 12 is turned on and the corresponding second switch 43 is turned off, and both the set of switches 41 corresponding to the first calculation circuit 11 and the set of switches 41 corresponding to the third calculation circuit 13 are turned off, then the fourth set of data flowing to the fourth calculation circuit 14 may include the second set of data. The fourth calculation circuit 14 can be configured to perform a fourth calculation on the second set of data.

[0104] For example, if the first switch 42 corresponding to the second calculation circuit 12 is off, the corresponding second switch 43 is on, and both the set of switches 41 corresponding to the first calculation circuit 11 and the set of switches 41 corresponding to the third calculation circuit are off, then the fourth set of data flowing to the fourth calculation circuit 14 may include the second set of calculation results. The fourth calculation circuit can be configured to perform a fourth calculation on the second set of calculation results.

[0105] Thus, the fourth calculation circuit 14 can perform a fourth calculation based on different sets of fourth data.

[0106] Figure 5 This is a schematic diagram of the structure of a data flow-based vector processor according to some embodiments of the present disclosure.

[0107] like Figure 5 As shown, the data flow-based vector processor 500 includes a data flow-based computing unit (e.g., data flow-based computing unit 100) of any of the above embodiments, a data buffer (DB) 51, a direct memory access (DMA) module 52, and a control register (CSR) 53.

[0108] Control register 53 can be configured to send a first drive signal and a second drive signal corresponding to the computation task in response to a control signal. For example, control register 53 can send the first drive signal to data buffer 51 and the second drive signal to direct memory access module 52.

[0109] The data buffer 51 can be configured to buffer a first set of data and a second set of data. In response to a first drive signal corresponding to a computing task, the first set of data is transmitted to a first computing circuit 11 in the data flow-based computing unit 100, and the second set of data is transmitted to a second computing circuit 12 in the data flow-based computing unit 100.

[0110] For example, the data buffer 51 can be connected to the first computing circuit 11 and the second computing circuit 12 through two data paths, so that the first set of data can be transmitted to the first computing circuit 11 through one of the two data paths, and the second set of data can be transmitted to the second computing circuit 12 through one of the two data paths, so that the first computing circuit 11 and the second computing circuit 12 can perform corresponding calculations according to the data they receive.

[0111] Direct memory access module 52 can be configured to access external memory in response to a second drive signal corresponding to a computing task. Figure 5(Not shown in the image) Reads the first set of data and the second set of data, and transfers the first set of data and the second set of data to the data buffer 51. For example, the direct memory access module 52 can transfer the first set of data and the second set of data to the data buffer 51 through a data path connected to the data buffer 51.

[0112] This disclosure also provides an artificial intelligence chip, including a data flow-based vector processor (e.g., a data flow-based vector processor 500) from any of the above embodiments.

[0113] This disclosure also provides an accelerator, including the artificial intelligence chip of any of the above embodiments.

[0114] The following is combined Figures 6 to 7 This invention describes a data stream-based computation method according to some embodiments of the present disclosure.

[0115] Figure 6 This is a data stream-based computing method according to some embodiments of the present disclosure.

[0116] In step 602, the first calculation circuit performs a first calculation on the first set of data to obtain the first set of calculation results.

[0117] In step 604, the second calculation circuit, which is connected in parallel with the first calculation circuit, performs a second calculation on the second set of data to obtain the second set of calculation results.

[0118] In step 606, if the third set of data flowing to the third calculation circuit includes the first set of calculation results and the second set of calculation results, the third calculation circuit performs a third calculation on the third set of data to obtain the third set of calculation results.

[0119] Here, at least one of the duration of the first calculation and the duration of the second calculation may partially overlap with the duration of the third calculation.

[0120] In some embodiments, the first calculation and the second calculation may be the same.

[0121] In some embodiments, the data stream-based computation method may further include the following steps:

[0122] If the fourth set of data flowing to the fourth calculation circuit includes the third set of calculation results, the fourth calculation circuit performs a fourth calculation on the fourth set of data to obtain the fourth set of calculation results.

[0123] Here, the fourth calculation is different from both the first and third calculations, and the duration of the fourth calculation can partially overlap with the duration of the third calculation.

[0124] In some embodiments, the fourth calculation can be the inverse operation of the first calculation. For example, the first calculation can be a fixed-point to floating-point calculation, and the fourth calculation can be a floating-point to fixed-point calculation.

[0125] Figure 7 This is a data stream-based computing method according to other embodiments of this disclosure.

[0126] In step 702, the second calculation circuit, which is connected in parallel with the first calculation circuit, performs a second calculation on the second set of data to obtain the second set of calculation results.

[0127] In step 704, if the fifth set of data flowing to the fifth calculation circuit includes the second set of calculation results, the fifth calculation circuit performs a fifth calculation on the fifth set of data to obtain the fifth set of calculation results.

[0128] Here, the fifth calculation may differ from the second calculation, and the duration of the fifth calculation may partially overlap with the duration of the second calculation.

[0129] In some embodiments, the fifth calculation may be an exponential function calculation.

[0130] In some embodiments, the data stream-based computation method may further include the following steps:

[0131] If the fourth set of data flowing to the fourth calculation circuit includes the fifth set of calculation results, the fourth calculation circuit also performs a fourth calculation on the fourth set of data.

[0132] In some embodiments, the first computing circuit and the second computing circuit can correspond one-to-one with two sets of switches, each set of switches including a first switch and a second switch. Specifically, the first switch corresponding to the first computing circuit can be connected in parallel with the first computing circuit, and the second switch corresponding to the first computing circuit can be connected in series with the first computing circuit and in parallel with the first switch corresponding to the first computing circuit; similarly, the first switch corresponding to the second computing circuit can be connected in parallel with the second computing circuit, and the second switch corresponding to the second computing circuit can be connected in series with the second computing circuit and in parallel with the first switch corresponding to the second computing circuit.

[0133] In this case, the third set of data flowing to the third calculation circuit can be different depending on the different conduction conditions of the two sets of switches.

[0134] Under the first condition, the third set of data flowing to the third computing circuit may include the first set of data and the second set of calculation results. Here, the first condition may include the first switch of the first computing circuit being turned on and the corresponding second switch being turned off, and the first switch of the second computing circuit being turned off and the corresponding second switch being turned on.

[0135] Under the second condition, the third set of data flowing to the third computing circuit may include the second set of data and the first set of calculation results. Here, the second condition may include the first switch corresponding to the first computing circuit being off and the corresponding second switch being on, and the first switch corresponding to the second computing circuit being on and the corresponding second switch being off.

[0136] Under the third condition, the third set of data flowing to the third computing circuit may include the first set of data and the second set of data. Here, the third condition may include both the first switch corresponding to the first computing circuit and the first switch corresponding to the second computing circuit being turned on, and both the second switch corresponding to the first computing circuit and the second switch corresponding to the second computing circuit being turned off.

[0137] In some embodiments, the first computing circuit, the second computing circuit, and the third computing circuit can each correspond to one of three sets of switches, each set of switches including a first switch and a second switch. Specifically, the first switch corresponding to the first computing circuit can be connected in parallel with the first computing circuit, and the second switch corresponding to the first computing circuit can be connected in series with the first computing circuit and in parallel with the first switch corresponding to the first computing circuit; the first switch corresponding to the second computing circuit can be connected in parallel with the second computing circuit, and the second switch corresponding to the second computing circuit can be connected in series with the second computing circuit and in parallel with the first switch corresponding to the second computing circuit; the first switch corresponding to the third computing circuit can be connected in parallel with the third computing circuit, and the second switch corresponding to the third computing circuit can be connected in series with the third computing circuit and in parallel with the first switch corresponding to the third computing circuit.

[0138] In this case, depending on the different conduction conditions of these three sets of switches, the fourth set of data flowing to the fourth calculation circuit can be different.

[0139] Under the fourth condition, the fourth set of data flowing to the fourth computing circuit may include the first set of data. Here, the fourth condition may include the first switch corresponding to the first computing circuit and the first switch corresponding to the third computing circuit both being turned on, and the second switch corresponding to the first computing circuit, the second switch corresponding to the third computing circuit, and a set of switches corresponding to the second computing circuit all being turned off.

[0140] Under the fifth condition, the fourth set of data flowing to the fourth computing circuit may include the first set of calculation results. Here, the fifth condition may include the first switch corresponding to the first computing circuit being off and the corresponding second switch being on, and the first switch corresponding to the third computing circuit being on, the second switch corresponding to the third computing circuit being off, and a set of switches corresponding to the second computing circuit being off.

[0141] Under the sixth condition, the fourth set of data flowing to the fourth computing circuit may include the second set of data. Here, the sixth condition may include the first switch corresponding to the second computing circuit being turned on, the corresponding second switch being turned off, and both the set of switches corresponding to the first computing circuit and the set of switches corresponding to the third computing circuit being turned off.

[0142] Under the seventh condition, the fourth set of data flowing to the fourth calculation circuit may include the second set of calculation results. Here, the seventh condition may include the first switch corresponding to the second calculation circuit being off, the corresponding second switch being on, and both the set of switches corresponding to the first calculation circuit and the set of switches corresponding to the third calculation circuit being off.

[0143] In some embodiments, when the second computing circuit corresponds to a set of switches, the set of switches may include a first switch connected in parallel with the second computing circuit and a second switch connected in series with the second computing circuit and in parallel with the first switch corresponding to the second computing circuit.

[0144] Depending on the different conduction conditions of the switches corresponding to the second calculation circuit, the fifth set of data flowing to the fifth calculation circuit can be different.

[0145] Under the eighth condition, the fifth set of data flowing to the fifth computing circuit may include the second set of data. Here, the eighth condition may include the first switch corresponding to the second computing circuit being turned on and the corresponding second switch being turned off.

[0146] For a detailed description of the above data flow-based computation method, please refer to the relevant embodiments of the aforementioned data flow-based computation unit, which will not be repeated here.

[0147] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0148] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A dataflow-based vector processor, comprising a dataflow-based computing unit, the computing unit comprising a plurality of computing circuits, the plurality of computing circuits comprising: A first computing circuit is configured to perform a first calculation on a first set of data to obtain a first set of calculation results; The second computing circuit, connected in parallel with the first computing circuit, is configured to perform a second calculation on the second set of data to obtain a second set of calculation results. A third computing circuit is configured to perform a third calculation on the third set of data flowing to the third computing circuit to obtain a third set of calculation results, wherein at least one of the duration of the first calculation and the duration of the second calculation partially overlaps with the duration of the third calculation. A fourth computing circuit is configured to perform a fourth calculation on the fourth set of data to obtain a fourth set of calculation results when the fourth set of data flowing to the fourth computing circuit includes the third set of calculation results, wherein the fourth calculation is different from both the first calculation and the third calculation, and the duration of the fourth calculation partially overlaps with the duration of the third calculation. The vector processor also includes: A data buffer is configured to buffer the first set of data and the second set of data, and in response to a first drive signal corresponding to a computing task, transmits the first set of data to the first computing circuit and transmits the second set of data to the second computing circuit. A direct memory access module is configured to read the first set of data and the second set of data from off-chip memory in response to a second drive signal corresponding to the computing task, and to transfer the first set of data and the second set of data to the data cache; The control register is configured to send the first drive signal and the second drive signal in response to a control signal.

2. The vector processor according to claim 1, wherein, The first calculation is the same as the second calculation.

3. The vector processor according to claim 2, wherein, The fourth calculation is the inverse operation of the first calculation.

4. The vector processor according to claim 3, wherein, The first calculation is a fixed-point to floating-point conversion calculation, and the fourth calculation is a floating-point to fixed-point conversion calculation.

5. The vector processor according to any one of claims 2-4, wherein, The plurality of computing circuits also include: A fifth computing circuit is configured to perform a fifth calculation on the fifth set of data to obtain a fifth set of calculation results when the fifth set of data flowing to the fifth computing circuit includes the second set of calculation results, wherein the fifth calculation is different from the second calculation and the duration of the fifth calculation partially overlaps with the duration of the second calculation; The fourth computing circuit is further configured to perform the fourth calculation on the fourth set of data if the fourth set of data includes the fifth set of calculation results.

6. The vector processor according to claim 5, wherein, The fifth calculation is an exponential function calculation.

7. The vector processor according to claim 1 further includes at least one set of switches, wherein the at least one set of switches corresponds one-to-one with at least one of the plurality of computing circuits, and each set of switches includes a first switch connected in parallel with the corresponding computing circuit, and a second switch connected in series with the corresponding computing circuit and in parallel with the first switch.

8. The vector processor according to claim 7, wherein, The at least one set of switches includes two sets of switches that correspond one-to-one with at least two computing circuits.

9. The vector processor according to claim 5, wherein, The fourth computing circuit and the fifth computing circuit correspond one-to-one with two sets of switches. Each set of switches includes a first switch connected in parallel with the corresponding computing circuit, and a second switch connected in series with the corresponding computing circuit and in parallel with the first switch.

10. An artificial intelligence chip, comprising: The vector processor according to any one of claims 1-9.

11. A data flow-based computation method, executed by the vector processor according to any one of claims 1-9, comprising: The first computing circuit performs a first calculation on the first set of data to obtain the first set of calculation results; A second calculation circuit connected in parallel with the first calculation circuit performs a second calculation on the second set of data to obtain a second set of calculation results; When the third set of data flowing to the third computing circuit includes the first set of calculation results and the second set of calculation results, the third computing circuit performs a third calculation on the third set of data to obtain a third set of calculation results, wherein at least one of the duration of the first calculation and the duration of the second calculation partially overlaps with the duration of the third calculation. If the fourth set of data flowing to the fourth computing circuit includes the third set of calculation results, the fourth computing circuit performs a fourth calculation on the fourth set of data to obtain a fourth set of calculation results, wherein the fourth calculation is different from both the first calculation and the third calculation, and the duration of the fourth calculation partially overlaps with the duration of the third calculation.

12. The calculation method according to claim 11, wherein, The first calculation is the same as the second calculation.

13. The calculation method according to claim 12, wherein, The fourth calculation is the inverse operation of the first calculation.

14. The calculation method according to claim 13, wherein, The first calculation is a fixed-point to floating-point conversion calculation, and the fourth calculation is a floating-point to fixed-point conversion calculation.

15. The calculation method according to any one of claims 12-14, further comprising: If the fifth set of data flowing to the fifth computing circuit includes the second set of calculation results, the fifth computing circuit performs a fifth calculation on the fifth set of data to obtain a fifth set of calculation results, wherein the fifth calculation is different from the second calculation, and the duration of the fifth calculation partially overlaps with the duration of the second calculation; If the fourth set of data includes the calculation results of the fifth set, the fourth calculation circuit also performs the fourth calculation on the fourth set of data.

16. The calculation method according to claim 15, wherein, The fifth calculation is an exponential function calculation.

17. The calculation method according to claim 11, wherein, The first computing circuit and the second computing circuit correspond one-to-one with two sets of switches, each set of switches including a first switch and a second switch; The first switch corresponding to the first computing circuit is connected in parallel with the first computing circuit, and the second switch corresponding to the first computing circuit is connected in series with the first computing circuit and in parallel with the first switch corresponding to the first computing circuit. The first switch corresponding to the second calculation circuit is connected in parallel with the second calculation circuit, and the second switch corresponding to the second calculation circuit is connected in series with the second calculation circuit and in parallel with the first switch corresponding to the second calculation circuit. Under the first condition, the third set of data includes the first set of data and the second set of calculation results. The first condition includes the first switch corresponding to the first calculation circuit being turned on and the corresponding second switch being turned off, and the first switch corresponding to the second calculation circuit being turned off and the corresponding second switch being turned on. Under the second condition, the third set of data includes the second set of data and the first set of calculation results. The second condition includes the first switch corresponding to the first calculation circuit being turned off and the corresponding second switch being turned on, and the first switch corresponding to the second calculation circuit being turned on and the corresponding second switch being turned off. Under the third condition, the third set of data includes the first set of data and the second set of data. The third condition includes that the first switch corresponding to the first computing circuit and the first switch corresponding to the second computing circuit are both turned on, and the second switch corresponding to the first computing circuit and the second switch corresponding to the second computing circuit are both turned off.

18. The calculation method according to any one of claims 12-14, wherein, The first computing circuit, the second computing circuit, and the third computing circuit correspond one-to-one with three sets of switches, and each set of switches includes a first switch and a second switch. The first switch corresponding to the first computing circuit is connected in parallel with the first computing circuit, and the second switch corresponding to the first computing circuit is connected in series with the first computing circuit and in parallel with the first switch corresponding to the first computing circuit. The first switch corresponding to the second calculation circuit is connected in parallel with the second calculation circuit, and the second switch corresponding to the second calculation circuit is connected in series with the second calculation circuit and in parallel with the first switch corresponding to the second calculation circuit. The first switch corresponding to the third computing circuit is connected in parallel with the third computing circuit, and the second switch corresponding to the third computing circuit is connected in series with the third computing circuit and in parallel with the first switch corresponding to the third computing circuit. Under the fourth condition, the fourth set of data includes the first set of data. The fourth condition includes that the first switch corresponding to the first computing circuit and the first switch corresponding to the third computing circuit are both turned on, and the second switch corresponding to the first computing circuit, the second switch corresponding to the third computing circuit, and a set of switches corresponding to the second computing circuit are all turned off. Under the fifth condition, the fourth set of data includes the first set of calculation results. The fifth condition includes the first switch corresponding to the first calculation circuit being off and the corresponding second switch being on, and the first switch corresponding to the third calculation circuit being on and the second switch corresponding to the third calculation circuit being off, and a set of switches corresponding to the second calculation circuit being off. Under the sixth condition, the fourth set of data includes the second set of data. The sixth condition includes the first switch corresponding to the second calculation circuit being turned on and the corresponding second switch being turned off, and both the first set of switches corresponding to the first calculation circuit and the third set of switches corresponding to the third calculation circuit being turned off. Under the seventh condition, the fourth set of data includes the second set of calculation results. The seventh condition includes the first switch corresponding to the second calculation circuit being off, the corresponding second switch being on, and both the first set of switches corresponding to the first calculation circuit and the third set of switches corresponding to the third calculation circuit being off.

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