Computing method and device based on computing array of memory-compute integrated structure

Abstract

The application provides a computing method and device based on a computing array. A plurality of weights are stored in the computing array. The method comprises: determining a computing bit width of first data and determining a weight bit width of the computing array for computing the first data according to a data feature of the first data; and setting bits of the weights stored in the computing array for participating in the computation according to the weight bit width before determining a computing result corresponding to the first data by using the computing array. In the scheme, when the data is computed by using a neural network, the computing bit width of the data and the bits of the weights stored in the array for participating in the computation are adaptively adjusted according to the data feature, so that the computing cost of the computing array can be reduced and the computing power consumption of the computing array can be reduced.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and in particular to a computing method and apparatus based on a computing array with an in-memory computing structure. Background Technology

[0002] Neural networks (NNs) have achieved groundbreaking progress and high accuracy in fields such as game super-resolution, image recognition, speech recognition, and natural language processing due to their powerful data modeling capabilities. However, NNs require significant computational resources, and the most basic and important computation in a NN is matrix-vector multiplication. The matrix-vector multiplication and addition operations of large-scale NNs pose a significant challenge to applications with high real-time requirements and power sensitivity. Summary of the Invention

[0003] This application provides a computing method and apparatus based on a computing array with an in-memory computing structure, which can shorten the latency of the computing array performing NN calculations and reduce the power consumption of the calculation.

[0004] In one aspect, this application provides a computation method based on a computing array.

[0005] The computation array stores weights with multiple bits. The method includes: determining the computation bit width of the first data based on its data characteristics; determining the weight bit width of the computation array for calculating the first data based on the computation bit width; setting the bits involved in the calculation within the weights based on the weight bit width; and determining the calculation result corresponding to the first data using the computation array.

[0006] In the above scheme, when performing neural network calculations on the first data, the computation bit width is determined based on the data characteristics of the first data, and the bits involved in the calculation are set in the weights stored in the computation array. This adaptively adjusts the weight bit width, thereby reducing the computational overhead and power consumption of the computation array. Compared to storing multiple weights of different bit widths in the array, this scheme avoids the problem of increased array computation time due to weight loading. Compared to deploying multiple arrays storing weights of different bit widths, this scheme does not increase the array area and has the advantage of low power consumption.

[0007] In one possible implementation, the data features of the first data include the similarity of data between adjacent frames in the first data.

[0008] In the above scheme, the complexity of the first data can be determined based on the similarity of data in adjacent frames, thereby determining the computational bit width and corresponding weight bit width of the first data. Complex data uses a high computational bit width, while simple data uses a low computational bit width.

[0009] In one possible implementation, the computational units storing the multiple bits of the weight are each connected to a bit line. The step of setting the bits involved in the calculation of the weight according to the weight bit width includes: generating control signals corresponding to each bit line according to the weight bit width and the index of each bit line; and using the control signals to turn on or off the computational units connected to each bit line.

[0010] In the above scheme, control signals for each bit line are generated based on the determined weight bit width. The calculation units on the bit lines are controlled by the control signals, thereby achieving the purpose of setting the bits involved in the calculation of the weight, that is, adjusting the bit width of the weight stored in the calculation array.

[0011] In one possible implementation, determining the calculation result corresponding to the first data using the computing array includes: truncating the first data according to the computing bit width to obtain the second data; performing calculations on the second data using the computing array to obtain the output of the computing array; and shifting and accumulating the output of the computing array to obtain the calculation result corresponding to the first data.

[0012] In one possible implementation, the step of using the computing array to calculate the second data and obtaining the output of the computing array includes: adjusting the input voltage of the computing array according to the second data to obtain the output of the computing array.

[0013] Secondly, this application also provides a computing device based on a computing array. The computing array stores multi-bit weights. The device includes: a determination module, a setting module, and a computing module.

[0014] The determining module is used to determine the computational bit width of the first data based on the data characteristics of the first data, and is also used to determine the weight bit width of the computation array for calculating the first data based on the computational bit width.

[0015] The setting module is used to set the bits involved in the calculation of the weight according to the weight bit width.

[0016] The calculation module is used to determine the calculation result corresponding to the first data using the calculation array.

[0017] In one possible implementation, the data features of the first data include the similarity between data from adjacent frames within the first data. 204

[0018] In one possible implementation, the computational unit storing the multiple bits of the weight is connected to a bit line, and the setting module is specifically used to: generate a control signal corresponding to each bit line according to the weight bit width and the index of each bit line; and use the control signal to turn on or off the computational unit connected to each bit line.

[0019] In one possible implementation, the calculation module is specifically used to: truncate the first data according to the calculation bit width to obtain the second data; perform calculations on the second data using the calculation array to obtain the output of the calculation array; and perform shifting and accumulation on the output of the calculation array to obtain the calculation result corresponding to the first data.

[0020] In one possible implementation, the computing module is further configured to: adjust the input voltage of the computing array according to the second data to obtain the output of the computing array.

[0021] Thirdly, this application also provides a computing device. The computing device includes a processor and a memory, the processor being configured to execute a computer program stored in the memory to implement the methods described in the first aspect and its optional embodiments.

[0022] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium includes instructions that, when executed on a computing device, cause the computing device to perform the method as described in the first aspect and its optional embodiments.

[0023] Fifthly, this application also provides a computer program product. The computer program product includes program code that, when executed by a computing device, causes the computing device to perform the method as described in the first aspect and its optional embodiments.

[0024] Any of the devices, computer storage media, or computer program products provided above are used to execute the methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the corresponding solutions in the corresponding methods provided above, and will not be repeated here. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of an XB array in a computing array provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the structure of a computing system based on a computing array provided in an embodiment of this application;

[0027] Figure 3 This is a flowchart of a computing array-based computing method provided in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of adjacent frames in video stream data processed by a computing array according to an embodiment of this application;

[0029] Figure 5 This is a schematic diagram illustrating the bits involved in the calculation of the weights stored in the computing array, provided in an embodiment of this application.

[0030] Figure 6 This is a schematic diagram illustrating the truncation of first data based on the calculated bit width, provided in an embodiment of this application.

[0031] Figure 7 This is a visualization diagram of the results obtained by performing enhanced depth super-resolution network calculations on two sample images using a computing array with different computing bit widths and weight bit widths, according to an embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the structure of a computing device based on a computing array provided in an embodiment of this application;

[0033] Figure 9 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0035] In the description of the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0036] In the description of the embodiments in this application, the term "and / or" is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0038] Neural networks (NNs), in the fields of machine learning and cognitive science, are computational models that mimic biological neural networks. NNs can include convolutional neural networks and residual networks, among others. A neural network comprises a multi-layered structure, and the working principle of each layer can be represented by a mathematical expression. From a physical perspective, the operation of each layer in a neural network can be understood as transforming input data into output data through five operations on the input data. These five operations include dimensionality increase / decrease, scaling up / scaling down, rotation, translation, and bending. The first three operations are performed by vector multiplication of the weights and the input data in the mathematical expression.

[0039] The computation of large-scale neural networks requires a long time and consumes a lot of power to complete the aforementioned operations. General-purpose processors in computing devices cannot meet the real-time and power consumption requirements when performing neural network calculations. Therefore, designing dedicated neural network accelerators has become an important development direction.

[0040] In one example, a neural network accelerator may include a compute array with an in-memory computing architecture that stores the weights of the neural network and performs computations on the input data based on those weights to implement vector multiplication and addition operations in neural network computation.

[0041] In one example, the aforementioned in-memory computing array may include multiple processing element (PE) arrays arranged in a matrix. Each PE array includes multiple crossbar arrays (or XB arrays) arranged in a matrix, and each XB array includes multi-row, multi-column computing units. In the in-memory architecture, the XB array is the core module for implementing storage and computing. Generally, XB arrays are typically multiply-accumulate arrays constructed from non-volatile storage media.

[0042] Figure 1 This is a schematic diagram of the XB array structure in a computing array of an in-memory computing architecture provided in an embodiment of this application. For example... Figure 1As shown, the XB array includes several rows and columns of computation units. Each row's computation unit (cell) is connected to the same word lines, and each column's computation unit is connected to the same bit lines. The weights of the neural network (NN) are stored in the computation units of the array in the form of electrical conductance after being binary encoded. The input data is represented in the form of voltage, and the sum of the currents in the computation array represents the calculation result of the input data and weights.

[0043] from Figure 1 As can be seen, the XB array can accept multiple data inputs in parallel and perform multiple multiplication and accumulation calculations on the columns. For example... Figure 1 As shown, the input voltages V1 to V4 are multiplied and accumulated with the weight bits (i.e., conductances G1 to G4) stored in the calculation unit on the first bit line, and then the output current I1 is generated.

[0044] Due to limitations such as manufacturing processes, in-memory computing arrays can only perform low-bit array computations, meaning they typically only perform single / low-bit calculations at a time. For example, digital computing arrays like SRAM and analog computing arrays like ReRAM have a representation precision of 1 bit per computing unit, meaning each unit stores one bit of the neural network's weights, and only performs 1-bit calculations at a time. When using computing arrays for neural network computations, it is usually necessary to convert multi-bit data into multiple low-bit data based on the computation bit width, and finally, the results of these multiple low-bit data are shifted and accumulated.

[0045] Given the aforementioned limitations and the numerical redundancy inherent in neural networks, the problems of long computation time and high power consumption in neural network computation can be solved by reducing the computational overhead of the computing array.

[0046] Specifically, the computational bit width of the input data can be adaptively adjusted based on its complexity, while still meeting computational accuracy requirements. For example, in game super-resolution computing scenarios, the complexity of super-resolution calculations differs between simple and complex game scenes. Therefore, a lower computational bit width can be used for simple game scenes to save computation time and power consumption. A higher computational bit width can be used for complex game scenes to meet computational accuracy requirements.

[0047] Generally, when adaptively adjusting the computational bit width of the input data, the weight bit width stored in the computation array needs to be adjusted accordingly. For example, in a game super-resolution computation scenario, a simple game screen uses a 4-bit weight bit width, while a complex game screen uses an 8-bit weight bit width. After the computation array completes the super-resolution computation for a simple game screen using 4-bit weights, when performing super-resolution computation for a complex game screen, the weights need to be adjusted to 8-bit weights. When switching back to a simple game screen, the weights need to be readjusted to 4-bit weights.

[0048] To achieve the aforementioned goal of adaptively adjusting the weight bit width, this application provides two exemplary solutions.

[0049] In one example, multiple bit-width weights can be pre-stored in the computation array. In specific applications, different bit-width weights can be selected for computation based on different input data.

[0050] In one example, multiple computation arrays storing weights of different bit widths can be pre-deployed. In practical applications, one computation array can be used to compute the input data first, and the result can be used to determine whether it meets the accuracy requirements of the neural network. If it does not meet the requirements, another computation array is selected for recalculation. For example, a computation array storing high-bit-width weights and a computation array storing low-bit-width weights can be pre-deployed. When performing game super-resolution calculations, the computation array storing high-bit-width weights can be used first. If the result exceeds the accuracy requirements of the neural network, the computation array storing low-bit-width weights can be selected for recalculation. Another example is cascading the computation array storing low-bit-width weights and the computation array storing high-bit-width weights. The input data first passes through the computation array storing low-bit-width weights to obtain the result. The accuracy of the result is then judged, and if it does not meet the accuracy requirements, the input data is fed into the computation array storing high-bit-width weights for computation.

[0051] In the example above, when deploying a computing array to store weights of multiple bit widths, the array needs to load weights of matching bit widths for different computing bit widths. Loading weights multiple times significantly increases the computation time of the computing array and increases the latency of the neural network accelerator.

[0052] In the example above, deploying multiple computing arrays that store weights of different bit widths will increase the chip area of ​​the neural network accelerator, and at the same time increase the power consumption of the neural network accelerator.

[0053] Based on the above description, this application provides a computing system with a computing array featuring an in-memory computing architecture. For example... Figure 2 As shown, the computing system 200 includes a recognizer 201, a first controller 202, a second controller 203, a computing array 204, and a shift accumulator 205. Specifically, the computing array 204 stores multi-bit weights of the neural network.

[0054] Specifically, the recognizer 201 is used to identify the complexity of the input first data, and, while satisfying the neural network calculation accuracy, to determine the calculation bit width corresponding to the first data and the weight bit width of the calculation array 204 for performing neural network calculations on the first data.

[0055] Specifically, the first controller 202 is used to truncate the first data according to the calculation bit width and obtain second data with a length matching the calculation bit width. The first controller 202 is also used to obtain the voltage signal corresponding to the second data and adjust the input voltage of the calculation array according to the voltage signal.

[0056] Specifically, the second controller 203 is used to generate control signals for each bit line in the computing array 204 according to the weight bit width output by the recognizer 201, and control the computing units on each bit line of the computing array 204 according to the control signals, so as to set the bits participating in the calculation in the weight stored in the computing array 204.

[0057] Specifically, after being configured, the computing array 204 is used to output the current corresponding to the second data based on the input voltage adjusted according to the second data.

[0058] Specifically, the shift accumulator 205 is used to perform shift accumulation based on the output of the computing array 204 to obtain the calculation result of the first data. Specifically, the current output by the computing array 204 can be converted into binary code, and the binary-coded data can be shifted and accumulated to obtain the calculation result of the first data.

[0059] Based on this, embodiments of this application provide a computation method based on a computing array. This method can be applied to a computing device, which includes the aforementioned computing array. Specifically, while ensuring the accuracy of neural network computation, the method sets the bits involved in the computation of the weights in the computing array according to the weight bit width corresponding to the first data, and then uses the computing array to perform computation on the first data.

[0060] Compared to the solutions in the previous examples, this method does not increase the computation time and chip area of ​​the computing array, and can solve the problems of long computation time and high power consumption in large-scale neural network computation.

[0061] The specific execution process of the functions implemented by the above system is described below with reference to the method embodiments.

[0062] Figure 3 This is a flowchart illustrating a computation method based on a computing array, as provided in an embodiment of this application. The computing array may include the aforementioned in-memory computing structure. The computing array stores multi-bit weights. This method is used to perform the functions implemented by the system described above.

[0063] like Figure 3 As shown, the method includes the following steps S301-S304.

[0064] In step S301, the calculation bit width of the first data is determined based on the data characteristics of the first data.

[0065] Before performing calculations on the first data, the computing device analyzes the first data to obtain its data characteristics. Then, based on the obtained data characteristics, the computing device matches the calculation bit width of the first data with a pre-set correspondence table between data characteristics and calculation bit widths.

[0066] In one example, the data features of the first data may include the similarity between adjacent frames in the first data. When the similarity is high, it indicates that the first data contains less dynamic content and more static content, and a lower computational bit width can be used for inference calculations. Conversely, a higher computational bit width can be used for inference calculations.

[0067] Specifically, the computing device can use a differential hashing algorithm to calculate the similarity between adjacent frames in the first data.

[0068] When the first data is Figure 4 When processing the image data shown in Figures a and b, the computing device can use a differential hashing algorithm to calculate... Figure 4 The similarity between adjacent frames in images a and b. After calculation, Figure 4 The similarity between the two frames in Figure a is 0.84375, indicating that... Figure 4 The image data shown in Figure a contains a lot of static content, so it can be computed using a lower computational bit width; Figure 4 The similarity between the two frames in image b is 0.4375, indicating that... Figure 4 The image data shown in Figure b contains a significant amount of dynamic content, allowing for computation using a higher bit width. Furthermore, when the first set of data includes data from two or more frames, the judgment can be made based on the average similarity of adjacent frames.

[0069] In one example, after determining the similarity between adjacent frames in the first data, the calculated bit width of the first data can be determined in the similarity-to-bit-width correspondence table shown in Table 1 below. In Table 1, the level intervals are defined as follows: Level 1 similarity is 0.7–1; Level 2 similarity is 0.4–0.7; and Level 3 similarity is 0.0–0.4. Figure 4 Taking image a as an example, the similarity of 0.84375 falls within the level 1 range, indicating that the bit width of the first data point is 4. Based on the above... Figure 4 Taking image b as an example, the similarity of 0.4375 is in level 2, which determines that the calculation bit width of the first data is 8.

[0070] Table 1. Relationship between similarity and bit width

[0071] Level range Calculate bit width Weighted bit width Level 1 4 4 Level 2 8 4 Level 3 8 8

[0072] In step S202, the weight bit width for the computation array to perform calculations on the first data is determined based on the computation bit width.

[0073] Specifically, the computing device can also match the weight bit width of the computing array to calculate the first data in the relationship table shown in Table 1.

[0074] In step S203, the bits involved in the calculation of the weight are set according to the weight bit width.

[0075] Due to the technological limitations of computing arrays described above, when storing multi-bit weights in a computing array, each computing unit stores only one bit of the weight; that is, one bit of the weight is stored in a computing unit in the form of electrical conductivity. When the weight is 8 bits, it can be stored through 8 consecutive computing units in a row. This can also be understood as the maximum weight bit width of the computing array being 8 bits when storing 8-bit weights.

[0076] Therefore, the computing device can generate control signals corresponding to each bit line based on the weight bit width determined in step S202 and the indexes of the bit lines connected to the computing units storing multi-bit weights. Then, based on the control signals of each bit line, the computing units connected to each bit line are turned on or off.

[0077] In one example, the control signal can be determined according to the formula x%S<m? 1:0. Here, x represents the bit line index, S represents the maximum weight bit width, and m represents the weight bit width determined in step S202. When the control signal for the bit line with index x is 1, the computation unit on that bit line is in the on state. When the control signal for the bit line with index x is 0, the computation unit on that bit line is in the off state.

[0078] Specifically, such as Figure 5 As shown, multiple bits of the weight can be deployed in the computation array in the order of high bit > low bit. When the computation array stores 8 bits of weight, the bit line index of the weight in the computation array is numbered from 0 to 7. Figure 5 (The order is from left to right). Accordingly, when the weight stored in the calculation array is 8 bits, and when step S202 determines that the weight bit width is 4, the control signals of the bit lines corresponding to multiple bits of the weight can be obtained according to the formula x%8<m? 1:0. For example, when x is 0, the remainder of 0 divided by 8 is 0, and the remainder is less than 4, so the control signal of the bit line with index 0 is 1. As another example, when x is 4, the remainder of 4 divided by 8 is 4, and the remainder is not less than 4, so the control signal of the bit line with index 0 is 0.

[0079] In one example, a controllable device can be set in the computing unit connected to each bit line in the computing array. This controllable device is used to receive the control signal of the bit line to control the computing unit on or off the bit line.

[0080] In step S304, the calculation result corresponding to the first data is determined using a calculation array.

[0081] The computing device can determine the second data from the first data, perform calculations on the second data using a configured computing array, and obtain the output of the computing array. Then, the output of the computing array is shifted and accumulated to obtain the calculation result corresponding to the first data.

[0082] Specifically, the computing device can use the first controller to truncate the first data according to the calculation bit width determined in step S301 to obtain the second data, that is, the length of the second data is equal to the value of the calculation bit width. For example... Figure 6 As shown, when the first data is an 8-bit data stream and the calculation bit width is 4, the lower 4 bits of the first data can be truncated to obtain the higher 4 bits of the second data.

[0083] Specifically, after obtaining the second data, the computing device can adjust the input voltage of the computing array according to each bit of the second data stream, obtain the output of the computing array after each adjustment of the input voltage, and perform shift accumulation based on the output after each adjustment. For example, the input voltage of the computing array can be adjusted once according to 1 bit of the second data stream "0001" to obtain one output of the array, then the input voltage of the computing array can be adjusted once according to 1 bit of the second data stream "1111" to obtain one output of the array, until the output of the array corresponding to each bit of the second data stream is obtained.

[0084] The above method embodiments can adjust the calculation bit width of the first data and the weight bit width of the calculation array for the first data for different first data. Under the premise of meeting the calculation accuracy, the calculation overhead of the array can be reduced and the power consumption of the array can be reduced.

[0085] In one example, this application uses the method described above to process sample images containing locks and sample images containing cats (e.g., ...) in the DIV2K dataset. Figure 7 The two images on the left (shown in the image) were used to perform enhanced deep super-resolution network (EDSR) computation to verify the effectiveness of the above method. The sample image containing the lock has more lock textures, while the sample image containing the cat has fewer ear textures; the former is a hard sample, and the latter is an easy sample. The computational array applied EDSR computation to the two images with different levels of difficulty.

[0086] Specifically, the computation array uses different computation bit widths and weight bit widths to... Figure 7 The calculations were performed on two sample images with different levels of complexity shown on the left, and the visualization of the results is shown below. Figure 7 As shown. Figure 7 The two rows of the graph in the middle represent the images of the lock and the cat's ears in the original sample images. The evaluation metrics for the calculation results are shown in Table 2, including the peak signal-to-noise ratio (PSNR) and bit operations per second (BitOps). 4a2w indicates a 4-bit computation bit width and a 2-bit weight bit width; 8a8w, 4a8w, 4a4w, and 2a4w are interpreted the same as 4a2w.

[0087] Table 2 Evaluation metrics for the results of residual network computation on image samples using computational arrays.

[0088] 8a8w 4a8w 4a4w 2a4w 4a2w PSNR 34.02 34.01 33.88 33.87 32.05 BitOps 100％ 50％ 25％ 12.5％ 12.5％

[0089] from Figure 7 As can be seen, for complex samples, 8w8a can barely meet visual requirements. With the same computational bit width, when the weight bit width is further reduced, the image begins to blur and fails to meet human visual requirements. In Table 2, the PSNR results for 4a2w and 8a8w are similar, but the BitOps differ significantly. Furthermore, in... Figure 7 In the calculation results shown, the difference between the results corresponding to 4a2w and 8a8w is small for human visual perception. Therefore, 4a2w can be used to replace 8a8w, reducing the number of calculation cycles from 8 to 4, and reducing BitOps by 87.5%. This reduces the array's computation time and power consumption while meeting accuracy requirements.

[0090] Based on the above method embodiments, this application also provides a computing device based on a computing array.

[0091] Figure 8 This is a schematic diagram of a computing device 800 based on a computing array provided in this application. This computing device 800 is applied to the aforementioned computing equipment and implements the aforementioned... Figure 3 The calculation method described above. For example... Figure 8 As shown, the computing device 800 includes a determination module 801, a setting module 802, and a computing module 803.

[0092] The determining module 801 is used to determine the calculation bit width of the first data based on the data characteristics of the first data, and is also used to determine the weight bit width of the calculation array for the first data based on the calculation bit width.

[0093] The setting module 802 is used to set the bits involved in the calculation of the weight according to the weight bit width.

[0094] The calculation module 803 is used to determine the calculation result corresponding to the first data using the calculation array.

[0095] It should be noted that, Figure 8 The computing device 800 provided in the illustrated embodiment executes Figure 3 The calculation method shown is only an example of the above-described division of functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the computing device 800 provided in the above embodiment and... Figure 3 The calculation method embodiments shown belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0096] Figure 9 This is a schematic diagram of the hardware structure of a computing device 900 provided in an embodiment of this application.

[0097] See Figure 9 The computing device 900 includes a processor 901, a memory 902, a communication interface 903, and a bus 904, which are interconnected via the bus 904. The processor 901, memory 902, and communication interface 903 may also be connected using other methods besides the bus 904.

[0098] The memory 902 can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical storage, hard disk, etc.

[0099] The processor 901 can be a general-purpose processor, which can be a processor that performs specific steps and / or operations by reading and executing contents stored in memory (e.g., memory 902). For example, the general-purpose processor can be a central processing unit (CPU). The processor 901 may include at least one circuit to perform... Figure 3 All or part of the steps of the calculation method provided in the illustrated embodiment.

[0100] The communication interface 903 includes input / output (I / O) interfaces, physical interfaces, and logical interfaces for interconnecting devices within the computing device 900, as well as interfaces for interconnecting the computing device 900 with other devices (such as other computing devices or user equipment). The physical interface can be an Ethernet interface, a fiber optic interface, an ATM interface, etc.

[0101] The bus 904 can be any type of communication bus used to interconnect the processor 901, memory 902 and communication interface 903, such as a system bus.

[0102] The aforementioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. Whether to dispose of the devices independently on different chips or integrate them on one or more chips often depends on the needs of the product design. This application does not limit the specific implementation of the aforementioned devices.

[0103] Figure 9 The computing device 900 shown is merely an example. In the implementation process, the computing device 900 may also include other components, which will not be listed one by one in this article.

[0104] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0105] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. It should be understood that in the embodiments of this application, the order of the process numbers does not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0106] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A computational method based on a computational array, characterized in that, The computing array includes multiple rows and columns of computing units, with each row of computing units connected to the same word line and each column of computing units connected to the same bit line. The computing array stores weights of multiple bits. The method includes: The computational bit width of the first data is determined based on the data characteristics of the first data, wherein the data characteristics characterize the complexity of the first data; Based on the calculated bit width, the weight bit width for the computing array to calculate the first data is determined; Based on the weight bit width, set the bits involved in the calculation of the weight; The calculation result corresponding to the first data is determined using the calculation array.

2. The method according to claim 1, characterized in that, The data features of the first data include the similarity of data between adjacent frames in the first data.

3. The method according to claim 1, characterized in that, Each computational unit storing multiple bits of the weight is connected to a bit line. The step of setting the bits involved in the calculation of the weight according to the weight bit width includes: Based on the weighted bit width and the index of each bit line, the control signal corresponding to each bit line is generated; The control signal is used to turn the computing units connected to each bit line on or off.

4. The method according to any one of claims 1-3, characterized in that, The step of using the computing array to determine the calculation result corresponding to the first data includes: Based on the calculated bit width, the first data is truncated to obtain the second data; The second data is processed using the computing array to obtain the output of the computing array; The output of the computing array is shifted and accumulated to obtain the calculation result corresponding to the first data.

5. The method according to claim 4, characterized in that, The step of using the computing array to perform calculations on the second data and obtaining the output of the computing array includes: The input voltage of the computing array is adjusted according to the second data to obtain the output of the computing array.

6. A computing device based on a computing array, characterized in that, The computing array includes multiple rows and columns of computing units, with each row of computing units connected to the same word line and each column of computing units connected to the same bit line. The computing array stores multiple bits of weights. The device includes: The determining module is used to determine the computational bit width of the first data based on the data characteristics of the first data, and is also used to determine the weight bit width of the computation array for computing the first data based on the computational bit width, wherein the data characteristics characterize the complexity of the first data; The setting module is used to set the bits involved in the calculation of the weight according to the weight bit width; A calculation module is used to determine the calculation result corresponding to the first data using the calculation array.

7. The apparatus according to claim 6, characterized in that, The data features of the first data include the similarity of data between adjacent frames in the first data.

8. The apparatus according to claim 6, characterized in that, Each computational unit storing the weights in multiple bits is connected to a bit line. The setting module is specifically used for: Based on the weighted bit width and the index of each bit line, the control signal corresponding to each bit line is generated; The control signal is used to turn the computing units connected to each bit line on or off.

9. The apparatus according to any one of claims 6-8, characterized in that, The calculation module is specifically used for: Based on the calculated bit width, the first data is truncated to obtain the second data; The second data is processed using the computing array to obtain the output of the computing array; The output of the computing array is shifted and accumulated to obtain the calculation result corresponding to the first data.

10. The apparatus according to claim 9, characterized in that, The calculation module is also specifically used for: The input voltage of the computing array is adjusted according to the second data to obtain the output of the computing array.

11. A computing device, characterized in that, The computing device includes a processor and a memory, the processor being configured to execute a computer program stored in the memory to implement the method of any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on a computing device, cause the computing device to perform the method as described in any one of claims 1 to 5.

13. A computer program product, characterized in that, Includes program code that, when a computing device runs the computer program product, causes the computing device to perform the method as described in any one of claims 1 to 5.

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