A display panel, a driving method for the display panel, and a display device.

Abstract

This application provides a display panel, a driving method for the display panel, and a display device. The display panel includes a light-emitting device, multiple pixel circuits, and multiple cascaded shift registers. The output terminal of each pixel circuit is electrically connected to the light-emitting device. Each pixel circuit includes a first transistor, and at least one operating cycle of the pixel circuit includes a first stage and at least one second stage. The output terminal of each shift register is electrically connected to the gate of the first transistor. Specifically, in the first stage of the pixel circuit, the output terminal of the shift register outputs an enable signal for a duration of t1; in the bias stage of the second stage of the pixel circuit, the output terminal of the shift register outputs an enable signal for a duration of t2; t2 < t1, t1 > 0, t2 > 0. In this application embodiment, by adjusting the duration of the pixel circuit in the bias stage, the low grayscale display effect of the display panel is improved.

Description

[Technical Field]

[0001] This application relates to the field of display technology, and in particular to a display panel, a driving method for the display panel, and a display device. [Background Technology]

[0002] Display panels using light-emitting devices such as organic light-emitting diodes (OLEDs), micro-LEDs, and mini-LEDs have advantages such as low power consumption, self-illumination, wide viewing angles, wide temperature ranges, and fast response times, and are widely used in the market. Among these, the pixel circuits used to drive the light-emitting devices are the core technology of display panels and are of significant research importance.

[0003] However, when existing pixel circuits drive light-emitting devices to emit light, the brightness uniformity of the display panel is poor and there may be screen flickering problems, especially when the display panel is in a low-frequency, low-grayscale state, the above problems are more obvious.

[0004] [Application Content]

[0005] In view of this, embodiments of this application provide a display panel, a driving method for the display panel, and a display device to solve the above problems.

[0006] In a first aspect, embodiments of this application provide a display panel, including a light-emitting device, multiple pixel circuits, and multiple cascaded shift registers. The output terminal of each pixel circuit is electrically connected to the light-emitting device. Each pixel circuit includes a first transistor, and at least one operating cycle of the pixel circuit includes a first stage and at least one second stage, the second stage including a bias stage. The output terminal of each shift register is electrically connected to the gate of the first transistor. Specifically, in the first stage of the pixel circuit, the output terminal of the shift register outputs an enable signal for a duration of t1; in the bias stage of the second stage of the pixel circuit, the output terminal of the shift register outputs the enable signal for a duration of t2; t2 < t1, t1 > 0, t2 > 0.

[0007] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0008] In this embodiment, by making the duration of the shift register outputting the enable signal in the second stage of the pixel circuit bias phase shorter than the duration of the shift register outputting the enable signal in the first stage of the pixel circuit, the bias duration of the pixel circuit is controlled to be shorter, thereby achieving flexible and controllable bias duration of the pixel circuit; and when the display panel needs to be biased for low-frequency display, over-biasing of the pixel circuit can be avoided. [Attached Image Description]

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application;

[0011] Figure 2 An equivalent circuit diagram of a pixel circuit provided in an embodiment of this application;

[0012] Figure 3 This is a timing diagram of one working cycle of the pixel circuit in one embodiment of this application;

[0013] Figure 4 This is a timing diagram of one working cycle of the pixel circuit in one embodiment of this application;

[0014] Figure 5 This is a timing diagram of the shift register section operating within one working cycle of the pixel circuit.

[0015] Figure 6 A schematic diagram of a display panel provided in an embodiment of this application;

[0016] Figure 7 This is a timing diagram of one working cycle of the pixel circuit in one embodiment of this application;

[0017] Figure 8 A schematic diagram of a display panel provided in an embodiment of this application;

[0018] Figure 9 A schematic diagram of a display panel provided in an embodiment of this application;

[0019] Figure 10 This is a schematic diagram of the luminous intensity of the light-emitting device during one working cycle of the pixel circuit.

[0020] Figure 11 The equivalent circuit diagram corresponding to the shift register provided in the embodiments of this application;

[0021] Figure 12 This is a timing diagram of the shift register receiving and outputting signals when the pixel circuit is in the first and second stages.

[0022] Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application.

Detailed Implementation Methods

[0023] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0024] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0025] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0026] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "roughly", "generally" and "generally" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0028] It should be understood that although terms such as "first," "second," etc., may be used to describe directions, transistors, signal lines, shift registers, etc., in the embodiments of this application, these terms should not be limited to these terms. These terms are only used to distinguish directions, transistors, signal lines, shift registers, etc., from one another. For example, without departing from the scope of the embodiments of this application, a first transistor may also be referred to as a second transistor, and similarly, a second transistor may also be referred to as a first transistor.

[0029] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0030] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0031] like Figure 1As shown, the display panel 10 provided in this embodiment includes a plurality of light-emitting devices L and a plurality of pixel circuits PC. The output terminal of the pixel circuit PC is electrically connected to the light-emitting devices L, and the pixel circuit PC provides light-emitting driving current or light-emitting driving voltage to the light-emitting devices L. The light-emitting devices L can specifically be at least one of organic light-emitting diodes (OLED), micro-LEDs, and mini-LEDs.

[0032] In addition, the pixel circuit PC and the light-emitting device L can be set in the display area AA of the display panel. Furthermore, the display area AA can also include multiple data lines DL, multiple control lines SL, and other signal lines.

[0033] The display panel 10 includes multiple data lines DL arranged along a first direction X and extending substantially along a second direction Y. The first direction X and the second direction Y can be perpendicular. The data lines DL are electrically connected to pixel circuits PC and transmit data voltage to the pixel circuits PC. Multiple pixel circuits PCs arranged along the second direction Y can be electrically connected to the same data line DL, that is, one data line DL can electrically connect multiple pixel circuits PCs arranged along the second direction Y.

[0034] The display panel 10 includes multiple control lines SL arranged along a second direction Y and extending substantially along a first direction X, where the first direction X and the second direction Y can be perpendicular. The control lines SL are electrically connected to pixel circuits PC and transmit scanning voltage to the pixel circuits PC. Multiple pixel circuits PCs arranged along the first direction X can be electrically connected to the same control line SL; that is, one control line SL can electrically connect multiple pixel circuits PCs arranged along the first direction X.

[0035] Figure 2 An equivalent circuit diagram of a pixel circuit provided in an embodiment of this application.

[0036] like Figure 2 As shown, the pixel circuit PC includes transistors M1, M2, M3, M4, M5, M6, M7, and storage capacitor Cst.

[0037] Specifically, transistor M1 has its gate electrically connected to the first control line S1, its first terminal electrically connected to the power supply voltage line PVDD, and its second terminal electrically connected to the input terminal of driving transistor M3; transistor M2 has its gate electrically connected to the second control line S2, its first terminal electrically connected to the data line DL, and its second terminal electrically connected to the input terminal of driving transistor M3; transistor M4 has its gate electrically connected to the third control line S3, its first terminal electrically connected to the output terminal of driving transistor M3, and its second terminal electrically connected to the gate of driving transistor M3; and transistor M5 has its gate electrically connected to the fourth control line S4. The first terminal of transistor M6 is electrically connected to the reset signal line DR, and the second terminal is electrically connected to the gate of the driving transistor M3; the gate of transistor M6 is electrically connected to the first control line S1, the first terminal is electrically connected to the output terminal of the driving transistor M3, and the second terminal is electrically connected to the anode of the light-emitting device L; the gate of transistor M7 is electrically connected to the fifth control line S5, the first terminal is electrically connected to the reset signal line DR, and the second terminal is electrically connected to the anode of the light-emitting device L; one plate of the storage capacitor Cst is electrically connected to the power supply voltage line PVDD, and the other plate is electrically connected to the gate of the driving transistor M3.

[0038] like Figure 2 As shown, the pixel circuit PC also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is electrically connected to the gate of the driving transistor M3, the second node N2 is electrically connected to the input terminal of the driving transistor M3, the third node N3 is electrically connected to the output terminal of the driving transistor M3, and the fourth node N4 is electrically connected to the anode of the light-emitting device L.

[0039] It should be noted that the pixel circuit in the display panel provided in this application can be as follows: Figure 2 As shown, other forms of circuits may also be used, and this application does not limit this. Hereinafter, Figure 2 The present invention will be explained with respect to the pixel circuit PC shown, in which transistors M1, M2, M3, M4, M5, M6 and M7 are all P-type transistors.

[0040] Figure 3 This is a timing diagram of one working cycle of the pixel circuit in one embodiment of this application.

[0041] Combination Figure 2 and Figure 3 As shown, at least one working cycle T of the pixel circuit PC includes a first stage E1 and at least one second stage E2. The pixel circuit PC completes one working cycle T after experiencing the first stage E1 and one second stage E2, or the pixel circuit PC completes one working cycle T after experiencing the first stage E1 and multiple second stages E2.

[0042] Within the same working cycle T, the first stage E1 occurs before the second stage T2, and the pixel circuit PC includes a light-emitting stage e3 in both the first stage E1 and the second stage E2. The first stage E1 can be a regular light-emitting stage, comprising a reset stage e1, a data voltage writing stage e2, and a light-emitting stage e3 performed sequentially. The second stage E2 can be a bias-based light-emitting stage, comprising a bias stage e4 and a light-emitting stage e3 performed after the bias stage e4.

[0043] Combination Figure 2 and Figure 3 The following describes the operation of the pixel circuit PC during a working cycle T, which includes the first stage E1 and the second stage E2:

[0044] When the pixel circuit PC is in the first stage E1, it first goes through the reset stage e1. In the reset stage e1, the fourth control line S4 transmits an enable signal, the transistor M5 in the pixel circuit PC turns on, and the reset voltage transmitted by the reset signal line DR is written to the first node N1 to reset the gate of the driving transistor M3. Then the pixel circuit PC goes through the data voltage writing stage e2. In the data voltage writing stage e2, the second control line S2 and the third control line S3 transmit enable signals respectively, the transistors M2 and M4 in the pixel circuit PC turn on, and the data voltage transmitted by the data line DL is transmitted to the first node N1 through the second node and the third node N3, and the data voltage is written to the gate of the driving transistor M3. After that, the pixel circuit PC goes through the light emission stage e3. In the light emission stage e3, the first control line S1 transmits an enable signal, the transistors M1 and M6 in the pixel circuit PC turn on, and the power supply voltage transmitted by the power supply voltage line PVDD is transmitted to the input terminal of the driving transistor M3 through the transistor M1. The driving transistor M3 conducts the generated light emission driving current to the anode of the light emission device L through the transistor M6.

[0045] Among them, combined Figure 2 and Figure 3 During the data voltage writing phase e2, the fifth control line S5 transmits an enable signal, turning on transistor M7 in the pixel circuit PC. The reset signal line DR transmits the reset voltage, which is then written to the fourth node N4, resetting the anode of the light-emitting device L. It should be noted that resetting the anode of the light-emitting device L can occur during the data voltage writing phase e2, or it can occur at other stages.

[0046] When the pixel circuit PC is in the second stage E2, it first goes through the bias stage e4 and then the light emission stage e3. During the bias stage e4, either the data line DL or the reset signal line DR can transmit the bias voltage.

[0047] In one technical solution, combined with Figure 2 and Figure 3 During the biasing phase e4, the second control line S2 transmits an enable signal, causing transistor M2 in the pixel circuit PC to turn on. The bias voltage transmitted by the data line DL is written to the second node N2 and / or the third node N3 to bias the second node N2 and / or the third node N3. That is, the data line DL transmits the data voltage during the data voltage writing phase e2 and the biasing phase e4; and transistor M2 is turned on during both the data voltage writing phase e2 and the biasing phase e4.

[0048] In this technical solution, the third control line S3 and the fifth control line S5 can be reused.

[0049] Figure 4 This is a timing diagram of one working cycle of the pixel circuit in one embodiment of this application.

[0050] In one technical solution, combined with Figure 2 and Figure 4 During the bias phase e4, the fifth control line S5 transmits an enable signal, turning on transistor M7 in the pixel circuit PC. The bias voltage transmitted by the reset signal line DR is written to the fourth node N4 to bias it. That is, the reset signal line DR transmits the reset voltage during the reset phase e2 and the bias voltage during the bias phase e4; and transistor M7 is turned on during the data voltage writing phase e2 and the bias phase e4.

[0051] In this technical solution, the second control line S2 and the third control line S3 can be reused.

[0052] In this application, the pixel circuit PC includes a first transistor, which is a name given to a portion of the transistors inside the pixel circuit PC. For example, the first transistor may be transistor M2 or transistor M7.

[0053] like Figure 1As shown, the display panel 10 also includes a shift register 01, which includes multiple cascaded shift registers S. For example, the shift register 01 includes n cascaded shift registers S, and these n cascaded shift registers S are sequentially shift register 011, shift register 012, shift register 013, shift register 014, ..., shift register 01n. The shift registers S can be arranged along the second direction Y, and adjacent shift registers S are electrically connected. Each shift register S includes an input terminal IN and an output terminal OUT. For two adjacent shift registers S, the input terminal IN of the subsequent shift register S is electrically connected to the output terminal OUT of the preceding shift register S, and the signal output by the preceding shift register S serves as a trigger signal to start the operation of the subsequent shift register S. Furthermore, the input terminal IN of the first-stage shift register S in shift register 01 is electrically connected to the start signal line 02 and receives the trigger signal. The output terminal of the shift register in shift register 01 is electrically connected to the gate of the first transistor and is used to control the first transistor to be in the on or off state.

[0054] The display panel also includes a first clock signal line CK and a second clock signal line XCK. Each shift register S in shift register 01 is electrically connected to the first clock signal line CK and the second clock signal line XCK. Each shift register S may include a first clock signal terminal CK1 and a first clock signal terminal CK2. The first clock signal terminals CK1 of multiple cascaded shift registers S are alternately electrically connected to the first clock signal line CK and the second clock signal line XCK, and the second clock signal terminals CK2 of multiple cascaded shift registers S are alternately electrically connected to the second clock signal line XCK and the first clock signal line CK. For example, the first clock signal terminal CK1 of shift register 011 is electrically connected to the first clock signal line CK; the first clock signal terminal CK1 of shift register 012 is electrically connected to the second clock signal line XCK; the first clock signal terminal CK1 of shift register 013 is electrically connected to the first clock signal line CK; and the first clock signal terminal CK1 of shift register 014 is electrically connected to the second clock signal line XCK. The second clock signal terminal CK2 of shift register 011 is electrically connected to the second clock signal line XCK; the second clock signal terminal CK2 of shift register 012 is electrically connected to the first clock signal line CK; the second clock signal terminal CK2 of shift register 013 is connected to the second clock signal line XCK; and the second clock signal terminal CK2 of shift register 014 is electrically connected to the first clock signal line CK.

[0055] The shift register 01 and the start signal line 02 can be set in the non-display area NA of the display panel 10.

[0056] Figure 5This is a timing diagram of the shift register during one working cycle of the pixel circuit.

[0057] like Figure 5 As shown, when the pixel circuit PC is in the first stage E1, the output terminal OUT of the shift register S outputs an enable signal for a duration of t1 and t1 > 0; when the pixel circuit PC is in the bias stage of the second stage E2, the output terminal OUT of the shift register S outputs an enable signal for a duration of t2 and t2 > 0, and t2 < t1, t1 > 0, t2 > 0. The duration of the enable signal output by the shift register S determines the duration for which the first transistor electrically connected to it is in the on state.

[0058] The first transistor in the pixel circuit PC is turned on for a duration of t1 and t1 > 0 during the first stage E1; the first transistor in the pixel circuit PC is turned on for a duration of t2 and t2 > 0 during the bias stage of the second stage E2. t2 < t1, t1 > 0, t2 > 0. When the first transistor in the pixel circuit PC is turned on during the bias stage of the second stage E2, it can transmit bias voltage to the second node N2 and / or the third node N3, or the fourth node N4 in the pixel circuit PC. That is, when the pixel circuit PC is operating during the bias stage of the second stage E2, the first transistor being turned on signifies that the pixel circuit PC is in the bias stage.

[0059] In this embodiment, by making the duration of the shift register S outputting the enable signal in the bias stage of the second stage E2 of the pixel circuit PC shorter than the duration of the shift register S outputting the enable signal in the first stage E1 of the pixel circuit PC, the bias duration of the pixel circuit PC is controlled to be shorter, thereby achieving flexible and controllable bias duration of the pixel circuit PC; and when the display panel 10 needs to be biased for low-frequency display, over-biasing of the pixel circuit PC can be avoided.

[0060] In one embodiment of this application, combined with Figure 1 , Figure 2 and Figure 3 In the pixel circuit PC, the gate of the first transistor is electrically connected to the second control line S2, its input terminal is electrically connected to the data line DL, and its output terminal is electrically connected to the input terminal of the driving transistor M3; that is, the first transistor corresponds to transistor M2. The data line DL is used to transmit data voltage in the first stage E1 and to transmit a first bias voltage in the second stage E2. In other words, in the data voltage writing stage e2 of the first stage E1, the first transistor writes the data voltage into the pixel circuit PC, and in the bias stage e4 of the second stage E2, the first transistor writes the first bias voltage into the pixel circuit PC to bias it.

[0061] It should be noted that the specific time period for the data line DL to transmit the data voltage can be the data voltage writing stage e2 in the first stage E1, and the specific time period for the data line DL to transmit the first bias voltage can be the bias stage e4 in the second stage E2.

[0062] The data line DL and the first transistor are used to control the data voltage to be written to the gate of the driving transistor M3 when the pixel circuit PC is in the first stage E1, and the data line DL and the first transistor are used to control the first bias voltage to be written to the input and / or output terminals of the driving transistor M3 when the pixel circuit PC is in the second stage E2. In the same cycle T, the magnitude of the first bias voltage may be equal to or unequal to the magnitude of the data voltage transmitted by the data line DL when the pixel circuit PC is in the first stage E1.

[0063] Combination Figure 1 , Figure 2 , Figure 3 and Figure 5 When transistor M2 in the pixel circuit PC is the first transistor, the output terminal OUT of the shift register S is electrically connected to the second control line S2, and the enable signal output by the output terminal OUT of the shift register S can control transistor M2 to turn on. The specific time period for the output terminal OUT of the shift register S to output the enable signal is the data voltage writing stage e2 in the first stage E1 and the bias stage e4 in the second stage E2. Where t2 < t1, the write duration t2 of the shift register S controlling the first bias voltage to write to the second node N2 and / or the third node N3 is less than the write duration t1 of the data voltage written to the first node N1 through the second node N2 and the third node N3.

[0064] In this embodiment, the output terminals OUT of multiple cascaded shift registers S in shift register 01 are electrically connected to transistor M2 in pixel circuit PC. By making the duration of the enable signal output by the output terminal OUT of shift register S during the data voltage writing phase e2 longer than the duration of the enable signal output during a bias phase e4, the bias duration of the second node N2 and the third node N3 of pixel circuit PC is controlled to be shorter, thereby achieving flexible and controllable bias duration of the second node N2 and the third node N3 of pixel circuit PC; in addition, when the display panel 10 requires bias for low-frequency display, over-biasing of the second node N2 and the third node N3 of pixel circuit PC can be avoided.

[0065] Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0066] In one embodiment of this application, combined with Figure 6 , Figure 2 and Figure 4In the pixel circuit PC, the gate of the first transistor is electrically connected to the fifth control line S5, its input terminal is electrically connected to the reset signal line DR, and its output terminal is electrically connected to the input terminal of the light-emitting device L. That is, the first transistor corresponds to transistor M7. The reset signal line DR is used to transmit the reset voltage in the first stage E1 and to transmit the second bias voltage in the second stage E2. In other words, the first transistor writes the reset voltage to the pixel circuit PC in the first stage E1, and in the bias stage e4 of the second stage E2, the first transistor writes the second bias voltage to the pixel circuit PC to bias it.

[0067] It should be noted that the specific time period during which the reset signal line DR transmits the reset voltage can be the data voltage writing stage e2 in the first stage E1, and the specific time period during which the data line DL transmits the first bias voltage can be the bias stage e4 in the second stage E2. It should also be noted that when the time period during which transistor M7 resets the fourth node N4 overlaps with other stages in the first stage E1, the specific time period during which the reset signal line DR transmits the reset voltage can also be any of those other stages in the first stage E1.

[0068] The reset signal line DR and the first transistor are used to control the reset voltage to be written to the anode of the light-emitting device L (the output terminal of the pixel circuit PC) when the pixel circuit PC is in the first stage E1. The reset signal line DR and the first transistor are also used to control the second bias voltage to be written to the anode of the light-emitting device L when the pixel circuit PC is in the second stage E2. In the same period T, the magnitude of this second bias voltage may be equal to or unequal to the magnitude of the reset voltage transmitted by the reset signal line DR when the pixel circuit PC is in the first stage E1.

[0069] Combination Figure 2 , Figure 4 and Figure 5 , Figure 6 When transistor M7 in the pixel circuit PC is the first transistor, the output terminal OUT of the shift register S is electrically connected to the fifth control line S2, and the enable signal output by the output terminal OUT of the shift register S can control transistor M7 to turn on. The specific time period for the output terminal OUT of the shift register S to output the enable signal is the data voltage writing stage e2 in the first stage E1 and the bias stage e4 in the second stage E2. Where t2 < t1, the write duration t2 of the shift register S controlling the second bias voltage to write to the fourth node N4 is less than the write duration t1 of the reset voltage to write to the fourth node N4.

[0070] In this embodiment, the output terminals OUT of the multiple cascaded shift registers S in shift register 01 are electrically connected to transistor M7 in pixel circuit PC. By making the duration of the enable signal output by the output terminal OUT of shift register S during the data voltage writing phase e2 longer than the duration of the enable signal output during a bias phase e4, the bias duration of the fourth node N4 of pixel circuit PC is controlled to be shorter, thereby achieving flexible and controllable bias duration of the fourth node N4 of pixel circuit PC; in addition, when the display panel 10 requires bias for low-frequency display, over-biasing of the fourth node N4 of pixel circuit PC can be avoided.

[0071] In one embodiment of this application, the pixel circuit PC further includes a second transistor, which is a name given to a portion of the transistors inside the pixel circuit PC. For example, the second transistor may be transistor M2 or transistor M7.

[0072] For the first transistor and the second transistor, the input terminal of one is electrically connected to the data line DL, and the input terminal of the other is electrically connected to the reset signal line DR, and its output terminal is electrically connected to the light-emitting device L. That is, of the first transistor and the second transistor, one is transistor M2 and the other is transistor M7. The data line DL is used to transmit data voltage to the input terminal of transistor M2 when the pixel circuit PC is in the first stage E1. The data line DL is also used to transmit a first bias voltage to the input terminal of transistor M2 when the pixel circuit PC is in the second stage E2. The reset signal line DR is used to transmit a reset voltage to the input terminal of transistor M7 when the pixel circuit PC is in the first stage E1. The reset signal line DR is also used to transmit a second bias voltage to the input terminal of transistor M7 when the pixel circuit PC is in the second stage E2. Therefore, of the first transistor and the second transistor, one can bias the second node N2 and / or the third node N3 in the bias stage e4 of the second stage E2, and the other can bias the fourth node N4 in the bias stage e4 of the second stage E2.

[0073] In this embodiment, the biasing of the second node N2 and / or the third node N3, and the biasing of the fourth node N4 can be completed in a second stage E2. It should be noted that the biasing of the fourth node N4 and the biasing of the second node N2 and / or the third node N3 can be performed simultaneously or in a time-sharing manner. Furthermore, within a work cycle T, the biasing of the fourth node N4 and the biasing of the second node N2 and / or the third node N3 can be completed in different second stages E2.

[0074] The following explanation uses transistor M2 as the first transistor and transistor M7 as the second transistor, with the biasing of the fourth node N4 occurring simultaneously with the biasing of the second node N2 and / or the third node N3. It is understandable that transistor M2 could also be the second transistor and transistor M7 could also be the first transistor.

[0075] Figure 7 This is a timing diagram of one working cycle of the pixel circuit in one embodiment of this application.

[0076] Combination Figure 2 and Figure 7 When transistor M2 in pixel circuit PC is the first transistor and transistor M7 in pixel circuit PC is the second transistor, the second control line S2, which is electrically connected to the gate of the first transistor (transistor M2), transmits enable signals in the data voltage writing stage e2 of the first stage E1 and the bias stage e4 of the second stage E2, respectively completing the data voltage writing and biasing of the second node N2 and / or the third node N3; the fifth control line S5, which is electrically connected to the gate of the second transistor (transistor M7), transmits enable signals in the data voltage writing stage e2 of the first stage E1 and the bias stage e4 of the second stage E2, respectively completing the reset voltage writing and biasing of the fourth node N4.

[0077] Specifically, the second control line S2 is electrically connected to the output terminal OUT of the shift register S, and the shift register S connected to the second control line S2 is used to control the turning on of the first transistor (transistor M2). The fifth control line S5 is electrically connected to the output terminal OUT of the shift register S, and the shift register S connected to the fifth control line S5 is used to control the turning on of the second transistor (transistor M7). The specific time periods for the output enable signals from the shift register S connected to the second control line S2 and the shift register S connected to the fifth control line S5 are the data voltage writing stage e2 in the first stage E1 and the bias stage e4 in the second stage E2. Where t2 < t1, the write duration t2 of the shift register S, which is electrically connected to the second control line S2, writing the first bias voltage to the second node N2 and / or the third node N3 is less than the write duration t1 of the data voltage to the second node N2 and / or the third node N3, and the write duration t2 of the shift register S, which is electrically connected to the fifth control line S5, writing the second bias voltage to the fourth node N4 is less than the write duration t1 of the reset voltage to the fourth node N4.

[0078] Figure 8 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0079] In one implementation, the gates of the first transistor and the second transistor in the same pixel circuit PC are electrically connected to the shift registers in different shift registers via different control lines SL. For example, as Figure 8 As shown, the display panel 10 includes a shift register 01 and a shift register 01', and the first transistor (transistor M2) is electrically connected to the output terminal OUT of the shift register S in the shift register 01 via the second control line S2, and the second transistor (transistor M7) is electrically connected to the output terminal OUT' of the shift register S in the shift register 01' via the fifth control line S5.

[0080] Combination Figure 8 and Figure 7 By controlling the shift register S in shift register 01 to output an enable signal for a duration of t1 during the data voltage writing phase e2 of the first stage E1 and to output an enable signal for a duration of t2 during the biasing phase e4 of the second stage E2, that is, by controlling the second control line S2 to transmit an enable signal for a duration of t1 during the data voltage writing phase e2 of the first stage E1 and to transmit an enable signal for a duration of t2 during the biasing phase e4 of the second stage E2, the first transistor completes writing the data voltage to the first node N1 of the pixel circuit PC and biasing the second node N2 and / or the third node N3, and makes the duration of the first transistor writing the data voltage to the first node N1 of the pixel circuit PC longer than the biasing duration of the first transistor biasing the second node N2 and / or the third node N3.

[0081] Combination Figure 8 and Figure 7 By controlling the shift register S in shift register 01' to output an enable signal for a duration of t1 during the data voltage writing phase e2 of the first stage E1 and to output an enable signal for a duration of t2 during the biasing phase e4 of the second stage E2, that is, by controlling the fifth control line S5 to transmit an enable signal for a duration of t1 during the data voltage writing phase e2 of the first stage E1 and to transmit an enable signal for a duration of t2 during the biasing phase e4 of the second stage E2, the second transistor completes writing the reset voltage to the fourth node N4 of the pixel circuit PC and biasing the fourth node N4, and makes the duration of the second transistor writing the reset voltage to the fourth node N4 of the pixel circuit PC longer than the biasing duration of the second transistor biasing the fourth node N4.

[0082] Figure 9 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0083] In one implementation, within the same pixel circuit PC, the gates of the first transistor and the second transistor can be electrically connected to the outputs of different stages of the shift register S in the same shift register O1. For example... Figure 9As shown, in the same pixel circuit PC, the first transistor is electrically connected to the data line DL and the second transistor is electrically connected to the reset signal line DR. Then, the shift register S electrically connected to the gate of the first transistor is the previous stage of the shift register S electrically connected to the gate of the second transistor.

[0084] For example, such as Figure 9 As shown, the output terminal of the shift register 013 is electrically connected to the first transistor of the pixel circuit in the third row and the second transistor of the pixel circuit in the fourth row. When the shift register S13 outputs an enable signal for a duration of t1, the first transistor in the third row pixel circuit and the second transistor in the fourth row pixel circuit enter the data voltage writing stage e2 of the first stage E1. The first transistor writes data voltage to the second node N2 and / or the third node N3 of the third row pixel circuit for a duration of t1, and the second transistor writes reset voltage to the fourth node N4 of the fourth row pixel circuit for a duration of t1. When the shift register S13 outputs an enable signal for a duration of t2, the first transistor in the third row pixel circuit and the second transistor in the fourth row pixel circuit enter the bias stage e4 of the second stage E2. The first transistor biases the second node N2 and / or the third node N3 of the third row pixel circuit for a duration of t2, and the second transistor biases the fourth node N4 of the fourth row pixel circuit for a duration of t2.

[0085] Figure 10 This is a schematic diagram of the luminous intensity of the light-emitting device during one operating cycle of the pixel circuit.

[0086] In this diagram, the vertical height of the curve represents the luminous intensity of the light-emitting device L. The solid curve illustrates the change in luminous intensity of the light-emitting device L in a prior art display panel during one working cycle of the pixel circuit PC, while the dashed curve illustrates the change in luminous intensity of the light-emitting device L in a display panel employing the inventive concept of this application during one working cycle of the pixel circuit PC.

[0087] Among them, such as Figure 10 As shown by the solid line, the light-emitting device L in the prior art emits light multiple times in one light-emitting cycle, and the maximum luminous brightness corresponding to each of these multiple light emission events is significantly different, as is the minimum luminous brightness corresponding to each of these multiple light emission events.

[0088] By biasing the second node N2 and / or the third node N3 of the pixel circuit in the second stage E2 within a working cycle, and by biasing the second node N2 and / or the third node N3 of the pixel circuit PC for a short duration, the maximum luminous intensity of the light-emitting device L in the second stage E2 can be flexibly adjusted, so that the maximum luminous brightness corresponding to the multiple luminous emission of the light-emitting device L in a luminous emission cycle is more balanced, thus reducing flicker.

[0089] By biasing the fourth node N4 of the pixel circuit in the second stage E2 within a working cycle, and by biasing the fourth node N4 of the pixel circuit PC for a short duration, the minimum luminous intensity of the light-emitting device L in the second stage E2 can be flexibly adjusted, so that the minimum luminous brightness corresponding to the multiple luminous emission of the light-emitting device L in a luminous emission cycle is more balanced, thus reducing flicker.

[0090] Figure 11 The equivalent circuit diagram corresponding to the shift register provided in the embodiments of this application is shown.

[0091] The following combination Figure 11 The shift register 01i describes the structure and operation of the shift register S, where 1≤i≤n.

[0092] The circuit of the shift register 01i includes transistors Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, storage capacitor C1, and storage capacitor C2.

[0093] Specifically, the gate of transistor Y1 is electrically connected to the first clock signal line CK, the first terminal is the input terminal IN of the shift register 01i, and the second terminal is electrically connected to the gate of transistor Y4; the gate of transistor Y2 is electrically connected to the first clock signal line CK, the first terminal receives the second fixed signal VGL, and the second terminal is electrically connected to the gate of transistor Y6; the gate of transistor Y3 is electrically connected to the input terminal of transistor Y2, the first terminal is electrically connected to the output terminal of transistor Y1, and the second terminal is electrically connected to the gate of transistor Y7; the gate of transistor Y4 is electrically connected to the output terminal of transistor Y1, the first terminal is electrically connected to the first clock signal line CK, and the second terminal is electrically connected to the gate of transistor Y8; the gate of transistor Y5 is electrically connected to the second clock signal line XCK, the first terminal is electrically connected to the output terminal of transistor Y1, and the second terminal is electrically connected to the gate of transistor Y8. The input terminal of transistor Y8 is electrically connected; the gate of transistor Y6 is electrically connected to the output terminal of transistor Y4, the first electrode is electrically connected to the output terminal of transistor Y5, and the second electrode is electrically connected to the input terminal of transistor Y8; the gate of transistor Y7 is electrically connected to the output terminal of transistor Y3, the first electrode is electrically connected to the second clock signal line XCK, and the second electrode is the output terminal of shift register 01i; the gate of transistor Y8 is electrically connected to the output terminal of transistor Y2, the first electrode receives the first fixed signal VGH, and the second electrode is the output terminal of shift register 01i; one plate of storage capacitor C1 is electrically connected to the gate of transistor Y7, and the other plate is electrically connected to the output terminal of shift register 01i; one plate of storage capacitor C2 is electrically connected to the gate of transistor Y8, and the other plate is electrically connected to the input terminal of transistor Y8.

[0094] The following explanation will be based on the example where all transistors in the shift register S are P-type transistors, the first fixed potential signal VGH is a DC high-level signal, and the second fixed potential signal VGL is a DC low-level signal.

[0095] Figure 12 This is a timing diagram of the shift register receiving and outputting signals when the pixel circuit is in the first and second stages.

[0096] First, the first clock signal line CK transmits a low-level enable signal to the shift register 01i, turning on transistors Y1 and Y2. The low-level enable signal received at the input terminal IN of the shift register 01i is written to the gate of transistor Y4 and the input terminal of transistor Y3, respectively. Since the second fixed potential signal VGL is a DC low-level signal, transistor Y3 remains on. The low-level signal received at the input terminal of transistor Y3 is written to one plate of storage capacitor C1 and the gate of transistor Y7, turning on transistor Y7. At this time, the high-level signal transmitted by the second clock signal line XCK is transmitted to the output terminal OUT of the shift register 01i, and the enable signal output by the shift register 01i is a high-level signal.

[0097] Subsequently, the first clock signal line CK transmits a high-level signal to the shift register 01i, transistors Y1 and Y2 are in the off state, the storage capacitor C1 conducts the stored low potential to the gate of transistor Y7, transistor Y7 turns on, and the low-level signal transmitted by the second clock signal line XCK is written to the output terminal OUT of the shift register 01i. At this time, the enable signal output by the shift register 01i is a low-level signal.

[0098] When the pixel circuit PC is in the first stage E1, the output terminal OUT of the shift register S outputs the enable signal for a duration of t1, where t1 ≥ 16μs; when the pixel circuit PC is in the second stage E2, the output terminal OUT of the shift register S outputs the enable signal for a duration of t2, where 5μs ≥ t2 ≥ 2μs.

[0099] In the embodiments of this application, t1≥2*t2.

[0100] The shift register S outputs the enable signal in the second stage E2 for no longer than twice the duration of the enable signal output in the first stage E1. This means that the bias duration of the pixel circuit PC is shorter, allowing the pixel circuit PC to achieve more flexible biasing. This makes it easier to adjust the light intensity of the light-emitting device L in the first stage E1 to be equal to the light intensity in the second stage E2.

[0101] like Figure 12As shown, when the pixel circuit PC is in the first stage E1, the pulse width of the enable signal transmitted by the first clock signal line CK and the pulse width of the enable signal transmitted by the second clock signal line XCK are both w1; when the pixel circuit PC is in the second stage E2, the pulse width of the enable signal transmitted by the first clock signal line CK and the pulse width of the enable signal transmitted by the second clock signal line XCK are both w2; where w1 > w2, so as to achieve t1 > t2.

[0102] Compared to the pulse width of the clock signal transmitted by the clock signal line when the pixel circuit PC is in the first stage E1, the pulse width of the clock signal transmitted by the clock signal line when the pixel circuit PC is in the second stage E2 is shorter. This means that the shift register S outputs the enable signal to the pixel circuit PC for a shorter duration in the second stage E2, that is, the bias duration of the pixel circuit PC is shorter. Therefore, the bias intensity of the pixel circuit PC can be adjusted by adjusting the pulse width of the clock signal, so that the light emission intensity of the light-emitting device L in the first stage E1 is the same as the light emission intensity in the second stage E2.

[0103] When the pixel circuit PC is in the first stage E1, the frequency of the enable signal transmitted by the first clock signal line CK and the frequency of the enable signal transmitted by the second clock signal line XCK are both f1; when the pixel circuit PC is in the second stage E2, the frequency of the enable signal transmitted by the first clock signal line CK and the frequency of the enable signal transmitted by the second clock signal line XCK are both f2; where f1 = f2.

[0104] During any working phase of one working cycle T of the pixel circuit PC, the frequency of the enable signal transmission on the two clock signal lines is the same, which means that the period of the enable signal transmission on the two clock signal lines is also the same. By adjusting the order and time interval of the enable signal transmission on the two clock signal lines, the duration of the enable signal output by the shift register S in the second phase E2 can be shortened, thereby shortening the bias duration of the pixel circuit PC, so that the luminous intensity of the light-emitting device L in the first phase E1 is the same as the luminous intensity in the second phase E2.

[0105] Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application.

[0106] like Figure 13 As shown, this application embodiment provides a display device 20, which includes the display panel 10 provided in the above embodiment. The display device 20 can be a mobile phone, or it can be an electronic device such as a computer or television.

[0107] The low-frequency display effect of the display device 20 provided in this application embodiment has been greatly improved.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Light-emitting devices; Multiple pixel circuits, the output terminals of which are electrically connected to the light-emitting device; The pixel circuit includes a first transistor; at least one operating cycle of the pixel circuit includes a first stage and at least one second stage, the second stage including a bias stage; Multiple cascaded shift registers, the output of which is electrically connected to the gate of the first transistor; In the first stage of the pixel circuit, the duration for which the output terminal of the shift register outputs the enable signal is t1; in the bias stage of the second stage of the pixel circuit, the duration for which the output terminal of the shift register outputs the enable signal is t2; t2 < t1, t1 > 0, t2 > 0. The input terminal of the first transistor is electrically connected to the data line, which is used to transmit data voltage in the first stage and to transmit a first bias voltage in the second stage. or; The input terminal of the first transistor is electrically connected to the reset signal line, and the output terminal of the first transistor is electrically connected to the light-emitting device. The reset signal line is used to transmit a reset voltage in the first stage and to transmit a second bias voltage in the second stage.

2. The display panel according to claim 1, characterized in that, The pixel circuit further includes a second transistor; of the first transistor and the second transistor, the input terminal of one is electrically connected to the data line, the input terminal of the other is electrically connected to the reset signal line, and the output terminal is electrically connected to the light-emitting device. The data line is used to transmit a data voltage in the first stage and a first bias voltage in the second stage, and the reset signal line is used to transmit a reset voltage in the first stage and a second bias voltage in the second stage. In the same pixel circuit, the gate of the first transistor and the gate of the second transistor are electrically connected to the output terminals of different stages of the shift register in the same shift register.

3. The display panel according to claim 1, characterized in that, 。 4. The display panel according to claim 3, characterized in that, t1≥16μs, 5μs≥t2≥2μs.

5. The display panel according to claim 1, characterized in that, The display panel further includes a first clock signal line and a second clock signal line; the shift register includes a first port and a second port; In the two shift registers of adjacent stages, the first port of one is electrically connected to the first clock signal line and the second port is electrically connected to the second clock signal line, while the first port of the other is electrically connected to the second clock signal line and the second port is electrically connected to the first clock signal line. Specifically, when the pixel circuit is in the first stage, the pulse width of the first clock signal line transmitting the enable signal and the pulse width of the second clock signal line transmitting the enable signal are both w1; when the pixel circuit is in the second stage, the pulse width of the first clock signal line transmitting the enable signal and the pulse width of the second clock signal line transmitting the enable signal are both w2, where w1 > w2.

6. The display panel according to claim 5, characterized in that, When the pixel circuit is in the first stage, the frequency of the enable signal transmitted by the first clock signal line and the frequency of the enable signal transmitted by the second clock signal line are both f1; when the pixel circuit is in the second stage, the frequency of the enable signal transmitted by the first clock signal line and the frequency of the enable signal transmitted by the second clock signal line are both f2, and f1=f2.

7. A display device, characterized in that, Includes the display panel as described in any one of claims 1-6.

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