Code compilation method and related device

Abstract

The present application provides a code compilation method and related devices, which are applied to the central processing unit of an electronic device, the electronic device includes a central processing unit and a parallel processor, the parallel processor includes a scalar instruction processing unit and a vector instruction processing unit, and the method includes: obtaining a target intermediate code to be compiled, the code type of the target intermediate code is a target type, and the target type is used to indicate an intermediate code whose code format is the same as the code format corresponding to any assembly language in a preset assembly language set; compiling the target intermediate code into a target instruction set that can be executed by a parallel processor. In this way, when developers are engaged in related development work on the above-mentioned parallel processor, they can use a simple and easy-to-understand intermediate code type as an intermediate representation of the compilation process, which reduces the development difficulty and promotes the development of software applications on the above-mentioned parallel processor to achieve a parallel processing process with faster processing speed and lower power consumption.

Description

Technical Field

[0001] The present application belongs to the general encoding, decoding or code conversion technology field of the new generation information technology industry, and specifically relates to a code compilation method and related devices. Background Art

[0002] In the parallel processing of data, the instruction set executed by the parallel processor contains both vector instructions related to data processing and scalar instructions unrelated to data processing. For traditional parallel processors (such as graphics processors GPU), they follow the Single Instruction Multiple Thread (SIMT) architecture to treat each instruction equally without distinguishing between vector instructions and scalar instructions in the instructions. In this way, scalar instructions will also be repeatedly executed in multiple threads, and since scalar instructions are unrelated to data processing, the repeated execution of scalar instructions is meaningless, resulting in the problem of wasted running time and power consumption in traditional parallel processors.

[0003] Currently, there is a new type of parallel processor that includes processing units that can execute scalar instructions and vector instructions respectively to achieve faster and lower power consumption parallel processing of data. However, due to the differences in hardware architecture, the compiler system for traditional parallel processors cannot be applied to this new type of parallel processor.

[0004] Traditional compiler systems, such as the LLVM (Low Level Virtual Machine) compiler system, compile source code into an intermediate representation (IR) code, such as LLVMIR, and then compile the intermediate representation code into machine code executable by a parallel processor. However, LLVM IR is a very complex machine abstraction level language. For developers, using this type of intermediate code is very difficult when performing related development work on the above-mentioned new parallel processors. Therefore, a compilation solution with simple intermediate codes and the ability to convert simple intermediate codes into instruction sets that can be executed by the above-mentioned new parallel processors is needed. Summary of the invention

[0005] The present application provides a code compilation method and related devices, in order to reduce the difficulty of developers in developing new parallel processors, so that electronic devices can achieve parallel processing with faster processing speed and lower power consumption.

[0006] In a first aspect, an embodiment of the present application provides a code compilation method, which is applied to a central processing unit of an electronic device, wherein the electronic device includes the central processing unit and a parallel processor, wherein the parallel processor includes a scalar instruction processing unit and a vector instruction processing unit group, and the method includes:

[0007] Obtaining a target intermediate code to be compiled, wherein the code type of the target intermediate code is a target type, and the target type is used to indicate an intermediate code having a code format identical to a code format corresponding to any one of the assembly languages ​​in a preset assembly language set;

[0008] The target intermediate code is compiled into a target instruction set that can be executed by the parallel processor, the target instruction set includes a target scalar instruction set and a target vector instruction set, the target scalar instruction set includes a plurality of scalar instructions that can be executed by the scalar instruction processing unit, the scalar instructions refer to instructions that are not related to data processing, and the target vector instruction set includes a plurality of vector instructions that can be executed by the vector instruction processing unit group, the vector instructions refer to instructions related to data processing.

[0009] In a second aspect, an embodiment of the present application provides a code compilation device, which is applied to a central processor of an electronic device, wherein the electronic device includes the central processor and a parallel processor, wherein the parallel processor includes a scalar instruction processing unit and a vector instruction processing unit group, and the device includes:

[0010] An acquisition unit, used for acquiring a target intermediate code to be compiled, wherein a code type of the target intermediate code is a target type, and the target type is used for indicating an intermediate code having a code format identical to a code format corresponding to any one of the assembly languages ​​in a preset assembly language set;

[0011] A compiling unit, used for compiling the target intermediate code into a target instruction set executable by the parallel processor, wherein the target instruction set includes a target scalar instruction set and a target vector instruction set, wherein the target scalar instruction set includes a plurality of scalar instructions executable by the scalar instruction processing unit, wherein the scalar instructions are instructions unrelated to data processing, and the target vector instruction set includes a plurality of vector instructions executable by the vector instruction processing unit group, wherein the vector instructions are instructions related to data processing.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising a central processing unit, a parallel processor, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the central processing unit, and the program includes instructions for executing the steps in the first aspect of the embodiment of the present application.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program / instruction stored thereon, which, when executed by a central processing unit, implements the steps in the first aspect of the embodiment of the present application.

[0014] It can be seen that in the embodiment of the present application, the central processing unit of the electronic device first obtains the target intermediate code of the target type of the code type to be compiled, and the target type is used to indicate the intermediate code whose code format is the same as the code format corresponding to any one of the assembly languages ​​in the preset assembly language set, and then compiles the target intermediate code into a target instruction set that can be executed by the parallel processor. In this way, when the developer is engaged in the relevant development work of the above-mentioned parallel processor, he can use a simple and easy-to-understand intermediate code type as an intermediate representation of the compilation process, which reduces the development difficulty and promotes the development of software applications on the above-mentioned parallel processor to achieve a parallel processing process with faster processing speed and lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 is a structural block diagram of an electronic device provided in an embodiment of the present application;

[0017] Figure 2 It is a flowchart of a code compilation method provided in an embodiment of the present application;

[0018] Figure 3 It is a block diagram of the functional units of a code compilation device provided in an embodiment of the present application;

[0019] Figure 4 This is another structural block diagram of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0022] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] See also Figure 1 , Figure 1 It is a structural block diagram of an electronic device provided in an embodiment of the present application. As shown in the figure, the electronic device 10 includes a central processing unit 11 and a parallel processor 12, and the central processing unit 11 and the parallel processor 12 are connected to realize data transmission. Among them, the parallel processor 12 includes a scalar instruction processing unit 121 and a vector instruction processing unit group 122, and the scalar instruction processing unit 121 and the vector instruction processing unit group 122 are connected to realize data transmission. The parallel processor 12 can specifically be a reconfigurable parallel processor RPP (Reconfigurable Parallel Processing), the scalar instruction processing unit 121 can specifically be a processor core in the RPP, and the vector instruction processing unit group 122 can specifically be another processor core in the RPP, which can include multiple vector instruction processing units. The scalar instruction processing unit 121 can execute scalar instructions at a higher speed and without repetition, and can also harden or configure vector instructions into the vector instruction processing unit group 122. After the vector instructions are hardened or configured into the vector instruction processing unit group 122, the multiple vector instruction processing units simultaneously process data in parallel to achieve higher speed and lower power consumption parallel processing.

[0024] A code compilation method provided by an embodiment of the present application is introduced below.

[0025] See also Figure 2 , Figure 2 is a flowchart of a code compilation method provided in an embodiment of the present application, and the method is applied to Figure 1In the central processing unit 11 shown, Figure 2 As shown, the method includes:

[0026] Step 201, obtaining the target intermediate code to be compiled.

[0027] Among them, the code type of the target intermediate code is the target type, and the target type is used to indicate an intermediate code whose code format is the same as the code format corresponding to any one of the preset assembly languages. The assembly languages ​​in the preset assembly language set are a variety of assembly languages ​​commonly used in the computer field, such as C language, python, etc. These assembly languages ​​are in line with people's code writing habits, so they are simple and easy to understand for developers. In this example, the code format of the target intermediate code is the same as the code format corresponding to any of the above-mentioned assembly languages. For example, the target intermediate code can be an intermediate code in the code format of C language.

[0028] In a possible example, the target intermediate code is an intermediate code whose code type is the target type and which is directly input by the user on the electronic device.

[0029] Among them, since the code type of the target intermediate code is the target type, it is simple and easy to understand and write for developers. Therefore, in this example, the developer can manually write the target intermediate code and input the written target intermediate code into the electronic device, which will be obtained by the central processing unit and perform subsequent compilation work.

[0030] It can be seen that in this example, the developer / user can manually write the target intermediate code and hand it over to the central processing unit for subsequent compilation. This is very necessary for staff who prefer assembly or scenarios where only assembly can be used. It broadens the application scenarios and reduces the difficulty of development.

[0031] In a possible example, the target intermediate code is an intermediate code of the target type obtained after compiling source code directly input by the user on the electronic device.

[0032] The source code may specifically be a source code written using a Computer Unified Device Architecture (CUDA) model, and the compilation process of the source code may specifically be a front-end compilation stage executed by a central processing unit.

[0033] Exemplarily, the parallel processor involved in the embodiment of the present application is a reconfigurable parallel processor RPP, and the software system used to implement the compilation method provided in the embodiment of the present application can be called an RPP compilation system. The RPP compilation system is developed and modified on the basis of the LLVM compiler system, so the RPP compiler system also conforms to the characteristics of the LLVM compiler system in structure, that is, it includes two stages: front-end compilation and back-end compilation. Among them, the front-end compilation stage is used to convert the source code written by the developer into an intermediate code, and the back-end compilation stage is used to convert the intermediate code into an instruction set executable by the target device, that is, machine code.

[0034] In the existing LLVM compiler system, the intermediate code obtained after the source code passes through the front-end compilation stage is LLVM IR, which is an abstract intermediate language. For developers who are not familiar with the LLVM architecture, it is very difficult to use this type of intermediate code when performing relevant development work on RPP. In the embodiment of the present application, the front-end compilation stage is responsible for the RPP front-end compiler developed and modified based on the LLVM compiler system. The RPP front-end compiler can convert the source code written by the developer into an intermediate code with a target code type, which is called RPP intermediate code. The code format used by the RPP intermediate code is the code format corresponding to a variety of assembly languages ​​commonly used by developers when writing source code, such as C language, python, etc., which is easy to understand for developers.

[0035] It can be seen that in this example, for the general scenario where the developer / user directly writes the source code, the central processing unit can execute the front-end compilation process suitable for the new parallel processor on the source code written by the developer / user, so as to convert the source code into a simple and easy-to-understand target intermediate code, thereby reducing the difficulty of development.

[0036] Step 202: compile the target intermediate code into a target instruction set executable by the parallel processor.

[0037] Among them, the target instruction set includes a target scalar instruction set and a target vector instruction set, the target scalar instruction set includes multiple scalar instructions that can be executed by the scalar instruction processing unit, and the scalar instructions refer to instructions that are not related to data processing. The target vector instruction set includes multiple vector instructions that can be executed by the vector instruction processing unit group, and the vector instructions refer to instructions related to data processing.

[0038] Taking the traditional compiler system as the LLVM compiler system, and the software system corresponding to the compilation method provided in the embodiment of the present application as the RPP compilation system as an example, the RPP compilation system continues the advantages of the LLVM compiler system, and can separate the front-end compilation stage and the back-end compilation stage, so that each stage can be executed on different computers. In one possible example, the RPP front-end compilation stage can be performed in the developer computer to convert the source code into the target intermediate code, and then the developer computer sends the target intermediate code to the user computer, and the user computer completes the RPP back-end compilation stage to obtain the target instruction set that can be executed by the user computer. In this way, the source code can be avoided from being exposed to the user computer while the instructions can be normally executed by the user computer. It can be understood that the above-mentioned developer computer and user computer can both be electronic devices involved in the embodiments of the present application.

[0039] In one possible example, the code format of the target intermediate code does not conform to the static single assignment format, and compiling the target intermediate code into a target instruction set that can be executed by the parallel processor includes: performing a code format conversion operation on the target intermediate code to obtain a standard intermediate code, the code format of the standard intermediate code conforms to the static single assignment format; and compiling the standard intermediate code into the target instruction set.

[0040] Among them, the Static Single Assignment (SSA) format means that the variables in the intermediate code can only be assigned once, and the code format of the target intermediate code is not in SSA format, because it is very convenient to write manually, and a register can be assigned multiple times, which adapts to the developer's thinking logic. According to the characteristics of the LLVM backend compiler, when the intermediate code conforms to the SSA format, it can enter the LLVM backend compilation process, and the RPP backend compiler is developed and modified based on the LLVM backend compiler. Therefore, the target intermediate code needs to conform to the SSA format before the subsequent compilation process can proceed. In this example, the central processing unit can convert the target intermediate code that does not conform to the SSA format into a standard intermediate code that conforms to the SSA format. In this way, when developers write intermediate codes, they can still write them in a simple way, and the format conversion operation can be handed over to the central processing unit for execution, which reduces the difficulty of development.

[0041] It can be seen that in this example, the central processing unit of the electronic device can convert the target intermediate code that does not conform to the static single assignment format into a standard intermediate code that conforms to the static single assignment format, ensuring the normal progress of the subsequent compilation process, and also allowing developers to write intermediate codes in a simpler way, reducing the difficulty of development.

[0042] In a possible example, before performing a code format conversion operation on the target intermediate code to obtain a standard intermediate code, the method further includes: parsing the target intermediate code to convert the target intermediate code into memory structured data.

[0043] Among them, the intermediate code obtained through the front-end compilation stage or the intermediate code directly written by the developer is still in text format, so the intermediate code in text format needs to be parsed into memory structured data, specifically, it can be parsed into data that conforms to the syntax tree structure, so that the code in text format can be executed by the processor for subsequent operations. It can be understood that in this example, the central processing unit performs a code format conversion operation on the target intermediate code, which is essentially processing the memory structured data corresponding to the target intermediate code to change the format of the target intermediate code.

[0044] In one possible example, compiling the standard intermediate code into the target instruction set includes: marking the scalar intermediate code and the vector intermediate code in the standard intermediate code; converting the scalar intermediate code into a scalar instruction set to be optimized, and converting the vector intermediate code into a vector instruction set to be optimized, to obtain a scalar-vector mixed instruction set to be optimized; and compiling the scalar-vector mixed instruction set to be optimized into the target instruction set.

[0045] Among them, since the code format of the target intermediate code is in line with the developer's assembly habits, when writing the code, the developer only needs to assume that the target intermediate code is executed in a processing unit (such as a scalar instruction processing unit), and at this time, only another instruction hidden therein (such as a vector instruction) needs to be marked. The marking of the scalar intermediate code and the vector intermediate code in the standard intermediate code can be specifically by analyzing whether the content of each instruction in the standard intermediate code is related to data processing, marking the instructions related to data processing, that is, the vector intermediate code, and the remaining unmarked instructions are the scalar intermediate code.

[0046] Among them, the process of converting the scalar intermediate code into the scalar instruction set to be optimized, and converting the vector intermediate code into the vector instruction set to be optimized is called instruction selection. In the traditional LLVM back-end compilation process, since the code input to the instruction selection stage is LLVM IR, which is a complex language, it is necessary to use a preset instruction selection template to realize the instruction selection of the intermediate code to the instruction set to be optimized. In the embodiment of the present application, the code input to the instruction selection stage is an intermediate code that conforms to the commonly used assembly language, is simple and easy to understand, and is marked with scalar types and vector types. Therefore, when selecting instructions, the central processing unit does not need to use an instruction selection template, but can directly convert the scalar intermediate code into the scalar instruction set to be optimized based on the above-mentioned commonly used assembly language and commonly used instruction selection methods, and convert the vector intermediate code into the vector instruction set to be optimized. Among them, this step can be automatically executed by the central processing unit through a program, or it can be manually converted by the developer. For example, after obtaining the scalar intermediate code and the vector intermediate code, the developer can translate each type of intermediate code into the corresponding type of instruction set by himself, and then re-input the translated instruction set into the electronic device to execute the subsequent compilation process. Due to the superiority of the intermediate code format, this process is not difficult for professional developers, which is called manual instruction selection.

[0047] Among them, when converting the vector intermediate code into the vector instruction set to be optimized, the conditional jump instruction in the vector instruction selects a pseudo instruction, but the vector instruction is executed in the vector instruction processing unit group, and the multiple vector instruction processing units in the vector instruction processing unit group correspond to multiple synchronous threads that rely on the SIMT mechanism, and it is impossible to implement conditional jumps, because the running conditions of different threads are not the same, resulting in some threads needing to jump and some threads not needing to jump, which violates the principle of SIMT. Therefore, in this example, when selecting the conditional jump instruction in the vector instruction, the Predicate mechanism can be used to achieve the same semantic effect without conditional jumps, thereby solving the above problem.

[0048] It can be seen that in this example, the central processing unit of the electronic device can mark both the scalar intermediate code and the vector intermediate code in the standard intermediate code, and select each type of intermediate code as the corresponding instruction set to obtain the scalar vector mixed instruction set to be optimized and enter the subsequent compilation process, and finally obtain the target instruction set that can be executed by the new parallel processor. At the same time, due to the superiority of the code format of the target intermediate code, developers can manually perform the instruction selection stage, which expands the scope of application and improves the flexibility of the compilation system.

[0049] In a possible example, compiling the scalar-vector hybrid instruction set to be optimized into the target instruction set includes: performing register allocation operations on multiple scalar instructions to be optimized in the scalar instruction set to be optimized according to the scalar physical registers corresponding to the scalar instruction processing unit to obtain a reference scalar instruction set; performing register allocation operations on multiple vector instructions to be optimized in the vector instruction set to be optimized according to the vector physical registers corresponding to the vector instruction processing unit group to obtain a reference vector instruction set; and compiling a reference scalar-vector hybrid instruction set composed of the reference scalar instruction set and the reference vector instruction set into the target instruction set.

[0050] Among them, the scalar instruction processing unit and the vector instruction processing unit group have their own physical registers and instruction sets. The above register allocation operation is actually the process of converting the virtual registers in the instruction into the corresponding physical registers, so that the instruction is also converted, that is, from the instruction set to be optimized to the reference instruction set. According to the traditional LLVM backend compilation process, LLVM IR needs to go through multiple optimization stages (pass) after instruction selection and before register allocation. In this example, the scalar-vector mixed instruction set to be optimized obtained after instruction selection has met the conditions for physical register allocation in the form of instructions. Therefore, after instruction selection, the central processing unit can directly perform register allocation operations on the instruction set, eliminating multiple optimization stages in the middle.

[0051] It can be seen that in this example, after obtaining the scalar-vector hybrid instruction set to be optimized, the central processing unit of the electronic device can directly perform corresponding types of register allocation on the scalar instruction set and the vector instruction set respectively, and convert the virtual registers in the instructions into physical registers to establish a correspondence between the instructions and the hardware. Compared with the traditional back-end compilation process, it can save multiple optimization stages while building a compilation solution suitable for new parallel processors, thereby improving compilation efficiency.

[0052] In a possible example, the register allocation operation is performed on multiple scalar instructions to be optimized in the scalar instruction set to be optimized according to the scalar physical registers corresponding to the scalar instruction processing unit to obtain a reference scalar instruction set, including: allocating a first scalar instruction set in the scalar instruction set to be optimized to the scalar physical registers according to a preset scalar register allocation algorithm to obtain a first reference scalar instruction set, the number of scalar virtual registers corresponding to the first scalar instruction set is the same as the number of scalar physical registers; allocating a second scalar instruction set in the scalar instruction set to be optimized to the stack space corresponding to the scalar instruction processing unit to obtain a second reference scalar instruction set, the second scalar instruction set refers to an instruction set composed of scalar instructions in the scalar instruction set to be optimized except the first scalar instruction set; and determining the reference scalar instruction set according to the first reference scalar instruction set and the second reference scalar instruction set.

[0053] Among them, the preset scalar register allocation algorithm can be preset by the developer based on the importance of different scalar instructions in the scalar instruction set. For example, each scalar instruction in the scalar instruction set is sorted according to the importance, and the multiple scalar instructions in the front order form the first scalar instruction set, wherein the importance can refer to the number of times or frequency that the electronic device calls the instruction. If there are other scalar instructions in the scalar instruction set, that is, the second scalar instruction set, it indicates that the scalar physical registers of the electronic device are not enough to be allocated, and at this time, the second scalar instruction set needs to be allocated to the stack space corresponding to the scalar instruction processing unit. It should be noted that, under the traditional hardware architecture, since there is no need to distinguish between scalar instructions and vector instructions in instructions, the traditional stack space is also a whole. When there are not enough registers to allocate, the remaining instructions will be allocated to this overall stack space, but it is obvious that this method is not suitable for the new parallel processor architecture involved in this application; therefore, similar to the distinction between scalar physical registers and vector physical registers, in the embodiment of the present application, it is necessary to divide the above-mentioned stack space into stack space corresponding to the scalar instruction processing unit and stack space corresponding to the vector instruction processing unit group, and allocate instructions that are not allocated to physical registers to the corresponding stack space to ensure the normal operation of the compiler.

[0054] It can be seen that in this example, when there are not enough scalar physical registers to allocate, the central processing unit can allocate the remaining scalar instruction sets to the stack space corresponding to the scalar instruction processing unit to establish the correspondence between all scalar instructions and hardware to ensure the normal operation of the compiler.

[0055] In a possible example, the register allocation operation is performed on multiple vector instructions to be optimized in the vector instruction set to be optimized according to the vector physical registers corresponding to the vector instruction processing unit group to obtain a reference vector instruction set, including: allocating a first vector instruction set in the vector instruction set to be optimized to the vector physical registers according to a preset vector register allocation algorithm to obtain a first reference vector instruction set, the number of vector virtual registers corresponding to the first vector instruction set is the same as the number of vector physical registers; allocating a second vector instruction set in the vector instruction set to be optimized to the stack space corresponding to the vector instruction processing unit group to obtain a second reference vector instruction set, the second vector instruction set refers to an instruction set composed of vector instructions in the vector instruction set to be optimized except the first vector instruction set; and determining the reference vector instruction set according to the first reference vector instruction set and the second reference vector instruction set.

[0056] Among them, similar to the allocation method of the above-mentioned scalar physical registers, when there are not enough vector physical registers to allocate, the central processing unit will allocate the remaining vector instructions to the stack space corresponding to the vector instruction processing unit group to establish the correspondence between all vector instructions and hardware to ensure the normal operation of the compiler.

[0057] It can be seen that in the embodiment of the present application, the central processing unit of the electronic device first obtains the target intermediate code of the target type of the code type to be compiled, and the target type is used to indicate the intermediate code whose code format is the same as the code format corresponding to any one of the assembly languages ​​in the preset assembly language set, and then compiles the target intermediate code into a target instruction set that can be executed by the parallel processor. In this way, when the developer is engaged in the relevant development work of the above-mentioned parallel processor, he can use a simple and easy-to-understand intermediate code type as an intermediate representation of the compilation process, which reduces the development difficulty and promotes the development of software applications on the above-mentioned parallel processor to achieve a parallel processing process with faster processing speed and lower power consumption.

[0058] In accordance with the above-mentioned embodiments, please refer to Figure 3 , Figure 3 is a functional unit block diagram of a code compilation device provided in an embodiment of the present application, wherein the device is applied to Figure 1In the central processing unit 11 shown, the code compiling device 30 includes: an acquisition unit 301, used to acquire a target intermediate code to be compiled, the code type of the target intermediate code is a target type, and the target type is used to indicate an intermediate code whose code format is the same as the code format corresponding to any assembly language in a preset assembly language set; a compilation unit 302, used to compile the target intermediate code into a target instruction set that can be executed by the parallel processor, the target instruction set includes a target scalar instruction set and a target vector instruction set, the target scalar instruction set includes a plurality of scalar instructions that can be executed by the scalar instruction processing unit, the scalar instruction refers to an instruction that is not related to data processing, and the target vector instruction set includes a plurality of vector instructions that can be executed by the vector instruction processing unit group, and the vector instruction refers to an instruction related to data processing.

[0059] In one possible example, when the code format of the target intermediate code does not conform to the static single assignment format, in terms of compiling the target intermediate code into a target instruction set executable by the parallel processor, the compilation unit 302 is specifically used to: perform a code format conversion operation on the target intermediate code to obtain a standard intermediate code, the code format of the standard intermediate code conforms to the static single assignment format; and compile the standard intermediate code into the target instruction set.

[0060] In a possible example, in terms of compiling the standard intermediate code into the target instruction set, the compilation unit 302 is specifically used to: mark the scalar intermediate code and the vector intermediate code in the standard intermediate code; convert the scalar intermediate code into a scalar instruction set to be optimized, and convert the vector intermediate code into a vector instruction set to be optimized, to obtain a scalar-vector mixed instruction set to be optimized; and compile the scalar-vector mixed instruction set to be optimized into the target instruction set.

[0061] In a possible example, in terms of compiling the scalar-vector hybrid instruction set to be optimized into the target instruction set, the compiling unit 302 is specifically used to: perform register allocation operations on multiple scalar instructions to be optimized in the scalar instruction set to be optimized according to the scalar physical registers corresponding to the scalar instruction processing unit to obtain a reference scalar instruction set; perform register allocation operations on multiple vector instructions to be optimized in the vector instruction set to be optimized according to the vector physical registers corresponding to the vector instruction processing unit group to obtain a reference vector instruction set; and compile a reference scalar-vector hybrid instruction set composed of the reference scalar instruction set and the reference vector instruction set into the target instruction set.

[0062] In one possible example, in terms of performing register allocation operations on multiple scalar instructions to be optimized in the scalar instruction set to be optimized according to the scalar physical registers corresponding to the scalar instruction processing unit to obtain a reference scalar instruction set, the compilation unit 302 is specifically used to: allocate a first scalar instruction set in the scalar instruction set to be optimized to the scalar physical registers according to a preset scalar register allocation algorithm to obtain a first reference scalar instruction set, wherein the number of scalar virtual registers corresponding to the first scalar instruction set is the same as the number of scalar physical registers; allocate a second scalar instruction set in the scalar instruction set to be optimized to the stack space corresponding to the scalar instruction processing unit to obtain a second reference scalar instruction set, wherein the second scalar instruction set refers to an instruction set composed of scalar instructions in the scalar instruction set to be optimized except the first scalar instruction set; and determine the reference scalar instruction set according to the first reference scalar instruction set and the second reference scalar instruction set.

[0063] In a possible example, the target intermediate code is an intermediate code whose code type is the target type and which is directly input by the user on the electronic device.

[0064] In a possible example, the target intermediate code is an intermediate code of the target type obtained after compiling source code directly input by the user on the electronic device.

[0065] It can be understood that since the method embodiment and the device embodiment are different presentation forms of the same technical concept, the content of the method embodiment part in this application should be synchronously adapted to the device embodiment part and will not be repeated here.

[0066] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0067] Figure 4 is another structural block diagram of the electronic device provided in the embodiment of the present application. Figure 4 As shown, the electronic device 40 may include one or more of the following components: a central processor 401, and a memory 402 coupled to the central processor 401, wherein the memory 402 may store one or more computer programs, and the one or more computer programs may be configured to implement the methods described in the above embodiments when executed by the central processor 401. The electronic device 40 may be the electronic device 10 in the above embodiment, and the central processor 401 may be the central processor 11 in the above embodiment.

[0068] The central processing unit 401 utilizes various interfaces and lines to connect various parts within the entire electronic device 40, and performs various functions of the electronic device 40 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 402, and calling data stored in the memory 402.

[0069] The memory 402 may include a random access memory (RAM) or a read-only memory (ROM). The memory 402 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the above-mentioned various method embodiments, etc. The data storage area may also store data created by the electronic device 40 during use, etc. It is understandable that the electronic device 40 may include more or fewer structural elements than those in the above-mentioned structural block diagram, which is not limited here.

[0070] An embodiment of the present application also provides a computer storage medium, on which a computer program / instruction is stored. When the computer program / instruction is executed by a central processing unit, part or all of the steps of any method recorded in the above method embodiment are implemented.

[0071] An embodiment of the present application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0072] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0073] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0074] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0075] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0076] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a volatile memory or a non-volatile memory. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM) and direct RAM bus random access memory (DR RAM), among other media that can store program code.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present invention, and can make various changes and modifications, including the combination of the above-mentioned different functions and implementation steps, including software and hardware implementation methods, all of which are within the scope of protection of the present invention.

Claims

1. A code compilation method, applied to a central processing unit of an electronic device, wherein the electronic device comprises the central processing unit and a parallel processor, wherein the parallel processor comprises a scalar instruction processing unit and a vector instruction processing unit group, wherein the method comprises: Obtaining a target intermediate code to be compiled, wherein the code type of the target intermediate code is a target type, and the target type is used to indicate an intermediate code having a code format identical to a code format corresponding to any one of the assembly languages ​​in a preset assembly language set; Compiling the target intermediate code into a target instruction set executable by the parallel processor, the target instruction set comprising a target scalar instruction set and a target vector instruction set, the target scalar instruction set comprising a plurality of scalar instructions executable by the scalar instruction processing unit, the scalar instructions being instructions unrelated to data processing, and the target vector instruction set comprising a plurality of vector instructions executable by the vector instruction processing unit group, the vector instructions being instructions related to data processing; The assembly languages ​​in the preset assembly language set are multiple assembly languages ​​commonly used in the computer field, the target intermediate code is an intermediate code of the target type directly input by the user on the electronic device, and the code format of the target intermediate code does not conform to the static single assignment format; Among them, compiling the target intermediate code into a target instruction set executable by the parallel processor includes: performing a code format conversion operation on the target intermediate code to obtain a standard intermediate code, and the code format of the standard intermediate code conforms to the static single assignment format; marking the scalar intermediate code and the vector intermediate code in the standard intermediate code; converting the scalar intermediate code into a scalar instruction set to be optimized, and converting the vector intermediate code into a vector instruction set to be optimized, to obtain a scalar-vector hybrid instruction set to be optimized; and compiling the scalar-vector hybrid instruction set to be optimized into a target instruction set.

2. The method according to claim 1, characterized in that: The compiling the scalar-vector hybrid instruction set to be optimized into the target instruction set includes: Performing register allocation operations on a plurality of scalar instructions to be optimized in the scalar instruction set to be optimized according to the scalar physical registers corresponding to the scalar instruction processing unit to obtain a reference scalar instruction set; Performing register allocation operations on a plurality of vector instructions to be optimized in the vector instruction set to be optimized according to the vector physical registers corresponding to the vector instruction processing unit group to obtain a reference vector instruction set; A reference scalar-vector hybrid instruction set consisting of the reference scalar instruction set and the reference vector instruction set is compiled into the target instruction set.

3. The method according to claim 2, characterized in that: The step of performing register allocation operations on a plurality of scalar instructions to be optimized in the scalar instruction set to be optimized according to the scalar physical register corresponding to the scalar instruction processing unit to obtain a reference scalar instruction set includes: Allocating a first scalar instruction set in the scalar instruction set to be optimized to the scalar physical registers according to a preset scalar register allocation algorithm to obtain a first reference scalar instruction set, wherein the number of scalar virtual registers corresponding to the first scalar instruction set is the same as the number of scalar physical registers; Allocating a second scalar instruction set in the scalar instruction set to be optimized to a stack space corresponding to the scalar instruction processing unit to obtain a second reference scalar instruction set, wherein the second scalar instruction set refers to an instruction set consisting of scalar instructions in the scalar instruction set to be optimized except the first scalar instruction set; The reference scalar instruction set is determined according to the first reference scalar instruction set and the second reference scalar instruction set.

4. The method according to claim 1, characterized in that: The target intermediate code is an intermediate code of the target type obtained after compiling the source code directly input by the user on the electronic device.

5. A code compiling device, applied to a central processing unit of an electronic device, the electronic device comprising the central processing unit and a parallel processor, the parallel processor comprising a scalar instruction processing unit and a vector instruction processing unit group, the device comprising: An acquisition unit, used for acquiring a target intermediate code to be compiled, wherein a code type of the target intermediate code is a target type, and the target type is used for indicating an intermediate code having a code format identical to a code format corresponding to any one of the assembly languages ​​in a preset assembly language set; a compiling unit, configured to compile the target intermediate code into a target instruction set executable by the parallel processor, the target instruction set comprising a target scalar instruction set and a target vector instruction set, the target scalar instruction set comprising a plurality of scalar instructions executable by the scalar instruction processing unit, the scalar instructions being instructions unrelated to data processing, and the target vector instruction set comprising a plurality of vector instructions executable by the vector instruction processing unit group, the vector instructions being instructions related to data processing; The assembly languages ​​in the preset assembly language set are multiple assembly languages ​​commonly used in the computer field, the target intermediate code is an intermediate code of the target type directly input by the user on the electronic device, and the code format of the target intermediate code does not conform to the static single assignment format; Among them, compiling the target intermediate code into a target instruction set executable by the parallel processor includes: performing a code format conversion operation on the target intermediate code to obtain a standard intermediate code, and the code format of the standard intermediate code conforms to the static single assignment format; marking the scalar intermediate code and the vector intermediate code in the standard intermediate code; converting the scalar intermediate code into a scalar instruction set to be optimized, and converting the vector intermediate code into a vector instruction set to be optimized, to obtain a scalar-vector hybrid instruction set to be optimized; and compiling the scalar-vector hybrid instruction set to be optimized into a target instruction set.

6. An electronic device, characterized in that: The method comprises a central processing unit, a parallel processor, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the central processing unit, and the programs include instructions for executing the steps in the method according to any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a central processing unit, the steps of the method according to any one of claims 1 to 4 are implemented.

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