Low on-resistance high robustness bidirectional thyristor electrostatic protection device and manufacturing method

Abstract

The embodiment of the application provides a low conduction resistance high robustness bidirectional thyristor electrostatic protection device and a manufacturing method, which comprises a P-type substrate, an N-type buried layer, a P-type well, a P-type shallow well and the like; the second N+ injection area and the third N+ injection area are directly connected through a wire, and a P-type shallow well PB with high concentration is arranged directly below the second N+ injection area and the third N+ injection area, which can play an important role in reducing the forward and reverse conduction resistance and trigger voltage of the device; the first P+ injection area and the first N+ injection area are connected together and serve as an anode of the device, and the second P+ injection area and the fourth N+ injection area are connected together and serve as a cathode of the device, so that the device can effectively protect the core circuit of the chip and avoid the risk of latching in the case of significantly reducing the conduction resistance of the device. The device can be applied to ESD protection of an I / O port with a working voltage of-5.5-5.5V.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and more particularly to a low on-resistance, high-robustness, bidirectional thyristor ESD protection device and its manufacturing method. Background Technology

[0002] With advancements in semiconductor manufacturing processes, ESD-induced failures of integrated circuit chips and electronic products have become increasingly severe. ESD protection for electronic products and integrated circuit chips has become one of the major challenges faced by product engineers.

[0003] Compared to other ESD devices, traditional silicon controlled rectifiers (SCRs) have advantages such as a dual-conductance modulation mechanism, high discharge efficiency per unit area, small parasitic capacitance per unit area, and the ability to achieve very high robustness with a small area. However, traditional SCRs have drawbacks such as excessively high trigger voltage and excessively low sustaining voltage after triggering. Excessively high trigger voltage can cause the protection device to fail to protect the core circuit in time, while excessively low sustaining voltage can cause latch-up, rendering the ESD protection device ineffective and failing to guarantee the integrity of I / O port signal transmission.

[0004] Bidirectional thyristor devices are an improvement upon traditional thyristors, featuring a symmetrical structural layout. Their working principle is the same as that of traditional unidirectional thyristors, clamping voltage in both forward and reverse directions. A cross-sectional diagram of a traditional bidirectional thyristor electrostatic discharge (ESD) device is shown below. Figure 1 Its equivalent circuit diagram is shown in Figure 2When an ESD pulse is applied to the anode of a bidirectional SCR, the N-type deep well and the third P+ injection region form a reverse-biased PN junction. When this pulse voltage exceeds the avalanche breakdown voltage of this PN junction, a large avalanche current is generated inside the device. The current flows through the parasitic resistance of the second P-well to the other end, the cathode. When the voltage across this parasitic well resistor exceeds the forward conduction voltage of the vertical NPN transistor, this transistor turns on. After this transistor turns on, it provides base current to the lateral PNP transistor, and the lateral PNP transistor, when also turned on, also provides base current to the vertical NPN transistor, forming a positive feedback loop. When both parasitic transistors are fully turned on, the low-resistance SCR path also fully opens and participates in discharging the ESD current. The bidirectional SCR has a symmetrical structure. When an ESD pulse occurs at the cathode, the PN junction formed by the N-type deep well and the second P+ injection region undergoes avalanche breakdown, causing the PNP transistor and the NPN transistor to conduct sequentially to discharge static electricity. However, traditional SCRs have drawbacks such as high trigger voltage, high on-resistance, and low sustaining voltage. High trigger voltage and high on-resistance can cause the device to easily exceed the design window, while low sustaining voltage can easily cause latch-up. Therefore, it is necessary to reduce the trigger voltage to ensure that the device can turn on the protection core circuit in time when ESD current arrives, and at the same time increase the sustaining voltage of the bidirectional thyristor to avoid latch-up. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a simple, low-on-resistance, highly robust bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, which is applied to ESD protection design of I / O ports with operating voltages of -5.5 to 5.5V.

[0006] To achieve the above objectives, the technical solution of this invention is implemented as follows:

[0007] This invention provides a low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device, comprising a P-type substrate; an N-type buried layer in the P-type substrate; an N-type well above and in the middle of the N-type buried layer; a first P-well on the left side of the N-type buried layer and a second P-well on the right side of the N-type buried layer; the first P-well contains a first P+ injection region, a first N+ injection region, and a second N+ injection region, wherein the first P+ injection region is located to the left of the first P-well, the first N+ injection region is located to the right of the first P+ injection region and is attached to it, and the second N+ injection region is located to the right of the first N+ injection region.

[0008] The second P-well contains a second P+ injection region, a third N+ injection region, and a fourth N+ injection region. The second P+ injection region is located to the right of the second P-well, the fourth N+ injection region is located to the left of the second P+ injection region and is attached to it, and the third N+ injection region is located to the left of the second N+ injection region. An N-type well is provided between the first P-well and the second P-well. A floating N+ injection region is provided in the middle of the N-type well. At the same time, a second P-type shallow well PB and a third P-type shallow well PB are respectively arranged across the middle of the first P-well, the N-type well, and the second P-well. A first P-type shallow well PB and a fourth P-type shallow well PB are respectively provided directly below the second N+ injection region and the third N+ injection region. A first high-voltage N-well and a second high-voltage N-well are respectively provided on the left and right sides above the N-type buried layer. The first P+ injection region and the first N+ injection region are connected together and serve as the anode of the device, and the second P+ injection region and the fourth N+ injection region are connected together and serve as the cathode of the device.

[0009] Preferably, a first field oxygen isolation region is provided between the left side of the first P+ implantation region and the left edge of the P-type substrate; the right side of the first P+ implantation region is connected to the left side of the first N+ implantation region; a second field oxygen isolation region is provided between the right side of the first N+ implantation region and the left side of the second N+ implantation region; the left side of the second P+ implantation region is connected to the right side of the fourth N+ implantation region; a fifth field oxygen isolation region is provided between the left side of the fourth N+ implantation region and the right side of the third N+ implantation region; a third field oxygen isolation region is provided between the right side of the second N+ implantation region and the left side of the second P-type shallow well PB; a fourth field oxygen isolation region is provided between the left side of the third N+ implantation region and the right side of the third P-type shallow well PB; and a sixth field oxygen isolation region is provided between the right side of the second P+ implantation region and the right edge of the P-type substrate.

[0010] Preferably, the left portion of the first field oxygen isolation region is located on the surface of the P-type substrate, and the right portion of the first field oxygen isolation region is located on the surface of the first P-well; the left portion of the sixth field oxygen isolation region is located on the surface of the second P-well, and the right portion of the sixth field oxygen isolation region is located on the surface of the P-type substrate; the second field oxygen isolation region and the third field oxygen isolation region are located on the surface of the first P-well, and the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the second P-well.

[0011] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N+ injection region, the first P-well, and the N-type well constitute a vertical NPN transistor, the first P-well, the N-type well, and the second P-well constitute a horizontal PNP transistor structure, the second N+ injection region, the second P-well, and the N-type well constitute a vertical NPN transistor, and the first P-well, the N-type buried layer, and the second P-well constitute a horizontal PNP transistor.

[0012] Preferably, when a high-voltage ESD pulse reaches the anode of the device, the cathode is connected to a low potential. The ESD current flows along the P+ injection region into the first P-well, the first P-type shallow well PB, the second N+ injection region, the third N+ injection region, the fourth P-type shallow well PB, the second P-well, and then back to the second P+ injection region. When the ESD current increases to a certain value, the reverse PN junction formed by the third N+ injection region and the fourth P-type shallow well PB undergoes avalanche breakdown. The ESD current flows into the second P-well in large quantities through the low-resistance metal wire path between the second N+ injection region and the third N+ injection region, forming a voltage drop across the equivalent resistance of the second P-well. When the voltage drop reaches 0.7V, the right vertical NPN transistor turns on and provides base current to the left horizontal PNP transistor, thereby promoting its conduction and forming a positive feedback effect. At this time, the device is successfully triggered.

[0013] This invention also provides a method for fabricating a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device, the method comprising:

[0014] Step 1: Form an N-type buried layer in a P-type substrate;

[0015] Step 2: Generate an N-type trap in the middle above the N-type buried layer;

[0016] Step 3: Generate the first field oxygen isolation region, the second field oxygen isolation region, the third field oxygen isolation region, the fourth field oxygen isolation region, the fifth field oxygen isolation region, and the sixth field oxygen isolation region sequentially from left to right in the P-type substrate;

[0017] Step 4: Generate a first high-pressure N-well, a second high-pressure N-well, a first P-well, and a second P-well on both sides above the N-type buried layer, respectively.

[0018] Step 5: Generate a second P-type shallow well and a third P-type shallow well on both sides of the N-type well. A first P-type shallow well PB and a fourth P-type shallow well PB are respectively provided directly below the second N+ injection region and the third N+ injection region.

[0019] Step Six: In the first P-well, from left to right, a first P+ implantation region, a first N+ implantation region, a second N+ implantation region, and a first P-type shallow well PB and a second P-type shallow well PB are formed sequentially. In the second P-well, from left to right, a third P-type shallow well PB, a third N+ implantation region, a fourth P-type shallow well PB, a fourth N+ implantation region, and a second P+ implantation region are formed sequentially. Simultaneously, a floating N+ implantation region is formed between the second P-type shallow well and the third P-type shallow well. Furthermore, the left side of the first field oxygen isolation region contacts the left edge of the P-type substrate, the right side of the first field oxygen isolation region contacts the left side of the first P+ implantation region, the right side of the first P+ implantation region connects to the left side of the first N+ implantation region, and the right side of the first N+ implantation region contacts the left side of the second field oxygen isolation region. The right side of the second field oxygen isolation region contacts the left side of the second N+ implantation region, and the right side of the second N+ implantation region contacts the left side of the third field oxygen isolation region; the right side of the third field oxygen isolation region contacts the left side of the second P-type shallow well PB, the right side of the third P-type shallow well PB contacts the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region contacts the left side of the third N+ implantation region, the left side of the third N+ implantation region contacts the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region contacts the left side of the fourth N+ implantation region, the right side of the fourth N+ implantation region contacts the left side of the second P+ implantation region, the right side of the second P+ implantation region contacts the left side of the sixth field oxygen isolation region, and the right side of the sixth field oxygen isolation region contacts the right edge of the P-type substrate;

[0020] Step 7: Anneal the first P+ injection region, the first N+ injection region, the second N+ injection region, the floating N+ injection region in the N-type trap, the third N+ injection region, the fourth N+ injection region and the second P+ injection region to eliminate the migration of impurities in the injection region;

[0021] Step 8: Connect the first P+ injection region and the first N+ injection region together as the anode of the device, and connect the fourth N+ injection region and the second P+ injection region together as the cathode of the device.

[0022] Preferably, the method further includes:

[0023] A silicon dioxide thin film is grown on the P-type substrate, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop it to form a shallow isolation trench; the silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is removed.

[0024] This invention provides a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, the advantages of which are:

[0025] 1. This invention can reduce the trigger voltage and on-resistance and increase the sustaining voltage without increasing the device layout area, by changing the internal structural hierarchy and wiring of the device. The second N+ injection region is connected to the third N+ injection region through a metal wire, forming an additional conductive path. This conductive path spans the second P-type shallow well, the third P-type shallow well, and the intermediate N-type well, and has a low on-resistance. The breakdown voltage of the reverse PN junction formed by the first P-type shallow well PB and the second N+ injection region, as well as the reverse PN junction formed by the fourth P-type shallow well PB and the third N+ injection region, is small. This structural design can effectively reduce the device's trigger voltage and on-resistance. The intermediate floating N+ injection region can increase the doping concentration of the intermediate N-well, increase the base region concentration of the parasitic PNP transistor in the device's thyristor path, and thus improve the device's sustaining voltage.

[0026] 2. The second and third P-type shallow wells of the present invention can increase the anode-cathode spacing of the device, extend the effective length of the ESD current discharge path and thus increase its equivalent resistance, ultimately achieving the purpose of improving the device's holding voltage. The N-type buried layer can completely isolate the main structure of the thyristor from the P-type substrate, effectively improving the device's leakage protection capability.

[0027] 3. The dimensions S3 of the second N+ injection region and the third N+ injection region in the first P-well and the second P-well of the present invention are adjustable. When S3 is increased, the current transmission capability of the path formed by the second N+ injection region, the metal wire and the third N+ injection region will be improved, which will allow more current to pass through the path, ultimately leading to an increase in the trigger voltage of the device. Therefore, the trigger voltage of the device will increase with the increase of the dimension S3. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view of a currently known bidirectional SCR electrostatic discharge protection device;

[0029] Figure 2 The equivalent circuit diagram of the currently known bidirectional SCR electrostatic discharge protection device;

[0030] Figure 3 A cross-sectional view of a low on-resistance, high robust bidirectional thyristor electrostatic discharge (ESD) device provided in an embodiment of the present invention.

[0031] Figure 4 The equivalent circuit diagram of a low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device provided in an embodiment of the present invention is shown.

[0032] Figure 5The simulation diagram shows the total current density distribution of a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device provided in an embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0035] like Figure 3 As shown, a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device includes a P-type substrate 101; an N-type buried layer 201 is disposed in the P-type substrate 101; an N-type well 301 is located above and in the middle of the N-type buried layer 201; a first P-well 401 is disposed on the left side of the N-type buried layer 201, and a second P-well 402 is disposed on the right side of the N-type buried layer 201; the first P-well 401 contains a first P+ injection region 701, a first N+ injection region 702, and a second N+ injection region 703, wherein... The first P+ injection region 701 is located to the left of the first P-well 401, the first N+ injection region 702 is located to the right of the first P+ injection region 701 and is attached to it, and the second N+ injection region 703 is located to the right of the first N+ injection region 702; the second P-well 402 is provided with a second P+ injection region 707, a third N+ injection region 705 and a fourth N+ injection region 706, wherein the second P+ injection region 707 is located to the right of the second P-well 402. The fourth N+ injection region 706 is located to the left of the second P+ injection region 707 and is attached to it. The third N+ injection region 705 is located to the left of the second N+ injection region 703. At the same time, the third N+ injection region 705 and the second N+ injection region 703 are directly connected by a metal wire. In this way, the device can form an additional conductive path that crosses the second P-type shallow well 502, the third P-type shallow well 503 and the intermediate N-type well 301. It has a low on-resistance. The reverse PN junction formed by the first P-type shallow well 501 and the second N+ injection region 703 and the reverse PN junction formed by the fourth P-type shallow well 504 and the third N+ injection region 705 have low breakdown voltages. This structural design can effectively reduce the device's trigger voltage and on-resistance. The intermediate floating N+ injection region 704 can increase the doping concentration of the intermediate N-well 301 through diffusion effect, increase the base region concentration of the parasitic PNP transistor in the device's thyristor path, and thus improve the device's sustaining voltage.

[0036] An N-type well 301 is provided between the first P-well 401 and the second P-well 402. A floating N+ injection region 704 is provided in the middle of the N-type well 301. At the same time, a second P-type shallow well PB502 and a third P-type shallow well PB503 are respectively arranged across the middle of the first P-well 401, the N-type well 301 and the second P-well 402. The floating N+ injection region in the middle can increase the doping concentration of the middle N-well, increase the base region concentration of the parasitic PNP transistor in the thyristor path of the device, and thus improve the sustaining voltage of the device.

[0037] The second N+ injection region 703 and the third N+ injection region 705 are respectively provided with a first P-type shallow well PB501 and a fourth P-type shallow well PB504 directly below them; the left and right sides above the N-type buried layer 201 are respectively provided with a first high-voltage N-well 601 and a second high-voltage N-well 602; the first P+ injection region 701 and the first N+ injection region 702 are connected together and serve as the anode of the device, and the second P+ injection region 707 and the fourth N+ injection region 706 are connected together and serve as the cathode of the device.

[0038] In one embodiment, a first field oxygen isolation region 801 is provided between the left side of the first P+ implantation region 701 and the left edge of the P-type substrate 101; the right side of the first P+ implantation region 701 is connected to the left side of the first N+ implantation region 702; a second field oxygen isolation region 802 is provided between the right side of the first N+ implantation region 702 and the left side of the second N+ implantation region 703; the left side of the second P+ implantation region 707 is connected to the right side of the fourth N+ implantation region 706; a fifth field oxygen isolation region 805 is provided between the left side of the fourth N+ implantation region 706 and the right side of the third N+ implantation region 705; a third field oxygen isolation region 803 is provided between the right side of the second N+ implantation region 703 and the left side of the second P-type shallow well PB502; a fourth field oxygen isolation region 804 is provided between the left side of the third N+ implantation region 705 and the right side of the third P-type shallow well PB503; and a sixth field oxygen isolation region 806 is provided between the right side of the second P+ implantation region 707 and the right edge of the P-type substrate 101.

[0039] In one embodiment, the left portion of the first field oxygen isolation region 801 is located on the surface of the P-type substrate 101, and the right portion of the first field oxygen isolation region 801 is located on the surface of the first P-well 401; the left portion of the sixth field oxygen isolation region 806 is located on the surface of the second P-well 402, and the right portion of the sixth field oxygen isolation region 806 is located on the surface of the P-type substrate 101; the second field oxygen isolation region 802 and the third field oxygen isolation region 803 are located on the surface of the first P-well 401, and the fourth field oxygen isolation region 804 and the fifth field oxygen isolation region 805 are located on the surface of the second P-well 402.

[0040] In one implementation, such as Figure 4 As shown, when a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the first N+ injection region 702, the first P-well 401, and the N-type well 301 form a vertical NPN transistor, the first P-well 401, the N-type well 301, and the second P-well 402 form a horizontal PNP transistor structure, and the second N+ injection region 703, the second P-well 402, and the N-type well 301 form a vertical NPN transistor. The vertical parasitic NPN transistor in the first P-well 401 and the vertical parasitic vertical NPN transistor in the second P-well 402 can be combined in pairs with the horizontal PNP transistor to form a bidirectional SCR structure.

[0041] When the ESD high-voltage pulse reaches the anode of the device, the first P+ injection region 701 and the first N+ injection region 702 are at high potential, while the fourth N+ injection region 706 and the second P+ injection region 707 at the other end are at low potential cathodes. The third N+ injection region 705 and the fourth P-type shallow well located in the second P-well 402 are reverse biased. When the pulse voltage is higher than the avalanche breakdown voltage of the reverse-biased PN junction D2 formed by the third N+ injection region 705 and the fourth P-type shallow well, a large avalanche current will be generated inside the device. The avalanche current flows through the parasitic resistance of the second P-well 402 into the cathode. (See equivalent circuit diagram.) Figure 4 It can be seen that when the voltage drop across the parasitic resistance of the second P-well 402 is sufficiently large, the parasitic transistor T3 turns on. After T3 turns on, it provides current to the base of the parasitic transistor T2, forming a positive feedback loop. The forward SCR structure is then turned on to discharge static electricity. Similarly, when a forward ESD pulse occurs at the cathode, the reverse-biased PN junction D1, formed by the second N+ injection region 703 and the first P-type shallow well, undergoes avalanche breakdown. The avalanche current flows through the parasitic resistance of the first P-well 401 into the anode. (From the equivalent circuit diagram...) Figure 4 It can be seen that when the voltage drop generated by the avalanche current on the parasitic resistance of the first P-well 401 is large enough, the parasitic transistor T1 turns on. After the parasitic transistor T1 turns on, it will provide current to the base of the parasitic transistor T2. The two form a positive feedback loop, and the reverse SCR structure is turned on to discharge static electricity.

[0042] Compared to traditional bidirectional thyristor ESD protection devices, this device alters the trigger path of traditional thyristors. The parasitic resistance of the metal wire path traversed by the ESD pulse during the triggering stage is very small, effectively reducing the device's on-resistance. The reverse-biased PN junction formed by the second N+ injection region 703 and the first P-type shallow well, and the third N+ injection region 705 and the fourth P-type shallow well, allows the device to have a lower trigger voltage. Furthermore, this device possesses an additional discharge path, as shown in the simulation diagram of the device's total current density distribution. Figure 5It can be seen that the current density distribution is most concentrated below the second N+ injection region 703 and the third N+ injection region 705, indicating that this path is the main discharge path. At the same time, the current is also relatively concentrated in the N-type buried layer 201, indicating that this discharge path is the secondary discharge path. This discharge path can guide the current to flow deep into the device, which can effectively improve the device's sustaining voltage and failure current.

[0043] The intermediate floating N+ injection region 704 can increase the doping concentration of the intermediate N-type well 301, increase the base region concentration of the parasitic PNP transistor in the thyristor path of the device, and thus improve the sustaining voltage of the device.

[0044] The second P-type shallow well 502 and the third P-type shallow well 503 can increase the anode-cathode spacing of the device, which can effectively improve the sustaining voltage of the device. The N-type buried layer 201 can completely isolate the main structure of the thyristor from the P-type substrate 101, which can effectively improve the leakage protection capability of the device.

[0045] The dimensions S3 of the second N+ injection region 703 and the third N+ injection region 705 in the first P-well 401 and the second P-well 402 are adjustable. When S3 is increased, the current transmission capability of the path formed by the second N+ injection region 703, the metal wire and the third N+ injection region 705 will be improved, which will allow more current to pass through the path, ultimately leading to an increase in the device's trigger voltage. Therefore, the device's trigger voltage will increase with the increase of the dimension S3.

[0046] This invention also provides a method for fabricating a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device, comprising the following steps:

[0047] Step 1: Form an N-type buried layer 201 in a P-type substrate 101;

[0048] Step 2: Generate an N-type trap 301 in the middle above the N-type buried layer 201;

[0049] Step 3: The first field oxygen isolation region 801, the second field oxygen isolation region 802, the third field oxygen isolation region 803, the fourth field oxygen isolation region 804, the fifth field oxygen isolation region 805, and the sixth field oxygen isolation region 806 are formed sequentially from left to right in the P-type substrate 101.

[0050] Step 4: Generate a first high-pressure N-well 601, a second high-pressure N-well 602, a first P-well 401, and a second P-well 402 on both sides above the N-type buried layer 201, respectively.

[0051] Step 5: A second P-type shallow well and a third P-type shallow well are generated on both sides of the N-type well 301. A first P-type shallow well PB501 and a fourth P-type shallow well PB504 are respectively provided directly below the second N+ injection region 703 and the third N+ injection region 705.

[0052] Step Six: In the first P-well 401, from left to right, a first P+ implantation region 701, a first N+ implantation region 702, a second N+ implantation region 703, and a first P-type shallow well PB501 and a second P-type shallow well PB502 are formed sequentially. In the second P-well 402, from left to right, a third P-type shallow well PB503, a third N+ implantation region 705, a fourth P-type shallow well PB504, a fourth N+ implantation region 706, and a second P+ implantation region 707 are formed sequentially. Simultaneously, a floating N+ implantation region 704 is formed between the second P-type shallow well and the third P-type shallow well. The left side of the first field oxygen isolation region 801 contacts the left edge of the P-type substrate 101, the right side of the first field oxygen isolation region 801 contacts the left side of the first P+ implantation region 701, the right side of the first P+ implantation region 701 connects to the left side of the first N+ implantation region 702, and the right side of the first N+ implantation region 702 contacts the left side of the second field oxygen isolation region 802. The right side of the second field oxygen isolation region 802 contacts the left side of the second N+ implantation region 703, and the right side of the second N+ implantation region 703 contacts the left side of the third field oxygen isolation region 803; the right side of the third field oxygen isolation region 803 contacts the left side of the second P-type shallow well PB502, the right side of the third P-type shallow well PB503 contacts the left side of the fourth field oxygen isolation region 804, the right side of the fourth field oxygen isolation region 804 contacts the left side of the third N+ implantation region 705, the left side of the third N+ implantation region 705 contacts the left side of the fifth field oxygen isolation region 805, the right side of the fifth field oxygen isolation region 805 contacts the left side of the fourth N+ implantation region 706, the right side of the fourth N+ implantation region 706 contacts the left side of the second P+ implantation region 707, the right side of the second P+ implantation region 707 contacts the left side of the sixth field oxygen isolation region 806, and the right side of the sixth field oxygen isolation region 806 contacts the right edge of the P-type substrate 101;

[0053] Step 7: Anneal the first P+ injection region 701, the first N+ injection region 702, the second N+ injection region 703, the floating N+ injection region 704, the third N+ injection region 705, the fourth N+ injection region 706 and the second P+ injection region 707 in the N-type trap 301 to eliminate the migration of impurities in the injection region;

[0054] Step 8: Connect the first P+ injection region 701 and the first N+ injection region 702 together as the anode of the device, and connect the fourth N+ injection region 706 and the second P+ injection region 707 together as the cathode of the device.

[0055] Optionally, the method may further include:

[0056] A silicon dioxide thin film is grown on the P-type substrate 101, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop it to form a shallow isolation trench; the silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is removed.

[0057] The fabrication method of this invention for a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device is simple and easy to operate. The fabricated bidirectional SSD ESD device structure possesses a reverse avalanche breakdown surface with low breakdown voltage, effectively reducing the device's trigger voltage. It also has a trigger path with low parasitic resistance, effectively reducing the device's on-resistance. Simultaneously, this design provides the device with an additional ESD current discharge path, effectively increasing the device's failure current. This device can be applied to ESD protection designs for 0–5.5V I / O ports, effectively protecting the internal chip from latch-up risks. The example device of this invention uses a 0.25μm BCDMOS process.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) protection device, characterized in that, The device includes a P-type substrate; an N-type buried layer is disposed in the P-type substrate; an N-type well is located above and in the middle of the N-type buried layer; a first P-well is disposed on the left side of the N-type buried layer, and a second P-well is disposed on the right side of the N-type buried layer; the first P-well contains a first P+ injection region, a first N+ injection region, and a second N+ injection region, wherein the first P+ injection region is located on the left side of the first P-well, the first N+ injection region is located on the right side of the first P+ injection region and is attached to it, and the second N+ injection region is located on the right side of the first N+ injection region. The second P-well is provided with a second P+ injection region, a third N+ injection region and a fourth N+ injection region. The second P+ injection region is located on the right side of the second P-well, the fourth N+ injection region is located on the left side of the second P+ injection region and is attached to it, and the third N+ injection region is located on the left side of the second N+ injection region. At the same time, the third N+ injection region and the second N+ injection region are directly connected by a metal wire. An N-type well is provided between the first P-well and the second P-well. A floating N+ injection region is provided in the middle of the N-type well. At the same time, a second P-type shallow well PB and a third P-type shallow well PB are respectively arranged across the middle of the first P-well, the N-type well, and the second P-well. A first P-type shallow well PB and a fourth P-type shallow well PB are respectively provided directly below the second N+ injection region and the third N+ injection region. A first high-voltage N-well and a second high-voltage N-well are respectively provided on the left and right sides above the N-type buried layer. The first P+ injection region and the first N+ injection region are connected together and serve as the anode of the device. The second P+ injection region and the fourth N+ injection region are connected together and serve as the cathode of the device.

2. The low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, A first field oxygen isolation region is provided between the left side of the first P+ implantation region and the left edge of the P-type substrate; the right side of the first P+ implantation region is connected to the left side of the first N+ implantation region; a second field oxygen isolation region is provided between the right side of the first N+ implantation region and the left side of the second N+ implantation region; the left side of the second P+ implantation region is connected to the right side of the fourth N+ implantation region; a fifth field oxygen isolation region is provided between the left side of the fourth N+ implantation region and the right side of the third N+ implantation region; a third field oxygen isolation region is provided between the right side of the second N+ implantation region and the left side of the second P-type shallow well PB; a fourth field oxygen isolation region is provided between the left side of the third N+ implantation region and the right side of the third P-type shallow well PB; and a sixth field oxygen isolation region is provided between the right side of the second P+ implantation region and the right edge of the P-type substrate.

3. The low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device according to claim 2, characterized in that, The left portion of the first field oxygen isolation region is located on the surface of the P-type substrate, and the right portion of the first field oxygen isolation region is located on the surface of the first P-well; the left portion of the sixth field oxygen isolation region is located on the surface of the second P-well, and the right portion of the sixth field oxygen isolation region is located on the surface of the P-type substrate; the second field oxygen isolation region and the third field oxygen isolation region are located on the surface of the first P-well, and the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the second P-well.

4. The low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device according to claim 2, characterized in that, When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the first N+ injection region, the first P-well, and the N-type well constitute a vertical NPN transistor, the first P-well, the N-type well, and the second P-well constitute a horizontal PNP transistor structure, the second N+ injection region, the second P-well, and the N-type well constitute a vertical NPN transistor, and the first P-well, the N-type buried layer, and the second P-well constitute a horizontal PNP transistor.

5. The low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, When a high-voltage ESD pulse reaches the anode of the device, the cathode is connected to a low potential. The ESD current flows along the P+ injection region into the first P-well, the first P-type shallow well PB, the second N+ injection region, the third N+ injection region, the fourth P-type shallow well PB, the second P-well, and then back to the second P+ injection region. When the ESD current increases to a certain value, the reverse PN junction formed by the third N+ injection region and the fourth P-type shallow well PB undergoes avalanche breakdown. The ESD current flows into the second P-well in large quantities through the low-resistance wire path between the second N+ injection region and the third N+ injection region, forming a voltage drop across the equivalent resistance of the second P-well. When the voltage drop reaches 0.7V, the right vertical NPN transistor turns on and provides base current to the left horizontal PNP transistor, thereby promoting its conduction and forming a positive feedback effect. At this time, the thyristor path of the device is fully turned on and a large amount of ESD current is discharged.

6. A method for fabricating a low on-resistance, high-robustness bidirectional thyristor electrostatic discharge (ESD) device, characterized in that, The method includes: Step 1: Form an N-type buried layer in a P-type substrate; Step 2: Generate an N-type trap in the middle above the N-type buried layer; Step 3: Generate the first field oxygen isolation region, the second field oxygen isolation region, the third field oxygen isolation region, the fourth field oxygen isolation region, the fifth field oxygen isolation region, and the sixth field oxygen isolation region sequentially from left to right in the P-type substrate; Step 4: Generate a first high-pressure N-well, a second high-pressure N-well, a first P-well, and a second P-well on both sides above the N-type buried layer, respectively. Step 5: Generate a second P-type shallow well and a third P-type shallow well on both sides of the N-type well. A first P-type shallow well PB and a fourth P-type shallow well PB are respectively provided directly below the second N+ injection region and the third N+ injection region. Step Six: In the first P-well, from left to right, a first P+ implantation region, a first N+ implantation region, a second N+ implantation region, and a first P-type shallow well PB and a second P-type shallow well PB are formed sequentially. In the second P-well, from left to right, a third P-type shallow well PB, a third N+ implantation region, a fourth P-type shallow well PB, a fourth N+ implantation region, and a second P+ implantation region are formed sequentially. Simultaneously, a floating N+ implantation region is formed between the second P-type shallow well and the third P-type shallow well. Furthermore, the left side of the first field oxygen isolation region contacts the left edge of the P-type substrate, the right side of the first field oxygen isolation region contacts the left side of the first P+ implantation region, the right side of the first P+ implantation region connects to the left side of the first N+ implantation region, and the right side of the first N+ implantation region contacts the left side of the second field oxygen isolation region. The right side of the second field oxygen isolation region contacts the left side of the second N+ implantation region, and the right side of the second N+ implantation region contacts the left side of the third field oxygen isolation region; the right side of the third field oxygen isolation region contacts the left side of the second P-type shallow well PB, the right side of the third P-type shallow well PB contacts the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region contacts the left side of the third N+ implantation region, the left side of the third N+ implantation region contacts the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region contacts the left side of the fourth N+ implantation region, the right side of the fourth N+ implantation region contacts the left side of the second P+ implantation region, the right side of the second P+ implantation region contacts the left side of the sixth field oxygen isolation region, and the right side of the sixth field oxygen isolation region contacts the right edge of the P-type substrate; Step 7: Anneal the first P+ injection region, the first N+ injection region, the second N+ injection region, the floating N+ injection region in the N-type trap, the third N+ injection region, the fourth N+ injection region and the second P+ injection region to eliminate the migration of impurities in the injection region; Step 8: Connect the first P+ injection region and the first N+ injection region together as the anode of the device, and connect the fourth N+ injection region and the second P+ injection region together as the cathode of the device.

7. The method for manufacturing the low on-resistance, high robustness bidirectional thyristor electrostatic discharge (ESD) device according to claim 6, characterized in that, The method is preceded by: A silicon dioxide thin film is grown on the P-type substrate, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop it to form a shallow isolation trench; the silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is removed.

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