Processors, systems, machine-readable media, and methods for 5g-nr operation

Abstract

Application programming interfaces for indicating a number of wireless cells are disclosed, including apparatuses, systems, and techniques for performing one or more APIs. In at least one embodiment, a processor is configured to perform an API to indicate a number of 5G-NR cells that can be concurrently performed by one or more processors; the processor is configured to perform an API to indicate whether one or more processors are capable of concurrently performing a first number of 5G-NR cells; a processor comprising one or more circuits is configured to perform an API to indicate whether one or more resources of the one or more processors are allocated to perform 5G-NR cells; and / or the processor comprises one or more circuits configured to perform an API to indicate one or more techniques to be used by the one or more processors in performing one or more 5G-NR cells.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for fifth-generation new radio (“5G-NR”) operation. For example, a processor including one or more circuits is used to execute an application programming interface (“API”) to indicate the number of 5G-NR cells that can be executed concurrently by one or more processors (e.g., one or more graphics processing units (“GPUs”)). Background Technology

[0002] Processing 5G-NR workloads consumes significant amounts of memory, time, or computing resources. The amount of memory, time, or computing resources used to process 5G-NR workloads can be improved. Attached Figure Description

[0003] Figure 1 It is a schematic overview block diagram of a network protocol stack according to at least one embodiment;

[0004] Figure 2 It is according to at least one embodiment corresponding to the use of Figure 1 The flowchart of the network protocol stack's workload processing process;

[0005] Figure 3 It is a process flowchart according to at least one embodiment, including more details on processing workloads with the network protocol stack;

[0006] Figure 4 This is another process flowchart according to at least one embodiment, including more details on processing workloads with the network protocol stack;

[0007] Figure 5 This is another process flowchart according to at least one embodiment, including more details on processing workloads with the network protocol stack;

[0008] Figure 6 A method for using according to at least one embodiment is shown. Figure 1 A schematic flowchart illustrating the network protocol stack's workload processing;

[0009] Figure 7 A schematic diagram of an Accelerated Abstraction Layer (“AAL”) interface according to at least one embodiment is shown;

[0010] Figure 8 A diagram of an inline acceleration model according to at least one embodiment is shown;

[0011] Figure 9 An example data center system according to at least one embodiment is shown;

[0012] Figure 10AAn example of an autonomous vehicle according to at least one embodiment is shown;

[0013] Figure 10B The illustration shows an embodiment according to at least one of the embodiments. Figure 10A Examples of camera positions and field of view for autonomous vehicles;

[0014] Figure 10C It is shown that according to at least one embodiment Figure 10A A block diagram of an example system architecture for autonomous vehicles;

[0015] Figure 10D This illustrates an embodiment for use in a cloud-based server and Figure 10A A diagram of a system for communication between autonomous vehicles;

[0016] Figure 11 This is a block diagram illustrating a computer system according to at least one embodiment;

[0017] Figure 12 This is a block diagram illustrating a computer system according to at least one embodiment;

[0018] Figure 13 A computer system according to at least one embodiment is shown;

[0019] Figure 14 A computer system according to at least one embodiment is shown;

[0020] Figure 15A A computer system according to at least one embodiment is shown;

[0021] Figure 15B A computer system according to at least one embodiment is shown;

[0022] Figure 15C A computer system according to at least one embodiment is shown;

[0023] Figure 15D A computer system according to at least one embodiment is shown;

[0024] Figure 15E and Figure 15F A shared programming model according to at least one embodiment is shown;

[0025] Figure 16 An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0026] Figure 17A and Figure 17B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0027] Figure 18A and Figure 18B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0028] Figure 19 A computer system according to at least one embodiment is shown;

[0029] Figure 20A A parallel processor according to at least one embodiment is shown;

[0030] Figure 20B A partitioning unit according to at least one embodiment is shown;

[0031] Figure 20C A processing cluster according to at least one embodiment is shown;

[0032] Figure 20D A graphics multiprocessor according to at least one embodiment is shown;

[0033] Figure 21 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0034] Figure 22 A graphics processor according to at least one embodiment is shown;

[0035] Figure 23 This is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0036] Figure 24 At least a portion of a graphics processor according to one or more embodiments is shown;

[0037] Figure 25 At least a portion of a graphics processor according to one or more embodiments is shown;

[0038] Figure 26 It is at least a portion of a graphics processor according to at least one embodiment;

[0039] Figure 27 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0040] Figure 28 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0041] Figure 29A and Figure 29B The thread execution logic is shown, which includes an array of processing elements of a graphics processor core;

[0042] Figure 30A parallel processing unit (“PPU”) according to at least one embodiment is shown.

[0043] Figure 31 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated.

[0044] Figure 32 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0045] Figure 33 A streaming multiprocessor according to at least one embodiment is illustrated;

[0046] Figure 34 A network for transmitting data within a 5G wireless communication network is illustrated according to at least one embodiment;

[0047] Figure 35 A network architecture for a 5G LTE wireless network according to at least one embodiment is shown;

[0048] Figure 36 This is a diagram illustrating some basic functions of a mobile telecommunications network / system operating according to LTE and 5G principles according to at least one embodiment;

[0049] Figure 37 A radio access network, which may be part of a 5G network architecture according to at least one embodiment, is shown;

[0050] Figure 38 An example illustration of a 5G mobile communication system using multiple different types of devices according to at least one embodiment is provided;

[0051] Figure 39 An example advanced system according to at least one embodiment is shown;

[0052] Figure 40 The architecture of a network system according to at least one embodiment is shown;

[0053] Figure 41 Example components of a device according to at least one embodiment are shown;

[0054] Figure 42 An example interface of a baseband circuit according to at least one embodiment is shown;

[0055] Figure 43 An example of an uplink channel according to at least one embodiment is shown;

[0056] Figure 44 The architecture of a network system according to at least one embodiment is shown;

[0057] Figure 45 A control plane protocol stack according to at least one embodiment is shown;

[0058] Figure 46 A user plane protocol stack according to at least one embodiment is shown;

[0059] Figure 47 The components of a core network according to at least one embodiment are shown; and

[0060] Figure 48 Components of a system supporting Network Function Virtualization (“NFV”) according to at least one embodiment are shown. Detailed Implementation

[0061] Many specific details have been set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that these inventive concepts can be practiced without one or more of these specific details.

[0062] In at least one embodiment, in an Open Radio Access Network (“O-RAN”) deployment, one or more central processing units (“CPUs”) handle functional operations as part of a distributed unit (“DU”) or a centralized unit (“CU”). In at least one embodiment, in an O-RAN deployment, one or more CPUs can offload computationally intensive algorithm operations (such as physical layer signal processing, game processing, and video processing) to hardware accelerators in lower layers of the O-RAN network protocol stack. In at least one embodiment, the hardware accelerator can be a GPU, a field-programmable gate array (“FPGA”), an application-specific integrated circuit (“ASIC”), a system-on-a-chip (“SoC”), or other processors specifically designed for accelerated processing (e.g., one or more PPUs). In at least one embodiment, the hardware accelerators provide performance enhancements to processing operations in the O-RAN because they are designed to accelerate processing. For example, a GPU can execute thousands of operations in parallel compared to a CPU that performs operations serially.

[0063] In at least one embodiment, a 5G-NR service provider uses O-RAN to offer a range of services as part of “network slicing,” where different network slices of the 5G-NR network provide different types of services corresponding to different qualities of service (“QoS”). For example, a 5G-NR service provider provides one or more cells in a 5G-NR network with network slices employing enhanced mobile broadband (“eMBB”), ultra-reliable low-latency communication (“URLLC”), massive machine-type communication (“mMTC”), and / or vehicle-to-everything (“V2X”), where each service type has a different QoS; for example, URLLC is associated with ultra-low latency when handling 5G-NR workloads. In at least one embodiment, a cell refers to a portion of a 5G-NR network divided into geographical areas (e.g., 5G small cells). In at least one embodiment, a cell refers to a portion of a 5G-NR network operating using different frequency ranges or bands (e.g., macrocells, microcells, femtocells, or picocells).

[0064] In at least one embodiment, the hardware accelerator may have different capabilities for handling different types of 5G-NR workloads (e.g., workloads in different network slices with different QoS requirements). For example, a particular GPU or GPU group may inherently be better than a CPU for executing game-related mMTC workloads due to its parallel processing architecture; as another example, an FPGA or FPGA group programmed for low-latency workloads may be better than a CPU for executing URLLC workloads to meet QoS requirements because the programming is designed to reduce latency in the FPGA or FPGA group.

[0065] In at least one embodiment, applications deployed on an O-RAN network may be unaware of whether hardware accelerators in lower layers (e.g., Layer 1) are optimized for performing specific workloads to meet QoS requirements. More specifically, without determining what QoS requirements a hardware accelerator can meet, the application assumes that the hardware accelerator is standard and can meet predefined QoS requirements that may fall short of the capabilities of specialized hardware accelerators (e.g., newly designed GPUs optimized for machine learning operations), potentially leading to underutilization of hardware accelerator resources.

[0066] To illustrate the different capabilities of hardware accelerators and reduce underutilization of hardware accelerators designed for or specifically designed to handle workloads exceeding predefined standards, in at least one embodiment, apparatus, systems, and technologies execute one or more APIs that facilitate data communication between Layer 2 (“L2”) and Layer 1 (“L1”) of the O-RAN network protocol stack, enabling L2 and L1 to improve (e.g., optimize) the utilization of hardware accelerator resources in L1 to meet QoS requirements. In at least one embodiment, the one or more APIs may be executed by one or more processors, as described below, to exchange information between L2 and L1 of the O-RAN network protocol stack, allowing applications to determine, via L2, what QoS requirements one or more resources (e.g., hardware accelerators in L1) can meet when handling 5G-NR workloads in 5G-NR cells.

[0067] In at least one embodiment, the one or more APIs may be executed by one or more processors, as described below, to determine the maximum number of 5G-NR cells that resources in L1 can support while meeting required QoS requirements. For example, an application may use a set of APIs to determine how many 5G-NR cell resources in L1 can support URLLC workloads. Figures 3 to 6 The one or more APIs are disclosed in more detail. In at least one embodiment, because the application queries L1 to determine the maximum number of 5G-NR cells that can be supported while meeting quality requirements, the underutilization of hardware accelerators in L1 is reduced, since the application has queried the maximum number of cells that the resources in L1 can support while meeting quality parameters higher than predefined standards.

[0068] Figure 1 This is a schematic overview block diagram of a network protocol stack 100 according to at least one embodiment. In at least one embodiment, the network protocol stack 100 corresponds to or is used to perform one or more operations of an O-RAN network protocol stack or other network protocol stack for providing 5G-NR services. In other embodiments, the network protocol stack 100 corresponds to providing sixth-generation (6G) new radio network services or other wireless communication protocol stacks (e.g., any 3GPP wireless communication standard). In at least one embodiment, the network protocol stack 100 is used to support... Figures 34-38 and Figure 40 The network is publicly available in China.

[0069] Figure 1This includes a network protocol stack 100, an application 105, a layer 2 (“L2”) or higher layer 110 (also referred to as “L2+”), a layer 2 to layer 1 interface 115 (also referred to as “L2-L1 interface”), a driver 120, a first processor 125, a second processor 130, and a network interface controller 135. In at least one embodiment, L2 is associated with the 5G-NR data link layer, which is responsible for scheduling functions related to 5G-NR workloads. In at least one embodiment, layer 1 (“L1”) refers to the physical layer of the RAN protocol stack, which may be implemented as an L1 software library running on the first processor 125 (e.g., CPU) and / or the second processor 130 (e.g., an accelerated L1 run by an FPGA, GPU, ASIC, or SoC). In at least one embodiment, a layer refers to an abstraction of hardware that performs the functions or operations of a system, network, or computer; for example, L2 is an abstraction of hardware that performs data link and scheduling operations of an O-RAN network, and L1 is an abstraction of real-time hardware operations that perform physical layer operations of an O-RAN network (e.g., an O-RAN network). For example, a layer corresponds to an Open Systems Interconnection (OSI) model (e.g., L1, L2, L3) exposed by one or more interfaces used to handle the functions or operations of 5G-NR.

[0070] In at least one embodiment, application 105 is a RAN protocol stack program running on a host CPU (e.g., a first processor 125). For example, application 105 relates to software for a service provider of 5G-NR, used to provide eMBB, URLLC, mMTC, and / or V2X for one or more cells in a 5G-NR network. Although Figure 1 The diagram shows an application 105, but several applications can run on the network protocol stack 100, each application 105 providing the same or different services.

[0071] In at least one embodiment, the L2-L1 interface 115 enables application 105 to communicate with L1 and enables driver 120 in L1 to control first processor 125, second processor 130, and network interface controller 135. In at least one embodiment, application 105 uses L2-L1 interface 115 and one or more APIs to determine how many 5G-NR cells an L1 resource (e.g., a hardware accelerator) can concurrently support, schedule or prioritize workloads handled by the L1 resource, and perform operations to reconfigure or update the L1 resource as traffic conditions in the 5G-NR network change (see [link to API description] for more details on the one or more APIs). Figures 3 to 5In at least one embodiment, the L2-L1 interface 115 is an interface such as the fifth-generation functional application programming interface (5G FAPI), and / or a variant thereof. Figure 7 Further details regarding the L2-L1 interface are disclosed herein. In at least one embodiment, the L2-L1 interface 115 is connected to... Figure 7 It communicates with the Accelerated Abstraction Layer (AAL) interface disclosed in the document.

[0072] In at least one embodiment, driver 120 includes libraries for operating the first processor 125, the second processor 130, and the network interface controller 135. In at least one embodiment, driver, also referred to as a device driver, is a computer program that operates, controls, or otherwise provides an interface with various hardware, such as hardware accelerator devices and network communication / interface devices. In at least one embodiment, driver 120 includes one or more functions, processes, libraries, interfaces, and / or variations thereof that support the L2-L1 interface 115. In at least one embodiment, driver 120 is implemented such that the functionality of the L2-L1 interface 115 can be appropriately processed in relation to the first processor 125, the second processor 130, and the network interface controller 135.

[0073] In at least one embodiment, the first processor 125 is a processor with one or more circuits for performing operations corresponding to the network protocol stack 100. For example, the first processor 125 is a CPU configured to perform or operate a DU or CU of the O-RAN. In at least one embodiment, the second processor 130 is a hardware accelerator. The hardware accelerator may be a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), or other processors (e.g., parallel processing units) specifically designed to improve performance processing. In at least one embodiment, the first processor 125 (e.g., a CPU running a DU in the O-RAN network) can offload computationally intensive algorithms (such as physical (PHY) layer signal processing, game-related processing, video processing, and encryption processing) to the second processor 130 (e.g., a hardware accelerator).

[0074] In at least one embodiment, a network interface controller (NIC) 135 is a hardware component that connects one or more computing systems to one or more computing networks. In at least one embodiment, NIC 135 receives data to be processed by a first processor 125 or a second processor 130 (e.g., a hardware accelerator) and transmits the data processed by the first processor 125 or the second processor 130 to another component (e.g., a base station) in the O-RAN network. In at least one embodiment, NIC 135 receives data to be transmitted via an Accelerated Abstraction Layer interface (see... Figure 7 The NIC 135 processes data through one or more functions of the Accelerated Abstraction Layer interface and transmits the data processed by one or more functions of the Accelerated Abstraction Layer interface. In at least one embodiment, as part of providing 5G-NR services, the NIC 135 interacts with a Remote Radio Head (RRH), also known as a Remote Radio Unit (RRU).

[0075] Figure 2 A process flowchart for processing workloads of one or more 5G-NR cells according to at least one embodiment is shown. In at least one embodiment, a processor including one or more circuits or a system including one or more processors executes process 200 to process the O-RAN network protocol stack (e.g., such as...). Figure 1 The 5G-NR workload of the network protocol stack 100 shown.

[0076] In at least one embodiment, part or all of process 200 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented by hardware, software, or a combination thereof as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that executes jointly on one or more processors. In at least one embodiment, the code is stored in the form of a computer program on a computer-readable storage medium comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions available for executing process 200 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 200 is executed at least partially on a computer system (such as those described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) executes process 200. In at least one embodiment, process 200 may begin with determination operation 205 and proceed to mapping operation 210.

[0077] In at least one embodiment, at determination operation 205, one or more processors execute an API to determine the number of cells that can be concurrently processed by one or more hardware accelerators in L1 based on quality parameters. In at least one embodiment, the quality parameters relate to QoS requirements for processing workloads, such as quality thresholds to be met, which correspond to latency, throughput, reliability, and / or connectivity for processing one or more workloads corresponding to 5G-NR cells. In at least one embodiment, the quality parameters correspond to a Key Performance Indicator (KPI) (also referred to as “performance metrics”) matrix that can be accessed by the hardware accelerators processing one or more workloads so that input quality parameters from the API can be used by L1 to query (or determine) the relevant KPIs for the workload to meet the quality parameters. For example, in determination operation 102, one or more processors executing L2+ applications negotiate with one or more processors providing L1 in the O-RAN network to determine how many 5G-NR cells the hardware acceleration resources in L1 can support to meet the URLLC or mMTB workloads of these cells. In such an example, L1 can query hardware accelerator resources (such as GPUs, CPUs, FPGAs, ASICs, and / or SoCs) to determine how many 5G cells they can support while meeting the quality parameters of URLLC or mMTB workloads. More details about the API and the determination process are available in [link to API documentation]. Figure 3 China has made it public, such as Figure 2 As shown by "A" in the diagram.

[0078] At mapping operation 210, one or more processors execute an API to map a specific 5G-NR cell (e.g., cell ID) to hardware accelerator resources in L1, which will handle workloads to meet specific quality parameters negotiated by the API in determination operation 102. In at least one embodiment, one or more processors providing an L2+ or L2 application provide a cell identification number (e.g., cell ID) to one or more processors providing L1, so that L1 can receive the cell ID for mapping a specific hardware accelerator to an L1 resource. In at least one embodiment, after determination operation 205, the application has learned the maximum number of cells that L1 can support while meeting the quality parameters, so mapping operation 210 further specifies the cell IDs and the L1 hardware resources that will handle the workloads of these cells. In at least one embodiment, the API can respond to whether the mapping from cell ID to hardware accelerator resource is successful (e.g., "1") or unsuccessful (e.g., "0"). Further details about the API and mapping operation 210 are provided in [link to API documentation]. Figure 4 China has made it public, such as Figure 2 As shown by "B" in the diagram.

[0079] At algorithm selection operation 215, one or more processors execute an API to select an algorithm for processing 5G-NR workloads. In at least one embodiment, one or more processors providing L1 have access to a library including different processing algorithms (e.g., one or more techniques) to process specific workloads to meet quality parameters, such as a low-latency algorithm with low-latency quality parameters for processing the workload, or a high-throughput algorithm designed to process the workload to meet high-throughput quality parameters. In at least one embodiment, one or more processors including one or more circuits are configured to schedule workload processing sequentially or in parallel. In at least one embodiment, one or more processors execute an API that determines whether to process the workload sequentially or in parallel to meet quality parameters. Further details about the API and operation 215 are provided in [link to API]. Figure 5 China has made it public, such as Figure 2 As shown by "C" in the diagram.

[0080] At workload execution operation 220, in at least one embodiment, one or more processors execute one or more APIs to perform workloads that have been set up and mapped based on determination operation 102, mapping operation 210, and selection algorithm operation 215. In at least one embodiment, L2 may provide information related to the number of cells that the hardware resources in L1 can support to the O-RAN Service Management and Coordinator (SMO), thereby determining updated scheduling information. In at least one embodiment, one or more processors execute one or more APIs from 5G FAPI and / or variations thereof to perform one or more workloads. Figure 7 Further details regarding the use of the 5G FAPI or its variants to perform one or more workloads have been disclosed.

[0081] At traffic condition determination operation 225, in at least one embodiment, one or more processors or systems executing an application (e.g., an L2 or L2+ application) determine that traffic conditions have changed based on traffic monitoring of the network (e.g., a 5G-NR network supported by a service provider). In at least one embodiment, if one or more processors or systems executing the application determine that traffic conditions have changed (e.g., between day and night, or based on providing new 5G-NR services for different network slices), the one or more processors or systems executing the application determine a new number of cells that can be processed concurrently based on quality parameters (e.g., as in determination operation 205, but with new quality parameters corresponding to the changed traffic conditions). For example, if an application receives a request to change from URLLC to mMTB service, such an application determines new quality parameters based on the new service mMTB and requests to determine the maximum number of cells that resources in L1 can support based on the new quality parameters. In at least one embodiment, the one or more processors or systems executing the application determine that the traffic conditions have not changed, and the one or more processors or systems executing the application determine to continue executing the workload to support 5G-NR cells (e.g., those already mapped by mapping operation 210).

[0082] Following traffic condition determination operation 225, in at least one embodiment, one or more circuits may repeat process 200 or a portion thereof, for example, for a new application requesting the use of the hardware accelerator in L1. In at least one embodiment, traffic condition determination operation 225, including one or more circuits, one or more processors or systems, may terminate process 200 (e.g., the application has been completed to provide 5G-NR service).

[0083] Figure 3 According to at least one embodiment, it includes a network protocol stack 100 for processing (see... Figure 1 A more detailed process flowchart for the workload. (e.g.) Figure 2 The "A" is indicated in the text. Figure 3 Further details are provided regarding whether it can be integrated into process 300 or executed by an API. In at least one embodiment, process 300 is executed by one or more circuits to process the O-RAN network protocol stack (e.g., such as...). Figure 1 The 5G-NR workload of the network protocol stack 100 shown.

[0084] In at least one embodiment, process 300 (or any other process described herein, or variations and / or combinations thereof) is partially or entirely executed under the control of one or more computer systems configured with computer-executable instructions, and is implemented by hardware, software, or a combination thereof as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that executes jointly on one or more processors. In at least one embodiment, at least some of the computer-readable instructions available for executing process 300 are not stored using merely transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, process 300 is executed at least partially on computer systems (such as those described elsewhere in this disclosure). In at least one embodiment, process 300 is executed logically (e.g., by hardware, software, or a combination of hardware and software). In at least one embodiment, process 300 may begin with a call operation 310 and proceed to a response operation 315.

[0085] In at least one embodiment, at call operation 310, the application calls an API to query how many 5G-NR cells one or more L1 resources can support while meeting quality parameters (e.g., threshold QoS). In at least one embodiment, the API is referred to as the "QoS_config" API. In at least one embodiment, the API can receive input parameters, such as a QoS array (pointers to an array of integers) that includes quality parameters corresponding to one or more QoS requirements for processing one or more workloads corresponding to one or more 5G-NR cells. In at least one embodiment, the application calls the API and provides only the QoS array as input to determine how many maximum L1s can be supported while meeting the quality requirements in the QoS array. In at least one embodiment, the application calls the API to send a list of QoS requirements (e.g., [int Q1, int Q2, int Qn], where each QoS value maps to a set of KPIs corresponding to the quality parameters) to the L1 resources via the QoS array. For example, the QoS array can be mapped to one or more KPIs, as follows: Q1 "Latency Mode" refers to the maximum allowed latency limit when processing workloads, which is useful for URLLC; Q2 "Throughput Mode" refers to the minimum user throughput, which is useful for eMBB; Q3 "Reliability Mode" refers to the minimum reliability (calculated in bit error rate (BER) (KPI)), which is useful for mission-critical traffic, such as remote surgery; Q4 "Connectivity Mode" refers to the minimum number of end users per 5G-NR cell, which is useful for mMTC traffic. In at least one embodiment, call operation 310 can be performed to determine several different QoS parameters that the L1 resources can support (e.g., how many 5G-NR cells the resources in L1 can support while meeting latency requirements, and how many 5G-NR cells can be supported simultaneously to meet throughput requirements). In at least one embodiment, other values ​​can be input into the QoS array, such as the number of cells, throughput per cell, number of end users per cell, or combinations of other relevant factors used to process cell workloads.

[0086] In at least one embodiment, the application using the API may provide additional input parameters, such as a maximum cell array (e.g., pointers to an array of integers) corresponding to the maximum number of 5G-NR cells that need to be supported for a specific quality parameter and / or a tier array (e.g., pointers to an array of integers) corresponding to tiers of 5G-NR cells and services with higher or lower priority. In at least one embodiment, the maximum number of 5G-NR cells requested for support, or the cell tiers, or the tiers or workloads, are used by one or more APIs to schedule and process one or more workloads corresponding to one or more 5G-NR cells.

[0087] In at least one embodiment, at response operation 315, the application (e.g., via an API) receives a response from L1 indicating whether L1 can acknowledge the workload to support 5G-NR cells based on quality requirements. In at least one embodiment, based on the response from L1, L2+ can adjust its scheduling strategy; for example, applications in L2+ can schedule for a maximum number of cells less than or equal to the maximum number of cells in L1 that meet a certain quality parameter. In at least one embodiment, response operation 315 includes L1 responding with a simple "1" or "0" to indicate acknowledgment or rejection (acknowledgment may also include allow, enable, accept start, and execute; rejection may include denial, stop, prevent, or block). In at least one embodiment, response operation 315 includes L1 responding with acknowledgment and / or rejection, and includes the maximum number of cells that can be supported while meeting one or more quality parameters (e.g., QoS corresponding to a network slice).

[0088] In at least one embodiment, at scheduling operation 320, one or more processors or systems executing the application may provide the maximum number of cells to the scheduler, allowing the scheduler to make scheduling decisions based on the maximum number of cells. For example, the API may provide the maximum number of 5G-NR cells that it can support while meeting quality thresholds to an L2+ application or hardware device (e.g., SMO) responsible for processing L1 scheduling workloads. In at least one embodiment, scheduling operation 320 is optional, or may be performed prior to scheduling operation 320, such that scheduling is not based on the maximum number of available cells.

[0089] In at least one embodiment, after response operation 315 or scheduling operation 320, one or more processors or systems executing the application may repeat process 300 or portions thereof, for example, for a new application requesting the use of the hardware accelerator in L1. In at least one embodiment, after scheduling operation 320, one or more processors provide a result to process 200 and terminate process 300.

[0090] Figure 4 This is a process flowchart according to at least one embodiment, including more details on processing the workload of the network protocol stack. Figure 2 As indicated by the "B" mark in the document, Figure 4 Provides integration into Process 200 or with Figure 2 Further details regarding the parallel execution of process 400. In at least one embodiment, one or more processors or systems execute process 400 by executing an API. In at least one embodiment, process 400 is executed by one or more circuits to process the O-RAN network protocol stack (e.g., such as...). Figure 1 The 5G-NR workload of the network protocol stack 100 shown.

[0091] In at least one embodiment, part or all of process 400 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented by hardware, software, or a combination thereof as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that executes jointly on one or more processors. In at least one embodiment, at least some of the computer-readable instructions available for executing process 400 are not stored using merely transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, process 400 is executed at least partially on computer systems (such as those described elsewhere in this disclosure). In at least one embodiment, process 400 is executed logically (e.g., hardware, software, or a combination of hardware and software). In at least one embodiment, process 400 may begin with a call operation 410 and proceed to a mapping cell operation 415 (e.g., as...). Figure 2 (Part of mapping operation 210 in process 200).

[0092] In at least one embodiment, at operation 410, where an API is called to map cell workloads, one or more processor or system calls to the API are executed to map a specific 5G-NR cell (e.g., cell ID) to a specific resource in L1. In at least one embodiment, "to map" refers to mapping, allocating, or reserving L1 resources (e.g., hardware accelerators) to support or execute one or more workloads for a 5G-NR cell with a specific cell ID. In at least one embodiment, mapping refers to associating a 5G-NR cell with a specific hardware accelerator or a specific thread or computing resource in L1. For example, an API might be called to map the cell IDs of five 5G-NR cells to five different GPUs, or to map cell IDs to 10,000 different threads supported by different hardware accelerators in L1, where the mapping is based on associating a specific 5G-NR cell to meet the requirements of operation 205. Figure 2 ) or call operation 310 ( Figure 3 The quality parameters established in ) are described. In at least one embodiment, the API may be based on the quality parameters established in the determination operation 205 ( Figure 2 ) or call operation 310 ( Figure 3 The content established in ) maps the cell ID to other characteristics, such as priority, level, or combination.

[0093] In at least one embodiment, at cell mapping operation 415, one or more processors map a specific 5G-NR cell to hardware accelerator resources and respond to the application regarding whether such mapping was successful. In at least one embodiment, at map verification operation 420, one or more processors or systems providing L1 return an array with entries "1" or "0" to indicate whether the mapping was successful. In at least one embodiment, if the mapping is unsuccessful, one or more processors repeat cell mapping operation 415.

[0094] In at least one embodiment, after the verification mapping operation 420, one or more circuits may repeat process 400 or a portion thereof, for example, for a new application requesting the use of the hardware accelerator in L1. In at least one embodiment, after the verification mapping operation 420, one or more processors provide the result of process 400 to process 200 and terminate process 400.

[0095] Figure 5 This is a process flowchart according to at least one embodiment, including more details on processing the workload of the network protocol stack. Figure 2 As indicated by the "C" mark, Figure 5Further details are provided regarding what can be integrated into process 200. In at least one embodiment, process 500 is executed by one or more circuits to process the O-RAN network protocol stack (e.g., such as...). Figure 1 The 5G-NR workload of the network protocol stack 100 shown.

[0096] In at least one embodiment, part or all of process 500 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented by hardware, software, or a combination thereof as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that executes jointly on one or more processors. In at least one embodiment, at least some of the computer-readable instructions available for executing process 500 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transient computer-readable medium does not necessarily include non-transient data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 500 is executed at least partially on a computer system (such as those described elsewhere in this disclosure). In at least one embodiment, process 500 is executed logically (e.g., hardware, software, or a combination of hardware and software). In at least one embodiment, process 500 may begin with a call operation 510 and proceed to a response operation 515.

[0097] At operation 510, which involves calling a selection API, one or more processors or system calls of the application are executed to select a processing algorithm for a workload, wherein the workload is associated with supporting one or more 5G-NR cells, such as those established in process 200 or process 400. In at least one embodiment, one or more processors providing L1 can access a library including different processing algorithms (e.g., one or more technologies) to process a specific workload to meet quality parameters, such as a low-latency algorithm for processing a workload with low-latency quality parameters, or a high-throughput algorithm designed to process a workload to meet high-throughput quality parameters. In at least one embodiment, the API has quality parameters as input, and based on the quality parameters, the API searches a library of algorithms optimized for a specific workload that simultaneously meet the quality parameters. At selection operation 515, one or more processors or systems execute a selection of a processing algorithm based on a call to selection operation 510. In at least one embodiment, the API has a quality parameter as input, and based on the quality parameter, the API searches a library of algorithms optimized for a specific workload that simultaneously satisfy the quality parameter, and the API's response causes one or more processors to select an algorithm.

[0098] In addition to the selection algorithm, in at least one embodiment, one or more processors execute an API to determine a schedule or order for processing workloads (e.g., sequentially or in parallel to meet quality parameters or priorities). For example, if heterogeneous workloads are provided for processing by one or more cells, the API can cause one or more processors to schedule processing to prioritize groups with higher priorities than lower priorities in sequential processing (e.g., based on rank input received from another API). In at least one embodiment, for homogeneous workloads (e.g., without ranks or priorities), another scheduling strategy can be to group workloads based on the direction of data flow (e.g., downlink or uplink) and prioritize the processing of time-sensitive downlink operations over time-insensitive uplink operations.

[0099] In at least one embodiment, at query success operation 520, one or more processors or systems respond to the application via the L2-L1 interface, indicating whether the selection of an algorithm and / or scheduling for priority or rank was successful. For example, after L1 selects an algorithm and determines whether the workload is processed sequentially or in parallel, L1 may respond with "1" to indicate that the workload is being processed and the algorithm selection was successful. In at least one embodiment, if one or more processors determine that the selection was unsuccessful, the one or more processors may call the API again.

[0100] In at least one embodiment, after a successful query operation 520, one or more circuits may repeat process 500 or a portion thereof, for example, for a new application requesting the use of the hardware accelerator in L1. In at least one embodiment, after a successful query operation 520, one or more processors provide the result of process 500 to process 200 and terminate process 400.

[0101] Figure 6 A schematic block diagram of a process 600 for processing workloads according to at least one embodiment is shown. Figure 6 Including application 105 (e.g., from Figure 1 ), L2-L1 interface 115 (e.g., from Figure 1 ), first layer (L1) 605 and hardware accelerator 610 (e.g., from Figure 1The second processor 130). In at least one embodiment, one or more processors or systems execute process 600 when supporting 5G-NR services for multiple 5G-NR cells. In at least one embodiment, application 105 queries L1 605 via L2-L1 interface 115 to determine how many 5G-NR cells resources (e.g., hardware accelerators) in L1 605 can support, as indicated by QoS query 615. In at least one embodiment, the QoS query is based on quality parameters (e.g., latency corresponding to URLLC) and a set of KPIs for satisfying those quality parameters. In response to QoS query 615, L1 605 can respond to application 105 to acknowledge or reject the request to support the 5G-NR workload in QoS response / acknowledgment 620, and it can also respond with the number of cells that can be supported and satisfy the quality parameters (e.g., such as...). Figure 2 and Figure 3 (As discussed in the document). In at least one embodiment, if the request is acknowledged, application 105 communicates via the L2-L1 interface (e.g., using...). Figure 3 , Figure 4 and Figure 5 The L1 605 provides configuration parameters 625 to the L1 605 via the publicly available API. For example, application 105 provides a cell ID for a 5G-NR cell that will be supported by one or more hardware accelerators in the L1 605. After providing a configuration response 635, the L1 605 can assign a specific cell to a thread or hardware accelerator, as shown in operation allocation resource 630. For example, through interface L2-L1, the L1 can reserve a specific hardware accelerator 610 (e.g., 5 GPUs or 1 FPGA) to handle the workload to support the 5G-NR cell.

[0102] In at least one embodiment, L1 605 responds to application 105 with an acknowledgment response 635 via L2-L1 interface 115, for example, whether the mapping from cell ID to specific hardware accelerator 610 was successful. In at least one embodiment, after configuring response 635, application 105 can provide workloads and enqueue (e.g., prepare) workloads using workload enqueue 640. Next, in at least one embodiment, L1 605 selects, as... Figure 2 Algorithm 645 disclosed herein is used to process workloads such that the optimal algorithm is selected based at least on the quality parameters of the workload. For example, if the workloads have similar or identical QoS requirements, L1 can use libraries and drivers to enable the hardware accelerator to select homogeneous workload processing, or L1 can use libraries and drivers to enable the hardware accelerator to select heterogeneous processing algorithms (e.g., one algorithm for processing workloads with low latency QoS requirements and another algorithm for processing different workloads with high throughput requirements).

[0103] In at least one embodiment, L1 605 can select a scheduling mode 650, such as scheduling workload processing sequentially (e.g., processing workload A first, and then processing workload B). In at least one embodiment, based on the selected scheduling mode 650, L1 605 schedules workload processing 655 as sequential 660 (e.g., processing sequential workloads on an FPGA), parallel 665 (e.g., processing different workloads in parallel using a GPU or parallel processor), or a combination of sequential and parallel processing, such that the workload is processed to meet QoS requirements and is processed on time. In at least one embodiment, application 105 can query the status of workload 670 being processed in L1 605 and receive a response regarding the workload processing status 675 (e.g., workload processing has completed, is still in progress, has ended, or there is an error).

[0104] Figure 7 Figure 700 illustrates an Accelerated Abstraction Layer (AAL) interface according to at least one embodiment. In at least one embodiment, the AAL interface is also referred to as AAL, AAL API, AALI, and / or variations thereof. In at least one embodiment, application 105 (e.g., as...) Figure 1 (as disclosed in the document) via L2-L1 interface 115 (e.g., as...) Figure 1 The disclosed method utilizes the Accelerated Abstraction Layer Interface 706 to perform various functions, which are processed by drivers 708A, 708B, and 708C through kernel space 712 to enable hardware 718 (e.g., ... Figure 1 The first processor 125 disclosed herein performs one or more functions. In at least one embodiment, drivers 708A, 708B, and 708C are Figure 1 Drive 120 in the middle.

[0105] In at least one embodiment, application 105 includes one or more computer programs, application software, and / or variations thereof, which execute in connection with one or more layers of a cellular network, such as a 5G-NR network. In at least one embodiment, application 105 includes software that executes in connection with the L2 layer and higher layers (e.g., layers 3-7) of the network (e.g., a 5G-NR cellular network). In at least one embodiment, 5G-NR cellular network is also referred to as a 5G network, a 5G Long Term Evolution (LTE) network, a 5G wireless communication network, 5G, and / or variations thereof; further information regarding 5G cellular networks is available in [the relevant section]. Figures 33 to 46The following disclosure describes the application 105. In at least one embodiment, the application 105 includes various virtualized network functions (VNFs) and / or containerized or cloud-native network functions (CNFs) software applications. In at least one embodiment, the application 105 includes software that executes in relation to the application layer of a fifth-generation cellular network. Further information regarding the layers of a fifth-generation cellular network according to the Open Systems Interconnection (OSI) model is disclosed below.

[0106] In at least one embodiment, VNF refers to a software application that provides various network functions (such as file sharing, directory services, Internet Protocol (IP) configuration, and / or variations thereof) and utilizes a Network Function Virtualization (NFV) architecture. In at least one embodiment, NFV architecture refers to a network architecture in which various network functions and services are virtualized to run on various standardized hardware; further information about NFV can be found in... Figure 48 The description is found therein. In at least one embodiment, CNF refers to a network function provided through one or more container images. In at least one embodiment, a container image refers to an executable software package that includes components sufficient to perform one or more functions and / or processes. In at least one embodiment, the executable software package of the container image includes a minimal set of components for execution to perform one or more functions and / or processes.

[0107] In at least one embodiment, user space is a memory region that executes various application software and drivers. In at least one embodiment, user space, also referred to as user area, includes various software programs, interfaces, and libraries that enable interaction with the kernel. In at least one embodiment, software executing in user space includes input / output communication software, file system manipulation software, application software, and / or variations thereof. In at least one embodiment, processes executing in user space execute in a virtual memory space that cannot access the memory of other processes. In at least one embodiment, user space software 710 refers to software executing in user space. In at least one embodiment, the Accelerated Abstraction Layer Interface 706 and drivers 708A, 708B, and / or 708C execute as user space software 710. In at least one embodiment, user space software 710 executes at layer 1.

[0108] In at least one embodiment, application 105 utilizes accelerated abstraction layer interface 706 via L2-L1 interface 115. In at least one embodiment, L2-L1 interface 115 includes interface 104, which provides one or more interfaces for providing communication methods between L2 and L1. In at least one embodiment, L2-L1 interface 115 includes one or more interfaces, communication protocols, and / or variations thereof, which provide interfaces between various hardware and / or software components of L2 and various hardware and / or software components of Layer 1.

[0109] In at least one embodiment, the Acceleration Abstraction Layer Interface 706 defines various functions utilized by the layer application 105 to perform one or more workloads. In at least one embodiment, the Acceleration Abstraction Layer Interface 706 includes one or more interfaces, functions, and / or processes that provide connectivity to drivers 708A, 708B, and 708C capable of interacting with hardware 718 to enable hardware 718 to perform one or more functions specified in relation to commands submitted via the Acceleration Abstraction Layer Interface 706. In at least one embodiment, hardware 718 is a first processor 125 or a second processor 130. Figure 1 In at least one embodiment, the L2-L1 interface 115 is a 5G FAPI, and the acceleration abstraction layer interface 706 is implemented to process data formatted according to the 5G FAPI. In at least one embodiment, different implementations of the L2-L1 interface 115 correspond to different implementations of the acceleration abstraction layer interface 706, thereby enabling the acceleration abstraction layer interface 706 to process data formatted according to a specific implementation of the L2-L1 interface 115 (e.g., to be vendor-specific or vendor-agnostic).

[0110] In at least one embodiment, the Acceleration Abstraction Layer Interface 706 provides a set of API functions. In at least one embodiment, the Acceleration Abstraction Layer Interface 706 provides at least the Discover function, Initialize function, Create function, Set function, Get function, Destroy function, Enqueue function, Dequeue function, and / or variations thereof, each of which is disclosed in more detail below. In at least one embodiment, the API functions may be compatible with… Figure 3-5 Integrate with or use with the APIs publicly available in the documentation.

[0111] In at least one embodiment, the Discover API call includes no input parameters. In at least one embodiment, the parameters of the Discover API call may include an identifier of the physical device to be analyzed, an identifier of a specific attribute of the physical device to be analyzed, and may further include other parameters that may further define aspects of the available physical devices and their attributes.

[0112] In at least one embodiment, the response to the Discover API call includes a result data structure. In at least one embodiment, the result data structure is a predefined data structure populated with device-related information such as the number of devices, device identifiers, device names, device profiles, device characteristics, and / or variations thereof. In at least one embodiment, the result data structure is a data structure such as an array, a list, and / or variations thereof. In at least one embodiment, following the Discover API call, available physical devices (such as hardware accelerators) are analyzed and a data object including device-specific information is returned. In at least one embodiment, the device-specific information includes information corresponding to physical devices that can be used to handle one or more workloads, network functions, 5G new radio operations, and / or variations thereof.

[0113] In at least one embodiment, the Initialize API function is used to create a context, also referred to as an AAL context, which is a data structure indicating one or more aspects of a workload to be executed on one or more hardware accelerators. In at least one embodiment, the AAL context is also referred to as a PHY context, a context data structure, and / or variations thereof. In at least one embodiment, the AAL context refers to a portion of memory reserved for one or more configurable and queried data objects, also referred to as memory space. In at least one embodiment, the objects of the AAL API may include data objects indicating device / device attributes, task / task attributes, cell / cell attributes, and / or variations thereof. In at least one embodiment, the Initialize API call includes no input parameters. In at least one embodiment, the parameters for the Initialize API call may include an identifier of a specific location in the memory in which the AAL context is reserved, and may further include other parameters that may further define various aspects of the AAL context.

[0114] In at least one embodiment, the response to the Initialize API call includes a context pointer. In at least one embodiment, the context pointer is a pointer to a location in the memory of the AAL context. In at least one embodiment, after the Initialize API call, the location in memory is reserved for the AAL context, and a pointer indicating said location is returned.

[0115] In at least one embodiment, the Create API function is used to create objects in the AAL context. In at least one embodiment, the object can be a data structure and / or an object such as an array, list, and / or variations thereof, and can include cell objects, device objects, task objects, and / or variations thereof. In at least one embodiment, a device data object is a data object that includes device-specific information (e.g., hardware accelerator) such as device capabilities, device attributes, device status, device condition, and / or variations thereof. In at least one embodiment, a task data object is a data object that includes information associated with one or more tasks, workloads, and / or functions (e.g., PHY functions, PHY pipeline, 5G new radio operations, and / or variations thereof) to be performed, such as task attributes, task status, task condition, task priority (e.g., priority value / level), and / or variations thereof. In at least one embodiment, a cell data object is a data object that includes information associated with a cell such as cell attributes, cell status, cell condition, and / or variations thereof. In at least one embodiment, a cell refers to an area or region that provides cellular network services such as fifth-generation cellular networks. In at least one embodiment, a cell refers to an area or region that is part of a cellular network, such as a fifth-generation cellular network, to which data is transmitted and / or received.

[0116] In at least one embodiment, the parameters for the Create API call include a context pointer, an object configuration pointer, and an object identifier, and may further include other parameters that may further define aspects of the object to be created. In at least one embodiment, the context pointer parameter specifies the location of the AAL context, and input to the context pointer parameter may include a pointer to a location in the memory of the AAL context. In at least one embodiment, the object configuration pointer parameter specifies the location of an object configuration data object, which includes configuration information sufficient to configure a particular object, and input to the object configuration pointer parameter may include a pointer to a location in the memory of the object configuration data object. In at least one embodiment, the object configuration data object may be referred to as an object parameter, an object configuration parameter, configuration information, and / or variations thereof, and may be a data structure and / or object such as an array, a list, and / or variations thereof. In at least one embodiment, the configuration information may include information such as an identifier for an object type (e.g., cell, device, task, and / or variations thereof), characteristics of the object or object type, the state / attributes of the object, and / or variations thereof. In at least one embodiment, the object identifier parameter specifies the name of the object to be created, and input to the object identifier parameter may include the name or identifier of the object.

[0117] In at least one embodiment, the response to the Create API call includes an operation status. In at least one embodiment, after a Create API call instructing the creation of a specific object, the object is created at least in part based on an identifier specified by the object identifier parameter and configuration information specified by the object configuration pointer parameter, and is stored in an AAL context specified by the context pointer parameter. In at least one embodiment, an operation status is returned in response to the Create API call to indicate the status of the Create API call. In at least one embodiment, the operation status indicates whether the creation of the object indicated by the Create API call was successful, failed, or whether any other error occurred.

[0118] In at least one embodiment, the Get API function is used to retrieve information about objects within the AAL context. In at least one embodiment, the Get API function is used to perform a query to determine the state and attributes of an object. In at least one embodiment, the object can be a data structure and / or object such as an array, list, and / or variations thereof, and can include cell data objects, device data objects, task data objects, and / or variations thereof. In at least one embodiment, the parameters for the Get API call include a context pointer, an object configuration pointer, an object identifier, and may further include other parameters that can further define various aspects of the information about the object to be retrieved.

[0119] In at least one embodiment, the context pointer parameter specifies the location of the AAL context, and the input to the context pointer parameter may include a pointer to a location in the memory of the AAL context. In at least one embodiment, the object configuration pointer parameter specifies the location in the memory where configuration information is to be stored, and the input to the object configuration pointer parameter may include a pointer to a location in the memory. In at least one embodiment, the object identifier parameter specifies the name of the object about which information is to be retrieved, and the input to the object identifier parameter may include the name or identifier of the object.

[0120] In at least one embodiment, the response to a Get API call includes an operation status. In at least one embodiment, after a Get API call indicating a specific object specified by the object identifier parameter, configuration information for that specific object is retrieved and stored at a location specified by the object configuration pointer parameter. In at least one embodiment, the configuration information may include information such as an identifier for the object type (e.g., cell, device, task, and / or variants thereof), characteristics of the object or object type, the object's state / attributes, and / or variants thereof. In at least one embodiment, an operation status is returned in response to the Get API call to indicate the status of the Get API call. In at least one embodiment, the operation status indicates whether the information retrieval for the object indicated by the Get API call was successful, failed, or whether other errors occurred.

[0121] In at least one embodiment, the Set API function is used to set configuration information for objects in the AAL context. In at least one embodiment, the Set API function is used to change the state of objects, such as activating or deactivating cell data objects. In at least one embodiment, the object can be a data structure and / or object such as an array, list, and / or variations thereof, and can include cell data objects, device data objects, task data objects, and / or variations thereof. In at least one embodiment, parameters for the Set API call can include a context pointer, an object configuration pointer, an object identifier, and may further include other parameters that can further define various aspects of the configuration information of the object to be set.

[0122] In at least one embodiment, the context pointer parameter specifies the location of the AAL context, and the input to the context pointer parameter may include a pointer to a location in the memory of the AAL context. In at least one embodiment, the object configuration pointer parameter specifies a location in the memory where configuration information is stored, and the input to the object configuration pointer parameter may include a pointer to a location in the memory. In at least one embodiment, the configuration information may include information such as an identifier for an object type (e.g., cell, device, task, and / or variants thereof), characteristics of the object or object type, the state / attributes of the object, and / or variants thereof. In at least one embodiment, the configuration information may include information indicating the desired state of the object (e.g., activated or deactivated). In at least one embodiment, the object identifier parameter specifies the name of the object to be configured, and the input to the object identifier parameter may include the name or identifier of the object.

[0123] In at least one embodiment, the response to a Set API call includes an operation status. In at least one embodiment, after a Set API call instructing a specific object specified by the object identifier parameter, configuration information for that specific object is set at least in part based on configuration information specified by the object configuration pointer parameter. In at least one embodiment, an operation status is returned in response to the Set API call to indicate the status of the Set API call. In at least one embodiment, the operation status indicates whether setting the configuration information of the object indicated by the Set API call was successful, failed, or whether some other error occurred.

[0124] In at least one embodiment, the Destroy API function is used to destroy or otherwise delete objects within the AAL context. In at least one embodiment, the object may be a data structure and / or object such as an array, list, and / or variations thereof, and may include cell data objects, device data objects, task data objects, and / or variations thereof. In at least one embodiment, parameters for the Destroy API call may include a context pointer, an object configuration pointer, an object identifier, and may further include other parameters that may further define various aspects of the object to be destroyed.

[0125] In at least one embodiment, the context pointer parameter specifies the location of the AAL context, and the input to the context pointer parameter may include a pointer to a location in the memory of the AAL context. In at least one embodiment, the object configuration pointer parameter specifies the location of an object configuration data object that includes configuration information for a specific object, and the input to the object configuration pointer parameter may include a pointer to a location in the memory of the object configuration data object. In at least one embodiment, the object identifier parameter specifies the name of the object to be destroyed, and the input to the object identifier parameter may include the name or identifier of the object.

[0126] In at least one embodiment, the response to the Destroy API call includes an operation status. In at least one embodiment, after a Destroy API call indicative of a specific object specified by the object identifier parameter, the object is removed from or otherwise destroyed from the AAL context specified by the context pointer parameter. In at least one embodiment, an operation status is returned in response to the Destroy API call to indicate the status of the Destroy API call. In at least one embodiment, the operation status indicates whether the object deletion indicated by the Destroy API call was successful, failed, or whether some other error occurred.

[0127] In at least one embodiment, the Enqueue API function is used to submit one or more physical layer workloads. In at least one embodiment, the Enqueue API call instructs multiple 5G new radio operations. In at least one embodiment, workloads are also referred to as tasks, functions, operations, processes, and / or variations thereof. In at least one embodiment, priorities can be attached to individual workloads. In at least one embodiment, one or more workloads can be executed in parallel or in any specified order (e.g., sequentially and / or based on priority values / levels or other logic) via the Enqueue API function. In at least one embodiment, the parameters of the Enqueue API call may include a context pointer, a slot command, and may further include other parameters that may further define various aspects of the physical layer workload. In at least one embodiment, the Enqueue API function is utilized by various Layer 2-related software (e.g., VNF / CNF software) to submit one or more tasks, workloads, and / or functions to be processed.

[0128] In at least one embodiment, the context pointer parameter specifies the location of the AAL context, and input to the context pointer parameter may include a pointer to a location in memory of the AAL context. In at least one embodiment, the AAL context includes various information about multiple new 5G radio operations, such as the utilization of devices, tasks, cells, and / or variations thereof in relation to performing the multiple new 5G radio operations. In at least one embodiment, the AAL context indicates multiple new 5G radio operations through one or more data objects, such as cell data objects, device data objects, task data objects, and / or variations thereof. In at least one embodiment, the slot command parameter specifies one or more characteristics, parameters, and / or variations thereof of one or more workloads to be processed, and input to the slot command parameter may include a slot command data structure, a pointer to the slot command data structure, and / or variations thereof. In at least one embodiment, the slot command data structure is a data structure that includes configuration information sufficient to process one or more physical layer functions and / or workloads. In at least one embodiment, the slot command data structure includes information sufficient to process one or more uplink and / or downlink physical layer workloads, functions, and / or operations. In at least one embodiment, the slot command data structure includes one or more pointers to one or more buffers for data input / output. In at least one embodiment, the slot command data structure includes various information about one or more tasks to be processed, such as identifiers of the one or more tasks to be processed, the order of the one or more tasks to be processed, priority values ​​and / or levels of the one or more tasks to be processed, and / or variations thereof.

[0129] In at least one embodiment, the response to an Enqueue API call includes an operation status. In at least one embodiment, following an Enqueue API call indicating a specific workload, the specific workload is configured to execute in relation to the AAL context specified by the context pointer parameter and the information specified by the slot command parameter. In at least one embodiment, the Enqueue API call causes one or more workloads, tasks, and / or functions to be executed on one or more hardware accelerators. In at least one embodiment, an operation status is returned in response to the Enqueue API call to indicate the status of the Enqueue API call. In at least one embodiment, the operation status indicates whether the enqueueing of one or more tasks to be executed or performed as indicated by the Enqueue API call was successful, failed, or whether other errors occurred. In at least one embodiment, the operation status may also indicate one or more task identifiers of one or more workloads, tasks, and / or functions to be executed or performed as indicated by the Enqueue API call.

[0130] In at least one embodiment, the Dequeue API function is used to determine the status of one or more enqueued workloads. In at least one embodiment, the Dequeue function is used to determine the completion status of the execution of one or more tasks, workloads, and / or functions. In at least one embodiment, the parameters used for the Dequeue API call include a task identifier and may further include other parameters that may further define various aspects of the physical layer workload.

[0131] In at least one embodiment, the task identifier parameter specifies one or more tasks, workloads, and / or functions that have been queued via the Enqueue API call, and the input to the task identifier parameter may include identifiers of the one or more tasks, workloads, and / or functions. In at least one embodiment, the response to the Dequeue API call includes a task status. In at least one embodiment, after a Dequeue API call indicating one or more tasks, workloads, and / or functions specified by the task identifier parameter, the one or more tasks, workloads, and / or functions are identified, and their status is determined and returned as the task status. In at least one embodiment, the task status indicates whether the execution of one or more tasks, workloads, and / or functions indicated by the Dequeue API call was successful, failed, or whether other errors occurred. In at least one embodiment, the task status may indicate task completion or incompleteness, a measure of task completion, and / or various characteristics of the task.

[0132] In at least one embodiment, driver 708 includes hardware driver 708A, physical layer (PHY) driver 708B, and fronthaul (FH) driver 708C. In at least one embodiment, hardware driver 708A includes one or more interfaces and / or functions enabling communication with hardware accelerators, such as hardware accelerator unit 114. In at least one embodiment, PHY driver 708B includes one or more interfaces and / or functions sufficient to implement various physical layer functions. In at least one embodiment, PHY driver 708B includes one or more interfaces that interact with hardware driver 708A to enable hardware 718 to perform one or more functions and / or procedures. In at least one embodiment, FH driver 708C includes one or more interfaces and / or functions enabling communication with various network hardware and transceivers, such as NIC 135.

[0133] In at least one embodiment, kernel space 712 refers to a memory region in which code execution accesses any other memory and any underlying hardware. In at least one embodiment, kernel space 712 is a memory region in which the kernel runs. In at least one embodiment, kernel refers to one or more computer programs that facilitate interaction between hardware and software components. In at least one embodiment, kernel space 712 refers to code that enables interaction with various hardware, such as hardware 718. In at least one embodiment, the software of user-space software 710 interacts with hardware 718 through one or more processes in kernel space 712. In at least one embodiment, drivers 708A, 708B, and 708C enable hardware 718 to perform various functions and / or processes through kernel space 712.

[0134] Figure 8 Figure 800 illustrates an inline acceleration model according to at least one embodiment. In at least one embodiment, the inline acceleration model is also referred to as an inline acceleration offload architecture, an acceleration abstraction layer inline acceleration model, an end-to-end High-PHY inline acceleration model, and / or variations thereof. In at least one embodiment, the inline acceleration model is a model for accelerating various functions (e.g., 5G-NR operation), wherein per-function acceleration and input / output-based acceleration are performed on a physical interface (e.g., a hardware accelerator) as packets ingress (e.g., enter) and / or egress (e.g., leave). In at least one embodiment, Figure 800 depicts an inline acceleration model in which VNF / CNF software 804 utilizes an acceleration abstraction layer (AAL) interface 706 to perform network functions on a second processor 130 (e.g., a hardware accelerator).

[0135] In at least one embodiment, the second processor 130 is one or more dedicated computer hardware components that process and / or perform various network functions. In at least one embodiment, the second processor 130 includes hardware such as an FPGA, ASIC, DSP, GPU, SoC, and / or variations thereof. In at least one embodiment, the second processor 130 includes a CPU interface 808 that provides functionality to the second processor 130 for processing data received from an AAL interface 706. In at least one embodiment, the CPU interface 808 includes one or more interfaces, communication protocols, and / or variations thereof that provide an interface between the CPU and various CPU-related hardware and / or software components and the various hardware and / or software components of the second processor 130. In at least one embodiment, the CPU interface 808 processes various commands, functions, data, and / or variations thereof from the AAL interface 706.

[0136] In at least one embodiment, functions 812A and 812B are network functions, such as VNF, CNF, and / or variations thereof. In at least one embodiment, functions 812A and 812B represent various new 5G radio operations. In at least one embodiment, functions 812A and 812B represent functions to be processed, wherein processing of said functions can be accelerated by one or more hardware accelerators (such as the second processor 130). In at least one embodiment, functions 812A and 812B are physical layer functions, also referred to as PHY functions, PHY layer functions, PHY layer algorithms, and / or variations thereof.

[0137] In at least one embodiment, the VNF / CNF software 804 utilizes various functions of the AAL interface 706 to perform various functions on the second processor 130. In at least one embodiment, the VNF / CNF software 804 utilizes the Enqueue API functions to perform various functions. In at least one embodiment, the CPU interface 808 receives data from the VNF / CNF software 804 via the AAL interface 706, indicating various data, functions, and / or procedures, and causes the second processor 130 to perform various functions and / or procedures.

[0138] In at least one embodiment, for network functions including transmitting data (e.g., downlink operation), VNF / CNF software 804 utilizes AAL interface 706 to enqueue function 812A to be executed on the hardware accelerator, wherein the second processor 130 executes function 812A in relation to various data from VNF / CNF software 804, wherein the result of function 812A is transmitted to one or more other systems for further processing. In at least one embodiment, data for function 812A (e.g., the result of function 212A) is transmitted via various network interfaces (such as Ethernet interfaces, fronthaul communication interfaces, and / or variations thereof). In at least one embodiment, for network functions including receiving data (e.g., uplink operation), VNF / CNF software 804 utilizes AAL interface 706 to enqueue function 812B to be executed on the hardware accelerator, wherein the second processor 130 receives data from one or more other systems and executes function 812B in relation to the received data, wherein the result of function 812B is provided back to VNF / CNF software 804 for further processing. In at least one embodiment, data of function 812B (e.g., data to be processed by function 812B) is received via various network interfaces such as Ethernet interfaces, fronthaul communication interfaces and / or variations thereof.

[0139] Data Center

[0140] Figure 9 An example data center 900 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940. In at least one embodiment, the application layer 940 includes an application 105, and the application layer 940 can execute... Figures 3 to 6 Publicly disclosed operations, processes, and procedures.

[0141] In at least one embodiment, such as Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources (“nodes CR”) 916(1)-916(N), where “N” represents any integer, a positive integer. In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 916(1)-916(N) may be servers having one or more of the aforementioned computing resources.

[0142] In at least one embodiment, the grouped computing resources 914 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographic locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 914 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0143] In at least one embodiment, resource coordinator 912 may configure or otherwise control one or more nodes CR916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may include a Software Design Infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0144] In at least one embodiment, such as Figure 9As shown, framework layer 920 includes a job scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, framework layer 920 may include a framework of software 932 supporting software layer 930 and / or one or more applications 942 of application layer 940. In at least one embodiment, software 932 or application 942 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 938 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 932 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 900. In at least one embodiment, the configuration manager 934 may be able to configure different layers, such as the software layer 930 and the framework layer 920, which includes Spark and a distributed file system 938 for supporting large-scale data processing. In at least one embodiment, the resource manager 936 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 938 and the job scheduler 932. In at least one embodiment, the cluster or group computing resources may include group computing resources 914 on the data center infrastructure layer 910. In at least one embodiment, the resource manager 936 may coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0145] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least a portion of the nodes CR916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0146] In at least one embodiment, one or more applications 942 included in application layer 940 may include one or more types of applications used by at least a portion of nodes CR916(1)-916(N), grouped computing resources 914, and / or the distributed file system 938 of framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0147] In at least one embodiment, any of the configuration manager 934, resource manager 936, and resource coordinator 912 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 900 and can prevent underutilization and / or poor performance of the data center.

[0148] In at least one embodiment, data center 900 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 900 by using weight parameters calculated through one or more training techniques described herein.

[0149] In at least one embodiment, the data center 900 may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0150] Figure 10A An example of an autonomous vehicle 1000 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1000 executes application 105 (… Figure 1The autonomous vehicle 1000 includes the function of transmitting operations to the 5G-NR network protocol stack for processing. In at least one embodiment, the autonomous vehicle 1000 includes the function of executing... Figures 3 to 6 The process involves one or more processors or systems. In at least one embodiment, the autonomous vehicle 1000 (which may alternatively be referred to herein as "vehicle 1000") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1000 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0151] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In one or more embodiments, vehicle 1000 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1000 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0152] In at least one embodiment, vehicle 1000 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1000 may include, but is not limited to, propulsion system 1050, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to the drivetrain of vehicle 1000, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from throttle / accelerator 1052.

[0153] In at least one embodiment, when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is traveling), the steering system 1054 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1000 (e.g., along a desired path or route). In at least one embodiment, the steering system 1054 may receive signals from the steering actuator 1056. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1046 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1048 and / or brake sensors.

[0154] In at least one embodiment, the controller 1036 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 10A A controller 1036 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, controller 1036 may send signals to operate vehicle braking via brake actuator 1048, to operate steering system 1054 via one or more steering actuators 1056, and to operate propulsion system 1050 via one or more throttles / accelerators 1052. In at least one embodiment, one or more controllers 1036 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1000. In at least one embodiment, one or more controllers 1036 may include a first controller 1036 for autonomous driving functions, a second controller 1036 for functional safety functions, a third controller 1036 for artificial intelligence functions (e.g., computer vision), a fourth controller 1036 for infotainment functions, a fifth controller 1036 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1036 may handle two or more of the above functions, and two or more controllers 1036 may handle a single function and / or any combination thereof.

[0155] In at least one embodiment, one or more controllers 1036, in response to sensor data received from one or more sensors (e.g., sensor inputs), provide signals for controlling one or more components and / or systems of vehicle 1000. In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1058 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more Inertial Measurement Unit (IMU) sensors 1066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 1068, one or more wide-angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360-degree cameras), and remote cameras (…). Figure 10A (not shown in the image), medium-range camera ( Figure 10A (Not shown in the diagram) One or more speed sensors 1044 (e.g., for measuring the speed of vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more brake sensors (e.g., as part of brake sensor system 1046) and / or other sensor types are received.

[0156] In at least one embodiment, one or more controllers 1036 may receive input (e.g., represented by input data) from the dashboard 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, a voice signaler, a speaker, and / or other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 10A The HMI display 1034 may display information such as location data (e.g., the location of vehicle 1000, such as on a map), direction, the location of other vehicles (e.g., occupying a raster), information about objects, and the state of objects sensed by one or more controllers 1036. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0157] In at least one embodiment, vehicle 1000 further includes a network interface 1024 that can communicate over one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, network interface 1024 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0158] Figure 10B The illustration shows an embodiment according to at least one of the embodiments. Figure 10A Examples of camera positions and fields of view for an autonomous vehicle 1000. In at least one embodiment, the camera and its respective field of view are exemplary embodiments and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1000.

[0159] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1000. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent transparent (“RCCC”) color filter array, a red transparent transparent blue (“RCCB”) color filter array, a red blue green transparent (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0160] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0161] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”-printed) assembly, to cut out stray light and reflections from within the vehicle (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0162] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1000 can be used for surround view and, with the assistance of one or more controllers 1036 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0163] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor” color imager. In at least one embodiment, a wide-angle camera 1070 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the street, or bicycles). Although in Figure 10BOnly one wide-angle camera 1070 is shown in the illustration; however, in other embodiments, the vehicle 1000 may have any number (including zero) of wide-angle cameras 1070. In at least one embodiment, any number of remote cameras 1098 (e.g., a pair of remote stereo cameras) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 1098 may also be used for object detection and classification, as well as basic object tracking.

[0164] In at least one embodiment, any number of stereo cameras 1068 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1068 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1000, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1068 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1000 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 may also be used in addition to those described herein.

[0165] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1000 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1074 (e.g., such as...) Figure 10B The four surround cameras 1074 shown can be positioned on the vehicle 1000. In at least one embodiment, one or more surround cameras 1074 may include, but are not limited to, any number and combination of wide-angle cameras 1070, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras may be located at the front, rear, and sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may use three surround cameras 1074 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0166] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1000 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1098 and / or one or more mid-range cameras 1076, one or more stereo cameras 1068, one or more infrared cameras 1072, etc.), as described herein.

[0167] Figure 10C The illustration shows an embodiment according to at least one of the embodiments. Figure 10A A block diagram of an example system architecture for an autonomous vehicle 1000. In at least one embodiment, Figure 10C Each of one or more components, one or more features, and one or more systems of vehicle 1000 is shown as connected via bus 1002. In at least one embodiment, bus 1002 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network within vehicle 1000 used to help control various features and functions of vehicle 1000, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 can be read to find steering wheel angle, ground speed, engine rotation speed ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0168] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses 1002, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1002 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1002 may be used for a collision avoidance function, and a second bus 1002 may be used for actuation control. In at least one embodiment, each bus 1002 may communicate with any component of vehicle 1000, and two or more buses 1002 may communicate with the same component. In at least one embodiment, each of any number of system-on-chip (“SoC”) 1004, each of one or more controllers 1036, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0169] In at least one embodiment, vehicle 1000 may include one or more controllers 1036, such as those described herein. Figure 10A As described above. In at least one embodiment, one or more controllers 1036 can be used for a variety of functions. In at least one embodiment, controller 1036 can be coupled to any of various other components and systems of vehicle 1000 and can be used to control vehicle 1000, artificial intelligence of vehicle 1000, infotainment and / or other functions of vehicle 1000.

[0170] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1006, one or more GPUs 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data storage devices 1016, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1004 may be used to control vehicle 1000 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 may be combined with a high-definition (“HD”) map 1022 in a system (e.g., the system of vehicle 1000), the HD map 1022 being accessible from one or more servers via a network interface 1024. Figure 10C (Not shown in the image) Get map refresh and / or update.

[0171] In at least one embodiment, one or more CPUs 1006 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1006 can be active at any given time.

[0172] In at least one embodiment, one or more CPUs 1006 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (WFI) / Wait for Event (WFE) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1006 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0173] In at least one embodiment, one or more GPUs 1008 may include integrated GPUs (or “iGPUs” herein). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use a compute API. In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0174] In at least one embodiment, one or more GPUs 1008 may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1008 may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0175] In at least one embodiment, one or more GPUs 1008 may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as graphics double data rate type five synchronous random access memory (“GDDR5”), may be used.

[0176] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 1008 to directly access the page tables of one or more CPUs 1006. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1008 experiences a miss, an address translation request can be sent to one or more CPUs 1006. In response, in at least one embodiment, one or more CPUs 1006 can look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1008. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 1006 and one or more GPUs 1008, thereby simplifying the programming of one or more GPUs 1008 and the porting of applications to one or more GPUs 1008.

[0177] In at least one embodiment, one or more GPUs 1008 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 1008 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0178] In at least one embodiment, one or more SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more caches 1012 may include a Level 3 (“L3”) cache available for one or more CPUs 1006 and one or more GPUs 1008 (e.g., connected to CPUs 1006 and GPUs 1008). In at least one embodiment, one or more caches 1012 may include a write-back cache that can, for example, track the state of rows using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0179] In at least one embodiment, one or more SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1008 and offload some tasks from one or more GPUs 1008 (e.g., freeing up more cycles from one or more GPUs 1008 to perform other tasks). In at least one embodiment, one or more accelerators 1014 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0180] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphone 1096; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0181] In at least one embodiment, the DLA can perform any function of one or more GPUs 1008, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1008 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0182] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0183] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0184] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, DMA is capable of supporting any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA is capable of supporting up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0185] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0186] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0187] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0188] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0189] In at least one embodiment, one or more SoCs 1004 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0190] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) have broad applications for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, in an autonomous vehicle, such as vehicle 1000, the PVA may be designed to run classic computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0191] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0192] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0193] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1066 related to the vehicle 1000 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1064 or one or more RADAR sensors 1060).

[0194] In at least one embodiment, one or more SoCs 1004 (e.g., a hardware acceleration cluster) may include one or more data storage devices 1016 (e.g., memory). In at least one embodiment, one or more data storage devices 1016 may be on-chip memory of one or more SoCs 1004, which may store neural networks to be executed on one or more GPUs 1008 and / or DLAs. In at least one embodiment, one or more data storage devices 1016 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1012 may include L2 or L3 caches.

[0195] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1004s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1004s, and / or power state management of one or more SoCs 1004s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1004s may use the ring oscillator to detect the temperature of one or more CPUs 1006s, one or more GPUs 1008s, and / or one or more accelerators 1014s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1004s into a lower power state and / or place the vehicle 1000 into a driver's safe stopping pattern (e.g., bring the vehicle 1000 to a safe stop).

[0196] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0197] In at least one embodiment, one or more processors 1010 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0198] In at least one embodiment, one or more processors 1010 may further include a secure cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1010 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0199] In at least one embodiment, one or more processors 1010 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to generate the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1070, one or more surround cameras 1074, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1004, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0200] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0201] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0202] In at least one embodiment, one or more SoCs of SoC 1004 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1004 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0203] In at least one embodiment, one or more SoCs of SoC 1004 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1004 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1064, one or more RADAR sensors 1060, etc., which may be connected via Ethernet channels), data from bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1004 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1006 from routine data management tasks.

[0204] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data storage devices 1016, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0205] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0206] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU 1020s) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0207] In at least one embodiment, multiple neural networks can run simultaneously for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1008.

[0208] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1000. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0209] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1062, to execute emergency vehicle safety routines, slow down the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0210] In at least one embodiment, vehicle 1000 may include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1004 via high-speed interconnects (e.g., PCIe). In at least one embodiment, for example, one or more CPUs 1018 may include x86 processors. One or more CPUs 1018 may be used to perform any of a variety of functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1004, and / or monitoring the status and health of one or more controllers 1036 and / or on-chip infotainment system (“infotainment SoC”) 1030.

[0211] In at least one embodiment, vehicle 1000 may include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1004 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1020 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1000 (e.g., sensor data).

[0212] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas 1026 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and on the Internet) may be established between vehicle 1000 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles near vehicle 1000 (e.g., vehicles in front, to the side, and / or behind vehicle 1000). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1000.

[0213] In at least one embodiment, network interface 1024 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, network interface 1024 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0214] In at least one embodiment, the vehicle 1000 may further include one or more data storage devices 1028, which may include, but are not limited to, off-chip (e.g., one or more SoC 1004) storage. In at least one embodiment, the one or more data storage devices 1028 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0215] In at least one embodiment, the vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0216] In at least one embodiment, vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, one or more RADAR sensors 1060 may be used by vehicle 1000 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1060 may use a CAN bus and / or bus 1002 (e.g., to transmit data generated by one or more RADAR sensors 1060) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1060 are pulse Doppler RADAR sensors.

[0217] In at least one embodiment, one or more RADAR sensors 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1060 can help distinguish between stationary and moving objects and can be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1060 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1000 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1000 entering or leaving the lane.

[0218] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1060 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1038 for blind spot detection and / or lane change assistance.

[0219] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062, which may be positioned at the front, rear, and / or sides of the vehicle 1000, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1062 may operate at the ASIL B functional safety level.

[0220] In at least one embodiment, vehicle 1000 may include one or more LiDAR sensors 1064. In at least one embodiment, one or more LiDAR sensors 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1064 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1000 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1064 that can use Ethernet (e.g., providing data to a Gigabit Ethernet switch).

[0221] In at least one embodiment, one or more LiDAR sensors 1064 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1064 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such embodiments, one or more LiDAR sensors 1064 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 1000. In at least one embodiment, one or more LiDAR sensors 1064, in such embodiments, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0222] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1000. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from vehicle 1000 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture the reflected laser as intensity data for 3D ranging point clouds and co-registration.

[0223] In at least one embodiment, vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 may be located at the center of the rear axle of vehicle 1000. In at least one embodiment, one or more IMU sensors 1066 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1066 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1066 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0224] In at least one embodiment, one or more IMU sensors 1066 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1066 enable vehicle 1000 to estimate heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1066 without input from magnetic sensors. In at least one embodiment, one or more IMU sensors 1066 and one or more GNSS sensors 1058 can be combined in a single integrated unit.

[0225] In at least one embodiment, vehicle 1000 may include one or more microphones 1096 placed inside and / or around vehicle 1000. In at least one embodiment, in addition, one or more microphones 1096 may be used for emergency vehicle detection and identification.

[0226] In at least one embodiment, vehicle 1000 may further include any number of camera types, including one or more stereo cameras 1068, one or more wide-angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long-range cameras 1098, one or more mid-range cameras 1076, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1000. In at least one embodiment, the type of camera used depends on vehicle 1000. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example, but are not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 10A and Figure 10B Each camera can be described in more detail.

[0227] In at least one embodiment, the vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, the one or more vibration sensors 1042 may measure vibrations of components of the vehicle 1000 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0228] In at least one embodiment, vehicle 1000 may include ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1038 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0229] In at least one embodiment, the ACC system may use one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1000 and automatically adjusts the speed of vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1000 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0230] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1024 and / or one or more wireless antennas 1026 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1000 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1000, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0231] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1060, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual, haptic, and / or rapid braking pulses.

[0232] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0233] In at least one embodiment, when vehicle 1000 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1000 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1000.

[0234] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0235] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1000 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0236] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 1000 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first controller 1036 or the second controller 1036). For example, in at least one embodiment, ADAS system 1038 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1038 may be provided to a monitoring MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0237] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0238] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1004s.

[0239] In at least one embodiment, the ADAS system 1038 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0240] In at least one embodiment, the output of the ADAS system 1038 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0241] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1030 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1000. For example, the infotainment SoC 1030 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, vehicle, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1034, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1030 may be further used to provide information (e.g., visual and / or auditory) to vehicle users, such as information from ADAS system 1038, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0242] In at least one embodiment, the infotainment SoC 1030 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via bus 1002 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1030 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1036 (e.g., the main computer and / or backup computer of the vehicle 1000). In at least one embodiment, the infotainment SoC 1030 may cause the vehicle 1000 to enter a driver-to-safe-stop mode, as described herein.

[0243] In at least one embodiment, vehicle 1000 may further include instrument panel 1032 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1032 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). Instrument panel 1032 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1030 and instrument panel 1032. In at least one embodiment, instrument panel 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0244] Figure 10D It is based on at least one embodiment in a cloud-based server and Figure 10AA diagram of a system 1077 for communication between autonomous vehicles 1000. In at least one embodiment, system 1077 may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but is not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPU 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switch 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPU 1080). GPU 1084, CPU 1080, and PCIe switch 1082 may be interconnected with high-speed cables, such as, but not limited to, NVLink interface 1088 developed by NVIDIA and / or PCIe connection 1086. In at least one embodiment, the GPU 1084 is connected via NVLink and / or NVSwitch SoC, and the GPU 1084 and PCIe switch 1082 are connected via PCIe interconnect. In at least one embodiment, although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1078 may include, but is not limited to, any combination of any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0245] In at least one embodiment, one or more servers 1078 may receive image data representing images from vehicles via one or more networks 1090, the images showing unexpected or changed road conditions, such as recently started roadworks. In at least one embodiment, one or more servers 1078 may transmit neural network 1092, updated neural network 1092, and / or map information 1094, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 1090. In at least one embodiment, updates to map information 1094 may include, but are not limited to, updates to HD map 1022, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1092, updated neural network 1092, and / or map information 1094 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1078 and / or other servers).

[0246] In at least one embodiment, one or more servers 1078 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1090), and / or the machine learning model may be used by one or more servers 1078 to remotely monitor the vehicle.

[0247] In at least one embodiment, one or more servers 1078 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1078 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 may include a deep learning infrastructure in a data center using CPU power.

[0248] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of fast, real-time inference and can use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as image sequences and / or objects located by vehicle 1000 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1000, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1000 is malfunctioning, one or more servers 1078 may signal to vehicle 1000 to instruct the fail-safe computer of vehicle 1000 to take control, notify passengers, and complete a safe stopping operation.

[0249] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference.

[0250] Computer System

[0251] Figure 11 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof 1100 formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, the processor 1102 includes a first processor 125 or a second processor 130, wherein the processor 1102 can execute... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1100 may include, but is not limited to, components such as processor 1102, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1100 may include a processor, such as the PENTIUM® processor family or Xeon processor, available from Intel Corporation of Santa Clara, California. TM Itanium®, XScaleTM and / or StrongARM TM The system may use an Intel® Core™ or Intel® Nervana™ microprocessor, although other systems (including PCs, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0252] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0253] In at least one embodiment, computer system 1100 may include, but is not limited to, processor 1102, which may include, but is not limited to, one or more execution units 1108, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 11 is a single-processor desktop or server system, but in another embodiment, system 11 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to processor bus 1110, which can transmit data signals between processor 1102 and other components in computer system 1100.

[0254] In at least one embodiment, processor 1102 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0255] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1102. In at least one embodiment, the processor 1102 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of the general-purpose processor 1102, along with associated circuitry for executing the instructions, packaged data in the general-purpose processor 1102 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0256] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that can be executed by processor 1102.

[0257] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may direct data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0258] In at least one embodiment, computer system 1100 may use system I / O 1122, which is a proprietary hub interface bus, to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, a data storage 1124, a conventional I / O controller 1123 including a user input and keyboard interface, a serial expansion port 1127 (e.g., Universal Serial Bus (USB)), and a network controller 1134. In at least one embodiment, data storage 1124 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0259] In at least one embodiment, Figure 11 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 11 A system-on-a-chip (SoC) can be shown. In at least one embodiment, Figure 11The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1100 are interconnected using a compute fast link (CXL) interconnect.

[0260] Figure 12 This is a block diagram illustrating an electronic device 1200 utilizing a processor 1210 according to at least one embodiment. In at least one embodiment, the processor 1210 includes a first processor 125 or a second processor 130, wherein the processor 1210 can perform... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, the electronic device 1200 includes a first processor 125 or a second processor 130, wherein the processor 1102 can execute... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0261] In at least one embodiment, system 1200 may include, but is not limited to, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 uses a bus or interface coupling, such as an I²C bus, system management bus (“SMBus”), low pin count (LPC) bus, serial peripheral interface (“SPI”), high-definition audio (“HDA”) bus, serial advanced technology accessory (“SATA”) bus, universal serial bus (“USB”) (versions 1, 2, 3, etc.), or universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 12 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 12 An exemplary system-on-a-chip (SoC) can be illustrated. In at least one embodiment, Figure 12 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0262] In at least one embodiment, Figure 12This may include a display 1224, a touchscreen 1225, a touchpad 1230, a near-field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive “SSD or HDD” 1220 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless LAN unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) 1255, a camera (“USB 3.0 camera”) 1254 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0263] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1246, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1264, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1264 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 may be implemented as next-generation form factors (“NGFF”).

[0264] Figure 13 A computer system 1300 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described in this disclosure. In at least one embodiment, the computer system 1300 includes a first processor 125 or a second processor 130, wherein the computer system 1300 can perform... Figures 3 to 6 The process and procedures disclosed in China.

[0265] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Device Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1304 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1322 provides an interface to other computing devices and networks for receiving data from the computer system 1300 and transferring data to other systems.

[0266] In at least one embodiment, the computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0267] In at least one embodiment, Figure 14 A computer system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1400 includes, but is not limited to, a computer 1410 and a USB stick 1420. In at least one embodiment, the computer system 1400 includes a first processor 125 or a second processor 130, wherein the computer system 1400 can perform... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1410 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0268] In at least one embodiment, the USB stick 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1430 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1430 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0269] In at least one embodiment, the USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic enabling the processing unit 1430 to connect to a device (e.g., computer 1410) via the USB connector 1440.

[0270] Figure 15A An exemplary architecture is illustrated, in which multiple GPUs 1510-1513 are communicatively coupled to multiple multi-core processors 1505-1506 via high-speed links 1540-1543 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, GPUs 1510-1513 are part of a first processor 125 or a second processor 130, wherein GPUs 1510-1513 can perform... Figures 3 to 6 The processes and procedures disclosed herein. In one embodiment, the high-speed links 1540-1543 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0271] Furthermore, in one embodiment, two or more GPUs 1510-1513 are interconnected via high-speed links 1529-1530, which may use the same or different protocols / links as those used for high-speed links 1540-1543. Similarly, two or more multi-core processors 1505-1506 may be connected via high-speed link 1528, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocol / link may be used (e.g., via a common interconnect structure). Figure 15A This shows all communication between the various system components.

[0272] In one embodiment, each multi-core processor 1505-1506 is communicatively coupled to processor memories 1501-1502 via memory interconnects 1526-1527, and each GPU 1510-1513 is communicatively coupled to GPU memories 1520-1523 via GPU memory interconnects 1550-1553. Memory interconnects 1526-1527 and 1550-1553 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1501-1502 and GPU memories 1520-1523 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of processor memories 1501-1502 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0273] As described in this article, although the various processors 1505-1506 and GPUs 1510-1513 can be physically coupled to specific memories 1501-1502 and 1520-1523 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across the various physical memories. For example, processor memories 1501-1502 can each include 64 GB of system memory address space, and GPU memories 1520-1523 can each include 32 GB of system memory address space (resulting in a total addressable memory size of 256 GB in this example).

[0274] Figure 15BAdditional details are shown regarding the interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 according to an exemplary embodiment. The graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed link 1540. Alternatively, the graphics acceleration module 1546 may be integrated on the same package or chip as the processor 1507.

[0275] In at least one embodiment, the processor 1507 shown includes multiple cores 1560A-1560D, each core having a translation back buffer 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components (not shown) for executing instructions and processing data. Caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by the respective groups of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to a system memory 1518, which may include... Figure 15A The processor memory 1501-1502 in the memory.

[0276] Consistency of data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 is maintained via inter-core communication through the consistency bus 1564. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1564 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 1564 to snoop on cache accesses.

[0277] In one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. Specifically, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540 (e.g., PCIe bus, NVLink, etc.), and interface 1537 connects graphics acceleration module 1546 to link 1540.

[0278] In one implementation, the accelerator integrated circuit 1536 represents multiple graphics processing engines 1531, 1532, N of the graphics acceleration module 1546, providing cache management, memory access, context management, and interrupt management services. The graphics processing engines 1531, 1532, N may each include a separate graphics processing unit (GPU). Optionally, the graphics processing engines 1531, 1532, N may selectively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531-1532, N, or the graphics processing engines 1531-1532, N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0279] In one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. The MMU 1539 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1538 may store commands and data for effective access by graphics processing engines 1531-1532,N. In one embodiment, data stored in cache 1538 and graphics memories 1533-1534,M is kept consistent with core caches 1562A-1562D, 1556 and system memory 1514. As previously mentioned, this task can be accomplished via proxy circuitry 1525 representing cache 1538 and graphics memory 1533-1534, M (e.g., sending updates related to the modification / access of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0280] A set of registers 1545 stores the context data of the threads executed by graphics processing engines 1531-1532, N, and context management circuitry 1548 manages the thread context. For example, context management circuitry 1548 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1548 can store the current register value into a designated area in memory (e.g., identified by the context pointer). The register value can then be restored when returning to the context. In one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0281] In one implementation, MMU 1539 translates virtual / effective addresses from graphics processing engine 1531 into real / physical addresses in system memory 1514. One embodiment of accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. Graphics accelerator module 1546 may be dedicated to a single application executing on processor 1507, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 1531-1532, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0282] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system of the graphics acceleration module 1546, providing address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1531-1532.

[0283] Because the hardware resources of graphics processing engines 1531-1532, N are explicitly mapped to the actual address space seen by the host processor 1507, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1536 is to physically separate the graphics processing engines 1531-1532, N, so that they appear as independent units to the system.

[0284] In at least one embodiment, one or more graphics memories 1533-1534, M are coupled to each graphics processing engine 1531-1532, N, respectively. Graphics memories 1533-1534, M store instructions and data, which are processed by each graphics processing engine 1531-1532, N. Graphics memories 1533-1534, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0285] In one embodiment, to reduce data traffic on link 1540, a biasing technique can be used to ensure that the data stored in graphics memories 1533-1534, M is the data most frequently used by graphics processing engines 1531-1532, N, and preferably not used (or at least infrequently used) by cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1531-1532, N) in the core caches 1562A-1562D, 1556 and system memory 1514.

[0286] Figure 15C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, graphics processing engines 1531-1532, N communicate directly with the accelerator integrated circuit 1536 via a high-speed link 1540 through interfaces 1537 and 1535 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 1536 can perform operations related to... Figure 15B The operations described are the same. However, due to its close proximity to the coherence bus 1564 and caches 1562A-1562D, 1556, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1536 and a programming model controlled by graphics acceleration module 1546.

[0287] In at least one embodiment, graphics processing engines 1531-1532, N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1531-1532, N, thereby providing virtualization within a VM / partition.

[0288] In at least one embodiment, graphics processing engines 1531-1532, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1531-1532, N to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1531-1532, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1531-1532, N to provide access to each process or application.

[0289] In at least one embodiment, the graphics acceleration module 1546 or the respective graphics processing engines 1531-1532, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1514 and can be addressed using the effective address to physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1531-1532, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0290] Figure 15D An exemplary accelerator integration slice 1590 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1536. The application’s effective address space 1582 in system memory 1518 stores process element 1583. In one embodiment, process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. Process element 1583 includes the process state of the corresponding application 1580. A job descriptor (WD) 1584 included in process element 1583 may be a single job requested by the application, or may include a pointer to a job queue. In at least one embodiment, WD 1584 is a pointer to a job request queue in the application’s address space 1582.

[0291] The graphics acceleration module 1546 and / or the various graphics processing engines 1531-1532, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1584 to the graphics acceleration module 1546 to begin operations in a virtualized environment.

[0292] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1546 or an individual graphics processing engine 1531. When the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1536 for the owned partition; when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0293] In operation, the WD fetch unit 1591 in the accelerator integrated slice 1590 fetches the next WD 1584, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. Data from the WD 1584 can be stored in register 1545 and used by the MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of the MMU 1539 includes segment / page roaming circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. The interrupt management circuitry 1547 can handle interrupt events 1592 received from the graphics acceleration module 1546. When performing graphics operations, the effective address 1593 generated by the graphics processing engines 1531-1532,N is translated into a real address by the MMU 1539.

[0294] In one embodiment, for each graphics processing engine 1531-1532, N and / or graphics acceleration module 1546, the same set of registers 1545 is copied, and said registers 1545 can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1590. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0295]

[0296] Table 2 shows exemplary registers that can be initialized by the operating system.

[0297]

[0298] In one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531-1532,N. It includes all the information required for the graphics processing engine 1531-1532,N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0299] Figure 15EAdditional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598, in which a list of process elements 1599 is stored. The hypervisor real address space 1598 can be accessed via a hypervisor 1596, which virtualizes the graphics acceleration module engine for operating system 1595.

[0300] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models, wherein the graphics acceleration module 1546 is shared by multiple processes and partitions, time-slice sharing, and graphics-oriented sharing.

[0301] In this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. For the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 may comply with the following: (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1546 must provide a context saving and restoring mechanism; (2) the graphics acceleration module 1546 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1546 provides the ability to preempt job processing; and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1546 must be ensured.

[0302] In at least one embodiment, application 1580 needs to make a system call to operating system 1595 using graphics acceleration module 1546 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1546 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1546 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1546 and can take the form of graphics acceleration module 1546 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1546. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of accelerator integrated circuit 1536 and graphics acceleration module 1546 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1583. In at least one embodiment, the CSRP is one of registers 1545 that includes the effective address of a region in the application's address space 1582 for the graphics acceleration module 1546 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0303] Upon receiving a system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, the operating system 1595 uses the information shown in Table 3 to invoke the hypervisor 1596.

[0304]

[0305] Upon receiving a hypervisor call, hypervisor 1596 verifies that operating system 1595 has been registered and granted permission to use graphics acceleration module 1546. Then, hypervisor 1596 adds process element 1583 to the linked list of process elements of the corresponding graphics acceleration module 1546 type. The process element may include the information shown in Table 4.

[0306]

[0307] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1590 registers 1545.

[0308] like Figure 15F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1501-1502 and GPU memories 1520-1523. In this implementation, operations performed on GPUs 1510-1513 utilize the same virtual / effective memory address space to access processor memories 1501-1502 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501, a second portion to second processor memory 1502, a third portion to GPU memory 1520, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1501-1502 and GPU memories 1520-1523, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0309] In one embodiment, the bias / coherence management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherence between the caches of one or more host processors (e.g., 1505) and the GPUs 1510-1513, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 15F Several instances of bias / coherence management circuitry 1594A-1594E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1505 and / or within the accelerator integrated circuit 1536.

[0310] One embodiment allows GPU-attached memories 1520-1523 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memories 1520-1523 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1505 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memories 1520-1523 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in cases with high streaming write traffic to memory, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1510-1513. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0311] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1510-1513, the bias table can be implemented across the stolen memory range of one or more GPU-attached memories 1520-1523. Alternatively, the entire bias table can be maintained within the GPU.

[0312] In at least one embodiment, prior to actual access to GPU memory, the bias table entry associated with each access to GPU-attached memory 1520-1523 is accessed, causing the following operations: First, a local request from GPUs 1510-1513 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1520-1523. A local request from the GPU to find its page in the host bias is forwarded to processor 1505 (e.g., via the high-speed link described above). In one embodiment, a request from processor 1505 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1510-1513. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, in limited cases, purely hardware-based mechanisms.

[0313] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrations from the host processor 1505 bias to the GPU bias, but not for the reverse migration.

[0314] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1505 cannot cache. To access these pages, the processor 1505 may request access from the GPU 1510, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1505, and vice versa.

[0315] Figure 16 Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0316] Figure 16This is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 is part of a first processor 125 or a second processor 130, wherein the integrated circuit 1600 can perform... Figures 3 to 6 The processes and flows disclosed herein. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic, which includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I... 2 S / I 2 C controller 1640. In at least one embodiment, integrated circuit 1600 may include display device 1645 coupled to one or more of high-definition multimedia interface (HDMI) controller 1650 and mobile industrial processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by flash memory subsystem 1660, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1670.

[0317] Figures 17A-17B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0318] Figures 17A-17B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710, which can be fabricated using one or more IP cores, is illustrated according to at least one embodiment. In at least one embodiment, the graphics processor 1710 is part of a first processor 125 or a second processor 130, wherein the graphics processor 1710 can perform... Figures 3 to 6 The publicly disclosed process or procedure. Figure 17B An additional exemplary graphics processor 1740, which can be fabricated using one or more IP cores, is illustrated according to at least one embodiment. In at least one embodiment, Figure 17A The graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1710 and 1740 may be... Figure 16 A variant of the 1610 graphics processor.

[0319] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0320] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mappings for the graphics processor 1710, including virtual-to-physical address mappings for the vertex processor 1705 and / or fragment processors 1715A-1715N. Besides referencing vertex or image / texture data stored in one or more caches 1725A-1725B, this mapping may also reference vertex or image / texture data stored in memory. In at least one embodiment, one or more MMUs 1720A-1720B may be synchronized with other MMUs within the system, including with… Figure 16One or more application processors 1605, graphics processors 1615, and / or video processors 1620 are associated with one or more MMUs, enabling each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0321] In at least one embodiment, the graphics processor 1740 includes Figure 17A The graphics processor 1710 includes one or more MMUs 1720A-1720B, caches 1725A-1725B, and circuit interconnects 1730A-1730B. In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N-1 and 1755N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1755A-1755N and a tile unit 1758 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0322] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 18A It shows that it can be included in Figure 16 The graphics core 1800 within the graphics processor 1610, and in at least one embodiment, may be as follows: Figure 17B The unified shader cores shown are 1755A-1755N. Figure 18B A highly parallel general-purpose graphics processing unit 1830 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0323] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820, which are shared for execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1800. Slices 1801A-1801N may include supporting logic, including local instruction caches 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFU1812A-1812N), floating-point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double-precision floating-point units (DPFPU 1815A-1815N), and matrix processing units (MPU1817A-1817N).

[0324] In at least one embodiment, the FPU 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1815A-1815N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1812A-1812N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine).

[0325] Figure 18BA general-purpose processing unit (GPGPU) 1830 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 to allocate execution threads associated with those commands to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 can be used as a higher-level cache within the cache memory of computing clusters 1836A-1836H.

[0326] In at least one embodiment, the GPGPU 1830 includes memories 1844A-1844B, which are coupled to the computing cluster 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memories 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0327] In at least one embodiment, each of the computing clusters 1836A-1836H includes a set of graphics cores, for example... Figure 18A The graphics core 1800 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0328] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 1836A-1836H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840, enabling direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1830 reside in a separate data processing system and communicate via network devices accessible through the host interface 1832. In at least one embodiment, GPU link 1840 may be configured to enable connection to a host processor other than or as a replacement for host interface 1832.

[0329] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, when using the GPGPU 1830 for inference, the GPGPU may include fewer compute clusters 1836A-1836H compared to when using the GPGPU to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0330] Figure 19 A block diagram of a computer system 1900 according to at least one embodiment is shown. In at least one embodiment, the computer system 1900 includes a first processor 125 or a second processor 130, wherein the computer system 1900 can perform... Figures 3 to 6The process or flow disclosed herein. In at least one embodiment, the computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904, the system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that enables the computer system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 enables a display controller to provide output to one or more display devices 1910A, the display controller being included in one or more processors 1902. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0331] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to a memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 can be any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1912 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1912 form a graphics processing subsystem that can output pixels to one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, the one or more parallel processors 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B.

[0332] In at least one embodiment, system storage unit 1914 may be connected to I / O hub 1907 to provide a storage mechanism for computer system 1900. In at least one embodiment, I / O switch 1916 may be used to provide an interface mechanism to enable connectivity between I / O hub 1907 and other components, such as network adapter 1918 and / or wireless network adapter 1919 which may be integrated into the platform, and various other devices that can be added via one or more attachment devices 1920. In at least one embodiment, network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0333] In at least one embodiment, the computer system 1900 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1907. In at least one embodiment, the interconnection can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express) or other bus or point-to-point communication interfaces and / or protocols. Figure 19 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0334] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, memory hub 1905, processor 1902, and I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1900 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0335] processor

[0336] Figure 20AA parallel processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, the parallel processor 2000 includes a first processor 125 or a second processor 130, wherein the parallel processor 2000 can perform... Figures 3 to 6 The processes and flows disclosed herein. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is according to exemplary embodiments. Figure 19 The variant of the 1912, which includes one or more parallel processors, is shown.

[0337] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices using a hub or switch interface (e.g., a memory hub 1905). In at least one embodiment, the connection between the memory hub 1905 and the I / O unit 2004 forms a communication link 1913. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0338] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to assign commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is correctly configured and in an active state before assigning tasks to processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2012. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2012 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0339] In at least one embodiment, the processing cluster array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A-2014N of the processing cluster array 2012, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2012. In at least one embodiment, the different clusters 2014A-2014N of the processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0340] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0341] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0342] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0343] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0344] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing cluster array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0345] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0346] In at least one embodiment, any of clusters 2014A-2014N of the processing cluster array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, and clusters 2014A-2014N can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to a memory interface 2018 for communication with I / O unit 2004, and a connection to a local instance of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0347] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0348] Figure 20B This is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is... Figure 20AThis is an example of one of the partitioning units 2020A-2020N. In at least one embodiment, the partitioning unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). The L2 cache 2021 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2025. In at least one embodiment, the frame buffer interface 2025 communicates with memory cells in the parallel processor memory (such as...). Figure 20A It interacts with one of the memory cells 2024A-2024N (e.g., within the parallel processor memory 2022).

[0349] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0350] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A Clusters 2014A-2014N are used instead of partition units 2020. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2016 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 19 One or more display devices 1910) display, routed by processor 1802 for further processing, or by Figure 20A One of the processing entities within the parallel processor 2000 is routed for further processing.

[0351] Figure 20C This is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 20AAn example of one of the processing clusters 2014A-2014N. In at least one embodiment, the processing cluster 2014 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0352] In at least one embodiment, the operation of the processing cluster 2014 can be controlled by a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20A The scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2014 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2014 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data cross switch 2040 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 2040.

[0353] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0354] In at least one embodiment, instructions transmitted to the processing cluster 2014 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2034.

[0355] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use a cache memory within the processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20A The L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0356] In at least one embodiment, each processing cluster 2014 may include a memory management unit (“MMU”) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20AWithin the memory interface 2018. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more specifically, tiling) and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034 or the L1 cache or processing cluster 2014. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0357] In at least one embodiment, the processing cluster 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs a processed task to a data crossbar switch 2040 to provide the processed task to another processing cluster 2014 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2016. In at least one embodiment, a preROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 20A The PreROP 2042 unit is located together with the partition units 2020A-2020N. In at least one embodiment, the PreROP 2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0358] Figure 20D A graphics multiprocessor 2034 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2034 includes a first processor 125 or a second processor 130, wherein the graphics multiprocessor 2034 can perform... Figures 3 to 6The processes and flows disclosed herein. In at least one embodiment, the graphics multiprocessor 2034 is coupled to the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062 and one or more load / store units 2066. The GPGPU cores 2062 and the load / store units 2066 are coupled to the cache memory 2072 and the shared memory 2070 via a memory and cache interconnect 2068.

[0359] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched to instruction unit 2054 for execution. In at least one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2066.

[0360] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2034 (e.g., GPGPU core 2062, load / store unit 2066). In at least one embodiment, register file 2058 is partitioned among each functional unit, such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is partitioned among different thread bundles being executed by graphics multiprocessor 2034.

[0361] In at least one embodiment, each of the GPGPU cores 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0362] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0363] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a cross-switch interconnect that allows the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2072, the thread executing on GPGPU core 2062 can also programmatically store data in shared memory.

[0364] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions included in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0365] Figure 21 A multi-GPU computing system 2100 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 2100 includes a first processor 125 or a second processor 130, wherein the computing system 2100 can perform... Figures 3 to 6The processes and flows disclosed herein. In at least one embodiment, the multi-GPU computing system 2100 may include a processor 2102 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, the host interface switch 2104 is a PCI Express switch device that couples the processor 2102 to a PCI Express bus, through which the processor 2102 can communicate with the GPGPUs 2106A-D. The GPGPUs 2106A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2116. In at least one embodiment, the GPU-to-GPU links 2116 are connected to each of the GPGPUs 2106A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2116 enable direct communication between each of the GPGPUs 2106A-D without communication via the host interface bus 2104 to which the processor 2102 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2116, the host interface bus 2104 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2100 via one or more network devices. While in at least one embodiment, the GPGPUs 2106A-D are connected to the processor 2102 via the host interface switch 2104, in at least one embodiment, the processor 2102 includes direct support for the P2P GPU link 2116 and can be directly connected to the GPGPUs 2106A-D.

[0366] Figure 22 This is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a first processor 125 or a second processor 130, wherein the graphics processor 2200 can perform... Figures 3 to 6 The processes and flows disclosed herein. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated within a multi-core processing system.

[0367] In at least one embodiment, graphics processor 2200 receives multiple batches of commands via ring interconnect 2202. In at least one embodiment, the input commands are interpreted by command streamer 2203 in pipeline front-end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, command streamer 2203 provides commands to geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, command streamer 2203 provides commands to video front-end 2234, which is coupled to media engine 2237. In at least one embodiment, media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2233 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate an execution thread for the thread execution resources provided by at least one graphics core 2280A.

[0368] In at least one embodiment, the graphics processor 2200 includes scalable thread execution resources featuring modular cores 2280A-2280N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2200 may have any number of graphics cores 2280A to 2280N. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, the graphics processor 2200 is a low-power processor having a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A-2280N, each graphics core including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0369] Figure 23 This is a block diagram illustrating a microarchitecture for a processor 2300 according to at least one embodiment, the processor 2300 including logic circuitry for executing instructions. In at least one embodiment, the processor 2300 includes either a first processor 125 or a second processor 130, wherein the processor 2300 can execute... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, processor 2300 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, processor 2310 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled microprocessors employing MMX technology. TMRegisters. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2310 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0370] In at least one embodiment, processor 2300 includes an ordered front end (“front end”) 2301 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2301 may include several units. In at least one embodiment, instruction prefetcher 2326 fetches instructions from memory and provides the instructions to instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2328 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2328 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2330 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters complex instructions, microcode ROM 2332 provides the micro-instructions required to complete the operation.

[0371] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2332. In at least one embodiment, the trace cache 2330 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2332 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 has completed the micro-operation ordering of the instructions, the machine front end 2301 may resume fetching micro-operations from the trace cache 2330.

[0372] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2303 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2303 includes, but is not limited to, an allocator / register renamer 2340, a memory microinstruction queue 2342, an integer / floating-point microinstruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2304, and a simple floating-point scheduler (“simple FP scheduler”) 2306. In at least one embodiment, the fast scheduler 2302, the slow / general-purpose floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to as “microinstruction schedulers 2302, 2304, 2306”. In at least one embodiment, the allocator / register renamer 2340 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2340 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2340 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2342 for memory operations and an integer / floating-point microinstruction queue 2344 for non-memory operations, preceding the memory scheduler 2346 and microinstruction schedulers 2302, 2304, and 2306. In at least one embodiment, the microinstruction schedulers 2302, 2304, and 2306 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2302 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2304 and the simple floating-point scheduler 2306 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2302, 2304, and 2306 arbitrate the scheduling port to schedule microinstructions for execution.

[0373] In at least one embodiment, the execution block b11 includes, but is not limited to, an integer register file / branch network 2308, a floating-point register file / branch network (“FP register file / branch network”) 2310, address generation units (“AGU”) 2312 and 2314, fast arithmetic logic units (“fast ALU”) 2316 and 2318, a slow arithmetic logic unit (“slow ALU”) 2320, a floating-point ALU (“FP”) 2322, and a floating-point movement unit (“FP movement”) 2324. In at least one embodiment, the integer register file / branch network 2308 and the floating-point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310”. In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating-point ALU 2322, and floating-point movement unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0374] In at least one embodiment, register files 2308 and 2310 may be arranged between microinstruction schedulers 2302, 2304, and 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, the integer register file / tribute network 2308 performs integer operations. In at least one embodiment, the floating-point register file / tribute network 2310 performs floating-point operations. In at least one embodiment, each of the register files 2308 and 2310 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2308 and 2310 can communicate data with each other. In at least one embodiment, the integer register file / tribute network 2308 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2310 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0375] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324 can execute instructions. In at least one embodiment, register files 2308 and 2310 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2300 can be, but is not limited to, any number of execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324, and combinations thereof. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2322 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2316 and 2318. In at least one embodiment, the fast ALUs 2316 and 2318 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2320, because the slow ALU 2320 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUS 2312 and 2314. In at least one embodiment, the fast ALU 2316, fast ALU 2318, and slow ALU 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2316, fast ALU 2318, and slow ALU 2320 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 226, etc. In at least one embodiment, the floating-point ALU 2322 and the floating-point movement unit 2324 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2322 and the floating-point movement unit 2324 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0376] In at least one embodiment, microinstruction schedulers 2302, 2304, and 2306 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2300, processor 2300 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0377] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0378] Figure 24 A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2402 or processor cores 2407. In at least one embodiment, system 2400 includes either a first processor 125 or a second processor 130, wherein system 2400 can perform... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, system 2400 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0379] In at least one embodiment, system 2400 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2400 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2400 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0380] In at least one embodiment, each of the one or more processors 2402 includes one or more processor cores 2407 to process instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2407 is configured to process a particular instruction set 2409. In at least one embodiment, the instruction set 2409 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2407 may process a different instruction set 2409, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor core 2407 may also include other processing devices, such as a digital signal processor (DSP).

[0381] In at least one embodiment, processor 2402 includes cache memory 2404. In at least one embodiment, processor 2402 may have a single internal cache or more levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2402. In at least one embodiment, processor 2402 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2407 using known cache coherence techniques. In at least one embodiment, processor 2402 further includes a register file 2406, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2406 may include general-purpose registers or other registers.

[0382] In at least one embodiment, one or more processors 2402 are coupled to one or more interface buses 2410 to transmit communication signals, such as address, data, or control signals, between the processors 2402 and other components in the system 2400. In at least one embodiment, the interface bus 2410 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2410 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2402 includes an integrated memory controller 2416 and a platform controller hub 2430. In at least one embodiment, the memory controller 2416 facilitates communication between memory devices and other components of the processing system 2400, while the platform controller hub (PCH) 2430 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0383] In at least one embodiment, memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2420 may be used as system memory of processing system 2400 to store data 2422 and instructions 2421 for use when one or more processors 2402 execute an application or process. In at least one embodiment, memory controller 2416 is also coupled to an optional external graphics processor 2412, which may communicate with one or more graphics processors 2408 of processor 2402 to perform graphics and media operations. In at least one embodiment, display device 2411 may be connected to processor 2402. In at least one embodiment, display device 2411 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2411 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0384] In at least one embodiment, the platform controller hub 2430 enables peripheral devices to connect to the storage device 2420 and the processor 2402 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2446, a network controller 2434, a firmware interface 2428, a wireless transceiver 2426, a touch sensor 2425, and a data storage device 2424 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2424 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2425 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2426 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2428 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2434 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2410. In at least one embodiment, audio controller 2446 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2400 includes an optional legacy I / O controller 2440 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 2430 may also be connected to one or more Universal Serial Bus (USB) controllers 2442 that connect input devices, such as a keyboard and mouse combination 2443, a camera 2444, or other USB input devices.

[0385] In at least one embodiment, instances of the memory controller 2416 and platform controller hub 2430 may be integrated into a discrete external graphics processor, such as external graphics processor 2412. In at least one embodiment, the platform controller hub 2430 and / or the memory controller 2416 may be external to one or more processors 2402. For example, in at least one embodiment, system 2400 may include external memory controller 2416 and platform controller hub 2430, which may be configured as a memory controller hub and peripheral controller hub in a system chipset communicating with processor 2402.

[0386] Figure 25This is a block diagram of a processor 2500 having one or more processor cores 2502A-2502N, an integrated memory controller 2514, and an integrated graphics processor 2508 according to at least one embodiment. In at least one embodiment, the processor 2500 includes either a first processor 125 or a second processor 130, wherein the processor 2500 is capable of performing... Figures 3 to 6 The processes and procedures disclosed herein. In at least one embodiment, processor 2500 may include additional cores, up to and including additional cores 2502N indicated by dashed boxes. In at least one embodiment, each processor core 2502A-2502N includes one or more internal cache units 2504A-2504N. In at least one embodiment, each processor core may also access one or more shared cache units 2506.

[0387] In at least one embodiment, internal cache units 2504A-2504N and shared cache unit 2506 represent a cache memory hierarchy within processor 2500. In at least one embodiment, cache memory units 2504A-2504N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2506 and 2504A-2504N.

[0388] In at least one embodiment, the processor 2500 may further include a set of one or more bus controller units 2516 and a system agent core 2510. In at least one embodiment, one or more bus controller units 2516 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2510 provides management functions for various processor components. In at least one embodiment, the system agent core 2510 includes one or more integrated memory controllers 2514 to manage access to various external memory devices (not shown).

[0389] In at least one embodiment, one or more processor cores 2502A-2502N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2510 includes components for coordinating and operating cores 2502A-2502N during multi-threaded processing. In at least one embodiment, system agent core 2510 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2502A-2502N and graphics processor 2508.

[0390] In at least one embodiment, processor 2500 further includes a graphics processor 2508 for performing graph processing operations. In at least one embodiment, graphics processor 2508 is coupled to a shared cache unit 2506 and a system proxy core 2510 including one or more integrated memory controllers 2514. In at least one embodiment, system proxy core 2510 further includes a display controller 2511 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2511 may also be a separate module coupled to graphics processor 2508 via at least one interconnect, or it may be integrated within graphics processor 2508.

[0391] In at least one embodiment, ring-based interconnect unit 2512 is used to couple internal components of processor 2500. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2508 is coupled to ring interconnect 2512 via I / O link 2513.

[0392] In at least one embodiment, I / O link 2513 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2518 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2502A-2502N and graphics processor 2508 uses embedded memory module 2518 as a shared last-level cache.

[0393] In at least one embodiment, processor cores 2502A-2502N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2502A-2502N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2502A-2502N executing a common instruction set, while one or more other processor cores 2502A-2502N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2502A-2502N are heterogeneous in terms of microarchitectu...

Claims

1. A processor, comprising: Circuit, used for: Receive application programming interface (API) calls that indicate the number and quality parameters of 5G-NR cells; as well as In response to the API call, based at least in part on the quality parameters, it is determined whether one or more workloads corresponding to at least one of the indicated number of 5G-NR cells will be offloaded to be processed by one or more graphics processing units (GPUs), the quality parameters corresponding to the ability of the one or more GPUs to concurrently execute the indicated number of 5G-NR cells while satisfying the quality parameters. The circuitry is configured to perform data communication between a first layer and a second layer corresponding to the 5G-NR network protocol stack in response to the API call, wherein the second layer is configured to determine, at least in part, whether to offload the one or more workloads corresponding to at least one of the indicated number of 5G-NR cells to the first layer for processing by the one or more GPUs, based on the quality parameters provided from the second layer to the first layer.

2. The processor of claim 1, wherein the quality parameter corresponds to the one or more GPUs processing the one or more workloads to at least satisfy the quality parameter, and wherein the indicated number of 5G-NR cells corresponds to the maximum number of 5G-NR cells that the first layer can concurrently support at least in part based on the quality parameter.

3. The processor of claim 1, wherein the quality parameter corresponds to the latency, throughput, reliability, or connectivity of processing the one or more workloads corresponding to the 5G-NR cell.

4. The processor of claim 1, wherein the quality parameter is based on receiving a notification that 5G-NR network traffic conditions have changed, and the second layer is configured to determine whether the first layer is capable of handling the one or more workloads and to satisfy the quality parameter at least in part based on the changed 5G-NR network traffic conditions.

5. The processor of claim 1, wherein the first layer is configured to provide the second layer with, via the API call, the maximum number of 5G cells that the first layer can support, at least in part, based on the quality parameters.

6. The processor of claim 1, wherein the quality parameter corresponds to a performance index for processing the one or more workloads to satisfy the quality parameter.

7. The processor of claim 1, wherein the circuitry is configured to refuse to process one or more workloads in response to the API call, based on an indication from the first layer that it cannot satisfy the quality parameters corresponding to any number of 5G-NR cells.

8. The processor of claim 1, wherein the response to the API call corresponds to the confirmation or rejection of the one or more workloads to be processed by the one or more GPUs to meet the quality parameters.

9. The processor of claim 1, wherein the one or more workloads correspond to a slice of a 5G-NR network.

10. The processor of claim 9, wherein the 5G-NR network slice provides services corresponding to at least one of enhanced mobile broadband (eMBB) operation, ultra-reliable low-latency communication (URLLC) operation, massive machine-type communication (mMTC) operation, or vehicle-to-everything (V2X) operation.

11. A system for fifth-generation new radio (5G-NR) operation, comprising a memory for storing instructions, said instructions being the result of execution by one or more processors, causing the system to: Receive application programming interface (API) calls that indicate the number and quality parameters of 5G-NR cells; In response to the API call, based at least in part on the quality parameters, it is determined whether one or more workloads corresponding to at least one of the indicated number of 5G-NR cells are offloaded to be processed by one or more graphics processing units (GPUs), the quality parameters corresponding to the ability of the one or more GPUs to concurrently execute the indicated number of 5G-NR cells while satisfying the quality parameters; Data communication is performed between the first and second layers corresponding to the 5G-NR network protocol stack; and The determination of whether to offload one or more workloads corresponding to at least one of the indicated number of 5G-NR cells to the first layer for processing by the one or more GPUs is based at least in part on the quality parameters provided from the second layer to the first layer.

12. The system of claim 11, wherein the quality parameter corresponds to the one or more GPUs processing the one or more workloads to at least satisfy the quality parameter, and wherein the indicated number of 5G-NR cells corresponds to the maximum number of 5G-NR cells that the first layer can concurrently support at least in part based on the quality parameter.

13. The system of claim 11, wherein the quality parameter corresponds to the latency, throughput, reliability, or connectivity of processing the one or more workloads corresponding to the 5G-NR cell.

14. The system of claim 11, wherein the one or more processors include one or more graphics processing units (GPUs).

15. The system of claim 11, wherein the quality parameter corresponds to a performance index for processing the one or more workloads to satisfy the quality parameter.

16. The system of claim 11, wherein the first layer is configured to provide the second layer with, via the API call, the maximum number of 5G cells that the first layer can support, at least in part, based on the quality parameters.

17. The system of claim 11, further comprising: Based on the indication from the first layer, it cannot meet the response of the quality parameters corresponding to the indicated number of 5G-NR cells and therefore refuses to process one or more workloads.

18. The system of claim 11, wherein the response to the API call corresponds to the confirmation or rejection of the one or more workloads to be processed by the one or more GPUs to meet the quality parameters.

19. The system of claim 11, wherein the one or more workloads correspond to a slice of a 5G-NR network.

20. The system of claim 19, wherein the 5G-NR network slice provides services corresponding to at least one of enhanced mobile broadband (eMBB) operation, ultra-reliable low-latency communication (URLLC) operation, massive machine-type communication (mMTC) operation, or vehicle-to-everything (V2X) operation.

21. A machine-readable medium having stored thereon one or more instructions, said one or more instructions, if executed by one or more processors, causing one or more processors to at least: Receive application programming interface (API) calls that indicate the number and quality parameters of 5G-NR cells; In response to the API call, at least in part based on the quality parameters, it is determined whether one or more workloads corresponding to at least one of the indicated number of 5G-NR cells will be offloaded to be processed by one or more graphics processing units (GPUs), the quality parameters corresponding to capability information associated with concurrently executing the indicated number of 5G-NR cells while satisfying the quality parameters; Data communication is performed between the first and second layers corresponding to the 5G-NR network protocol stack; and The determination of whether to offload one or more workloads corresponding to at least one of the indicated number of 5G-NR cells to the first layer for processing by the one or more GPUs is based at least in part on the quality parameters provided from the second layer to the first layer.

22. The machine-readable medium of claim 21, wherein the quality parameter corresponds to at least one of latency, throughput, reliability, or connectivity in processing the one or more workloads.

23. The machine-readable medium of claim 21, wherein the one or more processors include one or more graphics processing units (GPUs).

24. The machine-readable medium of claim 21, wherein the quality parameter corresponds to a performance index for processing the one or more workloads to satisfy the quality parameter.

25. The machine-readable medium of claim 21, wherein the one or more instructions further cause the one or more processors to at least: The API call provides the maximum number of 5G cells that the first layer can support, at least in part, based on the quality parameters, from the first layer to the second layer.

26. The machine-readable medium of claim 21, wherein the one or more instructions further cause the one or more processors to at least: Based on the indication from the first layer that it cannot meet the response of the quality parameters corresponding to the number of the 5G-NR cells, it refuses to process one or more workloads.

27. The machine-readable medium of claim 21, wherein the response to the API call corresponds to an acknowledgment or rejection of the one or more workloads to be processed by the one or more GPUs to meet the quality parameters.

28. A method for operating fifth-generation new radio (5G-NR), comprising: Receive application programming interface (API) calls that indicate the number and quality parameters of 5G-NR cells; In response to the API call, at least in part based on the quality parameters, it is determined whether one or more workloads corresponding to at least one of the indicated number of 5G-NR cells will be offloaded to be processed by one or more graphics processing units (GPUs), the quality parameters corresponding to whether the one or more GPUs can concurrently execute the indicated number of 5G-NR cells while satisfying the quality parameters; Data communication is performed between the first and second layers corresponding to the 5G-NR network protocol stack; and The determination of whether to offload one or more workloads corresponding to at least one of the indicated number of 5G-NR cells to the first layer for processing by the one or more GPUs is based at least in part on the quality parameters provided from the second layer to the first layer.

29. The method of claim 28, wherein the quality parameter corresponds to a performance index for processing the one or more workloads to satisfy the quality parameter.

30. The method of claim 28, further comprising: The API call provides the maximum number of 5G cells that the first layer can support, at least in part, based on the quality parameters, from the first layer to the second layer.

31. The method according to claim 28, further comprising: Based on the indication from the first layer that it cannot meet the response of the quality parameters corresponding to the number of the 5G-NR cells, it refuses to process one or more workloads.

32. The method of claim 28, wherein the response to the API call corresponds to an acknowledgment or rejection of the one or more workloads to be processed by the one or more GPUs to meet the quality parameters.

33. The method of claim 28, wherein the one or more workloads correspond to a slice of a 5G-NR network, and wherein the 5G-NR slice provides services corresponding to at least one of enhanced mobile broadband (eMBB) operation, ultra-reliable low-latency communication (URLLC) operation, massive machine-type communication (mMTC) operation, or vehicle-to-everything (V2X) operation.

34. The method of claim 28, further comprising: The ability of one or more GPUs to satisfy the quality parameters for communication from the first layer to the second layer via the API call is at least in part used to confirm or reject one or more workloads to be processed by the one or more GPUs, wherein the API call is used for data communication between the first layer and the second layer corresponding to the 5G-NR network protocol stack.

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