Pulse frequency division output method and system

Abstract

This invention relates to the field of AC servo system technology, specifically to an FPGA-based method and system for frequency division output of position feedback pulses from an AC servo serial communication encoder. The method includes the following steps: periodically reading encoder position feedback data and calculating the difference between the position feedback data read in the current cycle and the position feedback data read in the previous cycle; converting the difference in position feedback data into a uniformly distributed pulse signal PCLK within the encoder position feedback data sampling period; using the pulse signal PCLK as a trigger clock to perform DDA calculation on the required number of output pulses per revolution, changing the state of the quadrature output pulses each time an overflow occurs, thereby generating frequency-divided quadrature pulse signals A and B. This invention provides an FPGA-based method for frequency division output of position feedback pulses from an AC servo serial communication encoder, which can realize frequency division output of serial communication encoder position feedback pulses according to the requirements of a host device.

Description

Technical Field

[0001] This invention relates to the field of AC servo system technology, specifically to an FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method and system. Background Technology

[0002] Encoders are among the most commonly used detection devices in various types of machinery. Based on their signal principles, they can be divided into incremental encoders and absolute encoders. Incremental encoders suffer from problems such as cumulative zero-point error, poor anti-interference, the need for power-off memory when the receiving device is stopped, and the need to find zero or a reference position upon startup. Absolute encoders are significantly superior to incremental encoders in positioning, but due to their high precision and large number of output bits, if parallel output is used, each output signal must be securely connected. For complex operating conditions, isolation is also required, resulting in a large number of connecting cable cores. This leads to numerous inconveniences and reduced reliability. Therefore, absolute encoders generally use serial output.

[0003] In high-precision AC servo systems, motors typically employ high-resolution absolute encoders for position feedback via serial communication. In many applications, it is required to convert motor encoder position data into pulse outputs to a host device. This usually requires the servo system to output two orthogonal signals A and B, and a home signal Z. For absolute encoders, since their output is position data, the challenge lies in how to output frequency-divisible encoder position feedback pulses according to the host device's requirements. Furthermore, this invention addresses existing problems in feedback pulse frequency division, such as inaccurate pulse count, output pulse frequency not adapting to changes in encoder feedback values, maximum divided pulse value being lower than the encoder's single-turn value, and the inability to modify the phase relationship of the two orthogonal signals A and B. Summary of the Invention

[0004] This invention addresses the technical problem in existing AC servo systems that cannot achieve frequency division output of serial communication encoder position feedback pulses according to the requirements of the host device. It provides an FPGA-based method and system for frequency division output of AC servo serial communication encoder position feedback pulses. This method can achieve frequency division output of serial communication encoder position feedback pulses according to the requirements of the host device, and the number of frequency division pulses is accurate, the output pulse frequency strictly follows the changes in the encoder feedback value, the maximum value of the frequency division pulse is not less than the encoder single-turn value, and the phase relationship of the two output orthogonal signals A and B pulses can be changed.

[0005] The technical solution adopted in this invention is as follows:

[0006] A method for frequency division output of position feedback pulse from an AC servo serial communication encoder based on FPGA, comprising the following steps:

[0007] S1: Periodically read encoder position feedback data and calculate the difference between the position feedback data read in this cycle and the position feedback data read in the previous cycle;

[0008] S2: Using the DDA algorithm, the difference in the position feedback data is converted into a uniformly distributed pulse signal PCLK within the encoder position feedback data sampling period.

[0009] S3: Using the pulse signal PCLK as the trigger clock, perform DDA calculation on the number of output pulses per revolution required for output. Change the state of the quadrature output pulse once for each overflow, thereby generating frequency-divided quadrature pulse signal A and frequency-divided quadrature pulse signal B.

[0010] Furthermore, the method further includes the following steps:

[0011] S4: Simultaneously count the pulse signal PCLK, and when the count value is equal to the preset zero position value, output the zero pulse signal Z.

[0012] Furthermore, step S1 specifically includes the following steps:

[0013] S11: Detects the rising edge of the encoder feedback data sampling period update signal to generate clock signal CK625;

[0014] S12: When the servo system is powered on and initialized, it reads the encoder position feedback data and writes the initial encoder position value to the frequency division output pulse number calculation module within the sampling period as the initial value of the encoder's current position value.

[0015] S13: Using the clock signal CK625 as the trigger signal, the current position value of the encoder is written into the frequency division output pulse number calculation module within the sampling period;

[0016] S14: Calculate the position pulse deviation to be output within the current clock cycle by using the difference between the position feedback data from the two samples.

[0017] Furthermore, step S2 specifically includes the following steps:

[0018] S21: Calculate the DDA factor, and generate the clock signal PGCK by dividing the system clock frequency. The frequency of the clock signal PGCK is equal to the frequency of the clock signal CK625 multiplied by the DDA factor.

[0019] S22: Write the position pulse deviation and DDA factor into the frequency divider pulse generator module, and use the clock signal PGCK as the trigger signal to accumulate the position pulse deviation. When the accumulated sum exceeds the DDA factor, it overflows and generates a uniformly distributed pulse signal PCLK.

[0020] Furthermore, step S3 specifically includes the following steps:

[0021] S31: Send the pulse signal PCLK to the quadrature output pulse generation module and write the number of output pulses per revolution into the quadrature output pulse generation module;

[0022] S32: Using the pulse signal PCLK as the accumulating clock, the number of output pulses per revolution is accumulated and counted, using 2 N As the criterion for accumulating overflow, N is the number of valid bits for encoder position feedback. Each overflow changes the state of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B. The phase relationship between the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B can be changed by inverting the pulse output signal.

[0023] Furthermore, step S4 specifically includes the following steps:

[0024] S41: The pulse signal PCLK is sent to the output pulse counter module to store the count value; when the count value is equal to the set zero position value, the zero point Z signal output counter module 7 generates the zero point pulse signal Z; the zero point Z signal output counter module can be controlled to work by outputting the Z signal enable signal.

[0025] Another aspect of the present invention provides an FPGA-based AC servo serial communication encoder position feedback pulse frequency division output system, comprising a first clock module, a second clock module, a frequency division output pulse count calculation module within a sampling period, a frequency division pulse generator module, a quadrature output pulse generation module, an output pulse counter module, and a zero-position Z signal output counter module, wherein...

[0026] The first clock module is used to generate the clock signal CK625 based on the rising edge of the update signal according to the sampling period of the encoder feedback data.

[0027] The second clock module is used to divide the system clock to generate the clock signal PGCK;

[0028] The frequency division output pulse number calculation module within the sampling period is used to calculate the encoder position pulse deviation between two samples under the trigger of clock signal CK625;

[0029] The frequency divider pulse generator module is used to accumulate the position pulse deviation with the clock signal PGCK as the trigger signal. When the accumulated sum exceeds the DDA factor, it overflows and generates a uniformly distributed pulse signal PCLK.

[0030] The quadrature output pulse generation module uses the pulse signal PCLK as the accumulation clock to accumulate and count the number of output pulses per revolution, using 2 NAs the criterion for judging the accumulation overflow, N is the number of valid bits of encoder position feedback. Each overflow changes the state of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B once. The phase relationship of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B can be changed by inverting the pulse output signal.

[0031] The output pulse counter module is used to count and store the pulse signal PCLK; the zero-point Z signal output counter module generates the zero-point pulse signal Z when the count value is equal to the set zero-point position value; the zero-point Z signal output counter module can be controlled to work by outputting an enable signal through the Z signal.

[0032] Furthermore, the FPGA used is the EG4X20 from Anlu Company.

[0033] The beneficial effects of the present invention are as follows: The present invention provides an FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method and system, which can realize the serial communication encoder position feedback pulse frequency division output according to the requirements of the host device. Moreover, the number of frequency division pulses is accurate, the output pulse frequency strictly follows the change of encoder feedback value, the maximum value of the frequency division pulse is not lower than the encoder single-turn value, and the phase relationship of the two output orthogonal signal A and B pulses can be changed. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the position feedback pulse frequency division output system of the FPGA-based AC servo serial communication encoder of the present invention.

[0036] Among them, the first clock module-1, the second clock module-2, the frequency division output pulse number calculation module-3, the frequency division pulse generator module-4, the quadrature output pulse generation module-5, the output pulse counter module-6, and the zero position Z signal output counter module-7 are all included. Detailed Implementation

[0037] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0038] like Figure 1 As shown, this invention provides a method for frequency division output of position feedback pulses from an AC servo serial communication encoder based on an FPGA. The method includes the following steps:

[0039] S1: Periodically read encoder position feedback data and calculate the difference between the position feedback data read in this cycle and the position feedback data read in the previous cycle;

[0040] S2: The DDA algorithm is used to convert the difference in position feedback data into a uniformly distributed pulse signal PCLK within the encoder position feedback data sampling period.

[0041] S3: Using the pulse signal PCLK as the trigger clock, perform DDA calculation on the number of output pulses per revolution required for output. Change the state of the quadrature output pulse once for each overflow, thereby generating frequency-divided quadrature pulse signal A and frequency-divided quadrature pulse signal B.

[0042] Thus, the FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method provided by this invention converts the position deviation within the encoder feedback data sampling period into a uniformly distributed pulse signal PCLK. Then, using the pulse signal PCLK as a trigger clock, the required output pulse number per revolution is calculated using DDA. Each overflow changes the state of the quadrature output pulse, thereby enabling the serial communication encoder position feedback pulse frequency division output to be realized according to the requirements of the host device. Furthermore, the number of pulse frequency divisions is accurate, the output pulse frequency strictly follows the changes in the encoder feedback value, and the maximum value of the frequency division pulse is not lower than the single revolution value of the encoder.

[0043] Furthermore, the FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method of the present invention further includes the following steps:

[0044] S4: Simultaneously count the pulse signal PCLK. When the count value equals the preset zero position value, output the zero pulse signal Z.

[0045] Thus, by counting the pulse signal PCLK, when the count value equals the preset zero position, the zero-point pulse signal Z is output. This achieves the function of outputting two orthogonal signals A and B and the origin signal Z to the host device.

[0046] In a preferred embodiment of the present invention, step S1 specifically includes the following steps:

[0047] S11: Detect the rising edge of the encoder feedback data sampling period update signal CK625_TRG to generate the clock signal CK625; (e.g., ...) Figure 1 As shown, edge detection is performed by the first clock module 1;

[0048] S12: When the servo system is powered on and initialized, it reads the encoder position feedback data and writes the encoder initial position value UD_INT_DAT to the frequency division output pulse number calculation module 3 within the sampling period as the initial value of the encoder current position value POS_SET_DAT.

[0049] S13: Using the clock signal CK625 as the trigger signal, write the encoder's current position value POS_SET_DAT into the frequency division output pulse number calculation module 3 within the sampling period;

[0050] S14: Calculate the position pulse deviation DIFF_DAT to be output within the current CK625 clock cycle by using the data difference between the two sampled current position values ​​POS_SET_DAT. Write this position pulse deviation DIFF_DAT into the frequency divider pulse generator module 4.

[0051] Furthermore, as a preferred embodiment of the present invention, step S2 specifically includes the following steps:

[0052] S21: Calculate the DDA factor MAX_DDA_DAT, and generate the clock signal PGCK by dividing the system clock SYSCLK. The frequency of the clock signal PGCK is equal to the frequency of the clock signal CK625 multiplied by the DDA factor MAX_DDA_DAT.

[0053] Assuming the encoder feedback data sampling period is T (unit: μs), based on the encoder's maximum speed V (unit: rpm) and the number of effective bits N in the encoder position feedback, calculate the DDA factor MAX_DDA_DAT, where MAX_DDA_DAT ≥ [V / (60 1000 1000) T; The second clock module 2 divides the system clock SYSCLK to generate the clock signal PGCK. The frequency of the clock signal PGCK is equal to the frequency of the clock signal CK625 multiplied by the DDA factor MAX_DDA_DAT.

[0054] S22: The position pulse deviation DIFF_DAT and the DDA factor MAX_DDA_DAT are written into the frequency divider pulse generator module 4. The position pulse deviation DIFF_DAT is accumulated using the clock signal PGCK as the trigger signal. When the accumulated sum exceeds the DDA factor MAX_DDA_DAT, it overflows, generating a uniformly distributed pulse signal PCLK, i.e. Figure 1 The intermediate pulse signal PN_UD_CNT_EN converts the position deviation into a uniformly distributed pulse output. This pulse signal PCLK is then sent to the quadrature output pulse generation module 5 and the output pulse counter module 6, respectively.

[0055] Furthermore, as a preferred embodiment of the present invention, step S3 specifically includes the following steps:

[0056] S31: Send the pulse signal PCLK to the quadrature output pulse generation module 5, and write the number of output pulses per revolution DIVCSEV into the quadrature output pulse generation module 5; the number of output pulses per revolution DIVCSEV is 4 times the number of frequency-divided quadrature pulse signals A or B per revolution.

[0057] S32: Using the pulse signal PCLK as the DDA accumulation clock, the number of output pulses DIVCSEV per revolution is accumulated and counted, using 2 N As the criterion for judging the accumulation overflow, N is the number of valid bits of encoder position feedback. Each time an overflow occurs, the state of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B is changed once.

[0058] The frequency-divided quadrature pulse signal A and frequency-divided quadrature pulse signal B have four possible states: 00, 01, 10, and 11. The phase relationship between frequency-divided quadrature pulse signals A and B, i.e., the phase lead or lag relationship between the two pulse signals, can be determined by the level of the pulse output inverted signal PG_Invert. Forward rotation results in 00, 10, 11, 01, and reverse rotation results in 00, 01, 11, 10. This allows the phase relationship of the output quadrature signals A and B in this embodiment to be modified.

[0059] Furthermore, as a preferred embodiment of the present invention, step S4 specifically includes the following steps:

[0060] S41: The pulse signal PCLK is sent to the output pulse counter module 6 to store the count value in UD_CNT; when the count value in UD_CNT is equal to the set zero position value ZERO_SET_DAT, the zero point Z signal output counter module 7 generates the zero point pulse signal Z; as needed, the zero point Z signal output counter module 7 is controlled to work by the Z signal output enable signal PHASE_Z_EN.

[0061] As can be seen from the above, the FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method and system provided in this embodiment can realize the serial communication encoder position feedback pulse frequency division output according to the requirements of the host device. Moreover, the number of frequency division pulses is accurate, the output pulse frequency strictly follows the change of encoder feedback value, the maximum value of the frequency division pulse is not lower than the single-turn value of the encoder, and the phase relationship of the two output orthogonal signals A and B pulses can be changed.

[0062] In addition, this embodiment also provides an FPGA-based AC servo serial communication encoder position feedback pulse frequency division output system, such as... Figure 1 As shown, the system includes a first clock module 1, a second clock module 2, a frequency-divided output pulse count calculation module 3, a frequency-divided pulse generator module 4, a quadrature output pulse generation module 5, an output pulse counter module 6, and a zero-position Z signal output counter module 7.

[0063] The first clock module 1 is used to generate the clock signal CK625 based on the rising edge of the encoder feedback data sampling period update signal CK625_TRG.

[0064] The second clock module 2 is used to divide the system clock SYSCLK to generate a clock signal PGCK. The frequency of the clock signal PGCK is equal to the frequency of the clock signal CK625 multiplied by the DDA factor MAX_DDA_DAT.

[0065] The frequency division output pulse number calculation module 3 within the sampling period is used to calculate the encoder position pulse deviation DIFF_DAT between two samples under the trigger of the clock signal CK625;

[0066] Frequency divider pulse generator module 4 is used to accumulate the position pulse deviation DIFF_DAT with the clock signal PGCK as the trigger signal. When the accumulated sum exceeds the DDA factor MAX_DDA_DAT, it overflows and generates a uniformly distributed pulse signal PCLK.

[0067] Quadrature output pulse generation module 5 is used to accumulate and count the number of output pulses DIVCSEV per revolution using the pulse signal PCLK as the accumulation clock. N As the criterion for judging the accumulation overflow, N is the number of valid bits of encoder position feedback. Each overflow changes the state of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B. The phase relationship of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B can be changed by the pulse output inversion signal PG_Invert.

[0068] The output pulse counter module 6 is used to count and store the pulse signal PCLK.

[0069] The zero-point Z signal output counter module 7 is used to generate a zero-point pulse signal Z when the count value is equal to the set zero-point position value ZERO_SET_DAT; the operation of the zero-point Z signal output counter module 7 can be controlled by the Z signal output enable signal PHASE_Z_EN.

[0070] The specific working method of this system is as described in the aforementioned embodiments, and will not be repeated here.

[0071] Preferably, the FPGA used in this embodiment is the EG4X20 from Anlu Company. Of course, those skilled in the art can choose other models to implement the present invention in other embodiments.

[0072] Any process or method description in the flowchart or otherwise herein can be understood as representing a circuit, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0073] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0074] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0075] The above embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for outputting position feedback pulses from an AC servo serial communication encoder based on an FPGA, characterized in that, Includes the following steps: S1: Periodically read encoder position feedback data and calculate the difference between the position feedback data read in this cycle and the position feedback data read in the previous cycle; S2: Using the DDA algorithm, the difference in the position feedback data is converted into a uniformly distributed pulse signal PCLK within the encoder position feedback data sampling period. S3: Using the pulse signal PCLK as the trigger clock, perform DDA calculation on the number of output pulses per revolution that needs to be output. Change the state of the quadrature output pulse once for each overflow, thereby generating frequency-divided quadrature pulse signal A and frequency-divided quadrature pulse signal B. Step S1 specifically includes the following steps: S11: Detects the rising edge of the encoder feedback data sampling period update signal to generate clock signal CK625; S12: When the servo system is powered on and initialized, read the encoder position feedback data and write the encoder initial position value to the frequency division output pulse number calculation module (3) within the sampling period as the initial value of the encoder current position value; S13: Using the clock signal CK625 as the trigger signal, write the current position value of the encoder into the frequency division output pulse number calculation module (3) within the sampling period. S14: Calculate the position pulse deviation to be output within the current clock cycle by using the difference between the position feedback data from the two samples; Step S2 specifically includes the following steps: S21: Calculate the DDA factor, and generate the clock signal PGCK by dividing the system clock frequency. The frequency of the clock signal PGCK is equal to the frequency of the clock signal CK625 multiplied by the DDA factor. S22: Write the position pulse deviation and DDA factor into the frequency divider pulse generator module (4), and use the clock signal PGCK as the trigger signal to accumulate the position pulse deviation. When the accumulated sum exceeds the DDA factor, it overflows and generates a uniformly distributed pulse signal PCLK. Step S3 specifically includes the following steps: S31: Send the pulse signal PCLK to the quadrature output pulse generation module (5) and write the number of output pulses per revolution into the quadrature output pulse generation module (5). S32: Using the pulse signal PCLK as the accumulating clock, the number of output pulses per revolution is accumulated and counted, using 2 N As the criterion for accumulating overflow, N is the number of valid bits for encoder position feedback. Each overflow changes the state of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B. The phase relationship between the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B can be changed by inverting the pulse output signal.

2. The FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method according to claim 1, characterized in that, The method further includes the following steps: S4: Simultaneously count the pulse signal PCLK, and when the count value is equal to the preset zero position value, output the zero pulse signal Z.

3. The FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method according to claim 1, characterized in that, Step S4 specifically includes the following steps: S41: Send the pulse signal PCLK to the output pulse counter module (6) to store the count value; when the count value is equal to the set zero position value, the zero point Z signal output counter module (7) generates the zero point pulse signal Z; the zero point Z signal output counter module (7) can be controlled to work by the Z signal output enable signal.

4. A pulse frequency division output system employing the FPGA-based AC servo serial communication encoder position feedback pulse frequency division output method as described in any one of claims 1-3, characterized in that, It includes a first clock module (1), a second clock module (2), a frequency division output pulse count calculation module (3) within the sampling period, a frequency division pulse generator module (4), a quadrature output pulse generation module (5), an output pulse counter module (6), and a zero-position Z signal output counter module (7), wherein, The first clock module (1) is used to generate a clock signal CK625 based on the rising edge of the update signal according to the sampling period of the encoder feedback data. The second clock module (2) is used to divide the system clock to generate the clock signal PGCK; The frequency division output pulse number calculation module (3) within the sampling period is used to calculate the encoder position pulse deviation between two samples under the trigger of the clock signal CK625; The frequency divider pulse generator module (4) is used to accumulate the position pulse deviation with the clock signal PGCK as the trigger signal. When the accumulated sum exceeds the DDA factor, it overflows and generates a uniformly distributed pulse signal PCLK. The quadrature output pulse generation module (5) is used to accumulate and count the number of output pulses per revolution using the pulse signal PCLK as the accumulation clock. N As the criterion for judging the accumulation overflow, N is the number of valid bits of encoder position feedback. Each overflow changes the state of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B once. The phase relationship of the frequency division quadrature pulse signal A and the frequency division quadrature pulse signal B can be changed by inverting the pulse output signal. The output pulse counter module (6) is used to count and store the pulse signal PCLK; the zero position Z signal output counter module (7) is used to generate the zero point pulse signal Z when the count value is equal to the set zero position value; the zero point Z signal output counter module (7) can be controlled to work by the Z signal output enable signal.

5. The pulse frequency division output system according to claim 4, characterized in that, The FPGA used is the EG4X20 from Anlu Company.

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