Ultra-low voltage difference LDO circuit based on substrate modulation multiplexing and adaptive power tube

Abstract

The present disclosure provides an ultra-low dropout LDO circuit based on substrate modulation multiplexing and adaptive power tube, comprising: a first input end of an operational amplifier is connected with an output end of the circuit, a second input end of the operational amplifier inputs a reference voltage, and an output end is connected with an input end of a unit gain buffer and a gate of a secondary power tube; an output end of the unit gain buffer is connected with a gate of a primary power tube and a substrate; a first pole of the primary and secondary power tubes is input with a first working voltage, a second pole of the primary and secondary power tubes is connected with the output end of the circuit, and the output end of the circuit is connected with a load. The present disclosure adjusts the substrate voltage of the power tube, thereby adjusting the threshold voltage of the power tube, and ensuring the normal working of the circuit under the condition of ultra-low voltage; meanwhile, the adaptive design of the primary and secondary power tubes enables the circuit to adjust the adaptive opening or closing of the primary and secondary power tubes according to the load current when the load jumps, improves the load capacity, and improves the performance of the circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an ultra-low dropout LDO circuit based on substrate modulation multiplexing and adaptive power tube. BACKGROUND

[0002] Energy harvesting technology can convert weak energy collected from the environment into electrical energy. In recent years, energy harvesting technology has been applied to many fields such as Internet of Things (IoT), wearable devices, wireless sensors, etc. The output voltage after energy harvesting is unstable, and often needs to be output by a low dropout linear regulator (LDO) to output a stable direct current voltage to stabilize the power supply for the subsequent load. LDO is widely used in various medium and low power occasions, especially in energy harvesting systems, due to its simple structure, few off-chip devices required, and small output ripple and noise. Due to the very weak energy source and low collection efficiency, energy harvesting has the pain points of low output voltage and high power consumption, which means that the input voltage of the LDO is low, and when the load changes, the load voltage stability of the LDO current output will be greatly affected. SUMMARY

[0003] The present disclosure provides an ultra-low dropout LDO circuit, comprising: an operational amplifier, a unit gain buffer, a main power tube and a secondary power tube; wherein the first input end of the operational amplifier is connected with the output end of the ultra-low dropout LDO circuit, the second input end of the operational amplifier inputs a reference voltage, and the output end of the operational amplifier is connected with the input end of the unit gain buffer and the gate of the secondary power tube; the output end of the unit gain buffer is connected with the gate of the main power tube and the substrate of the main power tube; the first poles of the main power tube and the secondary power tube both input a first working voltage, the second poles of the main power tube and the secondary power tube are both connected with the output end of the ultra-low dropout LDO circuit, and the output end of the ultra-low dropout LDO circuit is connected with a load.

[0004] Further, in the case that the load is less than a load threshold, the secondary power tube is turned on and the main power tube is turned off; in the case that the load is greater than or equal to the load threshold, the secondary power tube is turned off and the main power tube is turned on.

[0005] Further, the main power tube and the secondary power tube are both P-type transistors.

[0006] Further, the operational amplifier at least comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; wherein a gate of the first transistor is connected to the reference voltage, a first pole of the first transistor is connected to a second pole of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, a second pole of the fifth transistor and a second pole of the seventh transistor, a second pole of the first transistor is connected to a bias current; a gate of the second transistor is connected to a load voltage output by the output terminal of the ultra-low dropout LDO circuit, a first pole of the second transistor is connected to a gate of the third transistor, a second pole of the fourth transistor, a second pole of the sixth transistor, a gate of the sixth transistor and a gate of the eighth transistor, a second pole of the second transistor is connected to the bias current; a first pole of the third transistor, a first pole of the fourth transistor, a first pole of the fifth transistor, a first pole of the sixth transistor, a first pole of the seventh transistor and a first pole of the eighth transistor are input with the first working voltage; a second pole of the seventh transistor is connected to a first pole of the ninth transistor, a gate of the ninth transistor and a gate of the tenth transistor, a first pole of the eighth transistor is connected to a first pole of the tenth transistor, and a second pole of the eighth transistor is the output terminal of the operational amplifier; a second pole of the ninth transistor and a second pole of the tenth transistor are grounded.

[0007] Further, the first transistor, the second transistor, the ninth transistor and the tenth transistor are N-type transistors; and the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type transistors.

[0008] Further, the unit gain buffer at least comprises: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; wherein the gate of the eleventh transistor is connected with the output terminal of the operational amplifier, the first pole of the eleventh transistor inputs the first working voltage, the second pole of the eleventh transistor is connected with the first pole of the fifteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor; the gate of the twelfth transistor is connected with the output terminal of the operational amplifier, the first pole of the twelfth transistor is connected with the second pole of the thirteenth transistor, the first pole of the thirteenth transistor and the first pole of the fourteenth transistor both input the first working voltage, the second pole of the thirteenth transistor is connected with the gate of the thirteenth transistor and the gate of the fourteenth transistor, the second pole of the fourteenth transistor is connected with the substrate of the eleventh transistor and the first pole of the sixteenth transistor, and the second pole of the fourteenth transistor is the output terminal of the unit gain buffer; the second pole of the twelfth transistor, the second pole of the fifteenth transistor and the second pole of the sixteenth transistor are grounded.

[0009] Further, the eleventh transistor, the thirteenth transistor and the fourteenth transistor are all P-type transistors; the twelfth transistor, the fifteenth transistor M15 and the sixteenth transistor are all N-type transistors.

[0010] Further, an op-amp current biasing circuit is further included, the first input terminal of the op-amp current biasing circuit inputs the first working voltage, the second input terminal of the op-amp current biasing circuit is connected with the output terminal of the operational amplifier, and the output terminal of the op-amp current biasing circuit outputs a biasing current to the operational amplifier.

[0011] Further, the operational amplifier current bias circuit at least comprises a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a twenty-second transistor; wherein the first pole of the seventeenth transistor, the first pole of the eighteenth transistor and the first pole of the twenty-second transistor all input the first working voltage, the second pole of the seventeenth transistor is connected with the gate of the seventeenth transistor, the gate of the eighteenth transistor and the first pole of the nineteenth transistor, the second pole of the eighteenth transistor is connected with the first pole of the twentieth transistor, and the second pole of the eighteenth transistor serves as the output end of the operational amplifier current bias circuit; the second pole of the nineteenth transistor, the second pole of the twentieth transistor and the second pole of the twenty-first transistor are all grounded, the gate of the twenty-second transistor is connected with the output end of the operational amplifier, and the second pole of the twenty-second transistor is connected with the first pole of the twenty-first transistor, the gate of the twenty-first transistor, the gate of the twentieth transistor and the gate of the nineteenth transistor.

[0012] Further, the seventeenth transistor, the eighteenth transistor and the twenty-second transistor are all P-type transistors, and the nineteenth transistor, the twentieth transistor and the twenty-first transistor are all N-type transistors.

[0013] Further, the compensation circuit at least comprises a compensation capacitor and a zero-setting resistor, the first end of the compensation capacitor is connected with the output end of the operational amplifier, the second end of the compensation capacitor is connected with the first end of the zero-setting resistor, and the second end of the zero-setting resistor is connected with the output end of the ultra-low-dropout LDO circuit.

[0014] The beneficial effects of the embodiments of the present disclosure are as follows: by adding a unit gain buffer in the circuit to adjust the substrate voltage of the power tube, the threshold voltage of the power tube is adjusted, and the normal operation of the circuit under the ultra-low voltage condition is ensured; meanwhile, by using the adaptive design of the main power tube and the auxiliary power tube, when the load jumps, the circuit adjusts to adaptively turn on or turn off the main power tube or the auxiliary power tube according to the load current, the load capacity is improved, thereby improving the stability of the circuit under different load conditions, and the performance of the circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the one or more embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments described in the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor under the premise of these drawings.

[0016] Figure 1 A design schematic of an ultra-low dropout LDO circuit in an embodiment of the present disclosure;

[0017] Figure 2 A design schematic of an operational amplifier in an embodiment of the present disclosure;

[0018] Figure 3 Another design schematic of an ultra-low dropout LDO circuit in an embodiment of the present disclosure;

[0019] Figure 4 A design schematic of an operational amplifier current biasing circuit in an embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of the relationship between the biasing current and the load current in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of the present specification, the technical solutions in one or more embodiments of the present specification will be described in detail below in conjunction with the drawings in one or more embodiments of the present specification. Obviously, the described embodiments are only a part of the embodiments of the present specification, rather than all the embodiments. Based on one or more embodiments of the present specification, all other embodiments obtained by those skilled in the art without creative labor should fall within the protection scope of the present document.

[0022] Energy harvesting technology can convert weak energy in the environment into electrical energy. In recent years, energy harvesting technology has been applied to many fields such as Internet of Things, wearable devices, wireless sensors, etc. The output voltage after energy harvesting is unstable, and often needs to output stable DC voltage through a low dropout linear regulator (LDO) to stabilize the power supply for the subsequent load. LDO is widely used in various medium and low power applications, especially in energy harvesting systems, due to its simple structure, few off-chip devices required, and small output ripple and noise. Due to the very weak energy source and low collection efficiency, energy harvesting has the pain points of low output voltage and high power consumption, which is equivalent to a low input voltage for the LDO. Moreover, when the load changes, the load voltage stability of the LDO current output will be greatly affected.

[0023] In order to solve the above problems, an ultra-low dropout LDO circuit based on substrate modulation multiplexing and adaptive power tube is provided in an embodiment of the present disclosure. The circuit realizes a solution for outputting stable load voltage under low power voltage and low static current conditions based on substrate biasing and adaptive power tube.

[0024] Figure 1A design schematic of the ultra-low dropout LDO circuit of the present embodiment is shown. As shown in Figure 1 , the ultra-low dropout LDO circuit (hereinafter referred to as the circuit) of the present embodiment based on substrate modulation multiplexing and adaptive power tube at least includes an operational amplifier 10, a unity gain buffer 20, a main power tube MP2 and a secondary power tube MP1. The first input terminal of the operational amplifier 10 is connected with the output terminal of the circuit, and the output terminal of the circuit outputs a load voltage V OUT . The second input terminal of the operational amplifier 10 inputs a reference voltage V REF . The output terminal of the operational amplifier 10 is connected with the input terminal of the unity gain buffer 20 and the gate of the secondary power tube MP1. The output terminal of the unity gain buffer 20 is connected with the main power tube MP2 and the gate and the substrate of the main power tube MP2. The first pole of the main power tube MP2 and the secondary power tube MP1 both inputs a first working voltage V IN . The second pole of the main power tube MP2 and the secondary power tube MP1 are both connected with the output terminal of the circuit, and the output terminal of the circuit is connected with a load (in Figure 1 , represented by the current I L flowing through the load, C L represents the load capacitance). The first working voltage V IN is the voltage output by the energy harvesting system.

[0025] In the present embodiment, the operational amplifier 10 is mainly a gain boost amplifier, which is used to compare the load voltage V OUT output by the output terminal of the circuit with the reference voltage V REF , and transfer the voltage difference V EA between the two to the later stage, so as to finally adjust the voltage of the power tube gate, so that the load voltage V OUT tends to the reference voltage V REF .

[0026] In some embodiments, the operational amplifier 10 can be designed in a cross-coupled structure, input pair and push-pull output structure, so as to realize the gain boost of the amplifier. Specifically, a design schematic of the operational amplifier 10 is as shown in Figure 2As shown, it at least includes: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10; wherein the gate of the first transistor M1 is connected with a reference voltage, the first pole of the first transistor M1 is connected with the second pole of the third transistor M3, the gate of the fourth transistor M4, the gate of the fifth transistor M5, the second pole of the fifth transistor M5 and the second pole of the seventh transistor M7, the second pole of the first transistor M1 is connected with a bias current; the gate of the second transistor M2 is connected with a load voltage outputted by the output end of the circuit, the first pole of the second transistor M2 is connected with the gate of the third transistor M3, the second pole of the fourth transistor M4, the second pole of the sixth transistor M6, the gate of the sixth transistor M6 and the gate of the eighth transistor M8, the second pole of the second transistor M2 is connected with a bias current; the first pole of the third transistor M3, the first pole of the fourth transistor M4, the first pole of the fifth transistor M5, the first pole of the sixth transistor M6, the first pole of the seventh transistor M7 and the first pole of the eighth transistor M8 are inputted with a first working voltage; the second pole of the seventh transistor M7 is connected with the first pole of the ninth transistor M9, the gate of the ninth transistor M9 and the gate of the tenth transistor M10, the second pole of the eighth transistor M8 is connected with the first pole of the tenth transistor M10, and the second pole of the eighth transistor M8 is the output end of the operational amplifier 10; the second pole of the ninth transistor M9 and the second pole of the tenth transistor M10 are grounded.

[0027] It should be noted that, Figure 2 In the operational amplifier 10 shown in the figure, the first transistor M1, the second transistor M2, the ninth transistor M9 and the tenth transistor M10 are all N-type transistors, and the rest of the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are P-type transistors. Whether the first pole and the second pole of each of the above transistors correspond to the source or the drain is determined according to the type of transistor and the circuit design, and this embodiment will not be specifically described.

[0028] Corresponding to Figure 2 The design schematic diagram of the operational amplifier 10 shown in the figure, the cross-coupled structure is composed of transistors M3 and M4, and their respective gates are connected with the drain of the other one, and the accumulation and amplification of the signal are realized through the positive feedback loop, thereby improving the gain of the operational amplifier 10 as the first stage. In addition, the negative resistance generated by the cross-coupled structure can offset the equivalent resistance of the diode-connected transistors M5 and M6, effectively increasing the resistance of the internal nodes V X and V Y In addition, the input pair transistor and the push-pull output structure can also provide high-speed driving and high output current.

[0029] The unit gain buffer 20 is based on the differential voltage V EA The substrate modulation voltage V BODY The substrate voltage of the main power tube MP2 is reduced, so as to reduce the threshold voltage of the main power tube MP2, and ensure that the circuit can work normally under the condition of inputting ultra-low voltage (i.e. the first working voltage V IN ). Further, the substrate modulation voltage V BODY is used as the output voltage of the second stage operational amplifier, which can further reduce the power consumption of the main power tube MP2 and improve the efficiency of the whole circuit. The main power tube MP2 and the auxiliary power tube MP1 are adapted to open or close the value of the substrate modulation voltage V BODY output by the unit gain buffer 20 according to the load connected to the circuit, so as to improve the stability of the circuit under different load conditions.

[0030] Figure 3 Another design schematic of the ultra-low voltage difference LDO circuit in the embodiment is shown, and the specific circuit design of the unit gain buffer 20 is shown in Figure 3 , and the specific reference is shown in the part enclosed by the dashed box in Figure 3 . As shown in Figure 3 , the unit gain buffer 20 at least includes: the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16; wherein the gate of the eleventh transistor M11 is connected with the output terminal of the operational amplifier, the first pole of the eleventh transistor M11 inputs the first working voltage, and the second pole of the eleventh transistor M11 is connected with the first pole of the fifteenth transistor M15, the gate of the fifteenth transistor M15 and the gate of the sixteenth transistor M16; the gate of the twelfth transistor M12 is connected with the output terminal of the operational amplifier, the first pole of the twelfth transistor M12 is connected with the second pole of the thirteenth transistor M13, the first pole of the thirteenth transistor M13 and the first pole of the fourteenth transistor M14 both input the first working voltage, the second pole of the thirteenth transistor M13 is connected with the gate of the thirteenth transistor M13 and the gate of the fourteenth transistor M14, the second pole of the fourteenth transistor M14 is connected with the substrate of the eleventh transistor M11 and the first pole of the sixteenth transistor M16, and the second pole of the fourteenth transistor M14 is used as the output terminal of the unit gain buffer; the second pole of the twelfth transistor M12, the second pole of the fifteenth transistor M15 and the second pole of the sixteenth transistor M16 are grounded.

[0031] It should be noted that, in Figure 3In the unity-gain buffer 20 shown, the eleventh transistor M11, the thirteenth transistor M13, and the fourteenth transistor M14 are all P-type transistors; the twelfth transistor M12, the fifteenth transistor M15, and the sixteenth transistor M16 are N-type transistors. Furthermore, in this embodiment, both the main power transistor MP2 and the secondary power transistor MP1 are P-type transistors, and the turn-on threshold Vth2 of the main power transistor MP2 is higher than the turn-on threshold Vth1 of the secondary power transistor MP1. There is also a difference in the channel dimensions between the main and secondary power transistors.

[0032] Combination Figure 3 In the circuit shown, the main power transistor MP2 and the secondary power transistor MP1 can adaptively switch their on or off states according to the load conditions in the circuit. Specifically, under light load conditions, the fourteenth transistor M14 in the unity-gain buffer 20 operates in the deep linear region, and the voltage output to the gate of the main power transistor MP2 is relatively high. The voltage difference between the gate and the source of the main power transistor MP2 is greater than its threshold voltage Vth2, so the main power transistor MP2 is in the off state. The gate voltage of the secondary power transistor MP1 is the voltage difference Vth2 output from the operational amplifier 10. EA The voltage difference between its gate and source is less than the threshold voltage Vth1 of the secondary power transistor MP1, and the secondary power transistor MP1 is in the on state. Under heavy load conditions, the current I flowing through the load... L The boost causes the voltage difference V at the output of operational amplifier 10 to increase. EA The current I flowing through M11 in the unity-gain buffer 20 is reduced, thus decreasing. DS11 Increase the current I that is replicated to M14. DS14 Consequently, the substrate modulation voltage V of the overall output of the unity-gain buffer 20 also increases. BODY The voltage drop causes both the substrate voltage and gate voltage of the main power transistor MP2 to decrease. As the substrate voltage decreases, the threshold voltage Vth2 of the main power transistor MP2 decreases. As its gate voltage decreases, MP2 is turned on, and the secondary power transistor MP1 gradually turns off, automatically switching the circuit to a three-stage structure. It is important to note that the heavy and light loads mentioned in this embodiment can be defined by a pre-set load threshold. That is, when the load is less than the load threshold, the secondary power transistor MP1 is turned on and the main power transistor MP2 is turned off; when the load is greater than or equal to the load threshold, the secondary power transistor MP1 is turned off and the main power transistor MP2 is turned on. The specific value of this load threshold can be set according to the actual operating requirements of the LDO circuit, combined with the model or parameters of the main and secondary power transistors.

[0033] In addition, the substrate voltage of the main power tube MP2 is reused as the voltage of its own gate, which can reduce the introduction of an additional amplifier as the gate drive of the main power tube MP2, thereby reducing the power consumption of the overall circuit, and can ensure the normal voltage stabilization function of the main power tube MP2 under the condition of a lower gate-source voltage, thereby improving the power efficiency of the overall circuit.

[0034] The embodiment adjusts the substrate voltage of the power tube by adding a unit gain buffer in the circuit, thereby adjusting the threshold voltage of the power tube to as low as 100 mV, ensuring the normal operation of the circuit under the condition of ultra-low voltage; at the same time, the adaptive design of the main power tube and the auxiliary power tube is used to make the circuit adaptively turn on or turn off the main power tube or the auxiliary power tube according to the load current when the load jumps, so as to ensure the stability of the circuit in the full load range, reduce unnecessary current consumption, further reduce the static current, and improve the performance of the circuit.

[0035] In some embodiments, the circuit can further include an op-amp current biasing circuit 30, as shown in Figure 1 The first input end of the op-amp current biasing circuit 30 inputs a first working voltage V IN , and its second input end is connected with the output end of the operational amplifier 10 to input the differential voltage V EA output by the operational amplifier 10. The output end of the op-amp current biasing circuit 30 is used to output a biasing current to the operational amplifier 10 to adjust its working state. When the op-amp current biasing circuit 30 senses an increase in the load connected to the circuit (i.e., the differential voltage V EA decreases), the biasing current provided to the operational amplifier 10 is adaptively adjusted to reduce the transient recovery time and the up and down voltage of the operational amplifier 10, which can ensure that the circuit can still maintain a stable working state when the load changes rapidly, and reduce the problems of power consumption and noise, etc.

[0036] Figure 4 A design schematic of the op-amp current biasing circuit 30 in the embodiment is shown. As Figure 4As shown, the operational amplifier current bias circuit 30 includes at least a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a twenty-second transistor M22; wherein, the first terminal of the seventeenth transistor M17, the first terminal of the eighteenth transistor M18, and the first terminal of the twenty-second transistor M22 are all input with a first operating voltage, the second terminal of the seventeenth transistor M17 is connected to the gate of the seventeenth transistor M17, the gate of the eighteenth transistor M18, and the first terminal of the nineteenth transistor M19, and the eighteenth transistor... The second terminal of transistor M18 is connected to the first terminal of transistor M20 (the twentieth transistor). The second terminal of transistor M18 serves as the output terminal of the operational amplifier's current bias circuit. The second terminals of transistors M19, M20, and M21 are all grounded. The gate of transistor M22 is connected to the output terminal of the operational amplifier. The second terminal of transistor M22 is connected to the first terminal and gate of transistor M21, the gate of transistor M21, and the gate of transistor M20. Among these, transistors M17, M18, and M22 are P-type transistors, while transistors M19, M20, and M21 are N-type transistors.

[0037] Figure 5 The bias current I output by the operational amplifier current bias circuit 30 in this embodiment is shown. BIAS With load current I L The diagram illustrates the relationship between the load current IL on the horizontal axis and the bias current I on the vertical axis. BIAS Combining Figure 4 As can be seen from the circuit shown, when the load current I... L From I TH1 Upgraded to I TH2 When, bias current I BIAS It will also be from I accordingly MIN Upgraded to I BIAS,H Furthermore, this corresponding increase relationship is linear, meaning that when the load changes, the op-amp current bias circuit 30 can generate a bias current proportional to the load current, thereby quickly changing the operating state of the operational amplifier, reducing the transient recovery time and overshoot / overshoot voltage.

[0038] In some embodiments, the circuit may further include a compensation circuit 40, which is mainly connected between the output terminal of the operational amplifier 10 and the output terminal of the circuit, to separate poles and keep the circuit stable over the entire load current range. Specifically, it mainly includes a compensation capacitor C. M and zero-adjustment resistor R MThe first end of the compensation capacitor C M is connected with the output end of the operational amplifier 10, and the second end of the compensation capacitor C M is connected with the first end of the zeroing resistor R M , and the second end of the zeroing resistor R M is connected with the output end of the circuit, so that the circuit can keep high-efficiency and stable working state under different load conditions.

[0039] The ultra-low voltage difference LDO circuit has the advantages of ultra-low voltage difference, fast transient response, wide power voltage range, high linearity, low power consumption and full integration, and can be applied to an energy collection system with high requirements for static current and working voltage, to ensure high power efficiency and low power consumption.

[0040] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An ultra-low dropout (LDO) circuit based on substrate modulation multiplexing and adaptive power tube, characterized in that, The application relates to a power amplifier circuit. The first input end of the operational amplifier is connected with the output end of an ultra-low-dropout LDO circuit, the second input end of the operational amplifier inputs a reference voltage, the output end of the operational amplifier is connected with the input end of the unit-gain buffer and the gate of the auxiliary power tube; The output end of the unit-gain buffer is connected with the gate of the main power tube and the substrate of the main power tube; The first poles of the main power tube and the auxiliary power tube input a first working voltage, the second poles of the main power tube and the auxiliary power tube are connected with the output end of the ultra-low-dropout LDO circuit, and the output end of the ultra-low-dropout LDO circuit is connected with a load; The unit-gain buffer at least comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; wherein The gate of the eleventh transistor is connected with the output end of the operational amplifier, the first pole of the eleventh transistor inputs the first working voltage, and the second pole of the eleventh transistor is connected with the first pole of the fifteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor; The gate of the twelfth transistor is connected with the output end of the operational amplifier, the first pole of the twelfth transistor is connected with the second pole of the thirteenth transistor, the first pole of the thirteenth transistor and the first pole of the fourteenth transistor input the first working voltage, the second pole of the thirteenth transistor is connected with the gate of the thirteenth transistor and the gate of the fourteenth transistor, the second pole of the fourteenth transistor is connected with the substrate of the eleventh transistor and the first pole of the sixteenth transistor, and the second pole of the fourteenth transistor serves as the output end of the unit-gain buffer; The second poles of the twelfth transistor, the fifteenth transistor and the sixteenth transistor are grounded; The eleventh transistor, the thirteenth transistor and the fourteenth transistor are P-type transistors, and the twelfth transistor, the fifteenth transistor and the sixteenth transistor are N-type transistors. When the load is smaller than a load threshold, the auxiliary power tube is turned on and the main power tube is turned off; when the load is greater than or equal to the load threshold, the auxiliary power tube is turned off and the main power tube is turned on.

2. The ultra-low-dropout (LDO) circuit of claim 1, wherein, The main power tube and the auxiliary power tube are P-type transistors.

3. The ultra-low-dropout (LDO) circuit of claim 1, wherein, The operational amplifier at least comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; wherein 4. The ultra-low-dropout (LDO) circuit of claim 1, wherein, The gate of the first transistor is connected with the reference voltage, the first pole of the first transistor is connected with the second pole of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, the second pole of the fifth transistor and the second pole of the seventh transistor, the second pole of the first transistor is connected with a bias current, and the first pole of the second transistor is connected with the second pole of the third transistor. ​ The gate of the second transistor is connected to a load voltage output by the ultra-low dropout LDO circuit, the first electrode of the second transistor is connected to the gate of the third transistor, the second electrode of the fourth transistor, the second electrode of the sixth transistor, the gate of the sixth transistor and the gate of the eighth transistor, and the second electrode of the second transistor is connected to the bias current; The first electrode of the third transistor, the first electrode of the fourth transistor, the first electrode of the fifth transistor, the first electrode of the sixth transistor, the first electrode of the seventh transistor and the first electrode of the eighth transistor are all inputted with the first working voltage; The second electrode of the seventh transistor is connected to the first electrode of the ninth transistor, the gate of the ninth transistor and the gate of the tenth transistor, the second electrode of the eighth transistor is connected to the first electrode of the tenth transistor, and the second electrode of the eighth transistor is the output terminal of the operational amplifier; The second electrode of the ninth transistor and the second electrode of the tenth transistor are grounded.

5. The ultra-low-dropout (LDO) circuit of claim 4, wherein, The first transistor, the second transistor, the ninth transistor and the tenth transistor are all N-type transistors; The second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all P-type transistors.

6. The ultra-low-dropout (LDO) circuit of claim 1, wherein, The operational amplifier further comprises a bias current biasing circuit, the first input terminal of the bias current biasing circuit is inputted with the first working voltage, the second input terminal of the bias current biasing circuit is connected to the output terminal of the operational amplifier, and the output terminal of the bias current biasing circuit outputs a bias current to the operational amplifier.

7. The ultra-low-dropout (LDO) circuit of claim 6, wherein, The bias current biasing circuit at least comprises: The first electrode of the seventeenth transistor, the first electrode of the eighteenth transistor and the first electrode of the twenty-second transistor are all inputted with the first working voltage, the second electrode of the seventeenth transistor is connected to the gate of the seventeenth transistor, the gate of the eighteenth transistor and the first electrode of the nineteenth transistor, the second electrode of the eighteenth transistor is connected to the first electrode of the twentieth transistor, and the second electrode of the eighteenth transistor is the output terminal of the bias current biasing circuit; The second electrode of the nineteenth transistor, the second electrode of the twentieth transistor and the second electrode of the twenty-first transistor are all grounded, the gate of the twenty-second transistor is connected to the output terminal of the operational amplifier, and the second electrode of the twenty-second transistor is connected to the first electrode of the twenty-first transistor, the gate of the twenty-first transistor, the gate of the twentieth transistor and the gate of the nineteenth transistor. The seventeenth transistor, the eighteenth transistor and the twenty-second transistor are all P-type transistors; 8. The ultra-low-dropout (LDO) circuit of claim 7, wherein, The nineteenth transistor, the twentieth transistor and the twenty-first transistor are all N-type transistors. ​ 9. The ultra-low-dropout (LDO) circuit according to any one of claims 1 to 8, characterized in that, The compensation circuit comprises at least a compensation capacitor and a zero-setting resistor, a first end of the compensation capacitor is connected with the output end of the operational amplifier, a second end of the compensation capacitor is connected with a first end of the zero-setting resistor, and a second end of the zero-setting resistor is connected with the output end of the ultra-low-dropout LDO circuit.

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