An LED driving PWM pulse width modulation device and method

Abstract

An embodiment of the present invention discloses an LED driving PWM pulse width modulation device and method. The device includes: a grayscale data module for splitting grayscale data into high-bit grayscale data and low-bit grayscale data, and generating first high-bit grayscale data and second high-bit grayscale data based on the high-bit grayscale data; a PWM counter for counting PWM clock signals and dividing the PWM clock signals into high-bit clock data and low-bit clock data; a selector for time-division multiplexing either the first high-bit grayscale data or the second high-bit grayscale data to the PWM pulse width generation module based on the decoding result of the decoder; and the PWM pulse width generation module for outputting a PWM pulse width signal based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data. This device improves the visual refresh rate while maintaining the display grayscale and enhancing the display's detail.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to an LED driving PWM pulse width modulation device and method. Background Technology

[0002] Currently, the use of PWM (Pulse Width Modulation) for LED dimming is becoming increasingly common. With the expansion of application scenarios, LED electronic displays are appearing more and more frequently in people's lives. Visual refresh rate and grayscale level are important indicators for measuring the performance of LED electronic displays: a higher visual refresh rate results in a more stable image display, and even when shot with a high-speed camera, it can still present a continuous image without horizontal stripes or flickering; a higher grayscale level results in more detailed and richer displayed content. Traditional PWM methods cannot simultaneously achieve a high visual refresh rate and a high grayscale level at a relatively low PWM clock speed. Summary of the Invention

[0003] In view of this, the first embodiment of the present invention provides an LED driving PWM pulse width modulation device, comprising:

[0004] The module includes a grayscale data module, a PWM counter, a decoder, a selector, and a PWM pulse width generation module.

[0005] The grayscale data module is used to split the grayscale data into high-bit grayscale data and low-bit grayscale data, and generate first high-bit grayscale data and second high-bit grayscale data based on the high-bit grayscale data.

[0006] The PWM counter is used to count the PWM clock signal and divide the PWM clock signal into high-bit clock data and low-bit clock data;

[0007] The selector is used to select either the first high-bit grayscale data or the second high-bit grayscale data to the PWM pulse width generation module in a time-division manner according to the decoding result of the decoder.

[0008] The PWM pulse width generation module is used to output a PWM pulse width signal based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data.

[0009] In one specific embodiment, the grayscale data module is further used to determine the number of scattered sub-cycles of the PWM pulse width signal, and to calculate the frequency of the PWM clock signal based on the number of scattered sub-cycles of the PWM pulse width signal, the grayscale accuracy requirement, and the refresh rate requirement of the PWM pulse width signal.

[0010] The number of bits for high-bit grayscale data and the number of bits for low-bit grayscale data are determined based on the number of scattered sub-cycles of the PWM pulse width signal.

[0011] In one specific embodiment, the grayscale data module further includes an addition operation module, used to take the high-bit grayscale data as the first high-bit grayscale data, and the data obtained by adding the first high-bit grayscale data and the first value as the second high-bit grayscale data.

[0012] In one specific embodiment, the number of bits in the high-bit clock data is the same as the number of bits in the low-bit grayscale data, and the number of bits in the low-bit clock data is the same as the number of bits in the high-bit grayscale data.

[0013] In one specific embodiment, the decoder stores a decoding table, and determines the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data based on the decoding table, the received low-bit grayscale data, and the high-bit clock data.

[0014] In one specific embodiment, the decoder includes a decoding logic circuit. After the received low-bit grayscale data and high-bit clock data are processed by the decoding logic circuit, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined.

[0015] A second embodiment of the present invention provides an LED driving PWM pulse width modulation method, comprising:

[0016] The grayscale data is split into high-bit grayscale data and low-bit grayscale data, and a first high-bit data and a second high-bit data are generated based on the high-bit data.

[0017] The PWM clock signal is divided into high-bit clock data and low-bit clock data;

[0018] Based on the decoding result of the decoder, the first high-bit grayscale data or the second high-bit grayscale data is selected to the PWM pulse width generation module in a time-division manner.

[0019] The PWM pulse width signal is output based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data.

[0020] In one specific embodiment, the number of scattered sub-cycles of the PWM pulse width signal is determined, and the frequency of the PWM clock signal is calculated based on the number of scattered sub-cycles of the PWM pulse width signal, the grayscale accuracy requirement, and the refresh rate requirement of the PWM pulse width signal.

[0021] The number of bits for high-bit grayscale data and the number of bits for low-bit grayscale data are determined based on the number of scattered sub-cycles of the PWM pulse width signal.

[0022] In one specific embodiment, after the low-bit grayscale data and the high-bit clock data are processed by the decoding logic circuit included in the decoder, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined.

[0023] In one specific embodiment, the decoder traverses the decoder's stored decoder table, processes the low-bit grayscale data and the high-bit clock data according to the traversal results, and determines the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data, as well as the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data.

[0024] The beneficial effects of this invention are as follows:

[0025] This invention provides an LED driving PWM pulse width modulation device and method. By splitting grayscale data into high-bit grayscale data and low-bit grayscale data, and according to the decoding result of the decoder, the grayscale information in the high-bit grayscale data is evenly distributed in the PWM sub-cycle. This improves the visual refresh rate while maintaining the display grayscale and enhancing the display detail, and has broad application prospects. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram showing the existing PWM pulse signal waveform.

[0028] Figure 2 A schematic diagram of an LED driving PWM pulse width modulation device according to an embodiment of the present invention is shown.

[0029] Figure 3 A schematic diagram of a decoding table according to an embodiment of the present invention is shown.

[0030] Figure 4 A schematic diagram showing the final output PWM pulse signal waveform according to an embodiment of the present invention is provided.

[0031] Figure 5A schematic flowchart of an LED driving PWM pulse width modulation method according to an embodiment of the present invention is shown. Detailed Implementation

[0032] To make the present invention, its technical solutions, and advantages clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0033] To achieve both high visual refresh rates and high grayscale levels at relatively low PWM clock speeds, the mainstream technology currently employs an improved radical pulse width modulation (PWM) technique. This technique, compared to traditional PWM (such as...) Figure 1 Based on the PWM1 signal shown, the high-level time of a grayscale control signal is broken down into multiple shorter conduction times, thereby improving the visual refresh rate while maintaining the original display grayscale. The main principle of this improved radical pulse width modulation (PWM) technology is to divide the grayscale data into high-bit data (MSB) and low-bit data (LSB), repeatedly count the MSB data N times (N being the number of parts), and then count the LSB data once, resulting in the following... Figure 1 The final complete PWM waveform is shown in the PWM2 signal. Although this technique improves the visual refresh rate and maintains the display grayscale, it does not distribute the display portion of the low-bit LSB data more evenly within the pulse of the high-bit MSB data, and still loses some display detail to a certain extent.

[0034] To solve the above problems, such as Figure 2 As shown, one embodiment of the present invention provides an LED driving PWM pulse width modulation device, comprising:

[0035] The system comprises a grayscale data module 10, a PWM counter 20, a decoder 40, a selector 50, and a PWM pulse width generation module 60, among which...

[0036] The grayscale data module 10 is used to split grayscale data into high-bit grayscale data and low-bit grayscale data, and generate first high-bit grayscale data and second high-bit grayscale data based on the high-bit grayscale data.

[0037] The PWM counter 20 is used to count the PWM clock signal and divide the PWM clock signal into high-bit clock data and low-bit clock data.

[0038] The selector 50 is used to select either the first high-bit grayscale data or the second high-bit grayscale data to the PWM pulse width generation module in a time-division manner according to the decoding result of the decoder 40.

[0039] The PWM pulse width generation module 60 is used to output a PWM pulse width signal based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data.

[0040] The LED driver PWM pulse width modulation device provided in this embodiment splits grayscale data into high-bit grayscale data and low-bit grayscale data, and distributes the grayscale information in the high-bit grayscale data evenly in the PWM sub-cycle according to the decoding result of the decoder. While improving the visual refresh rate, it still maintains the display grayscale and improves the display fineness, which has broad application prospects.

[0041] In one specific embodiment, the grayscale data module is further used to determine the number of scattered sub-cycles of the PWM pulse width signal, and to calculate the frequency of the PWM clock signal based on the number of scattered sub-cycles of the PWM pulse width signal, the grayscale accuracy requirement, and the refresh rate requirement of the PWM pulse width signal.

[0042] In this embodiment, the number of scattered sub-cycles of the PWM is determined to be m = 16, and the preset grayscale accuracy requirement and the refresh rate requirement of the PWM pulse width signal are obtained.

[0043] The grayscale data is 16'b0010101010111000, the grayscale level requirement is 65536, and the refresh rate requirement for the PWM pulse width signal is Fpwm = 4kHz. Therefore, based on the number of scattered sub-cycles in the PWM, the PWM clock signal is:

[0044] Fclk=65536*Fpwm / m=16.38MHZ(clk=61ns);

[0045] The duration of the PWM sub-cycle is:

[0046] T=1 / Fpwm=1 / 4KHZ=250us.

[0047] The number of bits in the high-bit grayscale data DATA_MSB and the number of bits in the low-bit grayscale data DATA_LSB are determined based on the number of scattered sub-cycles of the PWM pulse width signal.

[0048] The number of bits in the low-bit grayscale data DATA_LSB is determined based on the number of scattered sub-cycles of the PWM pulse width signal.

[0049] i = log2m = log216 = 4;

[0050] So, what is the number of bits in the high-bit grayscale data DATA_MSB?

[0051] j=log265536–i=16–4=12;

[0052] Since the grayscale data is 16'b0010101010111000, then,

[0053] DATA_MSB=12'b001010101011, DATA_LSB=4'b1000.

[0054] It is worth noting that those skilled in the art can set the number of bits for grayscale data, the number of bits for low-bit grayscale data, and the number of bits for high-bit grayscale data according to actual conditions. For example, the number of bits for low-bit grayscale data is 3, and the number of bits for high-bit grayscale data is 13. The above examples are merely examples listed to better understand the technical solutions of the embodiments of the present invention and are not intended as the only limitation on the embodiments of the present invention.

[0055] In one specific embodiment, the number of bits k of the high-bit clock data CNT_MSB is the same as the number of bits i of the low-bit grayscale data DATA_LSB, for example, k = i = 4, and the number of bits l of the low-bit clock data CNT_LSB is the same as the number of bits j of the high-bit grayscale data DATA_MSB, for example, l = j = 12.

[0056] In one specific embodiment, the grayscale data module further includes an addition operation module, which uses the high-bit grayscale data as the first high-bit grayscale data data1, and the data obtained by adding the first high-bit grayscale data to the first value as the second high-bit grayscale data data2.

[0057] Since DATA_MSB = 12'b001010101011, then data1 = 12'b001010101011, and data2 = data1 + 1 = 12'b001010101100. The first and second high-order bits of grayscale data are used to generate two different PWM pulse widths in the PWM sub-cycle. The effective pulse width of the PWM sub-cycle corresponding to data1 is TP1 = data1 * clk = 683clk = 41663ns, and the effective pulse width of the PWM sub-cycle corresponding to data2 is TP2 = data2 * clk = 684clk = 41724ns.

[0058] It is understood that the above examples are merely examples listed for better understanding of the technical solutions of the embodiments of the present invention, and are not intended as the only limitation on the embodiments of the present invention. Those skilled in the art can set the type of the operation module and the first value according to the actual situation. The first value is 2, 3, etc., which are converted to binary as 10, 11 or other values, as long as the number of bits of the first high bit grayscale data and the second high bit grayscale data are the same.

[0059] In one specific embodiment, the decoder stores as follows: Figure 3 The decoding table shown is used to determine the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data, as well as the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data, based on the decoding table, the received low-bit grayscale data, and the high-bit clock data.

[0060] In this embodiment, for example, the grayscale data is 16'b0010101010111000, DATA_LSB = 4'b1000, according to Figure 3 The decoder output is 1 when CNT_MSB = 4'b0000, 4'b0010, 4'b0110, 4'b0100, 4'b1000, 4'b1010, 4'b1100, 4'b1110. Therefore, the number of sub-cycles of the PWM pulse width signal for the second high-bit grayscale data is 8, which corresponds to the 1st, 3rd, 5th, 7th, 9th, 11th, 13th, and 15th PWM sub-cycles. In other words, the effective pulse width TP2 is generated in the 1st, 3rd, 5th, 7th, 9th, 11th, 13th, and 15th PWM sub-cycles. When CNT_MSB = 4'b0001, 4'b0011, 4'b0111, 4'b0101, 4'b1001, 4'b1011, 4'b1101, 4'b1111, the decoder output is 0. Therefore, the number of sub-cycles of the PWM pulse width signal for the first high-bit grayscale data is 8, which corresponds to the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th PWM sub-cycles. That is, the effective pulse width TP1 is generated in the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th PWM sub-cycles. Through the decoder, the grayscale information of DATA_LSB is evenly distributed across the 16 PWM sub-cycles.

[0061] Those skilled in the art should understand that when the number of bits of grayscale data, the number of bits of low-bit grayscale data, or the number of bits of high-bit grayscale data changes, the above decoding table should be changed accordingly, which will not be elaborated here.

[0062] In another embodiment, the decoder includes a decoding logic circuit. After the received low-bit grayscale data and high-bit clock data are processed by the decoding logic circuit, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined.

[0063] The decoding table provided in the foregoing embodiments has a similar function to the logic decoding circuit provided in this embodiment. The relevant parts can be referred to the above description, and will not be repeated here.

[0064] Traditional PWM pulse waveforms, such as Figure 1As shown in PWM1, within a total PWM cycle time of 65536clk, its effective PWM pulse width is a high-level time of 10936clk.

[0065] An example of the PWM pulse waveform used in the main implementation of existing improved radical pulse width modulation (PWM) technology is as follows: Figure 1 As shown in PWM2, the PWM pulse width is divided into the DATA_MSB portion and the DATA_LSB portion, which are integrated to obtain the complete PWM waveform. The DATA_MSB portion PWM time is divided into 16 sub-cycles, each sub-cycle lasting 4095 clk. The effective PWM pulse width is DATA_MSB * clk = the high-level time of TP1, and this sub-cycle is repeated 16 times. The DATA_LSB portion has a cycle of 16 clk, and the effective PWM pulse width is DATA_LSB * clk = TP3 = 8 * 61ns = 488ns of high-level time. This cycle is counted only once. The total effective PWM pulse width is TP1 * 16 + TP3 = 10936 clk of high-level time.

[0066] In one specific embodiment, the final output modulated PWM pulse waveform of an embodiment provided by the present invention is as follows: Figure 4 As shown, the PWM cycle is divided into 16 sub-cycles, each sub-cycle lasting 4096 clk. The two effective pulse widths, TP1 and TP2, are distributed sequentially within these 16 sub-cycles based on the decoding results. In this embodiment, the high-level time of TP1 (41663 ns) is distributed in sub-cycles 1, 3, 5, 7, 9, 11, 13, and 15; the high-level time of TP2 (41724 ns) is distributed in sub-cycles 2, 4, 6, 8, 10, 12, 14, and 16. The total effective PWM pulse width is TP1*8 + TP2*8 = 10936 clk of high-level time. Compared to PWM2, the display portion of the low-bit DATA_LSB data is more evenly distributed within the pulses of the high-bit DATA_MSB data, improving the display's detail.

[0067] The LED driver PWM pulse width modulation device provided in this embodiment splits grayscale data into high-bit grayscale data and low-bit grayscale data, and distributes the grayscale information in the high-bit grayscale data evenly in the PWM sub-cycle according to the decoding result of the decoder. While improving the visual refresh rate, it still maintains the display grayscale and improves the display fineness, which has broad application prospects.

[0068] Corresponding to the LED driving PWM pulse width modulation device provided in the above embodiments, such as Figure 5As shown, one embodiment of this application also provides a modulation method using the above-described LED-driven PWM pulse width modulation device, comprising:

[0069] The grayscale data is split into high-bit grayscale data and low-bit grayscale data, and a first high-bit data and a second high-bit data are generated based on the high-bit data.

[0070] The PWM clock signal is divided into high-bit clock data and low-bit clock data;

[0071] Based on the decoding result of the decoder, the first high-bit grayscale data or the second high-bit grayscale data is time-divisionally selected to the PWM pulse width generation module;

[0072] The PWM pulse width signal is output based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data.

[0073] In one specific embodiment, the number of scattered sub-cycles of the PWM pulse width signal is determined, and the frequency of the PWM clock signal is calculated based on the number of scattered sub-cycles of the PWM pulse width signal, the grayscale accuracy requirement, and the refresh rate requirement of the PWM pulse width signal.

[0074] The number of bits for high-bit grayscale data and the number of bits for low-bit grayscale data are determined based on the number of scattered sub-cycles of the PWM pulse width signal.

[0075] The LED driving PWM pulse width modulation method provided in this embodiment splits grayscale data into high-bit grayscale data and low-bit grayscale data, and distributes the grayscale information in the high-bit grayscale data evenly in the PWM sub-cycle according to the decoding result of the decoder. This improves the visual refresh rate while maintaining the display grayscale and enhances the display detail, and has broad application prospects.

[0076] In one specific embodiment, after the low-bit grayscale data and the high-bit clock data are processed by the decoding logic circuit included in the decoder, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined.

[0077] In one specific embodiment, the decoder traverses the decoder's stored decoder table, processes the low-bit grayscale data and the high-bit clock data according to the traversal results, and determines the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data, as well as the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data.

[0078] Since the LED driving PWM pulse width modulation method provided in this application corresponds to the LED driving PWM pulse width modulation device provided in the above embodiments, the previous embodiments are also applicable to the LCD screen testing method provided in this embodiment, and will not be described in detail in this embodiment.

[0079] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. An LED driving PWM pulse width modulation device, characterized in that, include: The module includes a grayscale data module, a PWM counter, a decoder, a selector, and a PWM pulse width generation module. The grayscale data module is used to split the grayscale data into high-bit grayscale data and low-bit grayscale data, and generate first high-bit grayscale data and second high-bit grayscale data based on the high-bit grayscale data. The grayscale data module also includes an addition operation module, which is used to use the high-bit grayscale data as the first high-bit grayscale data, and the data after adding one to the first high-bit grayscale data as the second high-bit grayscale data. The PWM counter is used to count the PWM clock signal and divide the PWM clock signal into high-bit clock data and low-bit clock data; The grayscale data module is also used to determine the number of scattered sub-cycles of the PWM pulse width signal. The selector is used to determine the number and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number and position of the PWM pulse width signal for outputting the second high-bit grayscale data according to the decoding result of the decoder on the low-bit grayscale data. The first high-bit grayscale data or the second high-bit grayscale data is time-divisionally selected to the PWM pulse width generation module so that the display part of the low-bit data is evenly distributed into the pulse of the high-bit data in a decoding selection manner. The PWM pulse width generation module is used to output a PWM pulse width signal based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data.

2. The apparatus according to claim 1, characterized in that, The grayscale data module is also used to calculate the frequency of the PWM clock signal based on the number of scattered sub-cycles of the PWM pulse width signal, the grayscale accuracy requirement, and the refresh rate requirement of the PWM pulse width signal. The number of bits for high-bit grayscale data and the number of bits for low-bit grayscale data are determined based on the number of scattered sub-cycles of the PWM pulse width signal.

3. The apparatus according to claim 2, characterized in that, The number of bits in the high-bit clock data is the same as the number of bits in the low-bit grayscale data, and the number of bits in the low-bit clock data is the same as the number of bits in the high-bit grayscale data.

4. The apparatus according to claim 3, characterized in that, The decoder stores a decoding table and determines the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data based on the decoding table, the received low-bit grayscale data, and the high-bit clock data.

5. The apparatus according to claim 3, characterized in that, The decoder includes a decoding logic circuit. After the received low-bit grayscale data and high-bit clock data are processed by the decoding logic circuit, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined.

6. A method for LED driving PWM pulse width modulation, characterized in that, include: The grayscale data is split into high-bit grayscale data and low-bit grayscale data. First high-bit grayscale data and second high-bit grayscale data are generated based on the high-bit grayscale data. The number of scattering sub-cycles of the PWM pulse width signal is determined. The first high-bit grayscale data is the high-bit grayscale data, and the second high-bit grayscale data is the data after adding one to the first high-bit grayscale data. The PWM clock signal is divided into high-bit clock data and low-bit clock data; Based on the decoding result of the low-bit grayscale data by the decoder, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined. The first high-bit grayscale data or the second high-bit grayscale data is then time-divisionally selected to the PWM pulse width generation module so that the display portion of the low-bit data is evenly distributed into the pulse of the high-bit data in a decoding selection manner. The PWM pulse width signal is output based on the first high-bit grayscale data, the second high-bit grayscale data, and the low-bit clock data.

7. The method according to claim 6, characterized in that, The frequency of the PWM clock signal is calculated based on the number of scattered sub-cycles, grayscale accuracy requirements, and refresh rate requirements of the PWM pulse width signal. The number of bits for high-bit grayscale data and the number of bits for low-bit grayscale data are determined based on the number of scattered sub-cycles of the PWM pulse width signal.

8. The method according to claim 7, characterized in that, After the low-bit grayscale data and the high-bit clock data are processed by the decoding logic circuit included in the decoder, the number of sub-cycles and position of the PWM pulse width signal for outputting the first high-bit grayscale data and the number of sub-cycles and position of the PWM pulse width signal for outputting the second high-bit grayscale data are determined.

9. The method according to claim 7, characterized in that, The decoder traverses the decoder's stored decoder table, processes the low-bit grayscale data and the high-bit clock data based on the traversal results, and determines the number and position of the sub-cycles of the PWM pulse width signal for outputting the first high-bit grayscale data and the number and position of the sub-cycles of the PWM pulse width signal for outputting the second high-bit grayscale data.

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