A superscalar RISC-V processor implements an L2 cache access interface for dedicated computational acceleration.

Abstract

This invention belongs to the field of integrated circuit design technology, specifically a superscalar RISC-V processor-based L2 cache memory access interface for dedicated computational acceleration. The invention includes modified logic for the original coherence bus interface of the open-source XuanTie processor and a coprocessor L2 memory access controller. The modified logic for the coherence bus interface handles the processing logic of coprocessor memory access instructions at the coherence bus entry point, including a coherence bus borrowing interface. The coprocessor L2 memory access controller is responsible for the conversion and management of memory access requests between the coprocessor and the coherence bus interface, including a load control state machine and a memory control state machine, coprocessor memory access request conversion and splitting logic, load response order-preserving logic, and memory response order-preserving logic. The coprocessor connected to the main processor can perform memory access operations on the L2 cache in the system through this memory access interface, completing access to the data area shared with the main processor.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to an L2 cache access interface for superscalar RISC-V processors to implement dedicated computing acceleration. Background Technology

[0002] Conventional general-purpose processors (CPUs) can run any program and process various types of data, playing a vital role in many different application scenarios. Due to the continuous evolution of integrated circuit manufacturing processes, CPUs have steadily and rapidly developed, and the improvement in instruction-level parallelism and the emergence of multi-core architectures have also brought stable performance improvements at the architectural level. However, as semiconductor process development slows down, instruction-level parallelism is approaching its limits, and the improvement of multi-core architectures is also limited by the parallelism within programs. Therefore, application-specific processors (ASICs) optimized for specific application domains have a significant advantage in energy efficiency compared to conventional CPUs. However, completely replacing the functions of coprocessors with ASICs requires substantial hardware and software development costs and suffers from poor flexibility and scalability. Therefore, using ASICs as coprocessors integrated with general-purpose processors is a better choice. However, the data interaction efficiency between typical coprocessor interfaces and the main processor is low, severely limiting performance in computational scenarios where the coprocessor requires large amounts of data. Summary of the Invention

[0003] To overcome the shortcomings of existing technologies, the purpose of this invention is to propose an L2 Cache (secondary cache) memory access interface for superscalar RISC-V processors to implement dedicated computing acceleration, providing coprocessors with an interface to access the L2-Cache to meet the computing scenarios involving large amounts of data.

[0004] The superscalar processor refers to a processor that provides high throughput by implementing instruction-level parallelism, but still requires a coprocessor for acceleration in some specialized computing scenarios.

[0005] This invention provides a coprocessor L2 cache memory access interface, which can access the L2 cache and obtain data in the shared memory region with the main processor through the coherence bus unit of the superscalar RISC-V processor. Specifically, it consists of two parts: a modified coherence bus unit interface logic for the open-source XuanTie processor and a coprocessor L2 memory access controller. The modified coherence bus unit interface logic handles the processing logic of coprocessor memory access requests at the coherence bus unit entry point, including a coherence bus borrowing interface. The coprocessor L2 memory access controller manages the coprocessor memory access request and response behavior, performing conversion, splitting, and address data dealignment processing of coprocessor memory access requests, including a load control state machine and a storage control state machine, coprocessor memory access request conversion and splitting logic, load response order-preserving logic, and storage response order-preserving logic.

[0006] The conformance bus unit interface modification logic and coprocessor L2 memory access controller provided by this invention will be introduced using the open-source superscalar RISC-V processor—Xuantie C910—as an example. It includes: a conformance bus borrowing interface, a load control state machine and a memory control state machine, coprocessor memory access request conversion and splitting logic, load response ordering logic, and memory response ordering logic; wherein:

[0007] The coherence bus borrowing interface is a functional interface responsible for sending memory access requests from the coprocessor to the coherence bus and receiving memory access responses. This interface completes the processing logic of read and write requests and listening transactions at the interface between the coprocessor and the coherence bus. It performs staking processing on read and write memory access requests, processes listening transactions sent by the coherence bus unit to the coprocessor interface, and returns a response to the coherence bus that does not contain a listening transaction cache line.

[0008] The load control state machine is the control logic responsible for completing coprocessor load requests. It contains three states: load_idle, load_req, and load_resp. Load_idle represents the idle state, where no coprocessor load request is currently being processed; load_req represents the current receipt of a coprocessor load request; and load_resp represents the completion of receiving the coprocessor load request and the waiting for the load data response to be returned to the coprocessor.

[0009] The storage control state machine is the control logic responsible for handling coprocessor storage requests. It contains three states: store_idle, store_req, and store_resp. store_idle represents the idle state, where no coprocessor storage request is currently being processed; store_req represents the current state where a coprocessor storage request has been received; and store_resp represents the state where the coprocessor storage request has been received and the system is waiting for a storage response.

[0010] The coprocessor memory access request conversion and splitting logic is responsible for splitting memory access requests and converting them into ACE protocol consistency transaction requests. After a memory access request is issued by the coprocessor, it is split into several ACE protocol consistency transaction requests at the granularity of cache lines. Addresses of unaligned cache lines are aligned, and data is aligned before being sent to the consistency bus unit to access the L2 cache. For load memory access requests, they are converted into ReadOnce transactions in the ACE protocol and sent to the consistency bus unit through the read request channel. The response data is returned through the read response channel, processed, and then returned to the coprocessor. For storage memory access requests, they are converted into WriteUnique or WriteUniqueLine transactions in the ACE protocol and sent to the consistency bus unit through the write request channel. Data is sent through the write data channel, and the response is returned through the write response channel, processed, and then returned to the coprocessor.

[0011] The load response ordering logic is responsible for maintaining the order of out-of-order returned load data. Its main structure includes a read response buffer that can store 8 cache lines. When a load memory access request is initiated to the consistency bus, an item is allocated and assigned index information. After the load response is returned, it is used to fill the read response buffer. The data is then aligned and shifted according to the order of the read response buffer and then returned to the coprocessor. The released read buffer can be reassigned to new load requests.

[0012] The storage response ordering logic is responsible for maintaining the order of out-of-order write responses. Its main structure includes an 8-item write response buffer. When a storage request is initiated to the consistency bus, an item is allocated and index information is assigned. After the write response is returned, the write response buffer can be released. The released write response buffer can be reassigned to a new storage request. After all write responses are collected, the final write response is returned to the coprocessor.

[0013] The workflow for coprocessor memory access requests in the system is as follows:

[0014] (1) The coprocessor sends memory access requests through the L2Cache memory access interface. Load memory access requests and storage memory access requests are sent through two independent channels, and the two types of requests can be processed simultaneously.

[0015] (2) For a load memory access request, the request includes the physical address of the memory access and the number of bytes requested. When a load memory access request is received, the load control state machine jumps from the load_idle state to the load_req state. When the load request is received by the conversion and splitting processing logic, it jumps to the load_resp state to wait for a response. Unaligned memory access addresses are aligned, and memory access requests are split into several cache line granularities according to the number of bytes requested. They are converted into consistent transactions of the ACE protocol and then sent to the consistency bus unit to access the L2 cache. A read buffer is allocated for each memory access request. When the read response data returns from the consistency bus unit, it is filled into the read buffer according to the index. The data is shifted and aligned and then returned to the coprocessor in order. When all data responses are returned, the load control state machine jumps from the load_resp state to the load_idle state to receive the next load memory access request from the coprocessor.

[0016] (3) For a storage access request, the request includes the physical address of the accessed memory, the number of bytes requested, and the data to be stored. When a storage access request is received, the storage control state machine jumps from the store_idle state to the store_req state. When the storage access request is received by the conversion and splitting processing logic, the storage control state machine jumps from the store_req state to the store_resp state. For unaligned addresses and data, alignment is performed. The storage access request is split into several cache line-level storage access requests according to the number of bytes requested and converted into a consistent transaction of the ACE protocol. Then, it is sent to the consistency bus unit to access the L2Cache and an item of the write response buffer is allocated for each request. When the consistency bus unit returns the write response, the corresponding item is marked according to the index and then released in order. When all storage access responses are received, the final write response is sent to the coprocessor. The storage control state machine jumps from the store_resp state to the store_idle state and can receive the next storage access request from the coprocessor.

[0017] This invention provides a high-bandwidth L2Cache memory access interface for coprocessors with low interface logic complexity. The coprocessor can simultaneously read and write to the L2Cache through a simple memory access interface, accessing data in the memory area shared with the main processor. It is suitable for computing scenarios where the coprocessor needs to access large amounts of continuous data. Attached Figure Description

[0018] Figure 1This diagram shows the signal connections between the coprocessor's L2 Cache memory access interface and the main processor.

[0019] Figure 2 This diagram illustrates the interaction between the coprocessor's L2 Cache memory access interface and the main processor.

[0020] Figure 3 Flowchart of the process for loading memory access requests for the coprocessor L2Cache memory access interface.

[0021] Figure 4 A flowchart illustrating the process of storing memory access requests for the coprocessor's L2Cache memory access interface. Detailed Implementation

[0022] In this invention, the signal connection relationship between the coprocessor's L2 Cache memory access interface and the main processor is as follows: Figure 1 As shown, the coprocessor L2 Cache memory access interface is connected to the main processor through the DSA L2 controller. It consists of two parts: a load interface and a storage interface. The load interface is responsible for handling load requests and load response data, while the storage interface is responsible for handling storage requests, storage data, and storage responses.

[0023] Figure 2 This demonstrates the connection between the coprocessor and the main processor. The coprocessor connects to the DSA L2 controller via a memory access interface. The DSA L2 controller sends memory access requests to the main processor's coherence bus unit, which then accesses the L2 cache, thus enabling data interaction with the main processor. The coprocessor's load and store memory access requests use separate channels, allowing for simultaneous processing. Figure 3 This demonstrates the process of handling memory access requests. Figure 4 This demonstrates the processing flow of storage access requests. The specific workflow for a coprocessor's storage access request is as follows:

[0024] For a load memory access request, the coprocessor sends the memory access address and the number of bytes to be accessed to the DSA L2 controller through the load interface in the memory access interface. The read state machine in the DSA L2 controller jumps from the load_idle state to the load_req state, stores the memory access address and the number of bytes to be accessed, and then jumps to the load_resp state. After aligning the memory access address, it initiates a ReadOnce consistency transaction request in the ACE protocol to the consistency bus unit through the read request channel according to the granularity of the cache line. It also allocates a read response buffer for the request and uses the index information as the number of the request. After being queried at the entry point of the consistency bus unit, the request reaches the processing logic inside the consistency bus unit and then reads the data from the L2-Cache. The consistency bus unit always returns a listen response without a cache line for the cache consistency listen request. A request byte count counter is used to record the number of bytes that have been requested. The starting address of the next request to the coherence bus unit is calculated based on the request byte count counter and the memory access initial address. Each time a request is issued, the request byte count counter is incremented by the number of bytes requested. When the request byte count counter is less than the number of bytes accessed and the read response buffer is not full, requests are continuously sent to the coherence bus unit until the request byte count counter equals the number of bytes accessed.

[0025] For load memory access responses, the response data is returned from the coherence bus unit to the DSA L2 controller. Based on the response number, it is filled into the allocated read response buffer. The read response pointer starts from the head of the read response buffer. Once the read response buffer entry pointed to by the read response pointer has been filled, the aligned read data response is returned to the coprocessor, and the entry is released for the next request. The read response pointer then points to the next entry. Read response data is sent to the coprocessor in 16-byte increments. An indication signal is sent to the coprocessor simultaneously with the return of the last read response data. Furthermore, the read control state machine jumps from load_resp back to load_idle, ready to receive the next load memory access request from the coprocessor.

[0026] For memory access requests, the coprocessor sends the memory access address, the number of bytes to be accessed, and the data to be accessed to the DSA L2 controller through the memory access interface. The data is transmitted in multiple 16-byte increments. The write state machine in the DSA L2 controller jumps from the store_idle state to the store_req state, stores the memory access address and the number of bytes to be accessed, and then jumps to the store_resp state to initiate an ACE protocol consistency transaction request to the consistency bus unit. The coprocessor's memory request is split into several ACE protocol WriteUniqueLine and WriteUnique consistency transaction requests and sent to the consistency bus unit. After being processed at the consistency bus unit's entry point, the request reaches the processing logic inside the consistency bus unit and writes the data into the L2 cache. For requests with cache-line aligned addresses and a requested byte size greater than the cache line size, a WriteUniqueLine consistency transaction request is sent to the consistency bus at the cache line granularity, and the data is shifted and aligned before being sent to the consistency bus unit. For requests with non-cache-line aligned addresses, or requests with a byte size less than the cache line size, the request address is aligned to the bus width, and a WriteUnique consistency transaction request is sent to the consistency bus at the bus width granularity, and the corresponding data is shifted and aligned before being sent to the consistency bus unit. The memory access address is calculated based on the initial memory access address and the requested byte counter. For each request, a write response buffer is allocated for the request, and the index information is used as the request number. The requested byte counter is incremented by the requested byte size. When the requested byte counter equals the memory access byte size, the request is stopped from being sent to the consistency bus unit.

[0027] For memory access responses, after each write response is completed, it is returned from the coherence bus unit to the DSAL2 controller. The corresponding write response buffer entry is marked according to the response number. The write response pointer starts from the head of the write response buffer. When the write response buffer entry pointed to by the pointer has been marked, that entry can be released for the next request, and the pointer moves to the next entry. After all write responses have returned from the coherence bus unit, the DSA L2 controller sends a memory access response to the coprocessor, indicating that the memory access request is complete. The write control state machine then transitions from the store_resp state to the store_idle state, ready to receive the next memory access request from the coprocessor.

Claims

1. An L2 cache access interface for implementing dedicated computational acceleration in a superscalar RISC-V processor, characterized in that, It accesses the L2 cache and retrieves data from the shared memory region with the main processor through the coherence bus unit of the superscalar RISC-V processor; it consists of two parts: the coherence bus unit interface modification logic of the open-source XuanTie processor and the coprocessor L2 memory access controller; wherein, the coherence bus unit interface modification logic completes the processing logic of the coprocessor memory access request at the coherence bus unit entry, and the specific logic module includes the coherence bus unit borrowing interface; the coprocessor L2 memory access controller is responsible for managing the coprocessor memory access request behavior and response behavior, and completes the transformation, splitting and address data non-alignment processing of the coprocessor memory access request, and the specific logic module includes: load control state machine and storage control state machine, coprocessor memory access request transformation and splitting logic, load response order preservation logic, and storage response order preservation logic; wherein: The consensus bus unit borrowing interface is a functional interface responsible for sending memory access requests from the coprocessor to the consensus bus and receiving memory access responses. This interface completes the processing logic of read and write requests and listening transactions at the interface between the coprocessor and the consensus bus unit. It performs staking processing on read and write memory access requests respectively, processes the listening transactions sent by the consensus bus unit to the coprocessor interface, and returns a response to the consensus bus that does not contain a listening transaction cache line. The load control state machine is the control logic responsible for completing coprocessor load requests. It contains three states: load_idle, load_req, and load_resp. Load_idle represents the idle state, where no coprocessor load request is currently being processed. Load_req represents the current receipt of a coprocessor load request. Load_resp represents the completion of receiving the coprocessor load request and waiting for the load data to be returned to the coprocessor. The storage control state machine is the control logic responsible for completing coprocessor storage requests. It contains three states: store_idle, store_req, and store_resp. Store_idle represents the idle state, where no coprocessor storage request is currently being processed. Store_req represents the current receipt of a coprocessor storage request. Store_resp represents the completion of receiving the coprocessor storage request and waiting for the storage response. The coprocessor memory access request conversion and splitting logic is responsible for splitting memory access requests and converting them into ACE protocol consistency transaction requests. After a memory access request is issued by the coprocessor, it is split into several ACE protocol consistency transaction requests at the granularity of cache lines. Addresses of unaligned cache lines are aligned, and after data alignment, the requests are sent to the consistency bus unit to access the L2 cache. For load memory access requests, they are converted into ReadOnce transactions in the ACE protocol and sent to the consistency bus unit through the read request channel. The response data is returned through the read response channel, processed, and then returned to the coprocessor. For storage memory access requests, they are converted into WriteUnique or WriteUniqueLine transactions in the ACE protocol and sent to the consistency bus unit through the write request channel. Data is sent through the write data channel, and the response is returned through the write response channel, processed, and then returned to the coprocessor. The load response order preservation logic is responsible for preserving the order of out-of-order returned load data. Its structure includes a read response buffer with 8 cache lines. When a load memory access request is initiated to the consistency bus, an item is allocated and index information is assigned. After the load response is returned, it is used to fill the read response buffer. The data is then aligned and shifted according to the order of the read response buffer before being returned to the coprocessor. The released read buffer can be reassigned to a new load request. The storage response ordering logic is responsible for maintaining the order of out-of-order write responses. Its structure includes an 8-item write response buffer. When a storage request is initiated to the consistency bus, an item is allocated and index information is assigned. After the write response is returned, the write response buffer can be released. The released write response buffer can be reassigned to a new storage request. After all write responses are collected, the final write response is returned to the coprocessor.

2. The L2 Cache access interface according to claim 1, characterized in that, The workflow of the coprocessor memory access request in the system is as follows: (1) The coprocessor sends memory access requests through the L2 Cache memory access interface. Load memory access requests and storage memory access requests are sent through two independent channels, and the two types of requests can be processed simultaneously. (2) For a load memory access request, the request includes the physical address of the memory access and the number of bytes requested. When a load memory access request is received, the load control state machine jumps from load_idle to load_req. When the load request is received by the conversion and splitting processing logic, it jumps to load_resp to wait for a response. Unaligned memory access addresses are aligned, and memory access requests are split into several cache line granularities according to the number of bytes requested. They are converted into ACE protocol consistency transactions and then sent to the consistency bus unit to access the L2 Cache. A read buffer is allocated for each memory access request. When the read response data is returned from the consistency bus unit, it is filled into the read buffer according to the index. The data is shifted and aligned and then returned to the coprocessor in order. When all data responses are returned, the load control state machine jumps from load_resp to load_idle to receive the next load memory access request from the coprocessor. (3) For a storage access request, the request includes the physical address of the access, the number of bytes requested, and the data to be stored. When the storage access request is received, the storage control state machine jumps from the store_idle state to the store_req state. When the storage access request is received by the conversion and splitting processing logic, the storage control state machine jumps from the store_req state to the store_resp state. For unaligned addresses and data, alignment is performed. The access request is split into several cache line-level access requests according to the number of bytes requested and converted into a consistent transaction of the ACE protocol. Then, it is sent to the consistency bus unit to access the L2 cache and an item of the write response buffer is allocated for each request. When the consistency bus unit returns the write response, the corresponding item is marked according to the index and then released in order. When all access responses are received, the final write response is sent to the coprocessor. The storage control state machine jumps from the store_resp state to the store_idle state and can receive the next storage access request from the coprocessor.

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