Display device

Abstract

An object of the embodiment is to provide a display device capable of suppressing a decrease in reliability. According to the embodiment, a display device includes: a first substrate including a scan line extending along a first direction, a signal line extending along a second direction, a switching element including a drain electrode, a first connection electrode electrically connected to one end portion of the drain electrode, a pixel electrode overlapping the first connection electrode and electrically connected to the first connection electrode, and a power supply line separated from the first connection electrode and disposed around the pixel electrode; a second substrate including a second transparent substrate having a side surface, and a common electrode facing the pixel electrode; a liquid crystal layer disposed between the first substrate and the second substrate, and including a high-molecular dispersion type liquid crystal; and a light emitting module disposed along the side surface, the power supply line having a side edge extending along the second direction, the first connection electrode being a transparent electrode formed of the same material as the power supply line, and extending along the first direction and having an end portion facing the side edge.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices. Background Technology

[0002] In recent years, various devices using polymer-dispersed liquid crystals have been proposed that can switch between a scattering state that scatters incident light and a transparent state that allows incident light to pass through. In one example, a display device is described, comprising a first light-transmitting substrate, a second light-transmitting substrate, a liquid crystal layer having a polymer-dispersed liquid crystal encapsulated between the first and second light-transmitting substrates, and at least one light-emitting portion disposed opposite to at least one side of the first and second light-transmitting substrates.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-021974

[0006] Patent Document 2: Japanese Patent Application Publication No. 2020-091400 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] The purpose of this implementation is to provide a display device that can suppress reliability degradation.

[0009] Methods for solving problems

[0010] According to one embodiment, the display device includes:

[0011] A first substrate includes: a first transparent substrate, a scan line extending along a first direction, a signal line extending along a second direction intersecting the first direction, a switching element having a drain electrode extending in the second direction and electrically connected to the scan line and the signal line, a first connecting electrode electrically connected to one end of the drain electrode, a pixel electrode overlapping with and electrically connected to the first connecting electrode, and a power supply line separated from the first connecting electrode and disposed around the pixel electrode; a second substrate includes: a second transparent substrate having a side surface and a common electrode opposite to the pixel electrode; a liquid crystal layer disposed between the first substrate and the second substrate and comprising a polymer-dispersed liquid crystal; and a light-emitting module disposed along the side surface, the power supply line having a side edge extending along the second direction, the first connecting electrode being a transparent electrode formed of the same material as the power supply line and extending along the first direction and having an end opposite to the side edge.

[0012] Invention Effects

[0013] According to the embodiments, a display device that can suppress the reduction of reliability can be provided. Attached Figure Description

[0014] Figure 1 This is a top view illustrating an example of a display device DSP according to an embodiment.

[0015] Figure 2 This is a top view showing the area near the light-emitting module 100.

[0016] Figure 3 This is a top view showing an example of pixel PX.

[0017] Figure 4 It is shown Figure 3 A top view of an example of a pixel electrode PE configured in pixel PX.

[0018] Figure 5 It is shown Figure 4 A top view of an example of a switching element SW.

[0019] Figure 6 It shows along Figure 5 The cross-sectional view shown along line AB is an example of a display panel PNL containing the first substrate SUB1.

[0020] Figure 7 It shows along Figure 5 A cross-sectional view of an example of the first substrate SUB1 of the CD line shown.

[0021] Figure 8 It is shown Figure 3 A top view of an example of the insulating film IL and the light-shielding layer BM shown.

[0022] Figure 9 This is a top view showing another example of the configuration.

[0023] Figure 10 It shows along Figure 9 The cross-sectional view shown along line AB is an example of a display panel PNL containing the first substrate SUB1.

[0024] Figure 11 This is a cross-sectional view of the display device DSP. Detailed Implementation

[0025] The following description of this embodiment is based on the accompanying drawings. It should be noted that the disclosed text is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art without departing from the spirit of the invention are naturally included within the scope of this invention. Furthermore, regarding the drawings, to make the description clearer, the width, thickness, shape, etc., of each part are sometimes schematically shown compared to the actual embodiment; however, this is merely an example and does not limit the interpretation of the invention. Additionally, in this specification and the various figures, for constituent elements that perform the same or similar functions as those described with reference to previously presented figures, there are instances where the same reference numerals are used and repeated detailed descriptions are appropriately omitted.

[0026] Figure 1 This is a top view showing an example of the display device DSP according to this embodiment. In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but they may also intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to directions parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In this embodiment, the case of observing the XY plane defined by the first direction X and the second direction Y is referred to as top view.

[0027] The display device DSP includes a display panel PNL, a wiring substrate 1, an IC chip 2, and a light-emitting module 100.

[0028] The display panel PNL includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC containing a polymer-dispersed liquid crystal, and a sealing portion SE. The first substrate SUB1 and the second substrate SUB2 are formed as flat plates along the XY plane. The first substrate SUB1 and the second substrate SUB2 overlap when viewed from above. The overlapping area of ​​the first substrate SUB1 and the second substrate SUB2 includes the display area DA for displaying images.

[0029] The first substrate SUB1 includes a first transparent substrate 10, and the second substrate SUB2 includes a second transparent substrate 20. The first transparent substrate 10 has side surfaces 101 and 102 along a first direction X, and side surfaces 103 and 104 along a second direction Y. The second transparent substrate 20 has side surfaces 201 and 202 along the first direction X, and side surfaces 203 and 204 along the second direction Y.

[0030] exist Figure 1In the example shown, when viewed from above, sides 102 and 202, sides 103 and 203, and sides 104 and 204 overlap, but may not overlap. Side 201 does not overlap with side 101 and is located between side 101 and the display area DA. The first substrate SUB1 has an extension Ex between side 101 and side 201. That is, the extension Ex corresponds to the portion of the first substrate SUB1 that extends in the second direction Y from the portion that overlaps with the second substrate SUB2, and does not overlap with the second substrate SUB2.

[0031] In addition, Figure 1 In the example shown, the display panel PNL is formed as a rectangle extending in the first direction X. That is, sides 101 and 102, and sides 201 and 202 are sides along the long side of the display panel PNL, and sides 103 and 104, and sides 203 and 204 are sides along the short side of the display panel PNL. It should be noted that the display panel PNL can be formed as a rectangle extending in the second direction Y, or it can be formed as a square, or it can be formed as other polygonal shapes, or other shapes such as circles or ellipses.

[0032] Wiring substrate 1 and IC chip 2 are mounted on the extension portion Ex. Wiring substrate 1 is, for example, a flexible printed circuit board that can be bent. IC chip 2, for example, has a built-in display driver that outputs signals required for image display. It should be noted that IC chip 2 can also be mounted on wiring substrate 1. Figure 1 In the example shown, multiple wiring substrates 1 arranged in the first direction X are mounted on the display panel PNL, but a single wiring substrate 1 extending in the first direction X can also be mounted. Additionally, multiple IC chips 2 arranged in the first direction X are mounted on the display panel PNL, or a single IC chip 2 extending in the first direction X can also be mounted.

[0033] Details of the light-emitting module 100 will be described later. When viewed from above, the light-emitting module 100 overlaps with the extension Ex and is arranged along the side 201 of the second transparent substrate 20.

[0034] The sealing portion SE bonds the first substrate SUB1 and the second substrate SUB2 together. In addition, the sealing portion SE is formed in the shape of a rectangular frame, surrounding the liquid crystal layer LC between the first substrate SUB1 and the second substrate SUB2.

[0035] The liquid crystal layer LC is held between the first substrate SUB1 and the second substrate SUB2. Such a liquid crystal layer LC is configured to cover the area (including the display area DA) surrounded by the sealing portion SE when viewed from above.

[0036] like Figure 1As schematically enlarged, the liquid crystal layer LC comprises a polymer 31 and liquid crystal molecules 32. In one example, the polymer 31 is a liquid crystal polymer. The polymer 31 is formed as a rib extending along a first direction X and arranged in a second direction Y. The liquid crystal molecules 32 are dispersed in the gaps between the polymers 31, with their long axes oriented along the first direction X. Both the polymer 31 and the liquid crystal molecules 32 have optical anisotropy or refractive index anisotropy. The responsiveness of the polymer 31 to an electric field is lower than that of the liquid crystal molecules 32.

[0037] In one example, the orientation of polymer 31 remains almost unchanged regardless of the presence or absence of an electric field. On the other hand, when a high voltage above a threshold is applied to the liquid crystal layer LC, the orientation of the liquid crystal molecules 32 changes according to the electric field. In the initial orientation state (when no voltage is applied to the liquid crystal layer LC), the optical axes of polymer 31 and liquid crystal molecules 32 are approximately parallel, and almost all light incident on the liquid crystal layer LC passes through it (transparent state). When a voltage is applied to the liquid crystal layer LC, the orientation of the liquid crystal molecules 32 changes, and the optical axes of polymer 31 and liquid crystal molecules 32 intersect. Therefore, light incident on the liquid crystal layer LC is scattered within the liquid crystal layer LC (scattering state).

[0038] Figure 2 This is a top view showing the area near the light-emitting module 100. The light-emitting module 100 includes a plurality of light-emitting elements 110 and a light guide 120. The plurality of light-emitting elements 110 are arranged along a first direction X. The light guide 120 is formed as a rod extending in the first direction X. The light guide 120 is located between the sealing portion SE and the light-emitting elements 110.

[0039] The display area DA has multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. These pixels PX are represented by dashed lines in the figure. In addition, each pixel PX has a pixel electrode PE, which is represented by a quadrilateral with solid lines in the figure.

[0040] like Figure 2 As shown in the enlarged view, each pixel PX has a switching element SW. The switching element SW is, for example, composed of a thin-film transistor (TFT) and is electrically connected to the scan line G and the signal line S. The scan line G is electrically connected to the switching elements SW in each pixel PX arranged in the first direction X. The signal line S is electrically connected to the switching elements SW in each pixel PX arranged in the second direction Y. The pixel electrode PE is electrically connected to the switching element SW.

[0041] A common electrode CE and a power supply line CL are configured to cover the display area DA and its surrounding area. A specified voltage Vcom is applied to the common electrode CE. A voltage, for example, at the same potential as the common electrode CE, is applied to the power supply line CL.

[0042] Each pixel electrode PE is opposite the common electrode CE in the third direction Z. In the display area DA, the liquid crystal layer LC (specifically, liquid crystal molecules 32) is driven by the electric field generated between the pixel electrode PE and the common electrode CE. A capacitor CS is formed, for example, between the power supply line CL and the pixel electrode PE.

[0043] As explained later, the scan line G, signal line S, power supply line CL, switching element SW and pixel electrode PE are disposed on the first substrate SUB1, and the common electrode CE is disposed on the second substrate SUB2.

[0044] Figure 3 This is a top view showing an example of pixel PX. Here, only a portion of the structure contained in the first substrate SUB1 is shown.

[0045] The first substrate SUB1 includes multiple scan lines G, multiple signal lines S, a switching element SW, a power supply line CL, a metal line ML, an insulating film IL, and a connecting electrode (first connecting electrode) CN1.

[0046] As described above, multiple scan lines G extend in the first direction X. Multiple signal lines S extend in the second direction Y and intersect with the multiple scan lines G. In this specification, pixel PX corresponds to the area defined by two adjacent scan lines G and two adjacent signal lines S. A switching element SW is disposed at the intersection of the scan lines G and the signal lines S.

[0047] An insulating film IL is formed in each pixel PX in a lattice shape with a defined opening OP. The insulating film IL is, for example, an organic insulating film. The insulating film IL overlaps with the scan line G, the signal line S, and the switching element SW, respectively. The drain electrode DE of the switching element SW extends to the opening OP. The connecting electrode CN1 is formed in an island shape, located in the opening OP, and electrically connected to one end of the drain electrode DE.

[0048] Power supply lines CL are disposed on the insulating film IL, forming a grid surrounding pixel PX. The planar shape of the power supply lines CL is approximately the same as that of the insulating film IL. The power supply lines CL are separate from the connecting electrode CN1. The opening OPC of the power supply lines CL overlaps with the opening OP of the insulating film IL. Metal lines ML are disposed on the power supply lines CL, forming a grid surrounding pixel PX. The metal lines ML are formed to have a smaller width than the power supply lines CL and do not extend from the power supply lines CL when viewed from above. These power supply lines CL and metal lines ML overlap with the scan line G, signal line S, and switching element SW, respectively.

[0049] Figure 4 It is shown Figure 3This is a top view of an example of a pixel electrode PE configured in a pixel PX. The pixel electrode PE, indicated by a single-dotted line, overlaps with the opening OPC of the power supply line CL. Furthermore, the peripheral portion of the pixel electrode PE overlaps with the power supply line CL. An insulating film is sandwiched between the pixel electrode PE and the power supply line CL. Figure 2 The capacitor CS shown is formed between the periphery of the pixel electrode PE and the power supply line CL.

[0050] The connecting electrode CN1 is located in the opening OPC. The pixel electrode PE overlaps with the connecting electrode CN1 in the opening OPC. A contact hole CH1 is formed in the insulating film between the pixel electrode PE and the connecting electrode CN1. The pixel electrode PE is connected to the connecting electrode CN1 in the contact hole CH1. Thus, the pixel electrode PE is electrically connected to the switching element SW.

[0051] It should be noted that, Figure 4 The light-shielding layer BM, disposed on the second substrate SUB2, is shown in dashed lines. The light-shielding layer BM is formed in a lattice shape and overlaps with the power supply line CL, the switching element SW, and a portion of the connecting electrode CN1 when viewed from above. Of course, the light-shielding layer BM also... Figure 3 The scan line G, signal line S, and metal line ML shown overlap. Additionally, the light-shielding layer BM has an opening AP that overlaps with the pixel electrode PE when viewed from above. As described later, the contact hole CH1 is located at the opening AP.

[0052] Figure 5 It is shown Figure 4 The diagram shows a top view of an example of a switching element SW. The switching element SW includes a semiconductor SC, a gate electrode GE integrated with the scan line G, a source electrode SO integrated with the signal line S, a drain electrode DE, and an auxiliary gate electrode AG. The power supply line CL, indicated by a dashed line, overlaps with the switching element SW.

[0053] Semiconductor SC can be, for example, an oxide semiconductor, but it can also be polycrystalline silicon or amorphous silicon. Figure 5 In the example shown, three semiconductors SC overlap with the gate electrode GE and are arranged spaced apart along the second direction Y. An auxiliary gate electrode AG overlaps with the gate electrode GE and the semiconductors SC. The semiconductor SC is located between the gate electrode GE and the auxiliary gate electrode AG. The auxiliary gate electrode AG further overlaps with the scan line G. A connecting electrode CN2 is sandwiched between the scan line G and the auxiliary gate electrode AG.

[0054] A contact hole CH21 is formed in the insulating film between the scan line G and the connecting electrode CN2. The connecting electrode CN2 is connected to the scan line G through the contact hole CH21. A contact hole CH22 is formed in the insulating film between the connecting electrode CN2 and the auxiliary gate electrode AG. The auxiliary gate electrode AG is connected to the connecting electrode CN2 through the contact hole CH22. Thus, the auxiliary gate electrode AG and the gate electrode GE are similarly electrically connected to the scan line G. That is, the gate electrode GE and the auxiliary gate electrode AG are at the same potential as the scan line G.

[0055] The source electrode SO and the drain electrode DE extend along the second direction Y and are arranged at intervals along the first direction X. The source electrode SO is connected to one end of the semiconductor SC. The drain electrode DE is connected to the other end of the semiconductor SC. The drain electrode DE bends midway and extends to the opening OPC.

[0056] One end DEA of the drain electrode DE is located at the opening OPC and overlaps with the connecting electrode (second connecting electrode) CN3. A contact hole CH3 is formed in the insulating film between the drain electrode DE and the connecting electrode CN3. The drain electrode DE is connected to the connecting electrode CN3 in the contact hole CH3.

[0057] The connecting electrode CN1, indicated by a dashed line, is connected to the connecting electrode CN3. Therefore, the connecting electrode CN1 is electrically connected to the switching element SW, and in the contact hole CH1... Figure 4 The pixel electrode PE is electrically connected as shown. It should be noted that, as described later, the connecting electrode CN1 is a transparent electrode made of the same material as the power supply line CL. Furthermore, the drain electrode DE and the connecting electrode CN3 are made of metallic material.

[0058] The connecting electrode CN1 is formed in a way that extends in width along the first direction X, and has an end SS opposite to the side edge CLE of the power supply line CL that extends along the second direction Y. In one example, the end SS corresponds to the short side of the connecting electrode CN1 that extends along the second direction Y. In addition to the short side (end) SS, the connecting electrode CN1 also has long sides LS1 and LS2 extending along the first direction, and oblique sides OS1 and OS2 extending obliquely along directions intersecting the first direction X and the second direction Y. Oblique side OS1 connects the short side SS to the long side LS1, and oblique side OS2 connects the short side SS to the long side LS2.

[0059] When viewed from above, contact hole CH1 is formed at a position that does not overlap with the drain electrode DE and the connecting electrode CN3. Contact hole CH3 and contact hole CH1 are arranged in the first direction X. Furthermore, the drain electrode DE and contact hole CH1, or the connecting electrode CN3 and contact hole CH1, are arranged in the first direction X. Contact hole CH3, drain electrode DE, and connecting electrode CN3 are located between power supply line CL and contact hole CH1 in the first direction X.

[0060] Additionally, when viewed from above, the short side SS is located between the power supply line CL and the drain electrode DE (or the connecting electrode CN3). The distance D1 between the short side SS and the drain electrode DE along the first direction X is less than the distance D2 between the short side SS and the power supply line CL along the first direction X.

[0061] The power supply line CL has a recess CC that faces the connecting electrode CN1 when viewed from above. That is, a portion of the side edge CLE of the power supply line CL extending along the second direction Y is recessed. In other words, regarding the width of the power supply line CL extending along the second direction Y along the first direction X, the width of the portion adjacent to the connecting electrode CN1 is smaller than the width of the other portions. Therefore, compared to the case where the side edge CLE is formed as a straight line, the distance D2 between the power supply line CL and the connecting electrode CN1 can be increased.

[0062] It should be noted that, Figure 5 The light-shielding layer BM is shown in dashed lines. When viewed from above, the light-shielding layer BM overlaps with the drain electrode DE, the connecting electrode CN3, and the contact hole CH3, but does not overlap with the contact hole CH1. That is, the contact hole CH1 is located at the opening AP of the light-shielding layer BM. In summary, the connecting electrode CN1 is a transparent electrode as described above, but the portion of the connecting electrode CN1 that overlaps with the drain electrode DE (made of metallic material) and the connecting electrode CN3 overlaps with the light-shielding layer BM, while the other portion of the connecting electrode CN1 overlaps with the opening AP.

[0063] Figure 6 It shows along Figure 5 The cross-sectional view shown is an example of a display panel PNL including the first substrate SUB1 shown along line AB. The first substrate SUB1 includes a first transparent substrate 10, insulating films 11 to 13, insulating film IL, switching element SW, power supply line CL, metal line ML, pixel electrode PE, and alignment film AL1.

[0064] A gate electrode GE, integrated with the scan line G, is disposed on the first transparent substrate 10. An insulating film 11 covers the first transparent substrate 10 and the gate electrode GE. A semiconductor SC is disposed on the insulating film 11, directly above the gate electrode GE. A source electrode SO and a drain electrode DE, integrated with the signal line S, are disposed on the insulating film 11 and are respectively connected to the semiconductor SC. These source electrodes SO and drain electrodes DE are formed of the same metal material. An insulating film 12 covers the insulating film 11, the source electrode SO, and the drain electrode DE. Furthermore, the insulating film 12 is connected to the semiconductor SC between the source electrode SO and the drain electrode DE.

[0065] The auxiliary gate electrode AG is disposed on the insulating film 12, directly above the gate electrode GE and the semiconductor SC. The connecting electrode CN3 is disposed on the insulating film 12 and is connected to the drain electrode DE in a contact hole CH3 formed in the insulating film 12. The auxiliary gate electrode AG and the connecting electrode CN3 are formed of the same metallic material. The insulating film IL covers the auxiliary gate electrode AG. On the other hand, the connecting electrode CN3 is located at the opening OP and is exposed from the insulating film IL.

[0066] The power supply line CL is disposed on the insulating film IL. The connecting electrode CN1 is separate from the power supply line CL and is disposed on the insulating film 12 in the opening OP of the insulating film IL or the opening OPC of the power supply line CL. That is, the power supply line CL and the connecting electrode CN1 are essentially located on the same layer and formed together using the same material. The connecting electrode CN1 is disposed on the connecting electrode CN3 and is connected to the connecting electrode CN3.

[0067] A metal wire ML is disposed on top of and connected to the power supply line CL. An insulating film 13 covers the power supply line CL, the metal wire ML, and the connecting electrode CN1. Furthermore, the insulating film 13 is connected to the insulating film 12 between the power supply line CL and the connecting electrode CN1.

[0068] The pixel electrode PE is disposed on the insulating film 13 and is connected to the connecting electrode CN1 in the contact hole CH1 formed in the insulating film 13. The periphery of the pixel electrode PE is opposite to the power supply line CL and the metal line ML through the insulating film 13. The alignment film AL1 covers the pixel electrode PE and the insulating film 13.

[0069] Insulating films 11 to 13 are, for example, transparent inorganic insulating films such as silicon oxide, silicon nitride, and silicon oxynitride. Insulating film IL is, for example, a transparent organic insulating film such as acrylic resin. The power supply line CL, the connecting electrode CN1, and the pixel electrode PE are transparent electrodes formed from transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). That is, the connecting electrode CN1 and the pixel electrode PE, which are connected to each other in the contact hole CH1, are both transparent.

[0070] The second substrate SUB2 includes a second transparent substrate 20, a light-shielding layer BM, a common electrode CE, a protective layer (overcoat layer) OC, and an alignment film AL2.

[0071] A light-shielding layer BM is disposed on the inner surface 20A of the second transparent substrate 20. The light-shielding layer BM is positioned across the liquid crystal layer LC and opposite the switching element SW, insulating film IL, power supply line CL, metal line ML, connecting electrode CN3, contact hole CH3, etc. An opening AP of the light-shielding layer BM is positioned across the liquid crystal layer LC and opposite the pixel electrode PE, contact hole CH1, etc. A common electrode CE overlaps with the light-shielding layer BM and is disposed in the opening AP on the inner surface 20A, facing the pixel electrode PE across the liquid crystal layer LC. A protective layer OC is a transparent organic insulating film that covers the common electrode CE. An alignment film AL2 covers the protective layer. In the second substrate SUB2, the protective layer OC may be omitted. In this case, the alignment film AL2 directly covers the common electrode CE.

[0072] Figure 7 It shows along Figure 5 A cross-sectional view of an example of the first substrate SUB1 of the CD line shown. A connecting electrode CN2 is disposed on the insulating film 11 and is connected to the scan line G in a contact hole CH21 formed in the insulating film 11. The connecting electrode CN2 is formed of the same metal material as the source electrode SO and the drain electrode DE. An insulating film 12 covers the insulating film 11, the connecting electrode CN2, the source electrode SO, and the drain electrode DE. An auxiliary gate electrode AG is disposed on the insulating film 12 and is connected to the connecting electrode CN2 in a contact hole CH22 formed in the insulating film 12.

[0073] As described above, the power supply line CL and the connecting electrode CN1 are substantially disposed on the same layer, formed using the same material and in the same process, and are required to be electrically insulated from each other. In this embodiment, the connecting electrode CN1 has an end or short side SS that extends along the first direction X and is opposite to the side edge CLE of the power supply line CL that extends along the second direction Y. Therefore, compared to the case where the side edge CLE is opposite to the long side LS1 of the connecting electrode CN1, the risk of short circuit between the power supply line CL and the connecting electrode CN1 can be reduced.

[0074] Furthermore, the power supply line CL has a recess CC opposite to the connecting electrode CN1. Therefore, compared to the case where the side edge CLE is formed in a straight line, the distance between the power supply line CL and the connecting electrode CN1 can be increased, further reducing the risk of short circuit between the power supply line CL and the connecting electrode CN1. Thus, reliability degradation can be suppressed.

[0075] A contact hole CH1, which connects the connecting electrode CN1 to the pixel electrode PE, is formed at a position that does not overlap with the drain electrode DE and the connecting electrode CN3. The light-shielding layer BM overlaps with the drain electrode DE and the connecting electrode CN3, but does not overlap with the contact hole CH1. The drain electrode DE and the connecting electrode CN3 are formed of a metallic material, and unwanted reflected light at the drain electrode DE and the connecting electrode CN3 is blocked by the light-shielding layer BM. Therefore, the display quality degradation caused by unwanted reflected light is suppressed.

[0076] Furthermore, the reflectivity of the connecting electrode CN1 and the pixel electrode PE, which are formed as transparent electrodes, is lower than that of the drain electrode DE and the connecting electrode CN3, which are formed as metal electrodes. Therefore, even if the area containing the contact hole CH1 overlaps with the opening AP, the impact of unwanted reflected light at the connecting electrode CN1 and the pixel electrode PE on display quality is almost negligible. Conversely, the overlap between the area containing the contact hole CH1 and the opening AP helps to increase the display area and improve the brightness of the displayed image.

[0077] Figure 8 It is shown Figure 3 The diagram shows an example top view of the insulating film IL and the light-shielding layer BM. The insulating film IL, being an organic insulating film, is formed as described above into a lattice shape with defined openings OP. The insulating film IL has a portion ILX extending along a first direction X and a portion ILY extending along a second direction Y.

[0078] The light-shielding layer BM, indicated by dashed lines, is formed in a lattice pattern and overlaps with the insulating film IL when viewed from above. The light-shielding layer BM has a portion BMX extending along a first direction X and a portion BMY extending along a second direction Y. The width of portion BMX is greater than the width of portion ILX, and portion BMX overlaps with the first side edge XE of portion ILX extending along the first direction X. The width of portion BMY is less than the width of portion ILY, and portion BMY does not overlap with the second side edge YE of portion ILY extending along the second direction Y.

[0079] The light L1 emitted from the light-emitting module 100 propagates along the second direction Y. At this time, near the first side edge XE in the insulating film IL, which is approximately orthogonal to the propagation direction of light L1, even if undesirable scattering occurs, it is blocked by the portion of BMX that overlaps with a portion of ILX. Therefore, it is possible to suppress the degradation of display quality.

[0080] It should be noted that almost no scattering occurs near the second side edge YE in the insulating film IL, which is roughly parallel to the propagation direction of light L1. Therefore, the undesirable scattered light near the second side edge YE has a negligible impact on display quality. Conversely, the area near the second side edge YE overlaps with the opening AP, thereby contributing to an increase in display area and improving the brightness of the displayed image.

[0081] Next, we will explain other examples of the composition.

[0082] Figure 9 This is a top view showing another configuration example. The configuration of the switching element SW is similar to... Figure 5 The examples shown are the same, so explanations are omitted.

[0083] Figure 9 The example shown is similar to Figure 5 The example shown differs from the one shown in that it omits the connection electrodes CN1 and CN3. That is to say, Figure 4 The pixel electrode PE shown is connected to the drain electrode DE in a contact hole CH11 that overlaps with one end of the drain electrode DE DE, and is electrically connected to the switching element SW. The light-shielding layer BM, indicated by the dashed line, overlaps with the drain electrode DE and the contact hole CH11 when viewed from above.

[0084] Figure 10 It shows along Figure 9 The diagram shows a cross-sectional view of an example of a display panel PNL including the first substrate SUB1, as shown along line AB. Here, the main focus is on... Figure 6 The differences between the examples shown.

[0085] The insulating film 12 has a contact hole CH11 in the opening OP of the insulating film 11, which extends to the drain electrode DE. The insulating film 13 covers the power supply line CL, the metal line ML, the connecting electrode CN1, and the insulating film 12. The insulating film 13 has a contact hole CH12 in the opening OP, which extends to the insulating film 12. The contact hole CH12 overlaps with the contact hole CH11.

[0086] The pixel electrode PE is disposed on the insulating film 13, and is connected to the insulating film 12 in the contact hole CH12. Furthermore, it is connected to the drain electrode DE in the contact hole CH11. The light-shielding layer BM is positioned across the liquid crystal layer LC and is opposite to the switching element SW, the insulating film IL, the power supply line CL, the metal line ML, the drain electrode DE, the contact holes CH11 and CH12, etc. The opening AP of the light-shielding layer BM is positioned across the liquid crystal layer LC and is opposite to the pixel electrode PE, etc.

[0087] In this other configuration example, the same effect as described above can be achieved. Furthermore, by omitting the connecting electrode CN1, a short circuit between the power supply line CL and the pixel electrode PE can be prevented.

[0088] Next, an example of the configuration of the display device DSP in this embodiment will be described.

[0089] Figure 11 This is a cross-sectional view of the display device DSP. It should be noted that the display panel PNL only simplifies the main parts of the diagram.

[0090] In addition to the first substrate SUB1 and the second substrate SUB2, the display panel PNL also includes a third transparent substrate 30. The inner surface 30A of the third transparent substrate 30 faces the outer surface 20B of the second transparent substrate 20 in the third direction Z. An adhesive layer AD bonds the second transparent substrate 20 to the third transparent substrate 30. The third transparent substrate 30 is, for example, a glass substrate, but it can also be an insulating substrate such as a plastic substrate. The third transparent substrate 30 has the same refractive index as the first transparent substrate 10 and the second transparent substrate 20. The adhesive layer AD has the same refractive index as both the second transparent substrate 20 and the third transparent substrate 30.

[0091] The side surface 301 of the third transparent substrate 30 is located directly above the side surface 201 of the second transparent substrate 20. The light-emitting element 110 of the light-emitting module 100 is electrically connected to the wiring substrate F and is disposed between the first substrate SUB1 and the wiring substrate F in the third direction Z. The light guide 120 is disposed between the light-emitting element 110 and the side surface 201, and between the light-emitting element 110 and the side surface 301 in the second direction Y. The light guide 120 is bonded to the wiring substrate F through the adhesive layer AD1 and to the first substrate SUB1 through the adhesive layer AD2.

[0092] Next, refer to Figure 11 This describes the light L1 emitted from the light-emitting element 110.

[0093] The light-emitting element 110 emits light L1 towards the light guide 120. The light L1 emitted from the light-emitting element 110 propagates along the direction indicated by the arrow representing the second direction Y, passes through the light guide 120, and enters the second transparent substrate 20 from side 201, and then enters the third transparent substrate 30 from side 301. The light L1 entering the second and third transparent substrates 20 and 30 is repeatedly reflected while propagating within the display panel PNL. Light L1 entering the liquid crystal layer LC without applied voltage passes through the liquid crystal layer LC with almost no scattering. However, light L1 entering the liquid crystal layer LC with applied voltage is scattered by the liquid crystal layer LC.

[0094] Such a display device DSP can be viewed from the outer surface 10A of the first transparent substrate 10, and also from the outer surface 30B of the third transparent substrate 30. Furthermore, regardless of whether the display device DSP is viewed from the outer surface 10A or the outer surface 30B, the background of the display device DSP can be viewed through the display device DSP.

[0095] As explained above, according to this embodiment, a display device capable of suppressing reliability degradation can be provided.

[0096] It should be noted that several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0097] Explanation of reference numerals in the attached figures

[0098] DSP… Display device PNL… Display panel DA… Display area PX… Pixel SUB1… First substrate 10… First transparent substrate PE… Pixel electrode SW… Switching element DE… Drain electrode G… Scan line S… Signal line

[0099] CL…Power supply line CLE…Side edge CC…Recess

[0100] CN1… Connecting electrode (first connecting electrode) CN3… Connecting electrode (second connecting electrode)

[0101] SUB2…Second substrate 20…Second transparent substrate CE…Common electrode

[0102] LC…Liquid Crystal Layer 30…Third Transparent Substrate

[0103] 100…Light-emitting module 110…Light-emitting element

Claims

1. A display device comprising: a first transparent substrate, scan lines extending in a first direction, signal lines extending in a second direction intersecting the first direction, a switching element including a drain electrode extending in the second direction and electrically connected to the scan lines and the signal lines, a first connection electrode electrically connected to one end portion of the drain electrode, a pixel electrode overlapping the first connection electrode and electrically connected to the first connection electrode, and a supply line separated from the first connection electrode and disposed around the pixel electrode; a second substrate including a second transparent substrate having a side surface, and a common electrode facing the pixel electrode; a liquid crystal layer disposed between the first substrate and the second substrate and containing a polymer-dispersed liquid crystal; and a light emitting module disposed along the side surface, the supply line having a side edge extending in the second direction, the first connection electrode being a transparent electrode formed of the same material as the supply line, not overlapping the scan lines and the signal lines, extending in the first direction, and having an end portion facing the side edge, the supply line having a recess portion facing the first connection electrode when viewed in plan. a first substrate comprising:

2. The display device according to claim 1, wherein a contact hole through which the first connection electrode contacts the pixel electrode is formed at a position not overlapping the drain electrode when viewed in plan, and the drain electrode is located between the supply line and the contact hole in the first direction.

3. The display device according to claim 2, wherein the end portion is a short side extending in the second direction, the short side is located between the supply line and the drain electrode when viewed in plan, and a distance between the short side and the drain electrode is smaller than a distance between the short side and the supply line.

4. The display device according to claim 2, wherein the second substrate further includes a light shielding layer, and the light shielding layer overlaps the drain electrode and does not overlap the contact hole when viewed in plan.

5. The display device according to claim 2, wherein the first substrate further includes a second connection electrode interposed between the drain electrode and the first connection electrode, and the second connection electrode is located between the supply line and the contact hole in the first direction.

6. The display device according to claim 5, wherein the second substrate further includes a light shielding layer, and the light shielding layer overlaps the second connection electrode and does not overlap the contact hole when viewed in plan.

7. The display device according to claim 1, wherein the first substrate further includes an organic insulating film overlapping the scan lines, the signal lines, and the switching element, the organic insulating film has a first side edge extending in the first direction, and a second side edge extending in the second direction, the second substrate further includes a light shielding layer, and the light shielding layer overlaps the first side edge and does not overlap the second side edge when viewed in plan. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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