A ZYNQ-based method and system for accelerating forward inference in signal modulation recognition

Abstract

This invention relates to the field of signal modulation recognition technology, and particularly to a method and system for accelerating forward inference of signal modulation recognition based on ZYNQ. On the processing system PS side, a dual-core ARM processor reads the signal IQ data to be recognized stored in external memory via DMA, and writes the signal IQ data to be recognized into the programmable logic (PL) side buffer. On the PL side, a pre-trained convolutional neural network model is used to perform forward inference on the signal IQ data to be recognized, and the processing system PS side receives and executes the computational resource scheduling for the forward inference on the PL side. This invention designs a signal modulation recognition network model and represents the trained model structure using a high-level language. It optimizes the high-level language representation of the network model using high-level synthesis tools, enabling efficient, accurate, and fast signal modulation recognition in real-time signal scenarios on the ZYNQ scalable platform, showing promising application prospects in real-time signal modulation recognition scenarios.

Description

Technical Field

[0001] This invention relates to the field of signal modulation recognition technology, and in particular to a method and system for accelerating forward inference of signal modulation recognition based on ZYNQ. Background Technology

[0002] Traditionally, signal modulation identification primarily employs two algorithms. The first is the likelihood ratio algorithm, based on Bayesian theory, which determines the signal modulation mode by comparing the ratio of the likelihood function to a threshold that minimizes the error. However, this method is computationally complex and requires prior information, which is often scarce in most scenarios. The second is feature-based algorithms, which consist of two steps: feature extraction (instantaneous amplitude, frequency, phase, higher-order moments, higher-order statistics, etc.) and decision-making, using methods such as artificial neural networks, unsupervised clustering, support vector machines, and decision trees. However, feature extraction heavily relies on expert experience; if the extracted features are inappropriate, recognition performance will be significantly reduced.

[0003] In recent years, the rapidly developing deep learning technology has achieved groundbreaking results in various fields. Deep learning technology can extract high-dimensional information from received data, find the correspondence between input and output, and has extremely strong generalization ability. Therefore, the application of deep learning is receiving increasing attention. In the field of signal modulation recognition, researchers currently focus mainly on the design of network models, setting optimization goals to improve network accuracy, accelerate network convergence speed, and reduce training time. However, the acceleration effect in real-time scenarios is not ideal, thus affecting the application of deep learning algorithms in real-time signal modulation recognition scenarios. Furthermore, there is very little research on accelerating network forward inference operations in real-time scenarios in existing solutions. Summary of the Invention

[0004] To address this issue, the present invention provides a method and system for accelerating forward inference of signal modulation recognition based on ZYNQ, thereby solving the problem of poor real-time performance of deep learning methods in practical signal modulation recognition scenarios.

[0005] According to the design scheme provided by this invention, a method for accelerating forward inference of signal modulation recognition based on ZYNQ is provided, comprising:

[0006] On the PS side of the processing system, the dual-core ARM processor reads the IQ data of the signal to be identified stored in the external memory by calling DMA, and writes the IQ data of the signal to be identified into the buffer on the programmable logic PL side.

[0007] On the programmable logic (PL) side, a pre-trained convolutional neural network model is used to perform forward inference on the IQ data of the signal to be identified, and the processing system (PS) side receives and executes the computational resource scheduling of the programmable logic (PL) side in the forward inference.

[0008] As a forward inference acceleration method for signal modulation recognition based on ZYNQ of the present invention, it further includes: the processing system PS side and the programmable logic PL side read and write the signal IQ data to be recognized through the AXI bus, and the processing system PS side transmits control scheduling instructions to the programmable logic PL side through the AXI bus.

[0009] As a method for accelerating forward inference of signal modulation recognition based on ZYNQ in this invention, the forward inference of the IQ data of the signal to be recognized is further performed using a pre-trained convolutional neural network model, including:

[0010] First, a convolutional neural network model for signal modulation recognition is constructed, and the convolutional neural network model is trained based on a pre-set signal sample dataset.

[0011] Next, the trained convolutional neural network model is represented using a high-level language, and the trained convolutional neural network model is optimized in parallel using a high-level synthesis tool to transform the optimized convolutional neural network model into a hardware IP core.

[0012] Then, the hardware IP core is deployed on the programmable logic (PL) side of the ZYNQ chip to identify and output the IQ data to be identified read by the processing system (PS) side.

[0013] As a method for accelerating forward inference of signal modulation recognition based on ZYNQ in this invention, further, training a convolutional neural network model based on a preset signal sample dataset includes:

[0014] First, an open-source software radio platform is used to simulate and generate a simulation signal. The simulation signal includes digital modulation signals and analog modulation signals of preset types. Each type of modulation signal contains N signal-to-noise ratios, each signal-to-noise ratio has M sub-samples, and each sub-sample contains I-channel and Q-channel signals.

[0015] Next, the simulated signals of each modulation type under different signal-to-noise ratios are divided into training datasets and test datasets according to a preset ratio;

[0016] Then, based on the preset cross-entropy loss function, the convolutional neural network model is trained and optimized using the training dataset and the test dataset to obtain the trained convolutional neural network model.

[0017] As a method for accelerating forward inference of signal modulation recognition based on ZYNQ in this invention, further, a high-level language representation is used to represent the trained convolutional neural network model, and the trained convolutional neural network model is subjected to parallel optimization processing through a high-level synthesis tool, including:

[0018] In the high-level synthesis tool HLS, the trained convolutional neural network model is represented using a high-level C or C++ language to synthesize the high-level language representation of the convolutional neural network model into a corresponding register-transfer level implementation; and the hardware architecture is adjusted using preset specific instruction constraints.

[0019] As a method for accelerating forward inference of signal modulation recognition based on ZYNQ in this invention, the hardware architecture is further adjusted by using preset specific instruction constraints, including: expanding the nested loops in the input and output channels of the high-level language representation parallel optimization convolution operation in the convolutional neural network, and setting the different iterations of other nested loops in the convolutional neural network to run in a pipeline manner.

[0020] As a method for accelerating forward inference of signal modulation recognition based on ZYNQ in this invention, the nested loops of the input and output channels of the high-level language representation parallel optimization convolution operation in the convolutional neural network are further expanded. This includes: setting the number of input channels and the number of output channels of the convolution operation to n and m, respectively; setting the convolution operation parallel optimization structure as follows: using n multipliers to process the multiplication operation of the input features and their corresponding weights of different input channels in parallel; accumulating the n products in the form of an addition tree to obtain the convolution result of the corresponding output channel; and copying the convolution operation parallel optimization structure m times to obtain the convolution results of m different output channels in parallel output.

[0021] Furthermore, the present invention also provides a signal modulation recognition forward inference acceleration system based on ZYNQ, comprising: a data reading module and a parallel acceleration module, wherein,

[0022] The data reading module is used on the PS side of the processing system by a dual-core ARM processor to read the IQ data of the signal to be identified stored in the external memory by calling DMA, and write the IQ data of the signal to be identified into the buffer on the programmable logic PL side.

[0023] The parallel acceleration module is used to perform forward inference on the programmable logic (PL) side using a pre-trained convolutional neural network model to be identified (IQ) data, and to receive and execute the computational resource scheduling of the processing system (PS) side on the programmable logic (PL) side during forward inference.

[0024] The beneficial effects of this invention are:

[0025] This invention addresses the problem of accelerating forward inference for signal modulation recognition. It designs a network model for signal modulation recognition and uses a high-level language to represent the trained network model. Hardware IP optimization of the high-level language representation of the network model is performed using high-level synthesis tools, enabling efficient, accurate, and fast signal modulation recognition in real-time signal scenarios on the ZYNQ scalable platform. Furthermore, comparative experiments verify that this solution offers significant energy efficiency advantages while reducing latency and power consumption, demonstrating promising application prospects in real-time signal modulation recognition scenarios. Attached image description:

[0026] Figure 1 This is a schematic diagram of the forward inference acceleration process for signal modulation recognition based on ZYNQ in the embodiment;

[0027] Figure 2 This is a schematic diagram of the FPGA parallel unfolding structure in the convolution operation of the embodiment;

[0028] Figure 3 This is a schematic diagram illustrating the forward inference acceleration principle of signal modulation recognition in the embodiment;

[0029] Figure 4 This is a schematic diagram of the ZYNQ platform architecture in the embodiment. Detailed implementation method:

[0030] To make the objectives, technical solutions, and advantages of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and technical solutions.

[0031] The ZYNQ scalable platform is a heterogeneous architecture chip combining a traditional FPGA and a dual-core ARM processor. These two components can interact and complement each other, leveraging each other's strengths. The goal of deep learning algorithms in artificial intelligence is to find paths within the problem space, which can be achieved through forward and backward reasoning. A significant difference between forward and backward reasoning is that forward reasoning begins with initial data leading to the goal. Conversely, backward reasoning works in the opposite way, aiming to determine initial facts and information given a result. As described in the background section, this invention provides a method for accelerating forward reasoning operations in real-time network scenarios, based on ZYNQ. The specific process can be designed to include the following:

[0032] S101. On the PS side of the processing system, the dual-core ARM processor reads the IQ data of the signal to be identified stored in the external memory by calling DMA, and writes the IQ data of the signal to be identified into the buffer on the PL side of the programmable logic.

[0033] The ZYNQ platform series of scalable processing platforms has wide applications in high-end embedded application scenarios such as video surveillance, automotive driver assistance, and factory automation. This series of scalable processing platforms includes a wealth of hardware resources. In this embodiment, the processing system PS is used to read and write the target signal IQ data to be identified in real time and at high speed, in order to control and schedule the corresponding programmable logic PL side's multipliers and other computational processing resources.

[0034] Furthermore, the system can be configured to read and write the IQ data of the signal to be identified via an AXI bus between the processing system PS side and the programmable logic PL side, and the processing system PS side can transmit control scheduling commands to the programmable logic PL side via the AXI bus. The AXI protocol in the AXI bus enables read / write control from the PS side to the PL side, completing the data communication in the forward inference acceleration of signal modulation recognition.

[0035] S102. On the programmable logic PL side, a pre-set trained convolutional neural network model is used to perform forward inference on the IQ data of the signal to be identified, and the processing system PS side receives and executes the scheduling of computing resources in the forward inference on the programmable logic PL side.

[0036] The forward inference process using a pre-trained convolutional neural network model on the IQ data of the signal to be identified can be designed to include the following:

[0037] First, a convolutional neural network model for signal modulation recognition is constructed, and the convolutional neural network model is trained based on a pre-set signal sample dataset.

[0038] Next, the trained convolutional neural network model is represented using a high-level language, and the trained convolutional neural network model is optimized in parallel using a high-level synthesis tool to transform the optimized convolutional neural network model into a hardware IP core.

[0039] Then, the hardware IP core is deployed on the programmable logic (PL) side of the ZYNQ chip to identify and output the IQ data to be identified read by the processing system (PS) side.

[0040] Specifically, training a convolutional neural network model based on a pre-defined dataset of signal samples can be designed to include the following:

[0041] First, an open-source software radio platform is used to simulate and generate a simulation signal. The simulation signal includes digital modulation signals and analog modulation signals of preset types. Each type of modulation signal contains N signal-to-noise ratios, each signal-to-noise ratio has M sub-samples, and each sub-sample contains I-channel and Q-channel signals.

[0042] Next, the simulated signals of each modulation type under different signal-to-noise ratios are divided into training datasets and test datasets according to a preset ratio;

[0043] Then, based on the preset cross-entropy loss function, the convolutional neural network model is trained and optimized using the training dataset and the test dataset to obtain the trained convolutional neural network model.

[0044] A convolutional neural network model was constructed using the publicly available dataset RadioML2016.10a to achieve real-time modulation recognition of 11 types of signals. Hardware IP cores were converted based on the network model, and strategies such as loop optimization, ping-pong caching, and full on-chip mapping were employed to accelerate computation. The network model was deployed to the ZYNQ scalable platform, where received target signals (IQ samples) were identified as different modulation types in real time.

[0045] The RML2016.10a dataset, generated by GNU Radio software, contains 8 digital modulations and 3 analog modulations. Each modulation signal is configured with 20 signal-to-noise ratios (SNRs) ranging from -20 dB to 18 dB (intervals of 2). Each SNR has 1000 subsamples, each containing both I and Q signals, with 128 sampling points per signal. Since signals below 0 dB are heavily influenced by noise, making it difficult for neural networks to extract valuable information, training can be performed using only data from the RML2016.10a dataset with SNRs above 0 dB. Furthermore, for each modulation type at different SNRs, 80% of the data is used as training data, and 20% as test data.

[0046] A network model was designed based on the publicly available RML2016.10a dataset. In terms of network structure, a two-dimensional convolution is first used to fuse the I and Q pathways, followed by three consecutive one-dimensional convolutions to further extract features. Global max pooling is used for downsampling after the convolutional layers, and finally, two fully connected layers are used as classifiers, with ReLU activation functions for both. The network in this design can be trained using the TensorFlow framework, employing cross-entropy loss to calculate gradients and the Adam algorithm to optimize the learning rate. After 500 epochs of training, the model achieved an accuracy of 84.30% on the test set. The parameters of the network model during training are shown in Table 1.

[0047] Table 1

[0048]

[0049] In the high-level synthesis tool HLS, the trained convolutional neural network model can be represented using high-level languages ​​such as C or C++, and the high-level language representation of the convolutional neural network model can be synthesized into the corresponding register-transfer level implementation; and the hardware architecture can be adjusted using preset specific instruction constraints.

[0050] In this embodiment, the hardware IP is designed using High-level Synthesis (HLS) and optimization methods such as loop unrolling, loop pipelining, and full on-chip mapping are employed to accelerate computation. High-level synthesis tools allow programs to be implemented using only high-level languages ​​such as C and C++, synthesizing them into corresponding register-transfer level implementations. Furthermore, specific instruction constraints can be used to instruct and adjust the high-level synthesis tools to generate specific hardware architectures.

[0051] Among them, adjusting the hardware architecture by using preset specific instruction constraints includes: expanding the nested loops in the input and output channels of the high-level language representation parallel optimization convolution operation in the convolutional neural network, and setting the different loop iterations of other nested loops in the convolutional neural network to run in a pipeline manner.

[0052] The main operations in convolutional neural networks occur in the convolutional layers, which can be represented as a six-layer nested loop, with multiplication and accumulation performed in the innermost layer. During parallel optimization, if there are data dependencies across the unfolded dimensions, it will affect the final speedup. Analysis of the convolutional operation code revealed that there are no data dependencies between the input and output channels during computation. Therefore, in this embodiment, the unfolding is performed along both the input and output channels of the convolution.

[0053] Assuming a convolutional layer has n input channels and m output channels, the design employs n multipliers to process the multiplication of input features and their corresponding weights for different input channels in parallel. The n products are then summed together in an addition tree to obtain the convolution result for one output channel. This circuit structure can be replicated m times to output m different convolution results for different output channels in parallel. Its FPGA parallel deployment structure can be as follows: Figure 2 As shown, the input and output channels can be fully expanded, but the other four nested loops still execute sequentially. Furthermore, the other four nested loops can be pipelining using the `pragma HLS PIPELINE` instruction in Xilinx HLS, allowing different loop iterations to run in a pipelined manner. This parallel acceleration can be applied to all convolutional layers.

[0054] Due to FPGA hardware resource limitations, the accelerator uses a general-purpose convolutional acceleration array. Each layer of the neural network is executed sequentially within this array. This approach requires frequent data exchange between on-chip cache and off-chip DDR, increasing off-chip memory access pressure and impacting data throughput. Off-chip memory access operations in neural network accelerators consume more power than computation; therefore, reducing off-chip memory access is crucial for improving throughput and energy efficiency.

[0055] Due to the small size of the network, in this embodiment, see [reference needed]. Figure 3 As shown, all network layers can be deployed on-chip, with specific hardware modules implemented for each layer. Weight data and intermediate data for each layer are stored in on-chip buffers, and a ping-pong buffer is used to implement a coarse-grained pipeline between data transfer and convolution calculation. During forward inference, the input signal only needs to be read from outside the chip to complete the forward inference operation on-chip until the recognition result is output.

[0056] For hardware implementation details, see [link / reference]. Figure 4 As shown, the Xilinx ZYNQ chip was chosen to deploy the network model. Within the ZYNQ chip, hardware resources are divided into two main parts: a Processing System (PS) comprised of a dual-core ARM Cortex-A9 core and Programming Logic (PL) composed of an FPGA. The PS handles overall system control and scheduling. The AXI Lite Slave bus is used for command transmission, and the AXI master bus handles high-speed read / write of input and output data. The PL implements a neural network forward inference accelerator and acts as a peripheral on the AXI bus, receiving scheduling from the PS. A driver program is written on the PS to transmit control and scheduling commands to the PL via the AXI Lite Slave bus, enabling overall system control. Signal IQ data is stored in off-chip memory. During recognition, the PS controls Direct Memory Access (DMA), a feature provided by computer bus architecture that allows data to be sent directly from external devices such as disk drives to the motherboard's memory, enabling high-speed read / write between external memory and the PL's buffer. The PL (FPGA portion) accelerates neural network forward inference.

[0057] Furthermore, based on the above method, this embodiment of the invention also provides a ZYNQ-based signal modulation recognition forward inference acceleration system, comprising: a data reading module and a parallel acceleration module, wherein,

[0058] The data reading module is used on the PS side of the processing system by a dual-core ARM processor to read the IQ data of the signal to be identified stored in the external memory by calling DMA, and write the IQ data of the signal to be identified into the buffer on the programmable logic PL side.

[0059] The parallel acceleration module is used to perform forward inference on the programmable logic (PL) side using a pre-trained convolutional neural network model to be identified (IQ) data, and to receive and execute the computational resource scheduling of the processing system (PS) side on the programmable logic (PL) side during forward inference.

[0060] To verify the effectiveness of this solution, the following explanation is based on experimental data:

[0061] The MZ7100 development board was selected, with the Xilinx xc7z100-ffg900-2 chip. Vivado HLS 2017.4 was used to design and implement the accelerator IP. This tool can generate hardware IP cores from C and C++ code. Vivado 2017.4 was used to complete synthesis, placement, routing, and bit file generation.

[0062] The modulation recognition network was compared with two embedded platforms: an ARM Cortex-A9 processor on the ZYNQ7100 and a 128-core Maxwell GPU from NVIDIA's Jetson Nano development kit. When running on the ARM Cortex-A9, the recognition time per sample was 17.441 ms, and the power consumption was 30.78 mJ. On the Jetson Nano, the recognition time per sample was 7.694 ms, and the power consumption was 40.09 mJ.

[0063] Table 2

[0064]

[0065] As can be seen from the comparison results in Table 2, compared with other platforms, the neural network forward inference acceleration scheme in this case takes only 152 μm to complete one sample recognition and consumes only 0.625 mJ of power. It can achieve lower latency and energy consumption, and has significant energy efficiency advantages, providing a reference for the application of signal modulation recognition based on deep learning technology.

[0066] Unless otherwise specifically stated, the relative steps, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0067] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0068] The units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations are not considered to be beyond the scope of this invention.

[0069] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This invention is not limited to any particular combination of hardware and software.

[0070] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A ZYNQ-based signal modulation identification forward inference acceleration method, characterized in that, Comprise: On the processing system PS side, the dual-core ARM processor reads the to-be-identified signal IQ data stored on the external memory by calling the DMA and writes the to-be-identified signal IQ data into the programmable logic PL side buffer; On the programmable logic PL side, the preset trained convolutional neural network model is used to perform forward inference on the to-be-identified signal IQ data, receive and execute the operation resource scheduling of the processing system PS side in the forward inference of the programmable logic PL side. Wherein, the preset trained convolutional neural network model is used to perform forward inference on the to-be-identified signal IQ data, comprising: First, a convolutional neural network model for signal modulation identification is constructed, and the convolutional neural network model is trained according to a preset signal sample data set; Next, in the high-level synthesis tool HLS, the trained convolutional neural network model is represented by C or C++ high-level language, so as to synthesize the high-level language representation of the convolutional neural network model into a corresponding register transfer level implementation; and the hardware architecture is adjusted by using a preset specific instruction constraint, so as to use the high-level language representation of the trained convolutional neural network model, and perform parallel optimization processing on the trained convolutional neural network model by the high-level synthesis tool, and convert the optimized convolutional neural network model into a hardware IP core; Then, the hardware IP core is deployed to the programmable logic PL side on the ZYNQ chip to identify and output the to-be-identified signal IQ data read by the processing system PS side; And the hardware architecture is adjusted by using a preset specific instruction constraint, comprising: the nested loops in the input channel and output channel dimensions of the convolution operation represented by the high-level language in the convolutional neural network are unfolded, and the other nested loops in the convolution operation in the convolutional neural network are set to run in a pipeline manner between different loop iterations, wherein the nested loops in the input channel and output channel dimensions of the convolution operation represented by the high-level language in the convolutional neural network are unfolded, comprising: the number of input channels and output channels of the convolution operation is set as n and m respectively, and the convolution operation parallel optimization structure is set as: n multipliers are used to process the multiplication operation of the input features of different input channels and their corresponding weights in parallel, and the n products obtained are accumulated in the form of an addition tree to obtain the convolution result of the corresponding output channel; the convolution operation parallel optimization structure is copied m times to obtain the convolution results of m different output channels output in parallel.

2. The ZYNQ-based signal modulation identification forward reasoning acceleration method according to claim 1, wherein, Further comprising: the processing system PS side and the programmable logic PL side read and write the to-be-identified signal IQ data through the AXI bus, and the processing system PS side transmits control scheduling instructions to the programmable logic PL side through the AXI bus.

3. The ZYNQ-based signal modulation identification forward reasoning acceleration method of claim 1, wherein, According to the preset signal sample data set, the convolutional neural network model is trained, comprising: First, use the open source software radio platform to simulate and generate a simulation signal, wherein the simulation signal comprises a preset type of digital modulation signal and analog modulation signal, and each type of modulation signal contains N signal-to-noise ratios, M sub-samples for each signal-to-noise ratio, and I and Q signals for each sub-sample; Then, the simulation signals of each modulation type under different signal-to-noise ratios are divided into a training data set and a test data set according to a preset ratio; Then, the convolutional neural network model is trained and optimized based on a preset cross-entropy loss function and by using the training data set and the test data set, to obtain a trained convolutional neural network model.

4. A ZYNQ-based signal modulation identification forward inference acceleration system, characterized in that, Comprise: data reading module and parallel acceleration module, wherein, The data reading module is configured to read, on the processing system PS side, the to-be-identified signal IQ data stored on the external memory by calling the DMA through the dual-core ARM processor, and write the to-be-identified signal IQ data into the programmable logic PL side buffer; The parallel acceleration module is configured to perform forward inference on the to-be-identified signal IQ data on the programmable logic PL side by using the preset trained convolutional neural network model, and receive and execute the operation resource scheduling of the processing system PS side in the forward inference of the programmable logic PL side. First, a convolutional neural network model for signal modulation identification is constructed, and the convolutional neural network model is trained according to a preset signal sample data set; Then, in the high-level synthesis tool HLS, the trained convolutional neural network model is represented by using a C or C++ high-level language, so as to synthesize the high-level language representation of the convolutional neural network model into a corresponding register transfer level implementation; and the hardware architecture is adjusted by using a preset specific instruction constraint, so as to utilize the high-level language representation of the trained convolutional neural network model, and perform parallel optimization processing on the trained convolutional neural network model by using the high-level synthesis tool, to convert the optimized convolutional neural network model into a hardware IP core; Then, the hardware IP core is deployed to the programmable logic PL side on the ZYNQ chip, to identify and output the to-be-identified signal IQ data read by the processing system PS side. The adjustment of the hardware architecture by using the preset specific instruction constraint comprises: unfolding the nested loops in the input channel and the output channel of the parallel-optimized convolution operation in the high-level language representation of the convolutional neural network, and setting the nested loops in the convolution operation in the convolutional neural network to run in a pipeline manner between different loop iterations, wherein the unfolding of the nested loops in the input channel and the output channel of the parallel-optimized convolution operation in the high-level language representation of the convolutional neural network comprises: setting the number of input channels and the number of output channels of the convolution operation as n and m respectively, and setting the parallel-optimized structure of the convolution operation as: using n multipliers to perform multiplication operations on different input channels of input features and corresponding weights, and accumulating the n products in the form of an addition tree to obtain the convolution result of the corresponding output channel; and copying the parallel-optimized structure of the convolution operation m times to obtain the convolution results of m different output channels output in parallel. The system comprises a memory and a processor, the processor and the memory communicate with each other through a bus; the memory stores program instructions executable by the processor, and the processor calling the program instructions can execute the method of any one of claims 1-3.

5. An electronic device, comprising: ​ 6. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the method in any one of claims 1-3.

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