Display panel

Abstract

This invention discloses a display panel. During the compensation phase, the data writing module transmits the initial voltage input from the first voltage input terminal to the first terminal of the coupling module; and during the data writing phase, it transmits the data voltage input from the first voltage input terminal to the first terminal of the coupling module. The second terminal of the coupling module is connected to the control terminal of the driving module, enabling the writing of a voltage corresponding to the data voltage to the control terminal of the driving module through the data writing module and the coupling module. During the compensation phase, the compensation module compensates for the threshold voltage of the driving module. During the light-emitting phase, the driving module outputs a driving current to the light-emitting module through its second terminal, based on the first power supply voltage input from the second voltage input terminal to the first terminal of the driving module and the voltage at the control terminal of the driving module. In this embodiment, the pixel circuit of the display panel includes fewer circuit modules, simplifying the pixel circuit structure and improving the transmittance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] With the development of display technology, transparent display devices are being used more and more widely.

[0003] Transparent display devices include an array substrate, which contains pixel circuits and signal traces. In existing transparent display devices, the structure of the pixel circuits is relatively complex, and correspondingly, the signal traces connecting the pixel circuits are also relatively dense.

[0004] Therefore, the transmittance of existing transparent display devices is low, resulting in poor transparent display effects and the display quality of transparent display devices cannot be guaranteed. Summary of the Invention

[0005] This invention provides a display panel to simplify the structure of pixel circuits in the display panel, improve transmittance, enhance the transparent display effect, and ensure the display quality of the transparent display device.

[0006] This invention provides a display panel including multiple pixel circuits, each pixel circuit including a data writing module, a driving module, a compensation module, a coupling module, a storage module, and a light-emitting module.

[0007] The data writing module is connected to the first voltage input terminal. The data writing module is used to transmit the initial voltage input to the first voltage input terminal to the first terminal of the coupling module during the compensation phase; and to transmit the data voltage input to the first voltage input terminal to the first terminal of the coupling module during the data writing phase.

[0008] The second end of the coupling module is connected to the control terminal of the drive module; the storage module is used to store the potential of the control terminal of the drive module; the first end of the drive module is connected to the second voltage input terminal.

[0009] The compensation module is connected between the second end of the drive module and the control end of the drive module;

[0010] The driving module is used to output driving current to the light-emitting module through the second terminal of the driving module during the light-emitting stage, based on the first power supply voltage input to the first terminal of the driving module at the second voltage input terminal and the voltage of the control terminal of the driving module.

[0011] The data writing stage occurs between the compensation stage and the light emission stage.

[0012] Optionally, the display panel further includes a first voltage selection module, which includes a first input terminal, a second input terminal, a first control terminal, a second control terminal, and a first output terminal. The first output terminal is electrically connected to the first voltage input terminal. The first input terminal is connected to an initial voltage, and the second input terminal is connected to a data voltage.

[0013] The first voltage selection module is used to transmit an initial voltage to a first voltage input terminal in response to a first control signal from a first control terminal during the compensation phase; and to transmit a data voltage to a first voltage input terminal in response to a second control signal from a second control terminal during the data writing phase.

[0014] Optionally, each pixel circuit includes a first voltage selection module; or, the first voltage selection module is located in the non-display area of ​​the display panel, and the display panel also includes multiple data lines, with the output terminal of the first voltage selection module electrically connected to each data line in a corresponding manner; each data line is connected to the first voltage input terminal of a column of pixel circuits;

[0015] Optionally, the non-display area of ​​the display panel includes a setting frame area, and the first voltage selection module is located in the setting frame area; the setting frame area includes a lead-out line from the driver chip to extract data voltage, and the lead-out line is electrically connected to the data line.

[0016] Optionally, the display panel also includes a reset module, the input terminal of which is electrically connected to the second voltage input terminal, and the output terminal of which is electrically connected to the control terminal of the drive module; the reset module is used to transmit the reset voltage input at the second voltage input terminal to the control terminal of the drive module during the first reset phase; the compensation module is also used to be turned on during the first reset phase to transmit the reset voltage transmitted by the reset module to the second terminal of the drive module; wherein, the first reset phase is performed before the compensation phase;

[0017] Optionally, the drive module is also used to transmit the voltage at the first terminal of the drive module to the second terminal of the drive module during the second reset phase; the second reset phase occurs between the compensation phase and the data writing phase.

[0018] Optionally, the display panel further includes a second voltage selection module, which includes a third input terminal, a fourth input terminal, a third control terminal, a fourth control terminal, and a second output terminal. The second output terminal is electrically connected to the second voltage input terminal. The third input terminal is connected to a reset voltage, and the fourth input terminal is connected to a first power supply voltage. The second voltage selection module is used to transmit the reset voltage to the second voltage input terminal in response to a third control signal from the third control terminal during the first reset phase, and to transmit the first power supply voltage to the second voltage input terminal in response to a fourth control signal from the fourth control terminal during the light-emitting phase.

[0019] Optionally, the second voltage selection module further includes a fifth input terminal and a fifth control terminal, wherein the fifth input terminal is connected to a compensation voltage; the compensation voltage is less than the first power supply voltage; the second voltage selection module is also used to transmit the compensation voltage to the second voltage input terminal in response to the control signal of the fifth control terminal during the compensation phase; or, the second voltage selection module is used to transmit the first power supply voltage to the second voltage input terminal in response to the fourth control signal of the fourth control terminal during the compensation phase.

[0020] Optionally, each pixel circuit includes a second voltage selection module; or, the second voltage selection module is located in the non-display area of ​​the display panel, and the display panel also includes multiple first power supply lines, the output terminal of the first voltage selection module is electrically connected to the first power supply lines one by one; each first power supply line is connected to the second voltage input terminal of a column of pixel circuits;

[0021] Optionally, the non-display area of ​​the display panel includes a setting frame area, and the second voltage selection module is located in the setting frame area; the setting frame area includes a lead-out line from the driver chip to extract data voltage, and the lead-out line is electrically connected to the data line of the display panel.

[0022] Optionally, the second end of the driving module is connected to the first end of the light-emitting module, and the second end of the light-emitting module is connected to the third voltage input terminal; the display panel also includes a third voltage selection module, which includes a sixth input terminal, a seventh input terminal, a sixth control terminal, a seventh control terminal, and a third output terminal, and the third output terminal is electrically connected to the third voltage input terminal; the sixth input terminal is connected to the first cathode voltage, and the seventh input terminal is connected to the second cathode voltage; the second cathode voltage is greater than the first cathode voltage;

[0023] The third voltage selection module is used to transmit the second cathode voltage to the third voltage input terminal in response to the seventh control signal of the seventh control terminal in a phase other than the light emission phase; and is used to transmit the first cathode voltage to the third voltage input terminal in response to the sixth control signal of the sixth control terminal in the light emission phase.

[0024] Optionally, the drive module is specifically used to transmit the first power supply voltage input at the second voltage input terminal to the second terminal of the drive module during the compensation phase, and the compensation module is specifically used to transmit the voltage at the second terminal of the drive module to the control terminal of the drive module during the compensation phase.

[0025] Optionally, each pixel circuit includes a third voltage selection module; or, the third voltage selection module is located in the non-display area of ​​the display panel, and the second ends of the light-emitting modules in each column of pixel circuits in the display panel are interconnected; the display panel also includes a second power supply line, one end of which is electrically connected to a third output terminal, and the other end of which is connected to the third voltage input terminal of at least one column of pixel circuits.

[0026] Optionally, the non-display area of ​​the display panel includes a setting bezel area, and the third voltage selection module is located in the setting bezel area; the setting bezel area includes a lead-out line from the driver chip to extract data voltage, and the lead-out line is electrically connected to the data line of the display panel.

[0027] Optionally, the pixel circuit also includes an emissive control module, which is disposed between the second end of the driving module and the first end of the emissive module. The second end of the emissive module is connected to the third voltage input terminal. The emissive control module is used to turn on during the emissive phase and turn off during the phase other than the emissive phase according to the signal from its own control terminal.

[0028] Preferably, the third voltage input terminal transmits the same voltage to the second terminal of the light-emitting module during the light-emitting stage and in stages other than the light-emitting stage;

[0029] Preferably, the drive module is specifically used to transmit the first power supply voltage input at the second voltage input terminal to the second terminal of the drive module during the compensation phase, and the compensation module is specifically used to transmit the voltage at the second terminal of the drive module to the control terminal of the drive module during the compensation phase.

[0030] Optionally, the first reset phase of each pixel circuit is performed simultaneously, the compensation phase of each pixel circuit is performed simultaneously, the second reset phase of each pixel circuit is performed simultaneously, the data writing phase of each row of pixel circuits is performed row by row, and the light emission phase of each pixel circuit is performed simultaneously.

[0031] Optionally, the display panel also includes multiple first gate control lines, second gate control lines, and scan lines; each row of pixel circuits is connected to one first gate control line, one second gate control line, and one scan line. The first gate control line is connected to the control terminal of the reset module of the corresponding row of pixel circuits, the second gate control line is connected to the control terminal of the compensation module of the corresponding row of pixel circuits, and the scan line is connected to the control terminal of the data writing module of the corresponding row of pixel circuits.

[0032] Among them, the conduction pulse signals on each of the first gate control lines overlap, the conduction pulse signals on each of the second gate control lines overlap, the first conduction pulse signals on each scan line corresponding to the first reset stage and the compensation stage overlap, and the second conduction pulse signals on each scan line corresponding to the data writing stage do not overlap.

[0033] Optionally, the first end of the storage module is electrically connected to the first end of the drive module, and the second end of the storage module is electrically connected to the first or second end of the coupling module.

[0034] Optionally, the display panel also includes a substrate and a driving circuit layer located on one side of the substrate, with the pixel circuit located in the driving circuit layer; the driving circuit layer includes multiple stacked metal layers.

[0035] The metal layer includes a first patterned structure, wherein at least a portion of the edge of the first patterned structure of the metal layer projected orthogonally onto the substrate is covered by at least a portion of the first patterned structure of the other metal layer projected orthogonally onto the substrate.

[0036] Optionally, the driving circuit layer includes n stacked metal layers, where n is an integer greater than or equal to 2; wherein at least a portion of the first patterned structure of any of the (n-1) metal layers is orthogonally projected onto the substrate by the edge of the first patterned structure of the other metal layers.

[0037] Optionally, the first graphical structure includes signal lines and the composition structure of devices in the pixel circuit;

[0038] Optionally, at the corner positions of the signal line, the signal line is curved.

[0039] Optionally, the display panel also includes a substrate and a driving circuit layer located on one side of the substrate, with the pixel circuit located in the driving circuit layer; the driving circuit layer includes multiple stacked metal layers and an insulating layer between adjacent metal layers;

[0040] The metal layer includes a first patterned structure, and the insulating layer includes a second patterned structure; wherein at least a portion of the edge of the first patterned structure of the metal layer projected orthogonally onto the substrate is covered by the orthogonal projection of at least a portion of the second patterned structure of the insulating layer onto the substrate; and / or, wherein at least a portion of the edge of the second patterned structure of the insulating layer projected orthogonally onto the substrate is covered by the orthogonal projection of at least a portion of the first patterned structure of the metal layer onto the substrate; and / or, wherein at least a portion of the edge of the second patterned structure of the insulating layer projected orthogonally onto the substrate is covered by the orthogonal projection of at least a portion of the second patterned structure of another insulating layer onto the substrate;

[0041] Optionally, the driving circuit layer includes n layers of metal layers and m layers of insulating layers stacked together, where n is an integer greater than or equal to 2 and m is an integer greater than or equal to 1.

[0042] The edge of at least a portion of the first patterned structure of any metal layer projected onto the substrate is covered by the orthogonal projection of at least a portion of the first patterned structure of other metal layers and / or the second patterned structure of the insulating layer onto the substrate; the orthogonal projection of at least a portion of the second patterned structure of any insulating layer in the (m-1) layers onto the substrate is covered by the orthogonal projection of at least a portion of the first patterned structure of the metal layer and / or the second patterned structure of the other insulating layer onto the substrate.

[0043] Alternatively, the edge of at least a portion of the second patterned structure of any insulating layer projected onto the substrate is covered by the orthogonal projection of at least a portion of the second patterned structure of other insulating layers or the first patterned structure of a metal layer onto the substrate; the orthogonal projection of at least a portion of the first patterned structure of any metal layer in the (n-1) metal layers is covered by the orthogonal projection of at least a portion of the first patterned structure of other metal layers and / or the second patterned structure of the insulating layer onto the substrate.

[0044] Optionally, the first graphical structure includes signal lines and the composition structure of devices in the pixel circuit;

[0045] Optionally, at the corner positions of the signal line, the signal line is curved.

[0046] The display panel of this embodiment includes multiple pixel circuits, each comprising a data writing module, a driving module, a compensation module, a coupling module, a storage module, and a light-emitting module. During the compensation phase, the data writing module transmits the initial voltage input from the first voltage input terminal to the first terminal of the coupling module; and during the data writing phase, it transmits the data voltage input from the first voltage input terminal to the first terminal of the coupling module. The second terminal of the coupling module is connected to the control terminal of the driving module, thereby enabling the writing of a voltage corresponding to the data voltage to the control terminal of the driving module via the data writing module and the coupling module. The compensation module is connected between the second terminal of the driving module and the control terminal of the driving module, and can compensate for the threshold voltage of the driving module during the compensation phase. During the light-emitting phase, the driving module, based on the first power supply voltage input from the second voltage input terminal to the first terminal of the driving module and the voltage of the control terminal of the driving module, outputs a driving current through the second terminal of the driving module to the light-emitting module, thereby driving the light-emitting module. In the display panel of this embodiment, the pixel circuit includes fewer circuit modules, and correspondingly, the pixel circuit includes fewer circuit devices, which simplifies the pixel circuit structure. This also helps to simplify the wiring in the display panel, thereby improving the transmittance of the display panel, enhancing the transparent display effect, and ensuring the display quality of the transparent display device. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0050] Figure 4 This is a driving timing diagram of a display panel provided in an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0054] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0055] Figure 9 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0056] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0057] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0058] Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0059] Figure 13 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0060] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0061] Figure 15 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0062] Figure 16 yes Figure 1 This is a magnified view of a specific area;

[0063] Figure 17 This is a cross-sectional view of a display panel provided in an embodiment of the present invention;

[0064] Figure 18 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0065] Figure 19 yes Figure 18 A detailed structural diagram of the central cabling area;

[0066] Figure 20This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0067] Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0068] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0069] As described in the background section, existing transparent display devices have low transmittance, resulting in poor transparent display effects and compromised display quality. The inventors have discovered that this problem stems from the fact that existing transparent display devices typically employ a 7T1C pixel circuit, meaning each pixel circuit includes seven transistors and one capacitor. This results in a large number of circuit components, a complex pixel circuit structure, and consequently, a large number of signal lines connected to the pixel circuit, leading to dense wiring within the display device. Since the pixel circuit and its connected signal lines are located in the display area, the abundance of circuit components and dense wiring in the display area contributes to the low transmittance of the transparent display device, resulting in poor transparent display effects and compromised display quality.

[0070] For the reasons stated above, embodiments of the present invention provide a display panel. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 1The display panel includes multiple pixel circuits 100, each pixel circuit including a data writing module 110, a driving module 120, a compensation module 130, a coupling module 140, a storage module 150, and a light-emitting module 160. The data writing module 110 is connected to a first voltage input terminal V1. During the compensation phase, the data writing module 110 transmits the initial voltage input to the first voltage input terminal V1 to the first terminal of the coupling module 140; and during the data writing phase, it transmits the data voltage input to the first voltage input terminal V1 to the first terminal of the coupling module 140. The second terminal of the coupling module 140 is connected to the driving module. The drive module 120 has a control terminal; the storage module 150 is used to store the potential of the control terminal G1 of the drive module 120; the first terminal of the drive module 120 is connected to the second voltage input terminal V2; the compensation module 130 is connected between the second terminal of the drive module 120 and the control terminal of the drive module 120; the drive module 120 is used to output a drive current to the light-emitting module 160 through the second terminal of the drive module 120 according to the first power supply voltage input to the first terminal of the drive module 120 and the voltage of the control terminal of the drive module 120 during the light-emitting stage; wherein, the data writing stage is between the compensation stage and the light-emitting stage.

[0071] Specifically, within a single frame, the pixel circuit's operation involves at least the compensation phase, data writing phase, and light emission phase, performed sequentially. The operation of the pixel circuit 100 within a single frame is as follows:

[0072] During the compensation phase, the initial voltage input at the first voltage input terminal V1 is transmitted to the first terminal of the coupling module 140, fixing the potential of the first terminal of the coupling module 140 to the initial voltage. During the compensation phase, both the driving module 120 and the compensation module 130 are turned on. The voltage input from the second power input terminal to the first terminal of the driving module 120 is transmitted to the control terminal of the driving module 120 through the driving module 120 and the compensation module 130. The driving module 120 includes a driving transistor. When the voltage difference between the control terminal of the driving module 120 and the first terminal of the driving module 120 equals the threshold voltage of the driving transistor, the driving module 120 is critically turned off, thereby compensating for the threshold voltage of the driving transistor during the compensation phase.

[0073] During the data writing phase, the data voltage input at the first voltage input terminal V1 is transmitted to the first terminal of the coupling module 140, causing the potential of the first terminal of the coupling module 140 to jump from the initial voltage to the data voltage, where the data voltage can be a voltage different from the initial voltage. During the data writing phase, the compensation module 130 is turned off, so there is no direct path in the pixel circuit 100 to write voltage to the control terminals of the driving module 120 and the coupling module 140. The potential of the second terminal of the coupling module 140 jumps with the jump of the potential of the first terminal of the coupling module 140, that is, the potential of the control terminal of the driving module 120 jumps with the jump of the potential of the second terminal of the coupling module 140, thereby realizing the writing of a voltage corresponding to the data voltage to the control terminal of the driving module 120 through the data writing module 110 and the coupling module 140. Specifically, when the data voltage is different, the voltage difference between the data voltage and the initial voltage is different when the potential at the first terminal of the coupling module 140 jumps from the initial voltage to the data voltage. That is, the potential jump variable at the first terminal of the coupling module 140 is different. The potential jump variable at the second terminal of the coupling module 140 corresponds to the potential jump variable at the first terminal of the coupling module 140. In other words, the potential jump variable at the second terminal of the coupling module 140 corresponds to the data voltage. Thus, the voltage corresponding to the data voltage can be written to the control terminal of the drive module 120 through the data writing module 110 and the coupling module 140.

[0074] It should be noted that, in this embodiment, during the compensation phase, the voltage input to the second power input terminal must be sufficient to enable the drive module 120 to conduct, thereby ensuring that the threshold voltage of the drive transistors included in the drive module 120 can be compensated during the compensation phase.

[0075] During the light-emitting phase, the second power input terminal inputs a first power supply voltage to the first terminal of the driving module 120. The driving module 120 conducts according to the voltage at its control terminal and the first power supply voltage at the first terminal, generating a driving current to drive the light-emitting module 160 to emit light. Furthermore, due to the presence of the storage module 150, the potential at the control terminal of the driving module 120 can be stored and maintained during the light-emitting phase, resulting in minimal changes in the driving current generated by the driving module 120 during the light-emitting phase, thus ensuring the uniformity of the display panel.

[0076] The display panel of this embodiment includes multiple pixel circuits, each comprising a data writing module, a driving module, a compensation module, a coupling module, a storage module, and a light-emitting module. During the compensation phase, the data writing module transmits the initial voltage input from the first voltage input terminal to the first terminal of the coupling module; and during the data writing phase, it transmits the data voltage input from the first voltage input terminal to the first terminal of the coupling module. The second terminal of the coupling module is connected to the control terminal of the driving module, thereby enabling the writing of a voltage corresponding to the data voltage to the control terminal of the driving module via the data writing module and the coupling module. The compensation module is connected between the second terminal of the driving module and the control terminal of the driving module, and can compensate for the threshold voltage of the driving module during the compensation phase. During the light-emitting phase, the driving module, based on the first power supply voltage input from the second voltage input terminal to the first terminal of the driving module and the voltage of the control terminal of the driving module, outputs a driving current through the second terminal of the driving module to the light-emitting module, thereby driving the light-emitting module. In the display panel of this embodiment, the pixel circuit includes fewer circuit modules, and correspondingly, the pixel circuit includes fewer circuit devices, which simplifies the pixel circuit structure. This also helps to simplify the wiring in the display panel, thereby improving the transmittance of the display panel, enhancing the transparent display effect, and ensuring the display quality of the transparent display device.

[0077] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 2 and Figure 3 Optionally, the display panel also includes a first voltage selection module 200. The first voltage selection module 200 includes a first input terminal, a second input terminal, a first control terminal SW-Vini, a second control terminal SW-Vdata, and a first output terminal. The first output terminal is electrically connected to the first voltage input terminal V1. The first input terminal is connected to the initial voltage Vini, and the second input terminal is connected to the data voltage Vdata.

[0078] The first voltage selection module 200 is used to transmit the initial voltage Vini to the first voltage input terminal V1 in response to the first control signal of the first control terminal SW-Vini during the compensation phase; and to transmit the data voltage Vdata to the first voltage input terminal V1 in response to the second control signal of the second control terminal SW-Vdata during the data writing phase.

[0079] Specifically, during the compensation phase, the first control signal input to the first control terminal SW-Vini is a conduction control signal, which enables conduction between the first input terminal and the first output terminal. The initial voltage Vini can be transmitted to the first voltage input terminal V1 through the connection between the first input terminal and the first output terminal. During the data writing phase, the second control signal input to the second control terminal SW-Vdata is a conduction control signal, which enables conduction between the second input terminal and the first output terminal. The data voltage Vdata can be transmitted to the first voltage input terminal V1 through the connection between the second input terminal and the first output terminal.

[0080] refer to Figure 2 and Figure 3 Optionally, the first voltage selection module 200 may include a first transistor T10 and a second transistor T20. The gate of the first transistor T10 serves as the first control terminal SW-Vini of the first voltage selection module 200, the first electrode of the first transistor T10 serves as the first input terminal of the first voltage selection module 200, and the second electrode of the first transistor T10 serves as the first output terminal of the first voltage selection module 200. The gate of the second transistor T20 serves as the second control terminal SW-Vdata of the first voltage selection module 200, the first electrode of the second transistor T20 serves as the second input terminal of the first voltage selection module 200, and the second electrode of the second transistor T20 serves as the first output terminal of the first voltage selection module 200.

[0081] Continue to refer to Figure 2 In some optional embodiments of the present invention, each pixel circuit 100 includes a first voltage selection module 200; that is, the first voltage selection module 200 is disposed in the display area AA and is included in the pixel circuit 100, so that the bezel width of the display panel will not increase due to the setting of the first voltage selection module 200, which is beneficial to achieving a narrow bezel.

[0082] refer to Figure 3 In another optional embodiment of the present invention, the first voltage selection module 200 is disposed in the non-display area NAA of the display panel, and the display panel also includes multiple data lines D0. The output terminal of the first voltage selection module 200 is electrically connected to the data lines D0 in a one-to-one correspondence. Each data line D0 is connected to the first voltage input terminal V1 of a column of pixel circuits 100.

[0083] In this embodiment, the first voltage selection module 200 is located in the non-display area (NAA). Each first voltage selection module 200 can be used to control the voltage of the first voltage input terminal V1 of a column of pixel circuits 100. Specifically, in the column of pixel circuits 100 connected to the first voltage selection module 200, during the compensation phase of each pixel circuit 100, a conduction control signal is input to the first control terminal SW-Vini of the first voltage selection module 200, causing the first input terminal and the first output terminal of the first voltage selection module 200 to conduct. This enables the initial voltage Vini to be transmitted to the data line D0 through the connection path between the first input terminal and the first output terminal. The data line D0 can then transmit the initial voltage Vini to the first voltage input terminal V1 of the corresponding connected column of pixel circuits 100. The compensation phases of the same column of pixel circuits 100 can be performed simultaneously. In a row of pixel circuits 100 connected to the first voltage selection module 200, during the data writing phase of each pixel circuit 100, a conduction control signal is input to the second control terminal SW-Vdata of the first voltage selection module 200, causing the second input terminal and the first output terminal of the first voltage selection module 200 to conduct. This enables data transmission to the data line D0 through the connection path between the second input terminal and the first output terminal. The data line D0 can then transmit the data voltage Vdata to the first voltage input terminal V1 of the corresponding connected row of pixel circuits 100. The data writing phases of each row of pixel circuits 100 are performed sequentially in a time-division manner. During the data writing phase of each pixel circuit 100, the data voltage Vdata of the first voltage input terminal V1 can be transmitted to the first terminal of the coupling module 140 through the data writing module 110. By placing the first voltage selection module 200 in the non-display area NAA of the display panel, the number of circuit modules included in the pixel circuits 100 in the display area AA can be reduced, which is beneficial to improving the transmittance of the display panel.

[0084] Continue to refer to Figure 3 The display panel includes a display area AA and a non-display area NAA. The non-display area NAA includes a setting border area NAA1. The first voltage selection module 200 is located in the setting border area NAA1. The setting border area NAA1 includes a lead-out line that draws out the data voltage Vdata from the driver chip. The lead-out line is electrically connected to the data line D0.

[0085] Specifically, the non-display area (NAA) can include multiple border areas, for example, for Figure 3 For the display panel shown, the non-display area (NAA) can include the top bezel, bottom bezel, left bezel, and right bezel. The bezel area NAA1 is defined as the bezel area including the lead-out line from the driver chip for the data voltage Vdata. Figure 3The display panel shown has a set border area NAA1 that can be the bottom border area. The driver chip can also be located in the bottom border area, or on the non-emitting side of the display panel. Because the set border area NAA1 of the display panel itself requires numerous leads and circuit structures, such as the power supply providing the initial voltage Vini (or the leads connecting to the power supply providing the initial voltage Vini) and the leads leading to the data voltage Vdata from the driver chip, the first voltage selection module 200 is placed in the set border area NAA1 of the display panel. This makes it easier to connect the first voltage selection module 200 to the power supply providing the initial voltage Vini, and also makes it easier to connect the first voltage selection module 200 to the driver chip providing the data voltage Vdata. Furthermore, since the setting bezel area NAA1 of the display panel itself needs to be equipped with a lot of leads and circuit structures, the setting bezel area NAA1 itself has a certain width. By setting the first voltage selection module 200 in the setting bezel area NAA1, even if the width of the setting bezel area NAA1 is widened to a certain extent, the impact on the user experience is smaller compared to setting the first voltage selection module 200 in a bezel area that is narrower than the setting bezel area NAA1.

[0086] Figure 4 This is a driving timing diagram of a display panel provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 2 and Figure 3 The display panel shown, in which Figure 4 The driving timing diagram shown only illustrates the driving signals for the first voltage selection module (i.e., the driving signals for the first control terminal SW-Vini and the second control terminal SW-Vdata), and assuming that the first transistor T10 and the second transistor T20 in the first voltage selection module 200 are P-type transistors. (Reference) Figures 2-4 The operation of the pixel circuit in the display panel includes a compensation stage t1, a data writing stage t2, and a light emission stage t3.

[0087] in, Figure 2 and Figure 3 In the pixel circuit 100 of the display panel shown, the operation of the data writing module 110, driving module 120, compensation module 130, coupling module 140, storage module 150, and light-emitting module 160 occurs during the compensation stage t1, data writing stage t2, and light-emitting stage t3. Figure 1 The operation of the pixel circuit 100 of the display panel shown is the same, and will not be described again here.

[0088] because Figure 3 and Figure 4The display panel shown incorporates a first voltage selection module 200. The operation of the first voltage selection module 200 is described below. During the compensation phase t1, the first control signal input to the first control terminal SW-Vini of the first voltage selection module 200 is a low-level signal, and the first transistor T10 is turned on, transmitting the initial voltage Vini to the first voltage input terminal V1. During the data writing phase t2, the second control signal input to the second control terminal SW-Vdata of the first voltage selection module 200 is a low-level signal, and the second transistor T20 is turned on, transmitting the data voltage Vdata to the first voltage input terminal V1. During the light emission phase t3, both the first control signal at the first control terminal SW-Vini and the second control signal at the second control terminal SW-Vdata are high-level signals, and both the first transistor T10 and the second transistor T20 are turned off.

[0089] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 5 and Figure 6 Optionally, the pixel circuit 100 further includes a reset module 170. The input terminal of the reset module 170 is electrically connected to the second voltage input terminal V2, and the output terminal of the reset module 170 is electrically connected to the control terminal of the drive module 120. The reset module 170 is used to transmit the reset voltage input at the second voltage input terminal V2 to the control terminal of the drive module 120 during the first reset phase. The compensation module 130 is also used to turn on during the first reset phase and transmit the reset voltage transmitted by the reset module 170 to the second terminal of the drive module 120. The first reset phase is performed before the compensation phase.

[0090] In the first reset phase, the reset module 170 is turned on. A reset voltage is input to the second voltage input terminal V2, and this reset voltage is transmitted to the control terminal of the drive module 120 through the turned-on reset module 170, thus resetting the control terminal of the drive module 120. By including the reset module 170 in the pixel circuit 100, and by having the reset module 170 reset the control terminal of the drive module 120 and set an appropriate reset voltage in the first reset phase, it is ensured that in the subsequent compensation phase, the drive module 120 can be turned on based on the reset voltage at the control terminal and the voltage at its first terminal. This ensures that when the compensation module 130 is turned on during the compensation phase, it can compensate for the threshold voltage of the drive module 120, preventing the drive module 120 from failing to turn on due to uncleared data from the previous frame, thus preventing the compensation phase from proceeding normally. The magnitude of the reset voltage can be set by those skilled in the art based on the type of drive transistors included in the drive module 120 and the voltage input from the first power supply voltage input terminal to the first terminal of the drive module 120 during the first reset phase. The first reset voltage must ensure that the drive module 120 can be turned on during the first reset phase. The reset module 170 may include a reset transistor, the gate of which serves as the control terminal of the reset module 170, the first terminal of which serves as the first terminal of the reset module 170, and the second terminal of which serves as the second terminal of the reset module 170.

[0091] Based on the above embodiments, optionally, the driving module 120 is further configured to transmit the voltage at the first terminal of the driving module 120 to the second terminal of the driving module 120 during the second reset phase; the second reset phase is performed between the compensation phase and the data writing phase.

[0092] Specifically, after the compensation phase is completed, the drive module 120 is in a critical state between conduction and cutoff, which is the second reset phase. The drive module 120 can transmit the voltage of the first terminal to the second terminal of the drive module 120 to achieve the reset of the first terminal of the light-emitting module 160, ensuring that the first terminal of the light-emitting module 160 is fully reset.

[0093] It should be noted that, for Figure 5 and Figure 6 In the display panel shown, when the pixel circuit 100 is in operation during the second reset phase, it is necessary to ensure that after the voltage at the first end of the driving transistor is transmitted to the second end of the driving transistor during the second reset phase, the light-emitting module 160 will not emit light, so as to avoid the adverse effects of the light-emitting module 160 emitting light in stages other than the light-emitting phase on the display effect.

[0094] It should also be noted that during the second reset phase, the compensation module 130 is turned off, and the potential at the second terminal of the drive module 120 will no longer be transmitted to the control terminal of the drive module 120.

[0095] Continue to refer to Figure 5 and Figure 6 Optionally, the display panel also includes a second voltage selection module 300, which includes a third input terminal, a fourth input terminal, a third control terminal SW-Vref, a fourth control terminal SW-VDD, and a second output terminal. The second output terminal is electrically connected to the second voltage input terminal V2. The third input terminal is connected to the reset voltage Vref, and the fourth input terminal is connected to the first power supply voltage VDD.

[0096] The second voltage selection module 300 is used to transmit the reset voltage Vref to the second voltage input terminal V2 in response to the third control signal of the third control terminal SW-Vref during the first reset phase; and to transmit the first power supply voltage VDD to the second voltage input terminal V2 in response to the fourth control signal of the fourth control terminal SW-VDD during the light emission phase.

[0097] Specifically, in the first reset phase, the third control signal input to the third control terminal SW-Vref is a conduction control signal, which enables conduction between the third input terminal and the second output terminal. The reset voltage Vref can be transmitted to the second voltage input terminal V2 through the connection between the third input terminal and the second output terminal. In the light-emitting phase, the fourth control signal input to the fourth control terminal SW-VDD is a conduction control signal, which enables conduction between the fourth input terminal and the second output terminal. The first power supply voltage VDD can be transmitted to the second voltage input terminal V2 through the connection between the fourth input terminal and the second output terminal.

[0098] refer to Figure 5 and Figure 6 Optionally, the second voltage selection module 300 may include a third transistor T30 and a fourth transistor T40. The gate of the third transistor T30 serves as the third control terminal SW-Vref of the second voltage selection module 300, the first terminal of the third transistor T30 serves as the third input terminal of the second voltage selection module 300, and the second terminal of the third transistor T30 serves as the second output terminal of the second voltage selection module 300. The gate of the fourth transistor T40 serves as the fourth control terminal SW-VDD of the second voltage selection module 300, the first terminal of the fourth transistor T40 serves as the fourth input terminal of the second voltage selection module 300, and the second terminal of the fourth transistor T40 serves as the second output terminal of the second voltage selection module 300.

[0099] Among them, for Figure 5 and Figure 6As shown in the display panel, the second voltage selection module 300 can, during the compensation phase, respond to the fourth control signal of the fourth control terminal SW-VDD to transmit the first power supply voltage VDD to the second voltage input terminal V2. During the compensation phase, the fourth control signal input to the fourth control terminal SW-VDD is a conduction control signal, enabling conduction between the fourth input terminal and the second output terminal. The first power supply voltage VDD can then be transmitted to the second voltage input terminal V2 through the connection between the fourth input terminal and the second output terminal. During the compensation phase, the drive module 120 and the compensation module 130 transmit the first power supply voltage VDD to the control terminal of the drive module 120 to compensate for the threshold voltage of the drive module 120. This configuration simplifies the structure of the second voltage selection module 300. When the second voltage selection module 300 is placed in the display area AA, it ensures high transmittance of the display panel; when placed in the non-display area NAA, it prevents the bezel of the display panel from becoming too wide. However, since the first power supply voltage VDD is the voltage that can make the light-emitting module 160 emit light if it directly reaches the first terminal of the light-emitting module 160 through the drive module 120 when the drive module 120 is turned on, in order to avoid the light-emitting stage emitting light in stages other than the light-emitting stage, a switch needs to be set between the first terminal of the light-emitting module 160 and the second terminal of the drive module 120 to control the conduction state between the drive module 120 and the first terminal of the light-emitting module 160, or the voltage connected to the second terminal of the light-emitting module 160 can be set to be different in the light-emitting stage and in stages other than the light-emitting stage.

[0100] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 7 and Figure 8 Optionally, the second voltage selection module 300 further includes a fifth input terminal and a fifth control terminal SW-Vcom. The fifth input terminal is connected to the compensation voltage Vcom. The compensation voltage Vcom is less than the first power supply voltage VDD. The second voltage selection module 300 is also used to transmit the compensation voltage Vcom to the second voltage input terminal V2 in response to the control signal of the fifth control terminal SW-Vcom during the compensation phase.

[0101] Next, refer to Figure 7 and Figure 8 The second voltage selection module 300 also includes a fifth transistor T50, wherein the gate of the fifth transistor T50 serves as the fifth control terminal SW-Vcom of the second voltage selection module 300, the first terminal of the fifth transistor T50 serves as the fifth input terminal of the second voltage selection module 300, and the second terminal of the fifth transistor T50 serves as the second output terminal of the second voltage selection module 300.

[0102] and Figure 5 and Figure 6 The display panel shown is different; when the second voltage selection module 300 is... Figure 7 and Figure 8 In the structure shown, during the compensation phase, the fifth control signal input to the fifth control terminal SW-Vcom is a conduction control signal, causing the fifth input terminal and the second output terminal of the second voltage selection module 300 to conduct during the compensation phase. The compensation voltage Vcom is transmitted to the second voltage input terminal V2 through the connection path between the fifth input terminal and the second output terminal. During the compensation phase, the drive module 120 and the compensation module 130 transmit the compensation voltage Vcom to the control terminal of the drive module 120, achieving threshold voltage compensation for the drive module 120. In this embodiment, the compensation voltage Vcom is less than the first power supply voltage VDD. Optionally, the compensation voltage Vcom is a voltage that ensures the light-emitting module 160 will not light up when it reaches the second terminal of the drive module 120 through the first terminal and the first terminal of the light-emitting module 160 through the second terminal of the drive module 120. During the compensation phase, even if a switch is not set between the second end of the driving module 120 and the first end of the light-emitting module 160 in the pixel circuit 100 to control the conduction state between the driving module 120 and the first end of the light-emitting module 160, the light-emitting module 160 will not light up in stages other than the light-emitting phase; or if the voltage connected to the second end of the light-emitting module 160 is the same in the light-emitting phase and in stages other than the light-emitting phase, the light-emitting module 160 will not light up in stages other than the light-emitting phase.

[0103] Continue to refer to Figure 7 In some optional embodiments of the present invention, each pixel circuit 100 includes a second voltage selection module 300; that is, the second voltage selection module 300 is disposed in the display area AA and is included in the pixel circuit 100.

[0104] refer to Figure 8 In another optional embodiment of the present invention, the second voltage selection module 300 is disposed in the non-display area NAA of the display panel, and the display panel also includes multiple first power lines VDO. The output terminal of the first voltage selection module 200 is electrically connected to the first power lines VDO one by one. Each first power line VDO is connected to the second voltage input terminal V2 of a column of pixel circuits 100.

[0105] In this embodiment, the second voltage selection module 300 is located in the non-display area NAA. Each second voltage selection module 300 can be used to control the voltage of the second voltage input terminal V2 of a column of pixel circuits 100. Specifically, in the first reset phase of each pixel circuit 100 connected to the second voltage selection module 300, a conduction control signal is input to the third control terminal SW-Vref of the second voltage selection module 300, causing the third input terminal and the second output terminal of the second voltage selection module 300 to conduct. This enables the reset voltage Vref to be transmitted to the first power supply line VD0 through the connection path between the third input terminal and the second output terminal. The first power supply line VD0 can then transmit the reset voltage Vref to the second voltage input terminal V2 of the corresponding connected column of pixel circuits 100. The first reset phases of the same column of pixel circuits 100 can be performed simultaneously. In a row of pixel circuits 100 connected to the second voltage selection module 300, during the light-emitting phase of each pixel circuit 100, a conduction control signal is input to the fourth control terminal SW-VDD of the second voltage selection module 300, causing the fourth input terminal and the second output terminal of the second voltage selection module 300 to conduct. This enables the first power supply voltage VDD to be transmitted to the first power supply line VD0 through the connection path between the fourth input terminal and the second output terminal. The first power supply line VD0 can then transmit the first power supply voltage VDD to the second voltage input terminal V2 of the corresponding row of pixel circuits 100. The light-emitting phases of each row of pixel circuits 100 can be performed simultaneously. For the compensation phase, where the second voltage selection module 300 provides the first power supply voltage VDD to the second voltage input terminal V2, this can be achieved by inputting a conduction control signal to the fourth control terminal SW-VDD of the second voltage selection module 300 during the compensation phase. The compensation phases of pixels in the same row can also be performed simultaneously.

[0106] By placing the second voltage selection module 300 in the non-display area NAA of the display panel, the number of circuit modules included in the pixel circuit 100 in the display area AA can be reduced, which is beneficial to improving the transmittance of the display panel.

[0107] Continue to refer to Figure 8 Optionally, the display panel includes a display area AA and a non-display area NAA. The non-display area NAA includes a setting border area NAA1, and the second voltage selection module 300 is located in the setting border area NAA1. The setting border area NAA1 includes a lead-out line for the data voltage Vdata from the driver chip, and the lead-out line is electrically connected to the data line D0 of the display panel.

[0108] Specifically, the non-display area (NAA) can include multiple border areas, for example, for Figure 8For the display panel shown, the non-display area (NAA) can include the top bezel, bottom bezel, left bezel, and right bezel. The bezel area NAA1 is defined as the bezel area including the lead-out line from the driver chip for the data voltage Vdata. Figure 8 The display panel shown can have a bottom bezel area (NAA1). The driver chip can also be located in the bottom bezel area, or on the non-emitting side of the display panel. Because the bottom bezel area (NAA1) of the display panel requires numerous leads and circuit structures, such as a power supply for the reset voltage Vref (or leads connecting to the power supply for Vref), a power supply for the first power supply voltage VDD (or leads connecting to the power supply for VDD), and the leads for the data voltage Vdata derived from the driver chip, the second voltage selection module 300 is placed in the bottom bezel area (NAA1) of the display panel. This makes it easier to connect the second voltage selection module 300 to the power supply for the reset voltage Vref and also to the power supply for the first power supply voltage VDD. Furthermore, since the setting bezel area NAA1 of the display panel itself needs to be equipped with a lot of leads and circuit structures, the setting bezel area NAA1 itself has a certain width. By setting the second voltage selection module 300 in the setting bezel area NAA1, even if the width of the setting bezel area NAA1 is increased to a certain extent, the impact on the user experience is smaller compared to setting the second voltage selection module 300 in a bezel area that is narrower than the setting bezel area NAA1.

[0109] Continue to refer to Figure 7 and Figure 8 The display panel also includes multiple first gate control lines S0, which are connected to the control terminals of the reset module 170. (Continue to refer to...) Figures 1-8 The display panel also includes multiple second gate control lines S1 and multiple scan lines S2. In the pixel circuit 100, the data writing module 110 includes a data writing transistor T1. The gate of the data writing transistor T1 serves as the control terminal of the data writing module 110 and is connected to the scan line S2 in the display panel. The first terminal of the data writing transistor T1 serves as the first terminal of the data writing module 110 and is connected to the first voltage input terminal V1. The second terminal of the data writing transistor T1 serves as the second terminal of the data writing module 110 and is connected to the first terminal of the coupling module 140. The coupling module 140 may include a first capacitor C1, and the storage module 150 may include a second capacitor C2. The driving module 120 includes a driving transistor DT, and the compensation module 130 includes a compensation transistor T2. The gate of the compensation transistor T2 serves as the control terminal of the compensation module 130 and is connected to the second gate control line S1 in the display panel. The light-emitting module 160 may include a light-emitting device, which may be an organic light-emitting device or an inorganic light-emitting device; this embodiment does not specifically limit the specific light-emitting device.

[0110] The following are Figure 7 and Figure 8 The detailed working process of the display panel shown is explained below. Figure 9 This is a driving timing diagram of another display panel provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 7 and Figure 8 The display panel shown is... Figure 7 and Figure 8 The transistors shown are all P-type transistors, used as an example for illustration. (Reference) Figures 7-9 The operation of the display panel includes a first reset stage t4, a compensation stage t1, a second reset stage t5, a data writing stage t2, and a light emission stage t3. The data writing stage t2 of the display panel can include the data writing stages for each row of pixel circuits, with each row of pixel circuits' data writing stage denoted as a data writing sub-stage t21.

[0111] In the first reset phase t4, the first control signal input to the first control terminal SW-Vini of the first voltage selection module 200 is a low-level signal, the first transistor T10 is turned on, and the initial voltage Vini is transmitted to the first voltage input terminal V1. The signal on the scan line S2 is a low-level signal, the data writing transistor T1 is turned on, and the initial voltage Vini of the first power input terminal is transmitted to the first terminal of the coupling module 140. The third control signal input to the third control terminal SW-Vref of the second voltage selection module 300 is a low-level signal, the third transistor T30 is turned on, and the reset voltage Vref is transmitted to the second voltage input terminal V2. The signal on the first gate control line S0 is a low-level signal, the reset transistor T3 is turned on, and the reset voltage Vref of the second voltage input terminal V2 is transmitted to the control terminal of the drive module 120, thereby resetting the control terminal of the drive module 120. When the signal on the second gate control line S1 is low, the compensation transistor T2 is turned on. The reset voltage Vref is transmitted to the second terminal of the driving module 120 through the reset transistor T3 and the compensation transistor T2, thereby resetting the second terminal of the driving module 120 and also resetting the anode of the light-emitting device. The driving module 120 can be the drain of the driving transistor DT, and the first terminal of the driving module 120 can be the source of the driving transistor DT.

[0112] During compensation phase t1, the first control signal input to the first control terminal SW-Vini of the first voltage selection module 200 is a low-level signal, and the first transistor T10 is turned on, transmitting the initial voltage Vini to the first voltage input terminal V1. The signal on the scan line S2 is a low-level signal, and the data writing transistor T1 is turned on, transmitting the initial voltage Vini from the first power input terminal to the first terminal of the coupling module 140. The fifth control signal input to the fifth control terminal SW-Vcom of the second voltage selection module 300 is a low-level signal, and the fifth transistor T50 is turned on, transmitting the compensation voltage Vcom to the second voltage input terminal V2. The signal on the second gate control line S1 is a low-level signal, and the compensation transistor T2 is turned on. During compensation phase t1, the driving transistor DT is turned on according to the potential of its own control terminal and the first terminal. The compensation voltage Vcom is transmitted to the control terminal of the driving transistor DT through the driving transistor DT and the compensation transistor T2 until the gate potential of the driving transistor DT is equal to Vcom + Vth, where Vth is the threshold voltage of the driving transistor DT. During the compensation phase t1, the signal on the first gate control line S0 is a high-level signal, and the reset transistor T3 is turned off.

[0113] During the second reset phase t5, the signals on the first gate control line S0, the second gate control line S1, and the scan line S2 are all high-level signals, and the reset transistor T3, compensation transistor T2, and data write transistor T1 are all turned off. The operating state of the second voltage selection module 300 is the same as that in the compensation phase t1, so the voltage at the second voltage input terminal V2 is still the compensation voltage Vcom. The driving transistor DT is in a critical state between on and off, continuing to transmit the compensation voltage Vcom to the anode of the light-emitting device, thereby resetting the anode of the light-emitting device.

[0114] During the data writing stage t2, the second control signal input to the second control terminal SW-Vdata of the first voltage selection module 200 is a low-level signal, and the second transistor T20 is turned on, transmitting the data voltage Vdata to the first voltage input terminal V1. The data writing stage t2 of the display panel includes n data writing sub-stages t21, where n equals the number of rows of pixel circuits 100 in the display panel, and each data writing sub-stage t21 corresponds to the data writing stage t2 of one row of pixel circuits 100. Figure 9In the diagram, S2-Row1 represents the scan line connected to the control terminal of the data writing module 110 of the first row of pixel circuits 100 in the display panel, S2-Row2 represents the scan line connected to the control terminal of the data writing module 110 of the second row of pixel circuits 100 in the display panel, and S2-Row3 represents the scan line connected to the control terminal of the data writing module 110 of the third row of pixel circuits 100 in the display panel. The display panel may include w scan lines S2, and each scan line S2 is connected to a row of pixel circuits 100. During the data writing stage t2 of the display panel, the signals from the scan lines S2-Row1, S2-Row2, and S2-Row3 connected to the control terminals of the data writing modules 110 of the first row pixel circuit 100, up to the scan line S2 connected to the control terminal of the data writing module 110 of the w-th row pixel circuit 100, are low-level pulses in sequence. This causes the data writing modules 110 of the first row pixel circuit 100 to the data writing modules 110 of the w-th row pixel circuit 100 to be turned on sequentially, thus writing the data voltage Vdata into the pixel circuit 100 line by line. The data writing transistor T1 transmits the data voltage Vdata to the first terminal of the coupling module 140, causing the first terminal of the coupling module 140 to switch from the initial voltage Vini to the data voltage Vdata. The potential at the first terminal of the coupling module 140 changes from the initial voltage Vini to the data voltage Vdata. The voltage change at the first terminal of the coupling module 140 is ΔV1 = Vdata - Vini. At this time, the gate voltage of the driving transistor DT will change accordingly. The specific change is ΔV2 = k*(Vdata - Vini), k = C10 / (C10 + Other_g), where C10 is the capacitance value of the first capacitor C1, and Other_g is the capacitance value of other capacitors at the gate point. Then the gate potential of the driving transistor DT is Vcom + Vth + k*(Vdata - Vini).

[0115] During the light-emitting stage t3, the first control signal of the first control terminal SW-Vini and the second control signal of the second control terminal SW-Vdata of the first voltage selection module 200 are both high-level signals, and the first transistor T10 and the second transistor T20 are both turned off. The fourth control signal of the fourth control terminal SW-VDD of the second voltage selection module 300 is low-level, the fourth transistor T40 is turned on, and the first power supply voltage VDD is transmitted to the second power supply input terminal. The driving transistor DT is turned on according to the gate voltage and the first power supply voltage VDD, generating a driving current to drive the light-emitting device to emit light. Because the voltage on the first power supply line jumps from the compensation voltage Vcom to the first power supply voltage VDD, the voltage on the second voltage input terminal V2 jumps from the compensation voltage Vcom to the first power supply voltage VDD. The voltage jump change of the second voltage input terminal V2 is ΔV3 = VDD - Vcom. Correspondingly, the voltage at the first terminal of the coupling module 140 becomes Vdata + k1*(VDD - Vcom), and the voltage change at the first terminal of the coupling module 140 is k1*(VDD - Vcom), where k1 = C2 / (C1 + C2 + Other_n1). The gate of the driving transistor DT is coupled to Vcom + Vth + k*(Vdata - Vini) + k*k1*(VDD - Vcom). Therefore, Vgs-Vth = Vcom + Vth + k*(Vdata-Vini) + k*k1*(VDD-Vcom) – VDD-Vth in the light-emitting stage t3, where Vgs represents the voltage difference between the gate and the first electrode of the driving transistor DT. Thus, the pixel circuit 100 structure of the display panel in this embodiment can compensate for the threshold voltage of the driving transistor DT.

[0116] In some embodiments of the present invention, k and k1 are made to be 100% or close to 100% (e.g., 95%-99%), and the above formula is reduced to Vgs-Vth=Vcom+Vth+(Vdata-Vini)+(VDD-Vcom)–VDD-Vth=Vdata-Vini. During the light-emitting stage t3, the current I of the driving transistor DT is 1 / 2μ*Cox*W / L*(Vdata-Vini)2, ultimately compensating for the factors of VDD, Vcom, and Vth in the light-emitting current.

[0117] In another embodiment of the present invention, considering that the capacitance values ​​and areas of C1 and C2 required to achieve a ratio of 1 for k and k1 are very large, k and k1 can be made between 0.5 and 1.

[0118] Among them, for Figure 7 and Figure 8 The voltage input to the third voltage input terminal V3, which is connected to the second end of the light-emitting module in the display panel shown, can be a fixed voltage.

[0119] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figures 10-12 Optionally, the second end of the driving module 120 is connected to the first end of the light-emitting module 160, and the second end of the light-emitting module 160 is connected to the third voltage input terminal V3; the display panel also includes a third voltage selection module 400, which includes a sixth input terminal, a seventh input terminal, a sixth control terminal SW-VSS1, a seventh control terminal SW-VSS2, and a third output terminal, which is electrically connected to the third voltage input terminal V3; the sixth input terminal is connected to the first cathode voltage VSS1, and the seventh input terminal is connected to the second cathode voltage VSS2; the second cathode voltage VSS2 is greater than the first cathode voltage VSS1;

[0120] The third voltage selection module 400 is used to transmit the second cathode voltage VSS2 to the third voltage input terminal V3 in response to the seventh control signal of the seventh control terminal SW-VSS2 in stages other than the light emission stage; and to transmit the first cathode voltage VSS1 to the third voltage input terminal V3 in response to the sixth control signal of the sixth control terminal SW-VSS1 in the light emission stage.

[0121] Specifically, in stages other than the light-emitting stage, the sixth control signal input to the sixth control terminal SW-VSS1 is a conduction control signal, which enables conduction between the sixth input terminal and the third output terminal. The second cathode voltage VSS2 can be transmitted to the first voltage input terminal V1 through the connection between the sixth input terminal and the third output terminal. In the light-emitting stage, the seventh control signal input to the seventh control terminal SW-VSS2 is a conduction control signal, which enables conduction between the seventh input terminal and the third output terminal. The first cathode voltage VSS1 can be transmitted to the first voltage input terminal V1 through the connection between the seventh input terminal and the third output terminal. The second cathode voltage VSS2 is greater than the first cathode voltage VSS1. That is, the voltage transmitted from the second voltage selection module 300 to the third voltage input terminal V3 during stages other than the light-emitting stage is greater than the voltage transmitted from the second voltage selection module 300 to the third voltage input terminal V3 during the light-emitting stage. This ensures that the voltage across the light-emitting module 160 is smaller during stages other than the light-emitting stage, preventing the light-emitting module 160 from emitting light. Conversely, during the light-emitting stage, the voltage across the light-emitting module 160 is larger, allowing the light-emitting module 160 to emit light. For example, during the compensation stage, when the first voltage selection module 200 transmits the first power supply voltage VDD to the second voltage input terminal V2, the driving module 120 specifically transmits the first power supply voltage VDD input from the second voltage input terminal V2 to the second terminal of the driving module 120 during the compensation stage. The compensation module 130 specifically transmits the voltage from the second terminal of the driving module 120 to the control terminal of the driving module 120 during the compensation stage. Due to the configuration of the third voltage selection module 400, the light-emitting module 160 can be prevented from emitting light during the compensation stage.

[0122] The technical solution of this embodiment, by setting the display panel to include a third voltage selection module 400, can avoid the adverse effects of the light emission module 160 emitting light on the display effect during stages other than the light emission stage (e.g., at least one of the first reset stage, compensation stage, second reset stage, and data writing stage).

[0123] refer to Figures 10-12 Optionally, the third voltage selection module 400 may include a sixth transistor T60 and a seventh transistor T70. The gate of the sixth transistor T60 serves as the sixth control terminal SW-VSS1 of the third voltage selection module 400, the first terminal of the sixth transistor T60 serves as the sixth input terminal of the third voltage selection module 400, and the second terminal of the sixth transistor T60 serves as the third output terminal of the third voltage selection module 400. The gate of the seventh transistor T70 serves as the seventh control terminal SW-VSS2 of the third voltage selection module 400, the first terminal of the seventh transistor T70 serves as the seventh input terminal of the third voltage selection module 400, and the second terminal of the seventh transistor T70 serves as the third output terminal of the third voltage selection module 400.

[0124] Continue to refer to Figure 10 In some optional embodiments of the present invention, each pixel circuit 100 includes a third voltage selection module 400, that is, the third voltage selection module 400 is disposed in the display area AA, and the third voltage selection module 400 is included in the pixel circuit 100.

[0125] refer to Figure 11 and Figure 12 In some optional embodiments of the present invention, the third voltage selection module 400 is disposed in the non-display area NAA of the display panel, and the second ends of the light-emitting modules 160 in each column of pixel circuits 100 in the display panel are interconnected; the display panel also includes a second power supply line VS0, one end of the second power supply line VS0 is electrically connected to a third output terminal, and the other end of the second power supply line VS0 is connected to the third voltage input terminal V3 of at least one column of pixel circuits 100.

[0126] refer to Figure 11 The second ends of each light-emitting module 160 in the display panel (the second end of the light-emitting module 160 can be the cathode 161 of the light-emitting device) are interconnected; the display panel includes a second power supply line VS0 that at least partially surrounds the display area AA; the display panel includes a third voltage selection module 400; the third output terminal of the third voltage selection module 400 is connected to the third voltage input terminal V3 of each pixel circuit 100 through the second power supply line VS0. Figure 11 The display panel structure shown has fewer third voltage selection modules 400, which occupy less bezel area and helps to achieve a narrow bezel. Furthermore, it eliminates the need to set a second power supply trace VS0 in the display area AA, which simplifies the wiring complexity of the display area AA and thus improves the transmittance of the display area AA.

[0127] refer to Figure 12 The display panel includes multiple second power supply lines VS0 and a third voltage selection module 400 electrically connected to each of the second power supply lines VS0. The third output terminal of the third voltage selection module 400 is connected to the third voltage input terminal V3 of at least one column of pixel circuits 100 through the second power supply lines VS0. The second terminals of the light-emitting modules 160 connected to the same second power supply line VS0 can be interconnected (specifically, they can be interconnected through the cathodes 161 of the light-emitting devices included in the light-emitting modules 160), that is, interconnected with the third voltage input terminals V3 connected to the same second power supply line VS0. By electrically connecting the second power supply line VS0 to the third voltage input terminal V3 of at least one pixel circuit 100, the signal on the second power supply line VS0 can be transmitted to the third voltage input terminal V3 of at least one column of pixel circuits 100. Figure 12The structure of the display panel shown allows for a smaller load connected to the third output terminal of each third voltage selection module 400, reducing the performance requirements of the transistors included in the third voltage selection module 400 and making the structure of the display panel easier to implement.

[0128] Continue to refer to Figure 11 and Figure 12 The display panel includes a display area AA and a non-display area NAA. The non-display area NAA includes a setting border area NAA1. The third voltage selection module 400 is located in the setting border area NAA1. The setting border area NAA1 includes a lead-out line for the data voltage Vdata from the driver chip. The lead-out line is electrically connected to the data line D0 of the display panel.

[0129] It is understandable that, for reasons similar to the first voltage selection module 200 being set in the setting border area NAA1 and the second voltage selection module 300 being set in the setting border area NAA1, the third voltage selection module 400 is set in the setting border area NAA1, achieving a similar effect to the first voltage selection module 200 being set in the setting border area NAA1 and the second voltage selection module 300 being set in the setting border area NAA1, which will not be elaborated further here.

[0130] The following are Figures 10-12 The detailed working process of the display panel shown is explained below. Figure 13 This is a driving timing diagram of another display panel provided in an embodiment of the present invention. This driving timing can be used to drive... Figures 10-12 The display panel shown is... Figures 10-12 The transistors shown are all P-type transistors, used as an example for illustration. (Reference) Figures 11-13 The operation of the display panel includes a first reset stage t4, a compensation stage t1, a second reset stage t5, a data writing stage t2, and a light emission stage t3. The data writing stage t2 of the display panel can include the data writing stages for each row of pixel circuits, with each row of pixel circuits' data writing stage denoted as a data writing sub-stage t21.

[0131] In the first reset phase t4, the first control signal input to the first control terminal SW-Vini of the first voltage selection module 200 is a low-level signal, the first transistor T10 is turned on, and the initial voltage Vini is transmitted to the first voltage input terminal V1. The signal on the scan line S2 is a low-level signal, the data writing transistor T1 is turned on, and the initial voltage Vini of the first power input terminal is transmitted to the first terminal of the coupling module 140. The third control signal input to the third control terminal SW-Vref of the second voltage selection module 300 is a low-level signal, the third transistor T30 is turned on, and the reset voltage Vref is transmitted to the second voltage input terminal V2. The signal on the first gate control line S0 is a low-level signal, the reset transistor T3 is turned on, and the reset voltage Vref of the second voltage input terminal V2 is transmitted to the control terminal of the drive module 120, thereby resetting the control terminal of the drive module 120. When the signal on the second gate control line S1 is low, the compensation transistor T2 is turned on. The reset voltage Vref is transmitted to the second terminal of the driving module 120 through the reset transistor T3 and the compensation transistor T2, thereby resetting the second terminal of the driving module 120 and also resetting the anode of the light-emitting device. The driving module 120 can be the drain of the driving transistor DT, and the first terminal of the driving module 120 can be the source of the driving transistor DT. When the sixth control signal input to the sixth control terminal SW-VSS1 of the third voltage selection module 400 is high, the sixth transistor T60 is turned off. When the seventh control signal input to the seventh control terminal SW-VSS2 of the third voltage selection module 400 is low, the seventh transistor T70 is turned on, transmitting the second cathode voltage VSS2 to the second terminal of the light-emitting module 160 (i.e., transmitting the second cathode voltage VSS2 to the cathode of the light-emitting device), ensuring that during the first reset phase t4, the voltage difference between the first and second terminals of the light-emitting module 160 will not illuminate the light-emitting module 160.

[0132] During compensation phase t1, the first control signal input to the first control terminal SW-Vini of the first voltage selection module 200 is a low-level signal, the first transistor T10 is turned on, and the initial voltage Vini is transmitted to the first voltage input terminal V1. The signal on the scan line S2 is a low-level signal, the data writing transistor T1 is turned on, and the initial voltage Vini at the first power input terminal is transmitted to the first terminal of the coupling module 140. The fourth control signal input to the fourth control terminal SW-VDD of the second voltage selection module 300 is a low-level signal, the fourth transistor T40 is turned on, and the first power supply voltage VDD is transmitted to the second voltage input terminal V2. The signal on the second gate control line S1 is a low-level signal, and the compensation transistor T2 is turned on. During compensation phase t1, the driving transistor DT is turned on according to the potential of its own control terminal and the first terminal. The first power supply voltage VDD is transmitted to the control terminal of the driving transistor DT through the driving transistor DT and the compensation transistor T2 until the gate potential of the driving transistor DT is equal to VDD + Vth, where Vth is the threshold voltage of the driving transistor DT. During the compensation phase t1, the signal on the first gate control line S0 is a high-level signal, and the reset transistor T3 is turned off. The sixth control signal input to the sixth control terminal SW-VSS1 of the third voltage selection module 400 is a high-level signal, and the sixth transistor T60 is turned off; the seventh control signal input to the seventh control terminal SW-VSS2 of the third voltage selection module 400 is a low-level signal, and the seventh transistor T70 is turned on, transmitting the second cathode voltage VSS2 to the second terminal of the light-emitting module 160 (that is, transmitting the second cathode voltage VSS2 to the cathode of the light-emitting device), so as to ensure that during the compensation phase t1, the voltage difference between the first and second terminals of the light-emitting module 160 will not light up the light-emitting module 160.

[0133] During the second reset phase t5, the signals on the first gate control line S0, the second gate control line S1, and the scan line S2 are all high-level signals, and the reset transistor T3, compensation transistor T2, and data write transistor T1 are all turned off. The operating state of the second voltage selection module 300 is the same as that of the compensation phase t1, so the voltage at the second voltage input terminal V2 is still the first power supply voltage VDD. The driving transistor DT is in a critical state between conduction and turn-off, continuing to transmit the first power supply voltage VDD to the anode of the light-emitting device, thereby resetting the anode of the light-emitting device. When the sixth control signal input to the sixth control terminal SW-VSS1 of the third voltage selection module 400 is high, the sixth transistor T60 is turned off; when the seventh control signal input to the seventh control terminal SW-VSS2 of the third voltage selection module 400 is low, the seventh transistor T70 is turned on, transmitting the second cathode voltage VSS2 to the second terminal of the light-emitting module 160 (that is, transmitting the second cathode voltage VSS2 to the cathode of the light-emitting device), so as to ensure that the voltage difference between the first and second terminals of the light-emitting module 160 will not light up the light-emitting module 160 during the second reset phase t5.

[0134] During the data writing stage t2, the second control signal input to the second control terminal SW-Vdata of the first voltage selection module 200 is a low-level signal, and the second transistor T20 is turned on, transmitting the data voltage Vdata to the first voltage input terminal V1. The data writing stage t2 of the display panel includes n data writing sub-stages t21, where n equals the number of rows of pixel circuits 100 in the display panel, and each data writing sub-stage t21 corresponds to the data writing stage t2 of one row of pixel circuits 100. Figure 9In the diagram, S2-Row1 represents the scan line connected to the control terminal of the data writing module 110 of the first row of pixel circuits 100 in the display panel, S2-Row2 represents the scan line connected to the control terminal of the data writing module 110 of the second row of pixel circuits 100 in the display panel, and S2-Row3 represents the scan line connected to the control terminal of the data writing module 110 of the third row of pixel circuits 100 in the display panel. The display panel may include w scan lines S2, and each scan line S2 is connected to a row of pixel circuits 100. During the data writing stage t2 of the display panel, the signals from the scan lines S2-Row1, S2-Row2, and S2-Row3 connected to the control terminals of the data writing modules 110 of the first row pixel circuit 100, up to the scan line S2 connected to the control terminal of the data writing module 110 of the w-th row pixel circuit 100, are low-level pulses in sequence. This causes the data writing modules 110 of the first row pixel circuit 100 to the data writing modules 110 of the w-th row pixel circuit 100 to be turned on sequentially, thus writing the data voltage Vdata into the pixel circuit 100 line by line. The data writing transistor T1 transmits the data voltage Vdata to the first terminal of the coupling module 140, causing the first terminal of the coupling module 140 to switch from the initial voltage Vini to the data voltage Vdata. The potential at the first terminal of the coupling module 140 changes from the initial voltage Vini to the data voltage Vdata. The voltage change at the first terminal of the coupling module 140 is ΔV1 = Vdata - Vini. At this time, the gate voltage of the driving transistor DT will change accordingly. The specific change is ΔV2 = k*(Vdata - Vini), k = C10 / (C10 + Cother_g), where C10 is the capacitance value of the first capacitor C1, and Cother_g is the capacitance value of other capacitors at the gate point. Then the gate potential of the driving transistor DT is VDD + Vth + k*(Vdata - Vini). When the sixth control signal input to the sixth control terminal SW-VSS1 of the third voltage selection module 400 is high, the sixth transistor T60 is turned off; when the seventh control signal input to the seventh control terminal SW-VSS2 of the third voltage selection module 400 is low, the seventh transistor T70 is turned on, transmitting the second cathode voltage VSS2 to the second terminal of the light-emitting module 160 (that is, transmitting the second cathode voltage VSS2 to the cathode of the light-emitting device), so as to ensure that during the data writing stage t2, the voltage difference between the first and second terminals of the light-emitting module 160 will not light up the light-emitting module 160.

[0135] During the light-emitting stage t3, the first control signal of the first control terminal SW-Vini and the second control signal of the second control terminal SW-Vdata of the first voltage selection module 200 are both high-level signals, and the first transistor T10 and the second transistor T20 are both turned off. The fourth control signal of the fourth control terminal SW-VDD of the second voltage selection module 300 is low-level, the fourth transistor T40 is turned on, and the first power supply voltage VDD is transmitted to the second power supply input terminal. The driving transistor DT is turned on according to the gate voltage and the first power supply voltage VDD, generating a driving current to drive the light-emitting device to emit light. In the light-emitting stage t3, Vgs-Vth = VDD+Vth+k*(Vdata-Vini)–VDD-Vth, where Vgs represents the voltage difference between the gate and the first electrode of the driving transistor DT. Therefore, in this embodiment, the pixel circuit 100 structure of the display panel can achieve compensation for the threshold voltage of the driving transistor DT. Then, during the light-emitting stage t3, the current I of the driving transistor DT is I = 1 / 2μ*Cox*W / L*[k(Vdata-Vini)2], which ultimately compensates for the factors of VDD and Vth in the light-emitting current. The sixth control signal input to the sixth control terminal SW-VSS1 of the third voltage selection module 400 is at a low level, and the sixth transistor T60 is turned on; the seventh control signal input to the seventh control terminal SW-VSS2 of the third voltage selection module 400 is at a high level, and the seventh transistor T70 is turned off. The first cathode voltage VSS1 is transmitted to the second terminal of the light-emitting module 160 (that is, the second cathode voltage VSS2 is transmitted to the cathode of the light-emitting device), so as to ensure that during the light-emitting stage t3, the voltage difference between the first and second terminals of the light-emitting module 160 can light up the light-emitting module 160.

[0136] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 14 Optionally, the pixel circuit 100 further includes a light-emitting control module 180, which is disposed between the second terminal of the driving module 120 and the first terminal of the light-emitting module 160. The second terminal of the light-emitting module 160 is connected to a third voltage input terminal V3. The light-emitting control module 180 is used to turn on during the light-emitting phase and turn off during other phases according to the signal from its own control terminal. Optionally, the light-emitting control module 180 includes a light-emitting control transistor T4, the gate of which serves as the control terminal of the light-emitting control module 180, the first terminal of which serves as the first terminal of the light-emitting control module 180 and is electrically connected to the second terminal of the driving module 120, and the second terminal of which serves as the second terminal of the light-emitting control module 180 and is electrically connected to the first terminal of the light-emitting module 160.

[0137] The display panel may also include multiple light-emitting control signal lines. Each light-emitting control signal line can be connected to the control terminal of the light-emitting control module 180 in a row of pixel circuits 100. The light-emitting control signal line can transmit a light-emitting control signal to the control terminal of the corresponding light-emitting control module 180. The light-emitting control module 180 is turned on or off according to the received light-emitting control signal. During the light-emitting stage, the light-emitting control signal line transmits a conduction control signal to the corresponding pixel circuit 100, causing the light-emitting control module 180 to conduct. The driving current generated by the driving module 120 can reach the first terminal of the light-emitting module 160 through the light-emitting control module 180, thereby driving the light-emitting module 160.

[0138] Based on the above embodiments, optionally, the third voltage input terminal V3 transmits the same voltage to the second terminal of the light-emitting module 160 in both the light-emitting phase and other phases. Specifically, since the pixel circuit 100 includes a light-emitting control module 180 connecting the second terminal of the driving module 120 and the first terminal of the light-emitting module 160, the light-emitting control module 180 is turned off in phases other than the light-emitting phase. This prevents the potential of the second terminal of the driving module 120 from reaching the first terminal of the light-emitting module 160 in phases other than the light-emitting phase. This avoids the problem of the light-emitting module 160 lighting up in phases other than the light-emitting phase due to an excessively high potential at the second terminal of the driving module 120. In other words, the display panel of this embodiment does not require a third voltage selection module 400, and the voltage input to the third voltage input terminal V3 remains constant, preventing the light-emitting module 160 from lighting up in phases other than the light-emitting phase. Therefore, the number of components in the display panel can be reduced, which is beneficial for improving the light transmittance of the display panel and reducing the width of the display panel bezel.

[0139] Optionally, the drive module 120 is specifically used to transmit the first power supply voltage VDD input at the second voltage input terminal V2 to the second terminal of the drive module 120 during the compensation phase, and the compensation module 130 is specifically used to transmit the voltage at the second terminal of the drive module 120 to the control terminal of the drive module 120 during the compensation phase.

[0140] As described above, the configuration of the light-emitting control module 180 in the pixel circuit 100 can avoid the problem of excessive voltage difference between the first and second terminals of the light-emitting module 160, which would occur outside the light-emitting stage due to the excessively high potential at the second terminal of the driving module 120. Therefore, in this embodiment, the driving module 120 is configured to transmit the first power supply voltage VDD input at the second voltage input terminal V2 to the second terminal of the driving module 120 during the compensation stage. Specifically, the compensation module 130 transmits the voltage at the second terminal of the driving module 120 to the control terminal of the driving module 120 during the compensation stage. That is, in the compensation module 130, the voltage input at the second voltage input terminal V2 is the first power supply voltage VDD. During the compensation stage, the driving module 120 and the compensation module 130 transmit the first power supply voltage VDD to the control terminal of the driving module 120, thereby compensating for the threshold voltage of the driving module 120. Correspondingly, when the display panel includes a second voltage selection module 300, the second voltage selection module 300 can be... Figure 14 The structure shown is such that the second voltage selection module 300 does not need to be connected to a compensation voltage Vcom that is different from the first power supply voltage VDD. Correspondingly, the second voltage selection module 300 does not need to be equipped with a fifth transistor T50, which makes the structure of the second voltage selection module 300 simpler, reduces the number of transistors in the display panel, and reduces wiring complexity.

[0141] It should be noted that, Figure 14 The example shown is based solely on the fact that both the first voltage selection module 200 and the second voltage selection module 300 included in the display panel are located in the pixel circuit 100. In other alternative embodiments of the present invention, either the first voltage selection module 200 or the second voltage selection module 300 may also be located in the non-display area NAA. This embodiment does not impose any specific limitations on this.

[0142] Figure 15 This is a driving timing diagram of another display panel provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 14 The display panel shown is... Figure 14 The transistors shown are all P-type transistors, used as an example for illustration. (Reference) Figure 14 and Figure 15 The working process of the display panel includes the first reset stage t4, the compensation stage t1, the second reset stage t5, the data writing stage t2, and the light emission stage t3.

[0143] Among them, with Figure 10 Compared to the display panel shown, Figure 14Except for the third voltage selection module 400, the operation of the other circuit structures in the display panel shown in the first reset stage t4, compensation stage t1, second reset stage t5, data writing stage t2, and light emission stage t3 is the same as that in the other circuit structures shown in the display panel. Figure 10 All are the same, so I will not repeat them here. The following only refers to... Figure 14 The operation of the light-emitting control module 180 included in the pixel circuit 100 of the display panel shown will be explained.

[0144] During the first reset phase t4, the compensation phase t1, the second reset phase t5, and the data writing phase t2, the light-emitting control signal connected to the gate of the light-emitting control transistor T4 is a high-level signal, the light-emitting control transistor T4 is turned off, and the light-emitting device does not emit light.

[0145] During the light-emitting stage t3, the light-emitting control signal connected to the gate of the light-emitting control transistor T4 is a low-level signal, the light-emitting control transistor T4 is turned on, and the driving current generated by the driving transistor DT is sent to the anode of the light-emitting device, so the light-emitting device can emit light.

[0146] Based on the above embodiments, combined with Figure 9 , Figure 13 and Figure 15 The display panel driving timing shown optionally includes the following: the first reset phase t4 of each pixel circuit 100 is performed simultaneously; the compensation phase t1 of each pixel circuit 100 is performed simultaneously; the second reset phase t5 of each pixel circuit 100 is performed simultaneously; the data writing phase t2 of each row of pixel circuits 100 is performed row by row; and the light emission phase t3 of each pixel circuit 100 is performed simultaneously. That is, the first reset phase of the pixel circuit is denoted as the first reset phase of the display panel, the compensation phase of the pixel circuit is denoted as the compensation phase of the display panel, the second reset phase of the pixel circuit is also the reset phase of the display panel, and the light emission phase of the pixel circuit is also the light emission phase of the display panel. The data writing phase of the display panel includes the data writing phase of each row of pixel circuits.

[0147] Figure 16 yes Figure 1 This is a magnified view of a specific area. Figure 16 Can correspond Figure 11 The enlarged view corresponding to area 101 outlined by the dashed line is for reference. Figure 16 Optionally, the display panel may also include multiple first gate control lines S0, second gate control lines S1, and scan lines S2;

[0148] Each row of pixel circuits 100 is connected to a first gate control line S0, a second gate control line S1, and a scan line S2. The first gate control line S0 is connected to the control terminal of the reset module of the corresponding row of pixel circuits 100, the second gate control line S1 is connected to the control terminal of the compensation module of the corresponding row of pixel circuits 100, and the scan line S2 is connected to the control terminal of the data writing module of the corresponding row of pixel circuits 100.

[0149] Among them, the conduction pulse signals on each first gate control line S0 overlap, the conduction pulse signals on each second gate control line S1 overlap, the first conduction pulse signals on each scan line S2 corresponding to the first reset stage and the compensation stage overlap, and the second conduction pulse signals on each scan line S2 corresponding to the data writing stage do not overlap.

[0150] Specifically, the conduction pulse signals on each first gate control line S0 overlap, and the first conduction pulse signals corresponding to the first reset stage and compensation stage on each scan line S2 overlap, ensuring that the first reset stage of each pixel circuit 100 occurs simultaneously. The conduction pulse signals on each second gate control line S1 overlap, and the first conduction pulse signals corresponding to the first reset stage and compensation stage on each scan line S2 overlap, ensuring that the compensation stage of each pixel circuit 100 occurs simultaneously. The second conduction pulse signals corresponding to the data writing stage on each scan line S2 do not overlap, allowing the data writing stages of different rows of pixel circuits 100 to occur at different times. Specifically, the second conduction pulse signals from the scan line S2 connected to the first row of pixel circuits 100 to the scan line S2 connected to the last row of pixel circuits 100 arrive sequentially, ensuring that the data writing stage of each row of pixel circuits 100 occurs row by row. The overlapping conduction pulse signals on each light-emitting control line in the display panel ensure that the light-emitting stages of each pixel circuit 100 in the display panel occur simultaneously.

[0151] refer to Figure 16 The data lines D0 in the display panel include a first data line DR0, a second data line DG0, and a third data line DB0. The first data line DR0 connects to the pixel circuit 100 that drives the red light-emitting device in the display panel, the second data line DG0 connects to the pixel circuit 100 that drives the green light-emitting device in the display panel, and the third data line DB0 connects to the pixel circuit 100 that drives the blue light-emitting device in the display panel. The display area AA of the display panel is divided into a light-transmitting area AA1 and a wiring area AA2. The pixel circuits 100 are concentrated in the wiring area AA2. Every three pixel circuits 100 form a pixel circuit group 102. Each pixel circuit group 102 may include one pixel circuit that drives the red light-emitting device in the display panel, one pixel circuit that drives the green light-emitting device in the display panel, and one pixel circuit that drives the blue light-emitting device in the display panel.

[0152] Continue to refer to Figures 1-3 , Figures 5-8 , Figures 10-12 and Figure 14 Optionally, the first end of the storage module 150 is electrically connected to the first end of the drive module 120, and the second end of the storage module 150 is electrically connected to either the first or second end of the coupling module 140. In the above embodiments of the present invention, the case where the second end of the storage module 150 is electrically connected to the first end of the coupling module 140 is illustrated schematically. When the second end of the storage module 150 is connected to the second end of the coupling module 140, the working process is similar to that in the above embodiments and will not be repeated here. It should be noted that regardless of whether the second end of the storage module 150 is electrically connected to either the first or second end of the coupling module 140, it can directly or indirectly store the potential of the control terminal of the drive module 120.

[0153] As described in the above embodiments, the display panel includes pixel circuits and various signal lines. The pixel circuits include transistors and capacitors. The transistors, capacitors, and signal lines typically contain metal materials, which block light. Insulating layers are also provided between different metal layers, and these insulating layers also have light-blocking properties. This results in significant diffraction between the different layers, leading to high haze and poor light transmission in the display panel. To reduce diffraction, decrease haze, and improve light transmission, another display panel is described in this embodiment of the invention. Figure 17 This is a cross-sectional view of a display panel provided in an embodiment of the present invention. Figure 17 Can correspond Figure 16 Cross-sectional view of the center cabling area, see reference. Figure 17 Optionally, the display panel further includes a substrate 500 and a driving circuit layer located on one side of the substrate 500, with the pixel circuit 100 located in the driving circuit layer; the driving circuit layer includes multiple stacked metal layers 600; the metal layer 600 includes a first patterned structure 610, wherein at least a portion of the first patterned structure 610 of one metal layer 600 is orthogonally projected onto the substrate 500 by the orthogonal projection of at least a portion of the first patterned structure 610 of another metal layer 600 onto the substrate 500.

[0154] The first patterned structure 610 includes the component structure of the devices in the pixel circuit 100. For example, the first patterned structure 610 can serve as the gate, source, or drain of a transistor, and also as the electrode of a capacitor. The first patterned structure 610 also includes the component structure of signal lines; the first pattern can also directly serve as signal lines in the display panel, such as data lines or scan lines. Because the metal material blocks light, diffraction is easily generated at the exposed edges of the first patterned structure of the metal layer 600. In this embodiment, at least a portion of the first patterned structure 610 of one metal layer 600 projected orthogonally onto the substrate 500 is covered by at least a portion of the first patterned structure 610 of another metal layer 600 projected orthogonally onto the substrate 500, thereby reducing the exposed edges of the first patterned structure 610 of the metal layer 600 in the display panel, reducing interlayer diffraction, and thus reducing haze and improving transparency. In the embodiments of the present invention, the exposed edge of the first patterned structure 610 refers to the edge where the orthographic projection of the first patterned structure 610 on the substrate 500 is not covered by the orthographic projection of other light-blocking structures on the substrate 500.

[0155] Based on the above embodiments, optionally, the driving circuit layer includes n stacked metal layers 600, where n is an integer greater than or equal to 2; wherein at least a portion of the first patterned structure 610 of any of the (n-1) metal layers 600 is orthogonally projected onto the substrate 500 by the orthogonal projection of at least a portion of the first patterned structure 610 of the other metal layers 600 onto the substrate 500, thereby further reducing the exposed edges of the first patterned structure 610 of the metal layers 600 in the display panel, further reducing interlayer diffraction, and reducing haze.

[0156] Figure 18 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 18 It can correspond to Figure 17 Obtained by cutting along BB'. Figure 19 yes Figure 18 For a detailed structural diagram of the cabling area, please refer to... Figure 18 and Figure 19 Optionally, the display panel also includes a substrate 500 and a driving circuit layer located on one side of the substrate 500, with the pixel circuit 100 located in the driving circuit layer; the driving circuit layer includes multiple layers of metal layers 600 stacked together and an insulating layer 700 between adjacent metal layers 600.

[0157] The metal layer 600 includes a first patterned structure 610, and the insulating layer 700 includes a second patterned structure 710; wherein at least a portion of the edge of the first patterned structure 610 of the metal layer 600 projected orthogonally onto the substrate 500 is covered by at least a portion of the second patterned structure 710 of the insulating layer 700 projected orthogonally onto the substrate 500; and / or, wherein at least a portion of the edge of the second patterned structure 710 of the insulating layer 700 projected orthogonally onto the substrate 500 is covered by at least a portion of the first patterned structure 610 of the metal layer 600 projected orthogonally onto the substrate 500; and / or, wherein at least a portion of the edge of the second patterned structure 710 of the insulating layer 700 projected orthogonally onto the substrate 500 is covered by at least a portion of the second patterned structure 710 of the other insulating layer 700 projected orthogonally onto the substrate 500.

[0158] Because the metal material blocks light, diffraction easily occurs at the exposed edges of the first patterned structure of the metal layer 600. The insulating layer 700 also has a certain light-blocking property, so diffraction also occurs at the exposed edges of the second patterned structure of the insulating layer 700. Specifically, in this embodiment, the orthographic projection of the second patterned structure 710 of the insulating layer 700 onto the substrate 500 covers the edge of the orthographic projection of the first patterned structure 610 of the metal layer 600 onto the substrate 500, and / or the orthographic projection of the first patterned structure 610 of the metal layer 600 onto the substrate 500 covers the edge of the orthographic projection of the second patterned structure 710 of the insulating layer 700 onto the substrate 500, and / or the orthographic projection of the second patterned structure 710 of one insulating layer 700 onto the substrate 500 covers the edge of the orthographic projection of the second patterned structure 710 of another insulating layer 700 onto the substrate 500. This reduces the exposed edge of the first patterned structure 610 of the metal layer 600 in the display panel, reduces the exposed edge of the second patterned structure 710 of the display panel, reduces interlayer diffraction, and lowers haze. In the embodiments of the present invention, the exposed edge of the second patterned structure 710 refers to the edge where the orthographic projection of the second patterned structure 710 on the substrate 500 is not covered by the orthographic projection of other light-blocking structures on the substrate 500. Optionally, the distance between the first patterned structures 610 belonging to the same metal layer 600 is greater than or equal to 2 micrometers.

[0159] Based on the above embodiments, optionally, the driving circuit layer includes n layers of metal layers 600 and m layers of insulating layers 700 stacked together, where n is an integer greater than or equal to 2 and m is an integer greater than or equal to 1.

[0160] The edge of at least a portion of the first patterned structure 610 of any metal layer 600 projected onto the substrate 500 is covered by the orthogonal projection of at least a portion of the first patterned structure 610 of other metal layers 600 and / or the second patterned structure 710 of the insulating layer 700 onto the substrate 500; the orthogonal projection of at least a portion of the second patterned structure 710 of any insulating layer 700 in the (m-1) layers onto the substrate 500 is covered by the orthogonal projection of at least a portion of the first patterned structure 610 of the metal layer 600 and / or the second patterned structure 710 of the other insulating layer 700 onto the substrate 500; Alternatively, the edge of at least a portion of the second patterned structure 710 of any insulating layer 700 projected onto the substrate 500 is covered by the orthogonal projection of at least a portion of the second patterned structure 710 of other insulating layers 700 or the first patterned structure 610 of metal layer 600 onto the substrate 500; the orthogonal projection of at least a portion of the first patterned structure 610 of any of the (n-1) metal layers 600 onto the substrate 500 is covered by the orthogonal projection of at least a portion of the first patterned structure 610 of other metal layers 600 and / or the second patterned structure 710 of insulating layer 700 onto the substrate 500. That is, in the display panel, only the edge of the first patterned structure 610 of one metal layer 600 is exposed, or only the edge of the first patterned structure 610 of one insulating layer 700 is exposed, thereby minimizing interlayer diffraction, resulting in lower haze and further improving transparency.

[0161] It should be noted that, Figures 17-19 The diagram schematically illustrates the structure of a three-layer metal layer 600 in a display panel, consisting of a first metal layer 601, a second metal layer 602, and a third metal layer 603 stacked from one side of the substrate 500. In this embodiment, the second power supply line can be located in the first metal layer 601, the scan line, the light emission control signal line, and the data line can be located in the second metal layer 602, and the first power supply line can be located in the third metal layer 603. It should be noted that the scan line and the light emission control signal line extend in the same direction, while the data line extends in a different direction. At the intersection of the data line and the scan line, a crossing from another metal layer 600 is required, and at the intersection of the data line and the light emission control signal line, a crossing from another metal layer 600 is also required. Of course, the film layer arrangement for the signal lines in the display panel can be in other ways, and this embodiment does not specifically limit this. The metal layers 600 included in the display panel are not limited to... Figures 17-19The three layers shown can also be two, four, or more layers; this embodiment does not impose a specific limitation. Exemplarily, in other optional embodiments of the present invention, the metal layer 600 where the second power line is located can be flexibly configured. For example, the second power line can be located on the same layer as the anode of the light-emitting device in the display panel, and the orthogonal projection of the second power line onto the substrate 500 can cover at least a portion of the orthogonal projection edge of the first patterned structure 610 in the other metal layers 600 of the display panel onto the substrate 500.

[0162] by Figure 19 Taking the display panel shown as an example, the display panel also includes a first insulating layer 701, a second insulating layer 702, a third insulating layer 703, and a fourth insulating layer 704. The first patterned structure 610 of the third metal layer 603 blocks the edges of the second patterned structure 710 of the second insulating layer 702, the second patterned structure 710 of the fourth insulating layer 704, and the first patterned structure 610 of the second metal layer 602. Similarly, the first patterned structure 610 of the first metal layer 601 blocks the edges of the second patterned structure 710 of the third insulating layer 703 and the first patterned structure 610 of the third metal layer 603. In this embodiment, the first insulating layer 701 can be an interlayer insulating layer 700 (i.e., the insulating layer 700 between the metal layer 600 where the capacitor plates are located and the metal layer 600 where the transistor source and drain are located in the pixel circuit 100), the second insulating layer 702 and the third insulating layer 703 can be planarization layers, and the fourth insulating layer 704 can be a pixel definition layer.

[0163] Based on the above technical solution, optionally, when the edge of the orthographic projection of the first patterned structure 610 (or the second patterned structure 710) on the substrate 500 is covered by the orthographic projection of other first patterned structures 610 (or the second patterned structure 710) on the substrate 500, the distance between the edges of the orthographic projections of the two can be 2 micrometers to 4 micrometers.

[0164] Figure 20 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 20 Based on the above embodiments, optionally, at the corner position P1 of signal line L1, signal line L1 is an arc; this setting can avoid right-angle routing, further reduce diffraction, reduce haze, and make the transparent display clearer. Here, the corner position P1 of signal line L1 is the position where the extension direction of signal line L1 changes.

[0165] Based on the above embodiment, the signal line L1 located at the outermost edge of the display area AA, that is, the signal line L1 closest to the non-display area NAA in the display area, can be an arc to further reduce diffraction, lower haze, and make the transparent display clearer. Among these, Figure 20An example is shown where the signal line L1 closest to the left and right borders of the display area is an arc; the signal lines closest to the top and bottom borders of the display area are also arcs.

[0166] This invention also provides a display device. Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, for reference. Figure 21 The display device 1 provided in this embodiment of the invention includes the display panel 10 provided in any of the above embodiments of the invention. The display device can be... Figure 21 The mobile phone shown can also be a computer, television, smart wearable display device, etc., and the embodiments of the present invention do not make any special limitations on this.

[0167] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes multiple pixel circuits, each pixel circuit comprising a data writing module, a driving module, a compensation module, a coupling module, a storage module, and a light-emitting module; The data writing module is connected to the first voltage input terminal. The data writing module is used to transmit the initial voltage input to the first voltage input terminal to the first terminal of the coupling module during the compensation phase; and to transmit the data voltage input to the first voltage input terminal to the first terminal of the coupling module during the data writing phase. The second end of the coupling module is connected to the control end of the drive module; The storage module is used to store the potential of the control terminal of the drive module; the first terminal of the drive module is connected to the second voltage input terminal; The compensation module is connected between the second end of the drive module and the control end of the drive module; The driving module is used to output a driving current to the light-emitting module through the second terminal of the driving module during the light-emitting stage, based on the first power supply voltage input to the first terminal of the driving module from the second voltage input terminal and the voltage of the control terminal of the driving module. The data writing phase is located between the compensation phase and the light emission phase. The display panel further includes a substrate and a driving circuit layer located on one side of the substrate, wherein the pixel circuit is located in the driving circuit layer; the driving circuit layer includes multiple layers of metal stacked together. The metal layer includes a first patterned structure, wherein at least a portion of the edge of the first patterned structure of one metal layer projected orthogonally onto the substrate is covered by at least a portion of the first patterned structure of another metal layer projected orthogonally onto the substrate. or, The driving circuit layer further includes an insulating layer between adjacent metal layers; the metal layers include a first patterned structure, and the insulating layer includes a second patterned structure; wherein at least a portion of the first patterned structure of one metal layer is orthogonally projected onto the substrate by an orthogonal projection of at least a portion of the second patterned structure of one insulating layer onto the substrate; and / or, wherein at least a portion of the second patterned structure of one insulating layer is orthogonally projected onto the substrate by an orthogonal projection of at least a portion of the first patterned structure of one metal layer onto the substrate; and / or, wherein at least a portion of the second patterned structure of one insulating layer is orthogonally projected onto the substrate by an orthogonal projection of at least a portion of the second patterned structure of another insulating layer onto the substrate.

2. The display panel according to claim 1, characterized in that, It also includes a first voltage selection module, which includes a first input terminal, a second input terminal, a first control terminal, a second control terminal, and a first output terminal. The first output terminal is electrically connected to the first voltage input terminal. The first input terminal is connected to the initial voltage, and the second input terminal is connected to the data voltage. The first voltage selection module is configured to transmit the initial voltage to the first voltage input terminal in response to a first control signal from the first control terminal during the compensation phase; and to transmit the data voltage to the first voltage input terminal in response to a second control signal from the second control terminal during the data writing phase.

3. The display panel according to claim 1, characterized in that, Each of the pixel circuits includes one of the first voltage selection modules; Alternatively, the first voltage selection module is located in the non-display area of ​​the display panel, and the display panel further includes multiple data lines, with the output terminal of the first voltage selection module electrically connected to each of the data lines; each of the data lines is connected to the first voltage input terminal of a column of pixel circuits.

4. The display panel according to claim 3, characterized in that, The non-display area of ​​the display panel includes a set border area, and the first voltage selection module is located in the set border area; the set border area includes a lead-out line from the driver chip to which the data voltage is led out, and the lead-out line is electrically connected to the data line.

5. The display panel according to claim 1, characterized in that, It also includes a reset module, the input terminal of which is electrically connected to the second voltage input terminal, and the output terminal of which is electrically connected to the control terminal of the drive module; the reset module is used to transmit the reset voltage input at the second voltage input terminal to the control terminal of the drive module during the first reset phase; the compensation module is also used to conduct during the first reset phase to transmit the reset voltage transmitted by the reset module to the second terminal of the drive module; The first reset phase is performed before the compensation phase.

6. The display panel according to claim 5, characterized in that, The driving module is also used in the second reset phase to transmit the voltage at the first terminal of the driving module to the second terminal of the driving module; the second reset phase is performed between the compensation phase and the data writing phase.

7. The display panel according to claim 5, characterized in that, It also includes a second voltage selection module, which includes a third input terminal, a fourth input terminal, a third control terminal, a fourth control terminal, and a second output terminal. The second output terminal is electrically connected to the second voltage input terminal. The third input terminal is connected to the reset voltage, and the fourth input terminal is connected to the first power supply voltage. The second voltage selection module is configured to transmit the reset voltage to the second voltage input terminal in response to the third control signal of the third control terminal during the first reset phase; and to transmit the first power supply voltage to the second voltage input terminal in response to the fourth control signal of the fourth control terminal during the light emission phase.

8. The display panel according to claim 7, characterized in that, The second voltage selection module further includes a fifth input terminal and a fifth control terminal, wherein the fifth input terminal is connected to a compensation voltage; the compensation voltage is less than the first power supply voltage; the second voltage selection module is further configured to, during the compensation phase, transmit the compensation voltage to the second voltage input terminal in response to the control signal of the fifth control terminal; or, the second voltage selection module is configured to, during the compensation phase, transmit the first power supply voltage to the second voltage input terminal in response to the fourth control signal of the fourth control terminal.

9. The display panel according to claim 7, characterized in that, Each pixel circuit includes a second voltage selection module; or, the second voltage selection module is disposed in the non-display area of ​​the display panel, the display panel also includes multiple first power lines, the output terminal of the second voltage selection module is electrically connected to the first power lines one by one; each first power line is connected to the second voltage input terminal of a column of pixel circuits.

10. The display panel according to claim 9, characterized in that, The non-display area of ​​the display panel includes a set border area, and the second voltage selection module is located in the set border area; the set border area includes a lead-out line from the driver chip to which the data voltage is led out, and the lead-out line is electrically connected to the data line of the display panel.

11. The display panel according to claim 1, characterized in that, The second end of the driving module is connected to the first end of the light-emitting module, and the second end of the light-emitting module is connected to the third voltage input terminal; the display panel further includes a third voltage selection module, which includes a sixth input terminal, a seventh input terminal, a sixth control terminal, a seventh control terminal, and a third output terminal, and the third output terminal is electrically connected to the third voltage input terminal; the sixth input terminal is connected to a first cathode voltage, and the seventh input terminal is connected to a second cathode voltage; the second cathode voltage is greater than the first cathode voltage; The third voltage selection module is used to transmit the second cathode voltage to the third voltage input terminal in response to the seventh control signal of the seventh control terminal during a phase other than the light emission phase; and is used to transmit the first cathode voltage to the third voltage input terminal in response to the sixth control signal of the sixth control terminal during the light emission phase.

12. The display panel according to claim 11, characterized in that, The driving module is specifically used to transmit the first power supply voltage input at the second voltage input terminal to the second terminal of the driving module during the compensation phase, and the compensation module is specifically used to transmit the voltage at the second terminal of the driving module to the control terminal of the driving module during the compensation phase.

13. The display panel according to claim 11, characterized in that, Each of the pixel circuits includes one of the third voltage selection modules; Alternatively, the third voltage selection module is located in the non-display area of ​​the display panel, and the second ends of the light-emitting modules in each column of pixel circuits in the display panel are interconnected; the display panel also includes a second power supply line, one end of which is electrically connected to the third output terminal, and the other end of which is connected to the third voltage input terminal of at least one column of pixel circuits.

14. The display panel according to claim 13, characterized in that, The non-display area of ​​the display panel includes a set border area, and the third voltage selection module is located in the set border area; the set border area includes a lead-out line from the driver chip to which the data voltage is led out, and the lead-out line is electrically connected to the data line of the display panel.

15. The display panel according to claim 1, characterized in that, The pixel circuit also includes a light-emitting control module, which is disposed between the second end of the driving module and the first end of the light-emitting module. The second end of the light-emitting module is connected to a third voltage input terminal. The light-emitting control module is used to turn on during the light-emitting phase and turn off during other phases according to the signal from its own control terminal.

16. The display panel according to claim 15, characterized in that, The third voltage input terminal transmits the same voltage to the second terminal of the light-emitting module during the light-emitting phase and in phases other than the light-emitting phase.

17. The display panel according to claim 15, characterized in that, The driving module is specifically used to transmit the first power supply voltage input at the second voltage input terminal to the second terminal of the driving module during the compensation phase, and the compensation module is specifically used to transmit the voltage at the second terminal of the driving module to the control terminal of the driving module during the compensation phase.

18. The display panel according to claim 5, characterized in that, The first reset phase of each pixel circuit is performed simultaneously, the compensation phase of each pixel circuit is performed simultaneously, the second reset phase of each pixel circuit is performed simultaneously, the data writing phase of each row of pixel circuits is performed row by row, and the light emission phase of each pixel circuit is performed simultaneously.

19. The display panel according to claim 18, characterized in that, The display panel also includes multiple first gate control lines, second gate control lines, and scan lines; Each row of pixel circuits is connected to a first gate control line, a second gate control line, and a scan line. The first gate control line is connected to the control terminal of the reset module of the corresponding row of pixel circuits, the second gate control line is connected to the control terminal of the compensation module of the corresponding row of pixel circuits, and the scan line is connected to the control terminal of the data writing module of the corresponding row of pixel circuits. The conduction pulse signals on each of the first gate control lines overlap, the conduction pulse signals on each of the second gate control lines overlap, the first conduction pulse signals on each of the scan lines corresponding to the first reset phase and the compensation phase overlap, and the second conduction pulse signals on each of the scan lines corresponding to the data writing phase do not overlap.

20. The display panel according to claim 1, characterized in that, The first end of the storage module is electrically connected to the first end of the drive module, and the second end of the storage module is electrically connected to the first or second end of the coupling module.

21. The display panel according to claim 1, characterized in that, The driving circuit layer includes n stacked metal layers, where n is an integer greater than or equal to 2; wherein at least a portion of the edge of the first patterned structure projected onto the substrate by the orthogonal projection of the first patterned structure onto the substrate by at least a portion of the first patterned structure of the other metal layers is covered by the orthogonal projection of the first patterned structure onto the substrate.

22. The display panel according to claim 21, characterized in that, The first patterned structure includes signal lines and the composition structure of the devices in the pixel circuit.

23. The display panel according to claim 22, characterized in that, At the corner position of the signal line, the signal line is an arc.

24. The display panel according to claim 1, characterized in that, The driving circuit layer includes n layers of the metal layer and m layers of the insulating layer stacked together, where n is an integer greater than or equal to 2 and m is an integer greater than or equal to 1. At least a portion of the first patterned structure of any one of the metal layers is projected onto the substrate by an orthographic projection of at least a portion of the first patterned structure of the other metal layers and / or the second patterned structure of the insulating layer onto the substrate. At least a portion of the second patterned structure of any of the insulating layers in layer (m-1) is orthographically projected onto the substrate by at least a portion of the first patterned structure of the metal layer and / or the second patterned structure of the other insulating layers; Alternatively, the edge of at least a portion of the second patterned structure of any of the insulating layers projected onto the substrate is covered by the orthogonal projection of at least a portion of the second patterned structure of the other insulating layers or the first patterned structure of the metal layer onto the substrate; the orthogonal projection of at least a portion of the first patterned structure of any of the (n-1) metal layers onto the substrate is covered by the orthogonal projection of at least a portion of the first patterned structure of the other metal layers and / or the second patterned structure of the insulating layer onto the substrate.

25. The display panel according to claim 24, characterized in that, The first patterned structure includes signal lines and the composition structure of the devices in the pixel circuit.

26. The display panel according to claim 25, characterized in that, At the corner position of the signal line, the signal line is an arc.

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