Spaceborne high-speed parallel adaptive LDPC encoder

Abstract

The application discloses a satellite-borne high-speed parallel adaptive LDPC encoder, wherein an adaptive parameter setting module calculates various adaptive parameters required by subsequent processing according to an adaptive selection control word and a generation matrix; a high-speed parallel input data format arrangement module arranges input data into a format required by encoding and sends the input data into a high-speed parallel encoding calculation module and an output data format arrangement module in a p bit parallel mode; a generation matrix parameter storage management module is used for storing various generation elements of LDPC code generation matrices of different code rates; the high-speed parallel encoding calculation module multiplies input data and the generation matrix according to the adaptive parameters to obtain check bits of the LDPC code; and the output data format arrangement module splices the calculated check bits behind the parallel input data bits and outputs the check bits in a p bit parallel mode. The application breaks through two technologies of adaptive code stream compatible design and high-speed parallel processing and realizes real-time processing of 29 kinds of codes of 6.4 Gbps high-speed data.

Description

Technical Field

[0001] This invention belongs to the field of high-speed data transmission and processing technology, and relates to a spaceborne high-speed parallel adaptive LDPC encoder. Background Technology

[0002] Channel coding is a key technology for improving the reliability of satellite communication data transmission links, and low-density parity-check (LDPC) codes are currently the best performing channel coding methods. In practical satellite communications, the communication environment varies greatly at different times and locations due to factors such as terrain, buildings, and weather. To improve satellite channel utilization, various channel codes with different performance levels and code rates should be used to protect the signal to varying degrees. Furthermore, with the rapid development of satellite remote sensing technology, encoders must perform real-time error correction processing on massive amounts of data from various payloads; traditional serial LDPC coding methods can no longer meet the demands of high-speed processing.

[0003] CCSDS 131.1-O-2 recommends two types of LDPC codes: one is a single code rate 7 / 8 LDPC (8176, 7156) code for low Earth orbit satellite communication. The second is a series of LDPC codes with multiple code rates (1 / 2, 2 / 3, 3 / 4, 4 / 5) recommended for deep space communication systems, with 7 different code lengths across the 4 code rates, resulting in a total of 28 code types. In specific space missions, users select the most suitable LDPC code based on the severity of the mission environment and their requirements, considering factors such as code performance (including error leveling), encoding and decoding complexity (including the number of decoding iterations to achieve the required performance), compatibility with different code rates, and the maturity of hardware implementation and support.

[0004] 1) Characteristics of CCSDS standard low Earth orbit satellite 7 / 8 code rate LDPC:

[0005] The parity check matrix of the CCSDS standard 7 / 8 bitrate LDPC (8176, 7154) is composed of 2×16 511×511 cyclic matrices. The size of the parity check matrix is ​​1022×8176, as shown in equation (1):

[0006]

[0007] A i1,j1 (i1 = 1, 2; j1 = 1, 2, ..., 16) is a 511 × 511 cyclic matrix, A i1,j1 Each row and column of the matrix has two non-zero elements, meaning the row weight is 2. The parity check matrix consists of 2 × 16 circular matrices, so the row weight of the parity check matrix is ​​2 × 16 = 32, and the column weight is 2 × 2 = 4.

[0008] After a series of complex calculations, the generating matrix G with quasi-cyclic properties can be calculated. qc The format is as follows:

[0009]

[0010] Among them, B i,j (i = 1 to 14, j = 1, 2) is a 511*511 dimensional cyclic matrix, i.e., cyclic matrix B. i,j The data from the second to the last row is rotated one position to the right of the data in the previous row:

[0011]

[0012] Since 511*511 is not an integer multiple of the 16-bit width required for parallel implementation, in order to achieve high-speed parallelism, it is necessary to reduce the bit width of B. i,j Expanded to an extended matrix B' of 512*511 ij For details on the extended method, please refer to the patent "An LDPC Encoding Method Based on Bit Padded".

[0013]

[0014] The extended matrix B' i,j (i = 1 to 14, j = 1, 2) form a new 7168*1022 dimensional matrix P':

[0015]

[0016] (2) Characteristics of multi-rate LDPC in deep space communication under the CCSDS standard:

[0017] The LDPC codes used in the CCSDS standard for deep space communication are all quasi-cyclic LDPC codes, with four code rates: 1 / 2, 2 / 3, 3 / 4, and 4 / 5. The parity-check matrix for each code rate has the following form:

[0018]

[0019]

[0020]

[0021]

[0022] Where I M It is an M×M identity matrix, 0 M It is an M×M zero matrix, Π1~Π 26 It is an interwoven sparse matrix. Each Π k′(k′∈[1,26]) includes 16 cyclic matrices of size m=M / 4, which allows the calculation of the parity check matrix H for each code rate. M takes seven different values: 128, 256, 512, 1024, 2048, 4096, and 8192, corresponding to cyclic matrix sizes m of 32, 64, 128, 256, 512, 1024, and 2048. When M is different, the code parameters and code lengths for the same code rate are different, resulting in seven different codes for each code rate. This series of codes involves a total of 28 codes.

[0023] The generator matrices of the 28 LDPC codes with four code rates applicable to deep space communication in the CCSDS standard can be calculated through a series of complex calculations to obtain a generator matrix with compatibility characteristics. For details on the compatibility calculation, please refer to "Research on Spaceborne LDPC Code Compatibility Technology". The form of the generator matrix G is shown below:

[0024]

[0025] Where g i,j The generator matrix is ​​an m×m cyclic matrix with 12 columns used to calculate the parity bits. However, the standard recommends this series of codes in the form of a pruned code. During encoding, it is not necessary to calculate the pruned 4m parity bits. The part of the generator matrix of this series of codes that is actually used to calculate the parity bits is only 8 columns of cyclic matrix.

[0026] (3) Commonly used coding types for satellite channels

[0027] Currently, the three most commonly used coding schemes for satellite channels are 7 / 8 code rate LDPC (8176, 7156), 4 / 5 code rate LDPC (5120, 4096), and 1 / 2 code rate LDPC (8192, 4096). These are all among the 29 coding schemes recommended in the CCSDS standard 131.1-O-2. They are designed independently and the code rate cannot be switched according to the actual channel conditions. The 7 / 8 code rate LDPC (8176, 7156) has a high-speed parallel implementation scheme, while the other two are single-bit serial implementation methods.

[0028] Therefore, it is essential to develop a rate-adaptive high-speed parallel LDPC encoder. Summary of the Invention

[0029] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a spaceborne high-speed parallel adaptive LDPC encoder, which realizes high-speed parallel real-time processing of 29 LDPC codes recommended by the CSSDS standard, solves the problem of error correction for massive data transmission in the past 10 years, and meets the coding requirements of satellites for different performance channels in the next 10 years.

[0030] The solution of the present invention is:

[0031] A spaceborne high-speed parallel adaptive LDPC encoder includes an adaptive parameter setting module, a high-speed parallel input data format processing module, a generator matrix parameter storage and management module, a high-speed parallel encoding calculation module, and an output data format processing module.

[0032] Adaptive parameter setting module: Calculates various adaptive parameters required for subsequent processing based on the adaptive selection control word and generator matrix, and outputs them to the high-speed parallel encoding calculation module, generator matrix parameter storage and management module, and high-speed parallel input data format processing module;

[0033] High-speed parallel input data formatting module: Based on adaptive parameters, the input data is grouped and formatted into the format required for encoding, and sent to the high-speed parallel encoding calculation module and the output data formatting module in p-bit parallel mode; where p = 2, 4, 8, 16 or 32;

[0034] Generator matrix parameter storage management module: used to store the generator elements of LDPC code generation matrices with different code rates according to the adaptive parameters;

[0035] High-speed parallel encoding calculation module: Based on the adaptive parameters, it reads the generator elements of the corresponding generator matrix from the generator matrix parameter storage and management module, multiplies the input data and the generator matrix to obtain the check bits of the LDPC code, and outputs them to the output data format processing module.

[0036] Output data formatting module: The calculated check bits are concatenated into the parallel input data bits in p-bit parallel manner and output.

[0037] Preferably, the adaptive parameters include address start position parameters, calculation parameters, group length, number of parameter calculation groups, and number of groups.

[0038] Preferably, the high-speed parallel input data format processing module groups and organizes the input data into the format required for encoding. When 7 / 8 bit rate LDPC encoding is selected, the input data needs to be grouped and filled in units of 511 bits, with one 0 bit filled in every 511 information bits, becoming 512 bits, and then sent to the encoding calculation module in p-bit parallel mode. When other 28 codes are selected, no expansion processing is required. The data is directly grouped according to different values ​​of M and different bit rates and then sent to the high-speed parallel encoding calculation module in p-bit parallel mode.

[0039] Preferably, the generator matrix parameter storage management module uses eight 32-bit ROMs. The first two ROMs store the generator elements in columns 1 and 2 of the generator matrix G, which is adapted to 28 codes at 4 code rates for deep space communication systems, and the generator matrix G, which is adapted to 7 / 8 code rate LDPC for near-Earth communication. qcThe extended generators in the ROM are stored in the ROM, and the remaining 6 ROMs store the generators in columns 3 to 8 of the 28 code generation matrices G.

[0040] Preferably, the address depth of the first two ROMs is 4288, and the address depth of the remaining ROMs is 4064.

[0041] Preferably, the high-speed parallel encoding computation module adopts a p-bit high-speed parallel encoding method to parallelize the encoding process, i.e., C' p×y =K' p×z G k×n Where y = n ÷ p, z = k ÷ p, and C' p×y K' is the codeword after high-speed parallel encoding. p×z For information bits, G k×n The generator matrix is ​​defined by k, where k is the length of the information bits and n is the length of the encoded codeword.

[0042] Preferably, the generating matrix G is... k×n G is uniformly represented as a quasi-circular matrix qc The format is as follows:

[0043]

[0044] Where parameters t and g represent the number of parameter calculation groups and the number of groups, respectively, P i,j (1≤i≤t,1≤j≤g) is a circular subarray of size b×b, where b is the block length, the codeword length n=(t+g)×b, k is the information bit length, k=t×b, y=(t+g)×b÷p, z=t×b÷p;

[0045] P i,j The characteristics are as follows: the first row is the generator element of the generator matrix read from the generator matrix parameter storage and management module, and each of the remaining rows is the previous row rotated right by 1 bit;

[0046] Preferably, the k-bit input data grouped by the high-speed parallel input data format sorting module is input into the high-speed parallel encoding calculation module in p-bit parallel input mode to generate g×b-bit check bits;

[0047] The LDPC encoder uses g cyclic shift register groups B1, B2…B g and g registers a1, a2...a g Store data;

[0048] Each circular shift register group performs parallel computation using p circular shift registers, with its length set to the maximum value of 2048 bits for 29 different codes. Circular shift register group B j The data stored in the p circular shift registers are respectively labeled as follows: g registers a1, a2...a g Each of the shift registers has a length of 2048 bits, which is the maximum value of 29 codes; register a j The data stored in is identified as follows:

[0049] Preferably, the high-speed parallel encoding computation module performs parallel multiplication of the input data and the generator matrix to obtain the check bits of the LDPC code, as follows:

[0050] (1) During the first clock cycle, p bits of information [c1, c2, ..., c] are input in parallel. p ], using circular shift register group B j The p circular shift registers in the memory store the generator elements of the generator matrix read from the ROM, and the cyclic right bits 1, 2, 3...p-1 bits of the generator elements, i.e., the generator matrix P. 1,j Lines 1 to p; and registers a1, a2...a g The stored data in the matrix is ​​initialized to zero, and the generating matrix P 1,j The size is b×b;

[0051] (2) The p bits of information input in parallel are respectively coupled to the circular shift register group B. j The stored data are multiplied and accumulated and stored in register a. j : where register a j The l-th bit stores the data as It is a positive integer; For the previous clock cycle register a j The l-th bit stores the data, register a j The l-th bit is initially stored as 0;

[0052] (3) During the second clock cycle, the second group of p-bit information bits are input in parallel again: [c p+1 c p+2 c p×2 ]; and the circular shift register group B j The p circular shift registers in the array are each shifted p bits to the right in units of b, i.e., B j The p circular shift registers in the matrix P store the generator matrix P. 1,j Update lines p+1 to p×2. The value of ;

[0053] (4) The p bits of information input in parallel in step (3) are respectively coupled with the circular shift register group B. jThe stored data is multiplied and accumulated, and the accumulated result is compared with register a. j After adding the stored data, update register a. j The data stored in register a j The l-th bit stores the data as It is a positive integer; For the previous clock cycle register The l-th bit stores the data;

[0054] (5) And so on, after the b / p-th clock cycle, register a j The data vector stored in is [c1, c2, c3, ..., c b ]P 1,j ;

[0055] (6) During the b / p+1th clock cycle, input p bits of information in parallel [c b+1 c b+2 c b+p ]; using the circular shift register group B j The p circular shift registers in the matrix P store the generator matrix P respectively. 2,j Line 1 to line p;

[0056] (7) And so on, after the t×b / p-th clock cycle, where t is the number of groups, register a j The data stored in is Where: K w This represents the b-th information bit in the w-th group of input, where w = 1, 2, ..., t, and is a positive integer.

[0057] (8) After the calculation is completed, the b bit data stored in register a1 is connected to the b bit data stored in register a2, and so on. g The data is processed to obtain g×b bit parity bits.

[0058] Preferred, K w =[c (w-1)*b+1 ,c (w-1)*b+2 ,…,c wb ].

[0059] The advantages of this invention compared to the prior art are:

[0060] This invention designs and implements adaptive parallel coding for 29 types of LDPC codes with different code rates and code lengths, as recommended in the CCSDS standard 131.1-O-2. This adaptive encoder is compatible with the 7 / 8, 4 / 5, and 1 / 2 code rates (one of which) commonly used in current high-speed spaceborne data transmission, and further expands to meet the future needs of 2 / 3 and 3 / 4 code rate LDPC codes for deep space exploration. It focuses on breakthroughs in two key technologies: adaptive code stream compatibility design and high-speed parallel processing, achieving real-time processing of 6.4Gbps high-speed data from the 29 codes. Attached Figure Description

[0061] Figure 1 This is the interface diagram of the adaptive high-speed parallel encoder of the present invention;

[0062] Figure 2 This is a block diagram of the adaptive high-speed parallel encoder structure of the present invention;

[0063] Figure 3 This is a flowchart of the front-end input data processing in this invention;

[0064] Figure 4 This is a diagram of the encoder generation matrix storage structure of the present invention;

[0065] Figure 5 This is a space management diagram of the encoder generation matrix storage ROM of the present invention;

[0066] Figure 6 This is a block diagram of the SRAA circuit implemented by the high-speed parallel LDPC of the present invention;

[0067] Figure 7 This is a flowchart of the encoder output data processing of the present invention. Detailed Implementation

[0068] The present invention will be further described below with reference to the embodiments.

[0069] To address the current situation, this invention designs and implements adaptive parallel coding for 29 types of LDPC codes with different bit rates and bit lengths, as recommended in the CCSDS standard 131.1-O-2. This adaptive encoder is compatible with the commonly used 7 / 8, 4 / 5, and 1 / 2 bit rates (one of which) in current high-speed spaceborne data transmission, and further expands to meet the future needs of 2 / 3 and 3 / 4 bit rate LDPC codes for deep space exploration. It focuses on breakthroughs in two key technologies: adaptive bitstream compatibility design and high-speed parallel processing, achieving real-time processing of 6.4Gbps high-speed data from the 29 codes.

[0070] This invention can be applied to parallel bits of 2, 4, 8, 16, or 32 bits. The following explanation uses 16 bits as an example.

[0071] The adaptive high-speed parallel encoder has 1 bit clock signal, 1 bit reset signal, 1 bit type selection signal, 2 bit code rate selection signal, 3 bit code length selection signal, 1 bit accompanying gating signal, and 2 channels of 16-bit I and Q signals.

[0072] See the top-level interface diagram. Figure 1 As shown, the interface signal descriptions are detailed in Table 1:

[0073] Table 1 Interface Signal Description Table

[0074] Serial Number Signal name Bit width illustrate 1 Clkin 1 bit The encoder's operating clock can be input from 10MHz to 250MHz according to the speed requirements. 2 Reset 1 bit Global reset signal: high level resets, low level enables normal operation. 3 type_flag 1 bit Two types of encoding identifiers, 1 for low Earth orbit with a code rate of 7 / 8, and 0 for deep space communication with 28 different codes. 4 Rate_flag 2bit Valid when type_flag = 0: 00 (1 / 2 bitrate), 01 (2 / 3), 10 (3 / 4), 11 (4 / 5) 5 Code_flag 3bit Valid when type_flag = 0: 3 bits represent 7 different lengths of M. 6 Synin 1 bit Input data gating indicator signal, active high; 7 Idatin 16bit Channel I high-speed 16-bit parallel input data (to be encoded); 8 Qdatin 16bit Q-channel high-speed 16-bit parallel input data (to be encoded); 9 Synou 1 bit The encoded output data gating signal is active high. 10 Idatout 16bit Channel I high-speed 16-bit output data (already encoded); 11 Qdatout 16bit Q-channel high-speed 16-bit parallel output data (already encoded);

[0075] The correspondence between the control signals in the top-level interface of the adaptive high-speed parallel encoder and the 29 different performance codes is shown in Table 2 (the three code types highlighted in bold black are now used as independent code types in the current model):

[0076] Table 2. Correspondence between parameter settings and code types

[0077]

[0078] The block diagram of the adaptive high-speed parallel encoder is as follows: Figure 2 As shown, it mainly consists of five parts: an adaptive parameter setting module, a high-speed parallel input data format processing module, a generator matrix parameter storage and management module, a high-speed parallel encoding calculation module, and an output data format processing module.

[0079] Adaptive parameter setting module: Based on three adaptive selection control words (type_flag, rate_flag, and code_flag), it calculates various adaptive parameters required for subsequent processing according to the specific generator matrix design. These parameters include address start position parameters, calculation parameters, block length information parameters, etc., and are used to achieve adaptive switching between storage and calculation functions. The correspondence of each parameter is shown in the table below:

[0080] Table 3 Adaptive Parameter Setting Table

[0081]

[0082] The high-speed parallel input data formatting module groups and organizes the input data into the format required for encoding. When selecting 7 / 8 bitrate LDPC encoding, the input data needs to be grouped and padded in 511-bit units, with one 0 bit added to every 511 information bits, resulting in 512 bits. This data is then fed into the encoding calculation module in a 16-bit parallel manner. When selecting one of the other 28 code types, since their cyclic matrices are all multiples of 16 bits, no expansion processing is needed. The data is directly grouped according to different values ​​of M and different bitrates, and then fed into the encoding calculation module in a 16-bit parallel manner. The processing flowchart is as follows: Figure 3 As shown.

[0083] Generate matrix parameter storage management module: As shown in formula (3), in the quasi-cyclic generator matrix with a 7 / 8 bit rate, there are 14×2 cyclic subarrays involved in the encoding calculation. According to its quasi-cyclic structure, it is only necessary to store the first row (generator) of each subarray to obtain all the information. Therefore, it is necessary to store 28 generator matrix parameters of size 511, and the storage resources occupied can be calculated to be 28*511=14308bit.

[0084] As shown in formula (10), the CCSDS standard uses 28 LDPC codes with 4 code rates suitable for deep space communication. The storage resources for the generator matrix are no longer simply added together; storage resources can be reused for different code rates with the same M, saving significant resources for compatible designs. In formula (10), g... i,j The generator matrix is ​​an m×m cyclic matrix with 12 large columns used for calculating the parity bits. However, the standard recommends this series of codes in pruned form. During encoding, it is unnecessary to calculate the remaining 4m parity bits. The portion of the generator matrix actually used for calculating the parity bits is only 8 large columns of cyclic matrices. m has 7 different values. The total storage space occupied by the 28 deep space communication codes is:

[0085] 8*32*(32+64+128+256+512+1024+2048)=1040384bit.

[0086] The generation matrices for the 29 codes occupy a total of 14308 + 1040384 = 1054692 bits of storage space. From the above generation matrices, it can be seen that the generation matrix for the 7 / 8 code rate in low Earth orbit consists of 14*2 cyclic subarrays, while the generation matrix for the 28 codes in deep space communication consists of 32*8 cyclic subarrays. To maximize design compatibility while facilitating high-speed parallel encoding calculations, this encoder uses eight 32-bit ROMs. The first two ROMs store the generator elements g of the first and second large sub-cyclic arrays in the generation matrix (10). i,j (1≤i≤32,j=1、2), in addition to the generators B' of the two large sub-cyclic matrices in the extended generating matrix (3), i,j(i = 1~14, j = 1, 2). The remaining 6 ROMs store the generator elements in columns 3~8 of the generator matrix (10). The generator matrix storage structure is as follows: Figure 4 As shown.

[0087] In g i,j In the subarray, M takes 7 different values, and each g i,j There are also 7 different values, with lengths of 32, 64, 128, 256, 512, 1024, and 2048 respectively, which can be denoted as... Since the generator matrix for 4 / 5 bitrate has 32 rows of circular matrices, each ROM needs to store 32 of them. 32 32 32 32 32 indivual Each Occupies 1 address Occupies 2 addresses It occupies 4 addresses. Occupies 8 addresses Occupies 16 addresses. Occupying 32 addresses, It occupies 64 addresses. Each ROM stores the generator matrix of 28 deep space communication codes, with an address depth of 32 + 32 × 2 + 32 × 4 + 32 × 8 + 32 × 16 + 32 × 32 + 32 × 64 = 4064.

[0088] In the near-ground 7 / 8 code rate generator matrix, B' i,j There is only one length of 511, but for ease of storage, it is stored as 512, with each occupying B'. i,j Occupying 16 addresses, the generated matrix has 14 rows of cyclic subarrays, so each ROM needs to store 14 bytes. i,j The total address space occupied is 14 × 16 = 224.

[0089] As shown above, the address depth of the first two ROMs is 4288, and the address depth of the remaining ROMs is 4064. For ROM address space management, see [link to documentation]. Figure 5 As shown.

[0090] High-speed parallel encoding computation module: LDPC is a linear block code. Its most basic encoding method is implemented using a single-bit serial approach. The encoding process can be represented as the following matrix multiplication: C 1×n =K 1×k G k×n C 1×n K is the codeword after LDPC encoding. 1×k For information bits, Gk×n To generate the matrix, this invention uses 16-bit high-speed parallel encoding as an example, and parallelizes this process, which can be improved to C'. 16×y =K' 16×z G k×n Where y = n ÷ 16 and z = k ÷ 16, the generator matrix G of the 29 codes can be obtained. k×n Represented as a cyclic subarray G qc as follows:

[0091]

[0092] Where parameters t and g are the number of parameter calculation groups and the number of groups calculated in the adaptive settings, respectively, P i,j (1≤i≤t, 1≤j≤g) is a cyclic matrix of size b×b (where b is the group length parameter, k=t×b, n=(t+g)×b), characterized by: the first row being the generator element of the generator matrix read from the storage matrix, and each subsequent row being the cyclic right shift of the previous row by 1 bit. 16 bits of information participate in the encoding calculation simultaneously, achieving a throughput of 6.4Gbps. When reading from the ROM, the number of groups is calculated according to the adaptive parameter, which has two possible values: 2 or 8. When it is 2, only the first two calculation units (group B1, group B2) placed into the SRAA calculation circuit are read simultaneously from the first two ROMs; when it is 8, all eight calculation units (groups B1~B8) placed into the SRAA calculation circuit are read simultaneously from eight ROMs.

[0093] The k-bit information bits, after being expanded and grouped, are input in 16-bit parallel mode and multiplied by the cyclic matrix P to generate g×b-bit check bits. In the QC LDPC encoder, g cyclic shift register groups B1, B2…B are used. g and g registers a1, a2...a g Stores data. Among them, the circular shift register groups B1, B2…B g Each circular shift register group comprises 16 circular shift registers for parallel computation. Considering compatibility, its length is set to the maximum value of 2048 bits for 29 different codes. The data stored in the 16 circular shift registers in circular shift register group B1 are respectively labeled as follows: The data stored in the 16 circular shift registers in circular shift register group B2 are labeled as follows: And so on, register set B g The data stored in the 16 circular shift registers are labeled as follows: g registers a1, a2...a gThe length of each shift register is also the maximum value of 2048 bits for 29 cyclic matrices; the data stored in register a1 is identified as follows: The data stored in register a2 is identified as follows: When encoding different codes, the actual length of each register used is the group length parameter b (<=2048) bits, and the remaining positions can be left unused. The specific SRAA circuit block diagram is as follows: Figure 6 As shown.

[0094] The specific implementation steps are as follows:

[0095] (1) During the first clock cycle, 16 bits of information are input in parallel: [c1, c2, ..., c 16 The 16 circular shift registers in the aforementioned circular shift register group B1 store the circular matrix generator elements read from the generator matrix ROM, as well as the 1st, 2nd, 3rd...15th bits of the right circular shift of the generator elements, which is equivalent to the serial generator matrix P. 1,1 Rows 1 to 16 of (size b×b); the 16 circular shift registers in the above circular shift register group B2 store the generator matrix P respectively. 1,2 Lines 1 through 16, and so on, Circular shift register group B g The 16 circular shift registers in the array store the serial generator matrix P. 1,g Lines 1 to 16. And registers a1, a2…a g The stored data is initialized to zero, that is... Where l = 1 to b, i = 1 to g are positive integers;

[0096] (2) After formatting the input, the 16 bits of parallel input are multiplied by the data stored in the circular shift register group B1 and accumulated into register a1: where the l-th bit of register a1 stores the data as follows. It is a positive integer;

[0097] Simultaneously, the 16-bit information bits input in parallel are respectively connected to the circular shift register groups B2 to B1. g The data stored in the middle are multiplied and accumulated and stored in registers a2 to a3. g Then the data stored in the l-th bit of register a2 is And so on, register a g The l-th bit stores the data as It is a positive integer;

[0098] (3) During the second clock cycle, another 16 bits of information are input in parallel: [c 16+1 c 16+2 c16×2 The generator matrix P is then shifted 16 bits to the right in each of the 16 circular shift registers in group B1, meaning that each of the 16 circular shift registers in B1 stores a generator matrix P. 1,1 Update lines 16+1 to 16×2. The value of ;

[0099] At the same time, other circular shift register groups B2 to B... g The 16 circular shift registers in the array are each shifted 16 bits to the right in units of bits (b). Circular shift register groups B2 to B3 are... g The 16 circular shift registers in the matrix P store the extended matrix P. 1,2 ~P 1,g Update lines 16+1 to 2×16. The value of ;

[0100] (4) Multiply and accumulate the 16-bit information bits input in parallel in step (3) with the stored data in the circular shift register group B1. Add the accumulated result to the stored data in register a1 (the result of the previous calculation) and update the stored data in register a1. The l-th bit of register a1 stores the following data: ((l = 1, 2, ..., b are positive integers);

[0101] Simultaneously, the 16-bit information bits input in parallel in step (3) are respectively coupled with the circular shift register groups B2 to B1. g The stored data are multiplied and accumulated, and the accumulated result is compared with registers a2 to a2. g After adding the stored data, update registers a2 to a3. g The data stored in register a2 is: The l-th bit of register a2 stores the data as follows: And so on, register a g The l-th bit stores the data as (l = 1, 2, ..., b are positive integers).

[0102] (5) Following this pattern, after the b / 16th clock cycle, the data vector stored in register a1 is [c1, c2, c3, ..., c b ]P 1,1 The data vector stored in register a2 is [c1, c2, c3, ..., c b ]P 1,2 Similarly, register a g The data vector stored in is [c1, c2, c3, ..., c b ]P 1,g ;

[0103] (6) During the b / 16+1 clock cycle, input 16 bits of information in parallel: [c b+1 c b+2 c b+16 The 16 circular shift registers in the circular shift register group B1 are used to store the generation matrix P. 2,1 Rows 1 to 16, the 16 circular shift registers in the circular shift register group B2 respectively store the generator matrix P 2,2 Lines 1 through 16, and so on, Circular shift register group B g The 16 circular shift registers in the matrix P store the generator matrix P. 2,g Lines 1 to 16.

[0104] Following the calculation process in steps (1) to (5), after the 2b / 16th clock cycle, the data stored in register a1 is [c1, c2, c3, ..., c b ]P 1,1 +[c b+1 c b+2 c b+3 c 2b ]P 2,1 The data stored in register a2 is: [c1, c2, c3, ..., c b ]P 1,2 +[c b+1 c b+2 c b+3 c 2b ]P 2,2 Register a g The data stored in is: [c1, c2, c3, ..., c b ]P 1,g +[c b+1 c b+2 c b+3 c 2b ]P 2,g .

[0105] (7) And so on, after the t×b / 16th clock cycle (t is an adaptive parameter for the number of groups), the data stored in register a1 is The data stored in register a2 is And so on, register a g The data stored in is Where: K w =[c (w-1)*b+1 ,c (w-1)*b+2 ,…,c wb ], w = 1 to t are positive integers;

[0106] (8) After the calculation is completed, the b bit data stored in register a1 is connected to the b bit data stored in register a2, and so on. g The data is processed to obtain g×b bit parity bits.

[0107] Output data format processing module: The calculated g×b bit parity bits are concatenated in 16-bit parallel mode after the t×b bit parallel input information bits. If the selected encoding type is 7 / 8 low Earth orbit code, padding bit removal is also required. The flowchart of this part is as follows. Figure 7 As shown.

[0108] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A spaceborne high-speed parallel adaptive LDPC encoder, characterized in that: It includes an adaptive parameter setting module, a high-speed parallel input data format processing module, a generator matrix parameter storage and management module, a high-speed parallel encoding calculation module, and an output data format processing module; Adaptive parameter setting module: Calculates various adaptive parameters required for subsequent processing based on the adaptive selection control word and generator matrix, and outputs them to the high-speed parallel encoding calculation module, generator matrix parameter storage and management module, and high-speed parallel input data format processing module; High-speed parallel input data formatting module: Based on adaptive parameters, it groups and formats the input data into the required encoding format. p The data is fed into the high-speed parallel encoding and calculation module and the output data format processing module in a bit-parallel manner; in p =2, 4, 8, 16 or 32; Generator matrix parameter storage management module: used to store the generator elements of LDPC code generation matrices with different code rates according to the adaptive parameters; High-speed parallel encoding calculation module: Based on the adaptive parameters, it reads the generator elements of the corresponding generator matrix from the generator matrix parameter storage and management module, multiplies the input data and the generator matrix to obtain the check bits of the LDPC code, and outputs them to the output data format processing module. Output data formatting module: Converts the calculated check digits into... p The data is concatenated after the parallel input data bits in a bit-parallel manner and output. The generating matrix consists of several b×b cyclic submatrices. Composition, cyclic subarray The characteristics are as follows: the first row contains the generator elements of the generator matrix read from the generator matrix parameter storage and management module, and each subsequent row is the previous row circularly shifted right by 1 bit; the LDPC encoder uses g circular shift register groups B1, B2…B g and g registers a1, a2...a g Data storage, circular shift register group Register a is used for parallel storage of multiple rows of data in a circular subarray. j Used for cumulative calculation to obtain the check digit. , t, g To calculate the number of groups and the number of groups.

2. The spaceborne high-speed parallel adaptive LDPC encoder according to claim 1, characterized in that: The adaptive parameters include address start position parameters, calculation parameters, group length, number of parameter calculation groups, and number of groups.

3. The spaceborne high-speed parallel adaptive LDPC encoder according to claim 1, characterized in that: The high-speed parallel input data formatting module groups and organizes the input data into the format required for encoding. When selecting 7 / 8 bit rate LDPC encoding, the input data needs to be grouped and padded in 511-bit units, with one 0 bit padded for every 511 information bits, resulting in 512 bits. p The data is fed into the encoding calculation module in a bit-parallel manner; when selecting one of the other 28 codes, no expansion processing is needed, and the codes are directly grouped according to different values ​​of M and different code rates. p The data is fed into the high-speed parallel encoding and computation module in a bit-parallel manner.

4. The spaceborne high-speed parallel adaptive LDPC encoder according to claim 1, characterized in that: The generator matrix parameter storage management module uses eight 32-bit ROMs. The first two ROMs store the generator elements in columns 1 and 2 of the generator matrix G, which is suitable for 28 codes at four code rates in deep space communication systems, as well as the generator matrix suitable for LDPC at 7 / 8 code rates in near-Earth communication. The extended generators in the ROM are stored in the ROM, and the remaining 6 ROMs store the generators in columns 3 to 8 of the 28 code generation matrices G.

5. A spaceborne high-speed parallel adaptive LDPC encoder according to claim 4, characterized in that: The address depth of the first two ROMs is 4288, and the address depth of the remaining ROMs is 4064.

6. A spaceborne high-speed parallel adaptive LDPC encoder according to claim 2, characterized in that: The high-speed parallel encoding calculation module adopts p The high-speed parallel encoding method of bit encoding processes the encoding process in parallel, that is... ,in , ,in This refers to the codewords after high-speed parallel encoding. For information bits, The generator matrix is ​​defined by k, where k is the information bit length and n is the encoded codeword length.

7. A spaceborne high-speed parallel adaptive LDPC encoder according to claim 6, characterized in that: Generate matrix Unified representation as a quasi-circular matrix The format is as follows: Codeword length , , , .

8. A spaceborne high-speed parallel adaptive LDPC encoder according to claim 7, characterized in that: The high-speed parallel input data formatting module groups the k-bit input data into... p The high-speed parallel encoding and calculation module is input in a bit-parallel mode to generate g×b bit parity bits; Each circular shift register group passes through p Each circular shift register performs parallel computation, with its length set to the maximum value of 2048 bits for 29 different codes. The circular shift register group... In p The data stored in each circular shift register are labeled as follows: [ ]、[ ]、…、[ ]; g registers a1, a2…a g Each of the shift registers has a length of 2048 bits, which is the maximum value of 29 codes; registers The data stored in is identified as: [ ], .

9. A spaceborne high-speed parallel adaptive LDPC encoder according to claim 8, characterized in that: The high-speed parallel encoding computation module performs parallel multiplication of the input data and the generator matrix to obtain the check bits of the LDPC code, as follows: (1) During the first clock cycle, parallel input p bit information bits[ ], using a circular shift register set In p Each circular shift register stores the generator element of the generator matrix read from ROM, as well as the cyclic right bits 1, 2, 3... of the generator element. p- 1 bit, i.e., the generator matrix The first row to the second row p Line; and set registers a1, a2...a g The stored data in the matrix is ​​initialized to zero, and the generated matrix... Size is b×b ; (2) Parallel input p The bit information bits are respectively connected to the circular shift register group The stored data are multiplied and accumulated into a register. : where register The The data is stored in bits. , , where is a positive integer; For the previous clock cycle register The Bits store data, registers The The initial data stored is 0; (3) During the second clock cycle, input the second group in parallel again. p bit information bits: [ ]; and the circular shift register group In p Each circular shift register is shifted to the right in units of bits (b). p Position, that is In p Each of the circular shift registers stores the generator matrix. The p +1 line ~ the p ×2 lines, update , , The possible values ​​of ; (4) Input the parallel data from step (3) p The bit information bits are respectively connected to the circular shift register group The stored data is multiplied and accumulated, and the accumulated result is compared with the register. Update the register after adding the stored data. The data stored in the register The The data is stored in bits. , It is a positive integer; (5) And so on, the b / p After one clock cycle, the register The data vector stored in is ; (6) the b / p Parallel input at +1 clock cycle p bit information bits[ ]; using the circular shift register set In p Each of the circular shift registers stores the generator matrix. The first row to the second row p OK; (7) And so on, the t×b / p After one clock cycle, t is the number of groups, register The data stored in is ,in: This represents the b-th information bit in the w-th group of input. , where is a positive integer; (8) After the calculation is completed, the b bit data stored in register a1 is connected to the b bit data stored in register a2, and so on. g The data is processed to obtain g×b bit parity bits.

10. A spaceborne high-speed parallel adaptive LDPC encoder according to claim 9, characterized in that: 。

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