Lockstep comparator and related methods

Abstract

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry (322) having first outputs, and comparator logic (300) including selection logic (304) having first inputs and second outputs, individual ones of the first inputs coupled to the first outputs, first detection logic (306) having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic (308) having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic (310) having fifth inputs and fifth outputs, the third outputs and the fourth outputs coupled to the fifth inputs, and error detection logic (312) having sixth inputs coupled to the fifth inputs.

Description

[0001] This article generally deals with circuits, and more specifically with lockstep comparators and related methods. Background Technology

[0002] Safety protocols are used to ensure the safety of electrical and / or electronic systems. For example, the International Organization for Standardization (ISO) 26262 is an international standard concerning the functional safety of electrical and / or electronic systems in automobiles. Such safety protocols analyze the risks associated with electronic failures (e.g., a combination of the frequency and severity of injury). Failures corresponding to electronic equipment can be random or systematic. Random failures may correspond to hardware-related permanent or transient failures due to the loss of function of system components. Systematic failures may correspond to design flaws in software, incorrect specifications, and / or non-compliance with purpose. Such safety protocols can analyze the electrical risks associated with hardware processors that may handle signals to improve vehicle safety. Attached Figure Description

[0003] Figure 1 This is an illustration of an example system-on-chip (SoC) including an example lockstep comparator circuit system used to improve the reliability and security associated with the example hardware processor of the SoC.

[0004] Figure 2 yes Figure 1 A block diagram of an example implementation of an example hardware processor, the hardware processor including Figure 1 Example of a lockstep comparator circuit system.

[0005] Figure 3 yes Figure 1 and / or Figure 2 A schematic illustration of an example implementation of an example lockstep comparator circuit system.

[0006] Figures 4A to 4B yes Figure 1 and / or Figure 2 A schematic illustration of another example implementation of the example lockstep comparator circuit system.

[0007] Figure 5 It describes Figure 1 , Figure 2 , Figure 3 and / or Figures 4A to 4B The timing diagram shows an example operation of an example lockstep comparator circuit system.

[0008] Figure 6 This is a flowchart illustrating an example process that can be implemented using executable machine-readable instructions and / or using methods configured to... Figure 1 , Figure 2, Figure 3 and / or Figures 4A to 4B The example lockstep comparator circuit system is implemented in hardware to detect errors associated with one or more comparators.

[0009] Figure 7 This is another flowchart representing an example process that can be implemented using executable machine-readable instructions and / or using methods configured to... Figure 1 , Figure 2 , Figure 3 and / or Figures 4A to 4B The example lockstep comparator circuit system is implemented in hardware to detect errors associated with one or more comparators.

[0010] Figure 8 It is constructed to execute Figure 6 and / or Figure 7 Example process to implement Figure 1 , Figure 2 , Figure 3 and / or Figures 4A to 4B A block diagram of an example processing platform for an example lockstep comparator circuit system. Detailed Implementation

[0011] The accompanying drawings are not to scale. Generally, the same reference numerals will be used throughout the drawings and the accompanying written description to refer to the same or similar parts. As used herein, unless otherwise stated, connecting references (e.g., attachment, coupling, connection, and joining) may include intermediate members between the elements referred to by the connecting reference and / or relative movement between these elements. Thus, a connecting reference does not necessarily imply a direct connection between two elements and / or a fixed relationship between them.

[0012] Unless otherwise specified, descriptive terms such as “first,” “second,” and “third” do not require any particular priority, physical order, arrangement in a list, and / or any sorting, but are merely used as annotations and / or arbitrary names to distinguish elements for ease of understanding of the examples. In some examples, the descriptive term “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to in the claims by different descriptive terms such as “second” or “third.” In such cases, such descriptors are only used to clearly identify those elements that may, for example, share the same name in other respects. As used herein, “substantially real-time” means occurring in a near-instantaneous manner; it should be recognized that delays in computation time, transmission, etc., may exist in the real world. Therefore, unless otherwise stated, “substantially parallel” and “substantially real-time” mean real-time + / - 1 second.

[0013] With technological advancements, the complexity of computing and / or electrical devices has increased significantly. Such devices comprise hardware, software, and / or firmware for performing multiple specific functions. If errors occur in the hardware, software, and / or firmware, such devices may be unable to perform multiple specific functions, or may perform poorly when performing those functions. This inability to perform and / or poor performance can affect the outcomes of the relevant system, and / or more generally, the reliability and / or safety associated with the operation of the relevant system. To detect and / or correct these errors, devices may include functional safety hardware. For example, autonomous driving computing devices that facilitate the autonomous operation of vehicles (e.g., air-based vehicles, land-based vehicles, etc.) may include hardware that implements and / or otherwise meets functional safety requirements. Functional safety requirements may be based on the International Organization for Standardization (ISO) 26262, the International Electrotechnical Commission (IEC) 61508, etc. ISO 26262 is an international standard concerning the functional safety of electrical and / or electronic systems in automotive production. IEC 61508 is an international standard corresponding to the automatic protection of systems related to the application, design, deployment, and maintenance of safety.

[0014] Some applications utilize system-on-a-chip (SoC) hardware to perform computational tasks. Some such SoC hardware includes lockstepping hardware, such as a lockstep processor or central processing unit (CPU), to help comply with functional safety requirements. For example, "lockstepping CPU," "lockstepping processor," "lockstepping hardware," etc., can refer to a multi-core computing hardware resource in which two or more cores perform similar operations in parallel, and each core feeds its corresponding output to a corresponding comparator logic block to determine whether these outputs are equal. For example, the comparator logic block can detect a fault condition associated with the multi-core computing hardware resource in response to determining that the outputs(s) from two or more cores are unequal.

[0015] In some cases, functional safety standards mandate diagnostics and / or other testing of lockstepping hardware's lockstepping capabilities, functionality, etc. However, previous lockstepping testing implementations were intrusive to applications because lockstepping hardware might not be able to execute code with the same integrity during lockstepping functionality testing as it would during normal operation outside of testing. Alternatively, some previous lockstepping testing implementations utilized dual comparators to facilitate online test sequencing. However, these dual comparators might not operate in lockstep mode (e.g., they might not be configured to operate in lockstep mode) and do not provide the lockstepping testing functionality described herein.

[0016] Some previous lockstep testing implementations were very slow to complete. For example, in some previous lockstep testing implementations, the lockstep hardware might require 2*N cycles to compare N signals. In some such examples, a single lockstep comparator could be used, which could result in a very long self-test sequence. Some previous lockstep testing implementations may also lack the ability to isolate fault conditions of the lockstep hardware (such as faults associated with the lockstep comparator). Such isolation of fault conditions can provide benefits such as increased granularity of debugging information, which can be used to improve the operation of current or future lockstep hardware.

[0017] The examples described herein include lockstep comparators and related methods. In some of the described examples, the lockstep comparator outputs diagnostic data during the online operation of the lockstep hardware, which can help improve offline fault analysis associated with detected fault conditions of the lockstep hardware. In some of the described examples, the lockstep comparator includes two or more lockstep comparators that can implement online test sequencing. For example, these lockstep comparators can test lockstep functionality while the lockstep hardware is online and / or otherwise executing application code. Advantageously, lockstep comparators as described herein can test the lockstep functionality of lockstep hardware by replacing the relatively long test sequences of previous embodiments with redundant logic, without requiring the lockstep hardware to be taken offline. For example, lockstep comparators as described herein can complete diagnostic testing of lockstep hardware in 8 clock cycles, compared to thousands of clock cycles in some previous lockstep testing embodiments. Advantageously, the example lockstep comparator described herein can provide comprehensive debugging information (e.g., fault condition data, port information (e.g., port mismatch values)) to external hardware, software, and / or firmware (e.g., computing devices, user interfaces associated with computing devices, etc.).

[0018] Figure 1 This is an illustration of an example computing environment 100 including an example computing system 102, which includes an example lockstep comparator logic (LCL) 104 for identifying diagnostics and / or otherwise implementing tests on lockstep capabilities, functions, etc., of lockstep hardware. For example, LCL 104 can compare outputs from one or more cores, modules, etc., of the lockstep hardware and identify fault conditions based on these comparisons.

[0019] The computing system 102 includes an example central processing unit (CPU) 106, a first example acceleration resource (acceleration resource A) 108, a second example acceleration resource (acceleration resource B) 110, an example general-purpose processing resource 112, an example interface resource 114, an example bus 116, an example power supply 118, and an example data storage 120. In this example, the data storage 120 stores and / or otherwise includes example lockstep debugging data 122. Figure 1 The illustrated example further depicts an example user interface 124, an example network 126, and an example central facility 128, which can store lockstep debugging data 122.

[0020] In some examples, computing system 102 is a system-on-a-chip (SoC) representing one or more integrated circuits (ICs) (e.g., compact ICs) incorporated into components of a computer or other electronic system in a compact format. For example, computing system 102 may be implemented using a combination of one or more programmable processors, hardware logic, and / or hardware peripherals and / or interfaces. Alternatively or additionally, Figure 1 Example computing system 102 may include memory, input / output (I / O) ports, and / or auxiliary storage devices. For example, computing system 102 includes an LCL 104, CPU 106, first acceleration resource 108, second acceleration resource 110, general-purpose processing resource 112, interface resource 114, bus 116, power supply 118, data storage 120, memory, I / O ports, and / or auxiliary storage devices, all located on the same substrate. In some examples, computing system 102 includes digital, analog, mixed-signal, radio frequency (RF), or other signal processing capabilities.

[0021] In some examples, computing system 102 implements an electronic control unit (ECU) in a vehicle (e.g., a driver-operated vehicle, an autonomous vehicle, etc.). For example, computing system 102 may be an ECU that controls one or more components, functions, etc., of the vehicle. In some examples, computing system 102 may be an ECU that controls an engine (e.g., an internal combustion engine), a motor (e.g., an electric motor), a transmission, an infotainment system, a light detection and ranging (LIDAR) system, etc., and / or combinations thereof.

[0022] CPU 106 is a multi-core CPU. For example, CPU 106 includes multiple cores (e.g., computing cores, processor cores, etc.) that can execute instructions, application code, etc. First acceleration resource 108 is a graphics processing unit (GPU). For example, first acceleration resource 108 may be a GPU that generates computer graphics, performs general-purpose computing, etc. In some examples, first acceleration resource 108 may generate graphics for user interface 124. Second acceleration resource 110 is an AI accelerator. For example, second acceleration resource 110 may be a vision processing unit for implementing machine or computer vision computing tasks, object recognition computing tasks, etc. General-purpose processing resource 112 is a programmable processor. For example, general-purpose processing resource 112 may be a CPU, GPU, etc. Alternatively, one or more of the first acceleration resource 108, second acceleration resource 110, and / or general-purpose processing resource 112 may be different types of hardware, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs) (e.g., field-programmable gate arrays (FPGAs)).

[0023] Interface resource 114 is hardware that implements and / or represents one or more interfaces (e.g., computing interfaces, network interfaces, vehicle network or bus interfaces, industrial protocol network or bus interfaces, etc.). For example, interface resource 114 can be hardware, software, and / or firmware that implements communication devices (e.g., communication gateways, network interface cards (NICs), smart NICs, etc.) such as transmitters, receivers, transceivers, modems, industrial protocol gateways, residential gateways, wireless access points, and / or network interfaces to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 126. In some examples, communication is via... It can be implemented using various interfaces such as Controller Area Network (CAN) bus, Ethernet, Digital Subscriber Line (DSL), Wi-Fi, telephone line, coaxial cable, satellite, direct-access wireless, and cellular telephone systems. For example, interface resource 114 can be implemented using any type of interface standard, such as... Interfaces include CAN interface, Ethernet interface, Wi-Fi interface, Universal Serial Bus (USB), Near Field Communication (NFC) interface, and / or PCI Fast Interface.

[0024] The computing system 102 includes a power supply 118 for delivering power to the resources(s) of the computing system 102. In this example, the power supply 118 is implemented by one or more batteries (e.g., lithium-ion batteries or any other rechargeable battery or power source). For example, the power supply 118 can be charged using a power adapter or converter (e.g., an AC / DC power converter), a wall power outlet (e.g., a 110V AC wall power outlet, a 220V AC wall power outlet, etc.), etc. In some examples, the power supply 118 can be charged by a vehicle component such as an alternator.

[0025] The computing system 102 includes a data storage 120 for recording data (e.g., lockstep debugging data 122, etc.). The data storage 120 may be implemented using volatile memory (e.g., one or more triggers, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), etc.) and / or non-volatile memory (e.g., flash memory). The data storage 120 may also be implemented using one or more Double Data Rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, mobile DDR (mDDR), etc. The data storage 120 may also be implemented using one or more mass storage devices, such as multiple hard disk drives (HDDs), multiple optical disc drives (CDs), multiple digital versatile optical disc drives (DVDs), multiple solid-state drives, etc. Although in the illustrated example, the data storage 120 is depicted as a single data storage, the data storage 120 may be implemented using any number and / or multiple types of data storage. Furthermore, the data stored in data storage 120 can be in any data format, such as binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structure, etc.

[0026] The computing system 102 communicates with the user interface 124. For example, the user interface 124 may be implemented by a graphical user interface (GUI), an application display, etc., and may be presented to a user on one or more display devices that are circuit-connected to and / or otherwise communicate with the computing system 102. In such an example, a user (e.g., a customer, developer, vehicle maintenance technician, vehicle driver, vehicle passenger, etc.) controls the computing system 102 via the user interface 124. Alternatively, the computing system 102 may include and / or otherwise implement the user interface 124.

[0027] One or more of the following components communicate with bus 116: LCL 104A, CPU 106, first acceleration resource 108, second acceleration resource 110, general-purpose processing resource 112, interface resource 114, power supply 118, and data storage 120. For example, bus 116 corresponds to, represents, and / or otherwise includes at least one of a CAN bus, an internal integrated circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a Peripheral Component Interconnect (PCI) bus, or a JTAG interface. Alternatively or alternatively, bus 116 may implement any other type of computing bus or electrical bus.

[0028] Network 126 is the Internet. However, network 126 in this example can be implemented using any suitable wired and / or wireless network(s), including, for example, one or more data buses, one or more local area networks (LANs), one or more wireless LANs (WLANs), one or more cellular networks, one or more private networks, one or more public networks, etc. In some examples, network 126 enables computing system 102 to communicate with central facility 128.

[0029] Central facility 128 is implemented by one or more servers that collect and process lockstep debugging data 122 from computing system 102. Alternatively or additionally, central facility 128 may include, correspond to and / or otherwise represent any other type of computing device, such as desktop computer, mobile device (e.g., smartphone, internet-enabled smartphone, etc.), laptop computer, tablet computer (e.g., tablet computer, internet-enabled tablet computer, etc.).

[0030] In some examples, central facility 128 may obtain lockstep debugging data 122 from computing system 102 via network 126 through an internet interface for receiving internet messages (e.g., multiple Hypertext Transfer Protocol (HTTP) requests) including lockstep debugging data 122. Alternatively or additionally, central facility 128 may receive lockstep debugging data 122 from computing system 102 via network 126 using any other communication protocol, such as HTTP Secure Protocol (HTTPS), File Transfer Protocol (FTP), Secure File Transfer Protocol (SFTP), etc. In some examples, central facility 128 may analyze lockstep debugging data 122 to identify fault conditions of computing system 102 detected by LCL 104. Central facility 128 may identify multiple improvements to LCL 104 based on the identified fault conditions and subsequent analysis.

[0031] In some examples, LCL 104 includes redundant hardware and one or more comparators for detecting lockstep fault conditions. For example, LCL 104 may include redundant or separate instances of CPU 106, redundant or separate instances of first acceleration resource 108, redundant or separate instances of second acceleration resource 110, etc. For example, LCL 104 may include instances of CPU 106 and one or more comparators. In some examples, LCL 104 may execute instructions substantially in parallel with another resource of computing system 102. For example, LCL 104 and CPU 106 (or its cores) may execute the same instructions to generate their respective outputs, which form the basis for comparisons used to detect fault conditions(s).

[0032] In some examples, one or more of CPU 106, first acceleration resource 108, second acceleration resource 110, general-purpose processing resource 112, and / or interface resource 114 are lockstepping hardware. For example, CPU 106 may be a lockstepping CPU, first acceleration resource 108 may be a lockstepping GPU, etc. In some examples, CPU 106 is a lockstepping CPU, and LCL 104 performs a self-test on the lockstepping capabilities, functionality, etc. of CPU 106. For example, LCL 104 may include one or more comparators (e.g., lockstepping comparators) that can compare a first output of one or more cores of CPU 106 (and / or more generally CPU 106) with a second output of LCL 104 to detect lockstepping failures, and LCL may include another instance of CPU 106. In some examples, LCL 104 may detect lockstepping failures in response to the detection of a fault condition.

[0033] In some examples, LCL 104 performs relatively fast diagnostic execution. For instance, compared to previous lockstep testing techniques that could require thousands of CPU cycles, LCL 104 can complete a lockstep self-test of CPU 106 within 8 CPU cycles. In some examples, LCL 104 ensures that the corresponding resources are always online. For example, LCL 104 can perform a lockstep self-test of CPU 106 while CPU 106 is online and / or otherwise executing application code, instructions, etc. In some examples, LCL 104 can generate synthesis information that can be used to debug lockstep failures and output this synthesis information as lockstep debugging data 122. For example, LCL 104 may generate and / or otherwise output lockstep debug data 122 to include high-granularity data, such as identifiers of ports that failed self-tests (e.g., integrated circuit ports, hardware ports, etc.), program counter values ​​in response to the detection of a fault condition (e.g., registers in CPU 106 that include the address or location of instructions executed at a specified time), etc. In some examples, LCL 104 may freeze the comparison state in response to the detection of a fault condition and may make the comparison state readable (e.g., presenting the comparison state on user interface 124, storing the comparison state in lockstep debug data 122, etc.), latch the program counter value of CPU 106, etc., and / or combinations thereof.

[0034] Figure 2 This is a block diagram of an example lockstep wrapper 200. Lockstep wrapper 200 is used with systems (such as...) Figure 1 The lockstep encapsulator 200 is a logical construct associated with one or more parts of the computing system 102. For example, the lockstep encapsulator 200 can be implemented by hardware, software, firmware, and / or a combination thereof. In some examples, the lockstep encapsulator 200 can be implemented as... Figure 1 The LCL 104 and CPU 106. Alternatively, the lockstep package 200 can implement any other resources of the LCL 104 and computing system 102, such as the first acceleration resource 108, the second acceleration resource 110, etc.

[0035] Lockstep encapsulator 200 includes example main hardware 202, example auxiliary hardware 204, example input delay logic 206, example output delay logic 208, and example lockstep comparison control logic 210. In this example, lockstep comparison control logic 210 includes self-test control logic 212, first example comparator logic 214, second example comparator logic 216, and example memory 218. In this example, memory 218 includes lockstep debugging data 220.

[0036] The inputs of the main hardware 202 are via a bus (e.g., Figure 1The bus 116 is coupled to another resource of the computing system (e.g., computing system 102). The outputs of the main hardware 202 are coupled via the bus to the output delay logic 208 and / or another resource of the computing system. As used herein, the coupling associated with the inputs and / or outputs of components, devices, integrated circuits, etc., may be implemented by one or more terminals. For example, a first output terminal, a second output terminal, etc., of the main hardware 202 may be coupled to a corresponding input terminal in the first input terminal, a second input terminal, etc., of the output delay logic 208. In some examples, the one or more terminals may be constructed and / or otherwise constituted by aluminum, copper, or any other conductive material or combination thereof. In some examples, the one or more terminals may be implemented as pins (e.g., integrated circuit pins). Alternatively, the one or more terminals may be implemented as pins (e.g., conductive pins), tabs (e.g., conductive tabs), or any other type of electrical contact.

[0037] The output of output delay logic 208 is coupled to the inputs of the first comparator logic 214, the second comparator logic 216, and / or more generally, the inputs of lockstep comparison control logic 210. The input of input delay logic 206 may be coupled to another resource of the computing system via a bus. The output of input delay logic 206 is coupled to the input of auxiliary hardware 204. The output of auxiliary hardware 204 is coupled to the inputs of the first comparator logic 214, the second comparator logic 216, and / or more generally, the inputs of lockstep comparison control logic 210. The output of self-test control logic 212 is coupled to the inputs of the first comparator logic 214 and the second comparator logic 216. The output of the first comparator logic 214 is coupled to the input of memory 218. The output of the second comparator logic 216 is coupled to the input of memory 218. Alternatively or additionally, the outputs of the first comparator logic 214 and / or the second comparator logic 216 may be coupled to the main hardware 202, the second hardware 204, and / or different resources of the computing system via a bus.

[0038] In some examples, main hardware 202 may implement the resources of computing system 102. For example, main hardware 202 may implement CPU 106. Alternatively, main hardware 202 may be provided by Figure 1 The first acceleration resource 108, the second acceleration resource 110, etc., are implemented and / or otherwise correspond to the first acceleration resource, the second acceleration resource, etc. In some examples, the auxiliary hardware 204 may implement a redundant and / or otherwise separate instance of the main hardware 202. For example, the auxiliary hardware 204 may be implemented by another instance of CPU 106. Alternatively, the auxiliary hardware 204 may be implemented by... Figure 1The first acceleration resource 108, the second acceleration resource 110, etc. are implemented and / or otherwise correspond to the first acceleration resource, the second acceleration resource, etc.

[0039] In some examples, the self-test control logic 212 may be implemented by a hardware state machine. Alternatively, the self-test control logic 212 may be implemented by one or more analog or digital circuits, logic circuits, (multiple) programmable processors, (multiple) programmable controllers, (multiple) ASICs, (multiple) PLDs, and / or (multiple) FPLDs. In some examples, memory 218 may be implemented by non-volatile memory, volatile memory, etc. In some examples, lockstep debug data 220 may be... Figure 1 The lockstep debugging data 122 is used for implementation.

[0040] In this example, auxiliary hardware 204 is redundant hardware relative to primary hardware 202. In this example, auxiliary hardware 204 is configured in a lockstep configuration. For example, auxiliary hardware 204 may have the same inputs as primary hardware 202, which in this example correspond to example function input 222. For example, function input 222 may be implemented by computer-readable instructions, machine-readable instructions, and / or other hardware-readable instructions. In some examples, primary module 202 outputs example function output 224 in response to executing function input 222. In some examples, auxiliary module 204 outputs example lockstep output 226 in response to executing function input 222.

[0041] Lockstep encapsulator 200 includes input delay logic 206 for inserting a delay (e.g., time or timing delay) between the main hardware 202 of receive function input 222 and the auxiliary hardware 204 of receive function input 222. For example, input delay logic 206 may insert a delay to ensure that data, signals, etc., compared by first comparator logic 214, second comparator logic 216, etc., are time-aligned. In such an example, input delay logic 206 may respond to lockstep encapsulator 200 (and / or more generally, ...) Figure 1 The input delay logic 206 is inserted by using intermittent processing delays, propagation delays, etc., associated with one or more components of the computing system 102 to mitigate and / or otherwise reduce comparator errors. In some examples, the input delay logic 206 may be implemented by one or more analog circuits, one or more digital circuits, one or more logic circuits, etc.

[0042] Lockstep encapsulator 200 includes output delay logic 208 for inserting a delay (e.g., time or timing delay) between the main hardware 202 for outputting functional output 224 and the lockstep comparison control logic 210 for receiving functional output 224. For example, output delay logic 208 may insert a delay to ensure that data, signals, etc., compared by first comparator logic 214, second comparator logic 216, etc., are time-aligned. In such an example, output delay logic 208 may respond to lockstep encapsulator 200 (and / or more generally, ...) Figure 1 The intermittent processing delay, propagation delay, etc. associated with one or more components of the computing system 102 are inserted to mitigate and / or otherwise reduce comparator errors. In some examples, the output delay logic 208 may be implemented by one or more analog circuits, one or more digital circuits, one or more logic circuits, etc.

[0043] In the example operation, the main hardware 202 receives the function input 222 at a first time, and the auxiliary hardware 204 receives the function input 222 at a second time after the first time. For example, the time difference between the first and second times is implemented by the input delay logic 206. The main hardware 202 can generate a function output 224 based on the function input 222, and the auxiliary hardware 204 can generate a lockstep output 226 based on the function input 222.

[0044] In the example operation, the self-test control logic 212 may select (i) a first comparator logic 214 to perform a functional comparison on the functional output 224 and the lockstep output 226 to test the lockstep, and select (ii) a second comparator logic 216 to perform a self-test on the second comparator logic 216. Advantageously, the self-test control logic 212 may maintain lockstep online during the self-test by enabling at least one of the first comparator logic 214 or the second comparator logic 216 to perform a functional comparison during the self-test.

[0045] In the example operation, the first comparator logic 214 can be used to compare the functional output 224 and the lockstep output 226 to perform a functional comparison (e.g., output match) to test the comparison function of the lockstep comparison control logic 210. In the example operation, the second comparator logic 216 can perform a self-test. For example, the self-test control logic 212 can output all logic zeros (or all logic one) to the second comparator logic 216 to implement a match test. For example, the match test can be implemented by comparing a first set of logic zeros from the self-test control logic 212 with a second set of logic zeros from the self-test control logic 212. In some such examples, the match test can indicate whether one or more logic gates of the second comparator logic 216 remain stuck in and / or otherwise frozen in a logic one state (e.g., always outputting logic one), a logic zero state (e.g., always outputting logic zero), etc.

[0046] In some examples, the self-test logic control 212 may output all logic one to the second comparator logic 216 during a first cycle (e.g., a first clock cycle) or a first time period to determine whether one or more logic gates of the second comparator logic 216 remain fixed in a logic zero state. In some examples, the self-test control logic 212 may output all logic zero to the second comparator logic 216 during a second cycle (e.g., a second clock cycle) following the first cycle to determine whether one or more logic gates of the second comparator logic 216 remain fixed in a logic one state. For example, a match test can be performed over two clock cycles by outputting all logic one during the first cycle and all logic zero during the second cycle.

[0047] In some examples, the self-test control logic 212 may output a combination of values ​​to the second comparator logic 216 to implement a mismatch test. For example, the mismatch test may indicate whether one or more logic gates of the second comparator logic 216 remain fixed in and / or otherwise frozen in a logic one state (e.g., always outputting logic one), a logic zero state (e.g., always outputting logic zero), etc. In some examples, the self-test control logic 212 may output logic one to multiple first inputs of the logic gate(s) of the second comparator logic 216 and output logic zero to multiple second inputs of those logic gates during a first cycle (e.g., a first clock cycle) to determine whether one or more logic gates remain fixed in a logic zero (or logic one) state. In some examples, the self-test control logic 212 may output logic zero to multiple first inputs of the logic gate(s) of the second comparator logic 216 and output logic one to multiple second inputs of those logic gates during a second cycle (e.g., a second clock cycle) to determine whether one or more logic gates remain fixed in a logic zero (or logic one) state. For example, a mismatch test can be performed over two clock cycles by: (i) outputting logic one to (a plurality of) first inputs of logic gates and outputting logic zero to (a plurality of) second inputs of these logic gates during the first cycle, and (ii) outputting logic zero to (a plurality of) first inputs of logic gates and outputting logic one to (a plurality of) second inputs of these logic gates during the second cycle.

[0048] In the example operation, in response to the detection of a fault condition associated with the second comparator logic 216 based on the failure of at least one of a match test or a mismatch test, the second comparator 216 can output the fault condition, latching of the program counter value, etc., to the lockstep debugging data 220 in the memory 218. In the example operation, the lockstep comparison control logic 210 can make the lockstep debugging data 220 available for retrieval via the bus from the resources of the computing system 102. In the example operation, in response to a self-test performed by the second comparator logic 216, the self-test control logic 212 can select (i) the second comparator logic 216 to perform a functional comparison of the functional output 224 and the lockstep output 226 to check the function, and select (ii) the first comparator logic 214 to perform a self-test on the first comparator logic 214.

[0049] Although Figure 2 The diagram illustrates the implementation. Figure 1 The example method of LCL 104, but in Figure 2 One or more of the elements, processes, and / or devices illustrated in the diagram may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, Figure 2Example main hardware 202, example auxiliary hardware 204, example input delay logic 206, example output delay logic 208, example lockstep comparison control logic 210, example self-test control logic 212, first example comparator logic 214, second example comparator logic 216, example memory 218, example lockstep debug data 220 and / or more generally, the example lockstep wrapper 200 can be implemented by hardware, software, firmware and / or any combination of hardware, software and / or firmware. Therefore, for example, example main hardware 202, example auxiliary hardware 204, example input delay logic 206, example output delay logic 208, example lockstep comparison control logic 210, example self-test control logic 212, first example comparator logic 214, second example comparator logic 216, example memory 218, example lockstep debug data 220 and / or more generally, any one of the example lockstep package 200 may be implemented by one or more analog or digital circuits, logic circuits, (multiple) programmable processors, (multiple) programmable controllers, (multiple) GPUs, (multiple) DSPs, (multiple) ASICs, (multiple) PLDs and / or (multiple) FPLDs. When reading any device or system claim of this patent to cover purely software and / or purely firmware implementations, at least one of the following is specifically defined as including non-transitory computer-readable storage devices or disks containing software and / or firmware, such as memory, DVD, CD, Blu-ray disc, etc. (Example main hardware 202, example auxiliary hardware 204, example input delay logic 206, example output delay logic 208, example lockstep comparison control logic 210, example self-test control logic 212, first example comparator logic 214, second example comparator logic 216, example memory 218, and / or example lockstep debug data 220.) Figure 1 Example LCL 104 may include, except for or instead of Figure 2 One or more elements, processes, and / or devices other than those illustrated herein, and / or may include more than one of any or all of the illustrated elements, processes, and devices. As used herein, the phrase “communication,” including its variations, covers direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-off events.

[0050] Figure 3 This is a schematic diagram of example comparator logic 300. Comparator logic 300 can be... Figure 2 First comparator logic 214 Figure 2 The second comparator logic 216 and / or more generally Figure 1An example implementation of LCL 104. Comparator logic 300 includes first example latch logic 302, example selection logic 304, first example detection logic 306, second example detection logic 308, second example latch logic 310, and example error detection logic 312.

[0051] Comparator logic 300 includes first latch logic 302 for latching inputs from example buses 314, 316 to selection logic 304. Buses 314, 316 include a first example bus (CMP_BUS1) 314 and a second example bus (CMP_BUS2) 316. For example, the first bus 314 may be supplied by inputs from... Figure 2 The output delay logic 208 is used to implement this. In some examples, the second bus 316 can be supplied by the output delay logic 208. Figure 2 The first latch logic 302 is implemented using the lockstep output 226 of the auxiliary hardware 204. The first latch logic 302 includes a first example latch 318 and a second example latch 320. The first latch 318 and the second latch 320 are D flip-flops. Alternatively, the first latch 318 and / or the second latch 320 can be implemented using any other type of latch or flip-flop. The input of the first latch 318 is coupled to a first bus 314, and the input of the second latch 320 is coupled to a second bus 316.

[0052] Comparator logic 300 includes selection logic 304, which selects whether comparator logic 300 performs a functional comparison (e.g., lockstep test, online lockstep test, etc.) or a self-test based on commands, instructions, etc., from example self-test control logic 322. In some examples, self-test logic control logic 322 may be implemented... Figure 2 The self-test control logic 322 is provided. In some examples, the self-test control logic 322 may be implemented by a hardware state machine. Alternatively, the self-test control logic 322 may be implemented by one or more analog or digital circuits, logic circuits, (multiple) programmable processors, (multiple) programmable controllers, (multiple) ASICs, (multiple) PLDs and / or (multiple) FPLDs.

[0053] Selection logic 304 includes multiple example multiplexers 324, 326, 328, and 330, which include a first example multiplexer 324, a second example multiplexer 326, a third example multiplexer 328, and a fourth example multiplexer 330. The multiple multiplexers 324, 326, 328, and 330 include a first group of multiplexers and a second group of multiplexers. The first group of multiplexers includes a first portion of the multiple multiplexers 324, 326, 328, and 330. This first portion includes the first multiplexer 324 and the second multiplexer 326. The second group of multiplexers includes a second portion of the multiple multiplexers 324, 326, 328, and 330. This second portion includes the third multiplexer 328 and the fourth multiplexer 330.

[0054] The corresponding first input of the first group of multiplexers 324, 326, 328, and 330 is coupled to the output of the first latch 318. The corresponding second input of the first group of multiplexers 324, 326, 328, and 330 is coupled to the corresponding output of the self-test control logic 322. The corresponding first input of the second group of multiplexers 324, 326, 328, and 330 is coupled to the output of the second latch 320. The corresponding second input of the second group of multiplexers 324, 326, 328, and 330 is coupled to the corresponding output of the self-test control logic 322.

[0055] For clarity, Figure 3 Only four multiplexers for the selection logic 304 are depicted. Alternatively, multiplexers can be used... Figure 3 The depicted multiplexer uses fewer or more multiplexers to implement selection logic 304. For example, the number of multiplexers 324, 326, 328, 330 may correspond to the number of outputs to be tested from the resource. In some examples, the number of multiplexers 324, 326, 328, 330 may be equal to and / or otherwise correspond to the number of outputs from the resource. Figure 2 The main hardware 202 has twice the number of outputs to be tested.

[0056] Comparator logic 300 includes first detection logic 306 for detecting differences between the outputs of selection logic 304. First detection logic 306 includes a plurality of first example logic gates 332, 334. Logic gates 332, 334 are XOR logic gates. Alternatively, one or more of logic gates 332, 334 may be logic gates of different types. The plurality of first logic gates 332, 334 includes first example logic gate 332 and second example logic gate 334. The respective first inputs of logic gates 332, 334 are coupled to the respective outputs of a first set of multiplexers 324, 326, 328, 330. For example, the first input of the first logic gate 332 is coupled to the output of the first multiplexer 324, and the first input of the second logic gate 334 is coupled to the output of the second multiplexer 326. The corresponding second inputs of logic gates 332 and 334 are coupled to the corresponding outputs of a second group of multiplexers 324, 326, 328, and 330. For example, the second input of the first logic gate 332 is coupled to the output of the third multiplexer 328, and the second input of the second logic gate 334 is coupled to the output of the fourth multiplexer 330.

[0057] For clarity, Figure 3 Only two logic gates of the first detection logic 306 are depicted. Alternatively, a comparison can be used. Figure 3 The depicted logic gates may be fewer or more logic gates to implement the first detection logic 306. For example, the number of first logic gates 332, 334 may correspond to N / 2 logic gates, where N is the number of multiplexers 324, 326, 328, 330. In some examples, the number of first logic gates 332, 334 may be equal to and / or otherwise correspond to the number of gates from... Figure 2 The number of outputs to be tested in the main hardware 202.

[0058] Comparator logic 300 includes second detection logic 308 for detecting the presence of at least one logic one in the output of first detection logic 306. Second detection logic 308 includes second example logic gates 336 and 338, including a third example logic gate 336 and a fourth example logic gate 338. Third logic gate 336 is an OR logic gate. Fourth logic gate 338 is a NAND logic gate. Alternatively, third logic gate 336 and / or fourth logic gate 338 can be implemented using different types and / or numbers of logic gates. A corresponding first input of third logic gate 336 is coupled to a corresponding output of first logic gates 332 and 334. For example, a first input of third logic gate 336 is coupled to the output of first logic gate 332, and a second input of third logic gate 336 is coupled to the output of second logic gate 334. A corresponding input of fourth logic gate 338 is coupled to a corresponding output of first logic gates 332 and 334. For example, the first input of the fourth logic gate 338 is coupled to the output of the first logic gate 332, and the second input of the fourth logic gate 338 is coupled to the output of the second logic gate 334.

[0059] Comparator logic 300 includes second latch logic 310 for latching the output from second detection logic 308 to error detection logic 312. Second latch logic 310 includes a third example latch 340 and a fourth example latch 342. The third latch 340 and the fourth latch 342 are D flip-flops. Alternatively, the third latch 340 and / or the fourth latch 342 can be implemented using any other type of latch or flip-flop. The input of the third latch 340 is coupled to the output of a third logic gate 336. The input of the fourth latch 342 is coupled to the output of a fourth logic gate 338.

[0060] Comparator logic 300 includes a function for detecting AND... Figure 2 The lockstep encapsulator 200 includes error detection logic 312 for lockstep operation, functionality, and related fault conditions or errors. Error detection logic 312 includes a fifth example logic gate 344, a sixth example logic gate 346, a seventh example logic gate 348, and an eighth example logic gate 350. The fifth, sixth, and seventh logic gates 344, 346, and 348 are AND gates. Alternatively, one or more of the fifth, sixth, and / or seventh logic gates 344, 346, and 348 can be implemented using different types and / or numbers of logic gates. The eighth logic gate 350 is an OR gate. Alternatively, the eighth logic gate 350 can be implemented using different types and / or numbers of logic gates.

[0061] The first input of the fifth logic gate 344 is coupled to the output of the third latch 340. The second input of the fifth logic gate 344 (!SELF-TEST_MODE) is coupled to the external logic of the comparator logic 300. For example, the second input of the fifth logic gate 344 can be coupled to the output of the self-test control logic 322. For example, the second input can be configured to receive a first control signal implemented by !SELF-TEST_MODE. The output of the fifth logic gate 344 (FUNC_COMPARE_ERROR) is coupled to the external logic of the comparator logic 300. For example, the output of the fifth logic gate 344 can be coupled to... Figure 2 The memory 218.

[0062] The first input of the sixth logic gate 346 is coupled to the output of the third latch 340. The second input (MATCH_TEST) of the sixth logic gate 346 is coupled to the external logic of the comparator logic 300. For example, the second input of the sixth logic gate 346 can be coupled to the output of the self-test control logic 322. For example, the second input can be configured to receive a second control signal implemented by MATCH_TEST.

[0063] The first input of the seventh logic gate 348 is coupled to the output of the fourth latch 342. The second input (MISMATCH_TEST) of the seventh logic gate 348 is coupled to the external logic of the comparator logic 300. For example, the second input of the seventh logic gate 348 can be coupled to the output of the self-test control logic 322. For example, the second input can be configured to receive a second control signal implemented by MISMATCH_TEST.

[0064] The first input of the eighth logic gate 350 is coupled to the output of the sixth logic gate 346. The second input of the eighth logic gate 350 is coupled to the output of the seventh logic gate 348. The output (SELF-TEST_ERROR) of the eighth logic gate 350 can be coupled to the external logic of the comparator logic 300. For example, the output of the eighth logic gate 350 can be coupled to... Figure 2 The memory 218.

[0065] In example operation, self-test control logic 322 can select whether comparator logic 300 tests a lockstep comparison or a functional comparison. For example, self-test control logic 322 can instruct selection logic 304 and / or more generally instruct comparator logic 300 to test a comparison of functional outputs from first bus 314 and / or second bus 316. In such an example, self-test control logic 322 can disable the self-test mode signal (SELF-TEST_MODE). In such an example, self-test control logic 322 can output signals (e.g., selection signals) to multiple multiplexers 324, 326, 328, 330 to select inputs from first latch 318 and second latch 320 for output to first detection logic 306. For example, first logic gates 332, 334 can compare (multiple) first inputs from first bus 314 with (multiple) second inputs from second bus 316. The third logic gate 336 can activate logic one in response to at least one output from the first logic gates 332 and 334 being logic one. For example, the third logic gate 336 can activate logic one based on determining that one or more of the first logic gates 332 and 334 have detected a mismatch in one or more inputs from the inputs of buses 314 and 316. In such an example, the fifth logic gate 344 can activate logic one as the FUNC_COMPARE_ERROR signal based on the detected mismatch and the activation of the signal at the second input of the fifth logic gate 344.

[0066] In some examples, self-test control logic 322 may instruct selection logic 304 and / or more generally instruct comparator logic 300 to perform a self-test on comparator logic 300. In such examples, self-test control logic 322 may enable the self-test mode signal (SELF-TEST_MODE) and enable the match test mode signal (MATCH_TEST) to cause comparator logic 300 to perform a match test.

[0067] In some examples, the self-test control logic 322 causes the comparator logic 300 to perform a match test over two cycles. For example, the self-test control logic 322 may output signals (e.g., selection signals) to multiple multiplexers 324, 326, 328, 330 to select an input from the self-test control logic 322 for output to the first detection logic 306. For example, the self-test control logic 322 may output logic zero to each of the multiple multiplexers 324, 326, 328, 330 during the first cycle or output logic one to each of these multiplexers during the second cycle (after the first cycle) to perform a match test. In such an example, first logic gates 332, 334 may compare the logic zero output from the multiple multiplexers 324, 326, 328, 330 during the first cycle with the logic one output from the multiple multiplexers 324, 326, 328, 330 during the second cycle. In response to at least one output from the first logic gates 332 and 334 being logic one, the third logic gate 336 may enable logic one during a first cycle, which may indicate that at least one of the first logic gates 332 and 334 remains fixed in and / or otherwise latched in a logic one output state. In response to at least one output from the first logic gates 332 and 334 being logic one, the third logic gate 336 may enable logic one during a second cycle, which may indicate that at least one of the first logic gates 332 and 334 remains fixed in and / or otherwise latched in a logic zero output state. For example, the third logic gate 336 may enable logic one based on determining that one or more of the first logic gates 332 and 334 did not generate an output based on its input. In such an example, the sixth logic gate 346 may enable logic one to the eighth logic gate 350, which in turn enables logic one as the SELF-TEST_ERROR signal. In some such examples, a valid indication of the SELF-TEST_ERROR signal indicates a fault condition detected in comparator logic 300, and this indication can be stored as lockstep debugging data 220. Figure 2 In memory 218.

[0068] In some examples, the self-test control logic 322 can enable both the self-test mode signal (SELF-TEST_MODE) and the mismatch test mode signal (MISMATCH_TEST) to cause the comparator logic 300 to perform a mismatch test. In such examples, the self-test control logic 322 can output signals (e.g., selection signals) to multiple multiplexers 324, 326, 328, and 330 to select an input from the self-test control logic 322 for output to the first detection logic 306. For example, the self-test control logic 322 can output logic one to a first portion (e.g., the first multiplexer 324 and the second multiplexer 326) of the multiplexers 324, 326, 328, and 330 during a first cycle, and output logic zero to a second portion (e.g., the third multiplexer 328 and the fourth multiplexer 330). In such an example, self-test control logic 322 can output logic zero to the first portion (e.g., first multiplexer 324 and second multiplexer 326) of multiplexers 324, 326, 328, and 330 during a second cycle (after the first cycle), and output logic one to the second portion (e.g., third multiplexer 328 and fourth multiplexer 330). In some such examples, self-test control logic 322 can perform mismatch testing based on forcing the output of two different values ​​(e.g., multiple logic zeros, multiple logic ones, etc.) during these two cycles.

[0069] In such an example, first logic gates 332 and 334 can compare logic outputs from multiple multiplexers 324, 326, 328, and 330. In response to at least one output from the first logic gates 332 and 334 being logic zero, a fourth logic gate 338 can enable logic one, which can indicate that at least one of the first logic gates 332 and 334 remains locked in and / or otherwise latched into a logic zero output state. For example, the fourth logic gate 338 can enable logic one based on determining that one or more of the first logic gates 332 and 334 did not generate an output based on its input. In such an example, a seventh logic gate 348 can enable logic one to an eighth logic gate 350, which in turn enables logic one as a SELF-TEST_ERROR signal. In some such examples, the activation of the SELF-TEST_ERROR signal indicates a detected fault condition in comparator logic 300, and this indication can be stored as lockstep debugging data 220. Figure 2The memory 218 contains the self-test control logic 322, which advantageously performs a complete self-test of the comparator logic 300 within four cycles, based on completing a match test within two cycles and a mismatch test within two cycles.

[0070] Figures 4A to 4B This is a schematic diagram of an example dual comparator logic 400. Dual comparator logic 400 can be... Figure 2 The first comparator logic 214 and Figure 2 The second comparator logic 216 and / or more generally Figure 1 An example implementation of LCL 104. The dual comparator logic 400 includes a first example comparator logic 402 and a second example comparator logic 404. For example, the first comparator logic 402 may be implemented... Figure 2 First comparator logic 214 and / or Figure 2 The second comparator logic 216. In some examples, the second comparator logic 404 can be implemented. Figure 2 First comparator logic 214 and / or Figure 2 The second comparator logic is 216.

[0071] exist Figure 4A and / or Figure 4B The example self-test control logic 405 is further described below. In some examples, the self-test control logic 405 may be implemented. Figure 2 Self-test control logic 212 and / or Figure 3 The self-test control logic 405 is 322. In some examples, the self-test control logic 405 may be implemented by a hardware state machine. Alternatively, the self-test control logic 405 may be implemented by one or more analog or digital circuits, logic circuits, (multiple) programmable processors, (multiple) programmable controllers, (multiple) ASICs, (multiple) PLDs and / or (multiple) FPLDs. In this example, the output of the self-test control logic 405 is coupled to the inputs of the first comparator logic 402 and the second comparator logic 404. In some examples, the dual comparator logic 400 may include the self-test control logic 405.

[0072] The first comparator logic 402 includes a first example latch 406, a first example selection logic 408, a first example detection logic 410, a second example detection logic 412, a second example latch 414, a third example latch 416, and a first example error detection logic 418. The first selection logic 408 includes a first set of example multiplexers 420 and 422, including a first example multiplexer 420 and a second example multiplexer 422. The first selection logic 408 also includes a second set of example multiplexers 424 and 426, including a third example multiplexer 424 and a fourth example multiplexer 426. The first detection logic 410 includes first example logic gates 428 and 430, including a first example logic gate 428 and a second example logic gate 430. The second detection logic 412 includes a third example logic gate 432 and a fourth example logic gate 434. The first error detection logic 418 includes the fifth example logic gate 436, the sixth example logic gate 438, the seventh example logic gate 440, the eighth example logic gate 442, the ninth example logic gate 444, and the tenth example logic gate 446.

[0073] For clarity, Figures 4A to 4B Only four multiplexers of the first selection logic 408 are depicted. Alternatively, multiplexers can be used... Figures 4A to 4B The depicted multiplexers may be fewer or more multiplexers to implement the first selection logic 408. For example, the number of the first set of multiplexers 420, 422 and / or the number of the second set of multiplexers 424, 426 may correspond to the number of outputs to be tested from the resource. In some examples, the number of the first set of multiplexers 420, 422 and / or the number of the second set of multiplexers 424, 426 may be equal to and / or otherwise correspond to the number of outputs from the resource. Figure 2 The main hardware 202 has twice the number of outputs to be tested.

[0074] For clarity, Figures 4A to 4B Only two logic gates of the first detection logic 410 are depicted. Alternatively, a comparison can be used. Figures 4A to 4B The depicted logic gates may be fewer or more than a few logic gates to implement the first detection logic 410. For example, the number of first logic gates 428, 430 may correspond to N / 2 logic gates, where N is the number of multiplexers 420, 422, 424, 426 of the first selection logic 408. In some examples, the number of first logic gates 428, 430 may be equal to and / or otherwise correspond to the number of gates from the first selection logic 408. Figure 2 The number of outputs to be tested in the main hardware 202.

[0075] The second comparator logic 404 includes a fourth example latch 448, a second example selection logic 450, a third example detection logic 452, a fourth example detection logic 454, a fifth example latch 456, a sixth example latch 458, and a second example error detection logic 460. The second selection logic 450 includes a third set of example multiplexers 462 and 464, including the fifth and sixth example multiplexers 462 and 464. The second selection logic 450 also includes a fourth set of example multiplexers 466 and 468, including the seventh and eighth example multiplexers 466 and 468. The third detection logic 452 includes second example logic gates 470 and 472, including the first and second example logic gates 470 and 472. The second detection logic 454 includes the third example logic gate 474 and the fourth example logic gate 476. The second error detection logic 460 includes a fifth example logic gate 478, a sixth example logic gate 480, a seventh example logic gate 482, an eighth example logic gate 484, a ninth example logic gate 486, and a tenth example logic gate 488.

[0076] For clarity, Figures 4A to 4B Only four multiplexers of the second selection logic 450 are depicted. Alternatively, multiplexers can be used... Figures 4A to 4B The depicted multiplexers may include fewer or more multiplexers to implement the second selection logic 450. For example, the number of third-group multiplexers 462, 464 and / or fourth-group multiplexers 466, 468 may correspond to the number of outputs to be tested from the resource. In some examples, the number of third-group multiplexers 462, 464 and / or fourth-group multiplexers 466, 468 may be equal to and / or otherwise correspond to the number of outputs from the resource. Figure 2 The main hardware 202 has twice the number of outputs to be tested.

[0077] For clarity, Figures 4A to 4B Only two logic gates of the third detection logic 470 are depicted. Alternatively, a comparison can be used. Figures 4A to 4B The depicted logic gates may be fewer or more than required to implement the third detection logic 470. For example, the number of second logic gates 470, 472 may correspond to N / 2 logic gates, where N is the number of multiplexers 462, 464, 466, 468 of the second selection logic 450. In some examples, the number of second logic gates 470, 472 may be equal to and / or otherwise correspond to the number of gates from the second selection logic 450. Figure 2 The number of outputs to be tested in the main hardware 202.

[0078] The first latch 406, the second latch 414, the third latch 416, the fourth latch 448, the fifth latch 456, and the sixth latch 458 are D flip-flops. Alternatively, the first latch 318 and / or the second latch 320 can be implemented using any other type of latch or flip-flop. The first logic gates 428 and 430 and the second logic gates 470 and 472 are XOR logic gates. The third logic gate 432 of the second detection logic 412 and the third logic gate 474 of the fourth detection logic 454 are OR logic gates. The fourth logic gate 434 of the second detection logic 412 and the fourth logic gate 476 of the fourth detection logic 454 are NAND logic gates. The fifth logic gate 436, the sixth logic gate 438, the seventh logic gate 440, and the ninth logic gate 444 of the first error detection logic 418 are AND gates. The eighth gate 442 of the first error detection logic 418 and the eighth gate 484 of the second error detection logic 460 are inverter gates. The tenth gate 446 of the first error detection logic 418 and the tenth gate 488 of the second error detection logic 460 are OR gates. Alternatively, one or more gates of the first comparator logic 402 and / or one or more gates of the second comparator logic 404 can be used with AND gates. Figures 4A to 4B The different types and / or numbers of logic gates depicted in the illustrated examples are used to implement this.

[0079] The first comparator logic 402 includes a first latch 406 for latching inputs from a first example bus (CMP_BUS1) 489 to a first select logic 408. In some examples, the first bus 489 may be supplied by an input from a first example bus (CMP_BUS1) 489. Figure 2 The first comparator logic 402 includes a first selection logic 408, which is used to implement the output delay logic 208 based on the output of the example self-test control logic (e.g., ...). Figure 2 Self-test control logic 212 Figure 3 The self-test control logic 322, etc., uses commands and instructions to select whether the first comparator logic 402 performs a functional comparison (e.g., lockstep test, online lockstep test, etc.) or a self-test.

[0080] The corresponding first input of each multiplexer in the first group of multiplexers 420 and 422 is coupled to the first latch 406. The corresponding second input of each multiplexer in the first group of multiplexers 420 and 422 is coupled to the self-test control logic 405. The corresponding output of each multiplexer in the first group of multiplexers 420 and 422 is coupled to the corresponding first input of the first logic gates 428 and 430. For example, the first input of the first logic gate 428 is coupled to the output of the first multiplexer 420, and the first input of the second logic gate 430 is coupled to the output of the second multiplexer 422. For example, the second input of the first logic gate 428 is coupled to the output of the fifth multiplexer 462, and the second input of the second logic gate 430 is coupled to the output of the sixth multiplexer 464.

[0081] The first comparator logic 402 includes first detection logic 410 for detecting the difference between the outputs of the first selection logic 408. The outputs of the first logic gates 428 and 430 are coupled to the inputs of the third logic gate 432 and the fourth logic gate 434. For example, the outputs(multiple) of the first logic gate 428 are coupled to the first input of the third logic gate 432 and the first input of the fourth logic gate 434.

[0082] The first comparator logic 402 includes a second detection logic 412 for detecting the presence of at least one logic one in the output of the first detection logic 410. The outputs of the third logic gate 432 and the fourth logic gate 434 are coupled to the corresponding inputs of the second latch 414 and the third latch 416. For example, the output of the third logic gate 432 is coupled to the input of the second latch 414, and the output of the fourth logic gate 434 is coupled to the input of the third latch 416.

[0083] The output of the second latch 414 is coupled to the first input of the fifth logic gate 436 and the first input of the sixth logic gate 438. The output of the third latch 416 is coupled to the first input of the seventh logic gate 440 and the input of the eighth logic gate 442. The output of the eighth logic gate 442 is coupled to the first input of the ninth logic gate 444. The outputs of the sixth logic gate 438, the seventh logic gate 440, and the ninth logic gate 444 are coupled to the corresponding inputs of the tenth logic gate 446. The outputs of the fifth logic gate 436 (FUNC_COMPARE_ERROR1) and the tenth logic gate 446 (SELF-TEST_ERROR1) can be coupled to the external logic of the dual comparator logic 400. For example, the outputs of the fifth logic gate 436 and the tenth logic gate 446 can be coupled to... Figure 2 The memory 218.

[0084] The second comparator logic 404 includes a fourth latch 448 for latching inputs from the second example bus (CMP_BUS2) 490 to the second selection logic 450. In some examples, the second bus 490 may be supplied by inputs from... Figure 2 The auxiliary hardware 204 is used to implement the lockstep output 226. The second comparator logic 404 includes second selection logic 450, which is used to select based on the example self-test control logic (e.g., Figure 2 Self-test control logic 212 Figure 3 The second comparator logic 404 selects whether to perform a functional comparison (e.g., lockstep test, online lockstep test, etc.) or a self-test by using commands, instructions, etc. (such as the self-test control logic 322, etc.).

[0085] The corresponding first input of each multiplexer in the third group of multiplexers 462 and 464, and the corresponding first input of each multiplexer in the fourth group of multiplexers 466 and 468, are coupled to the fourth latch 448. The corresponding second input of each multiplexer in the third group of multiplexers 462 and 464 is coupled to the self-test control logic 405. The corresponding output of each multiplexer in the fourth group of multiplexers 466 and 468 is coupled to the corresponding first input of the second logic gates 470 and 472. For example, the first input of the first logic gate 470 is coupled to the output of the third multiplexer 424, and the first input of the second logic gate 472 is coupled to the output of the fourth multiplexer 426. For example, the second input of the first logic gate 470 is coupled to the output of the seventh multiplexer 466, and the second input of the second logic gate 472 is coupled to the output of the eighth multiplexer 468.

[0086] The second comparator logic 404 includes a third detection logic 452 for detecting the difference between the outputs of the second selection logic 450. The outputs of the second logic gates 470 and 472 are coupled to the inputs of the third logic gate 474 and the fourth logic gate 476. For example, the outputs(multiple) of the first logic gate 470 are coupled to the first input of the third logic gate 474 and the first input of the fourth logic gate 476.

[0087] The second comparator logic 404 includes a fourth detection logic 454 for detecting the presence of at least one logic one in the output of the third detection logic 452. The outputs of the third logic gate 474 and the fourth logic gate 476 are coupled to the corresponding inputs of the fifth latch 456 and the sixth latch 458. For example, the output of the third logic gate 474 is coupled to the input of the fifth latch 456, and the output of the fourth logic gate 476 is coupled to the input of the sixth latch 458.

[0088] The output of the fifth latch 456 is coupled to the first input of the fifth logic gate 478 and the first input of the sixth logic gate 480. The output of the sixth latch 458 is coupled to the first input of the seventh logic gate 482 and the input of the eighth logic gate 484. The output of the eighth logic gate 484 is coupled to the first input of the ninth logic gate 486. The outputs of the sixth logic gate 480, the seventh logic gate 482, and the ninth logic gate 486 are coupled to the corresponding inputs of the tenth logic gate 488. The outputs of the fifth logic gate 478 (FUNC_COMPARE_ERROR2) and the tenth logic gate 488 (SELF-TEST_ERROR2) can be coupled to the external logic of the dual comparator logic 400. For example, the outputs of the fifth logic gate 478 and the tenth logic gate 488 can be coupled to... Figure 2 The memory 218.

[0089] exist Figures 4A to 4B In the illustrated example, the dual comparator logic 400 is implemented using at least two different clock domains. In this example, the fourth latch 448, the fifth latch 456, and the sixth latch 458 are implemented using the first clock domain. In this example, the first latch 406, the second latch 414, and the third latch 416 are implemented using a second clock domain different from the first clock domain.

[0090] exist Figures 4A to 4B In the illustrated example, the dual comparator logic 400 includes a function for detecting AND... Figure 2 The lockstep encapsulator 200 includes a first error detection logic 418 and a second error detection logic 460 related to lockstep operation, functionality, and other fault conditions or errors. In this example, the dual comparator logic 400 implements two test modes (TM1 and TM2). For example, the dual comparator logic 400 can perform a self-test on the first comparator logic 402 to implement test mode 1 (TM1). In such an example, in response to determining that a self-test is to be performed on the first comparator logic 402, the self-test control logic 405 and / or more generally, the dual comparator logic 400 can enable the first test mode signal (TM1) and / or disable the second test mode signal (TM2). In some examples, the dual comparator logic 400 can perform a self-test on the second comparator logic 404 to implement test mode 2 (TM2). In such an example, in response to determining that a self-test is to be performed on the second comparator logic 404, the self-test control logic 405 and / or more generally the dual comparator logic 400 may invalidate the first test mode signal and / or enable the second test mode signal.

[0091] In some examples, the second input (!TM1 and !COMPARATOR1_SELF-TEST_ERROR_FORCING_MODE) of the fifth logic gate 436 of the first error detection logic 418 is coupled to the self-test control logic 405. For example, the second input of the fifth logic gate 436 may be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input is enabled in response to the dual comparator logic 400 operating at TM2 (e.g., !TM1) and the first comparator logic 402 not performing a self-test (e.g., !COMPARATOR1_SELF-TEST_ERROR_FORCING_MODE).

[0092] In some examples, the second input (TM1_MATCH_TEST) of the sixth logic gate 438 of the first error detection logic 418 is coupled to the self-test control logic 405. For example, the second input of the sixth logic gate 438 may be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input may be made valid in response to a self-test (e.g., a match test) performed on the first comparator logic 402. For example, a match test may be performed by outputting all logic zeros (or logic ones) from the self-test control logic 405 through the first set of multiplexers 420, 422 and the third set of multiplexers 462, 464 to test whether one or more of the first logic gates 428, 430 remain fixed in and / or otherwise latched to a logic one (or logic zero) state.

[0093] In some examples, the second input (TM1_MISMATCH_TEST) of the seventh gate 440 of the first error detection logic 418 is coupled to the self-test control logic 405. For example, the second input of the seventh gate 440 may be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input may be made valid in response to a self-test (e.g., a mismatch test) performed on the first comparator logic 402. For example, the mismatch test may be performed over two cycles. For example, during the first cycle, the first set of multiplexers 420, 422 may output all logic one from the self-test logic 405, and the third set of multiplexers 462, 464 may output all logic zero from the self-test control logic 405 to test whether one or more of the first gates 428, 430 remain fixed in and / or otherwise latched to a logic zero (or logic one) state. In such an example, during the second cycle following the first cycle, the first set of multiplexers 420, 422 can output all logic zeros from the self-test logic 405, and the third set of multiplexers 462, 464 can output all logic ones from the self-test control logic 405 to test whether one or more of the first logic gates 428, 430 remain fixed in and / or otherwise latched to the logic zero (or logic one) state.

[0094] In some examples, the second input (!COMPARATOR1_ERROR_FORCING_MODE and COMPARATOR1_SELF-TEST_ERROR_FORCING_MODE) of the ninth logic gate 444 of the first error detection logic 418 is coupled to the self-test control logic 405. For example, the second input may be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input is made valid in response to the first comparator logic 402 not operating in error-forced mode (!COMPARATOR1_ERROR_FORCING_MODE) and the first comparator logic 402 performing a self-test (which can be indicated by the validity of the signal COMPARATOR1_SELF-TEST_ERROR_FORCING_MODE depicted in the example in the illustration).

[0095] In some examples, in response to the first comparator logic 402 operating in error-forced mode (which can be implemented by activating the signal COMPRATOR1_ERROR_FORCING_MODE depicted in the example in this illustration), the first comparator logic 402 can invert one of the functional outputs from the first bus 489. This may trigger a mismatch, which can be indicated by activating logic one of the fifth logic gate 436.

[0096] In some examples, the second input of the fifth logic gate 478 of the second error detection logic 460 (indicated by the signals !TM2 and !COMPARATOR2_SELF-TEST_ERROR_FORCING_MODE as depicted in the illustrated example) is coupled to the self-test control logic 405. For example, the second input may be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input is enabled in response to the dual comparator logic 400 operating at TM1 (which can be implemented using the signal !TM2 as depicted in the illustrated example) and the second comparator logic 404 not performing a self-test (which can be implemented using the signal !COMPARATOR2_SELF-TEST_ERROR_FORCING_MODE as depicted in the illustrated example).

[0097] In some examples, the second input of the sixth logic gate 480 of the second error detection logic 460 (indicated by the signal TM2_MATCH_TEST as depicted in the example shown in the figure) is coupled to the self-test control logic 405 of the dual comparator logic 400. For example, the second input of the sixth logic gate 480 may be coupled to the output of the self-test control logic 405. In some such examples, the signal at the second input may be made valid in response to a self-test (e.g., a match test) performed on the second comparator logic 404. For example, the match test may be implemented by outputting all logic zeros (or logic one) from the self-test control logic 405 through the second set of multiplexers 424, 426 and the fourth set of multiplexers 466, 468 to test whether one or more of the second logic gates 470, 472 remain fixed in and / or otherwise latched into a logic one state.

[0098] In some examples, the second input of the seventh logic gate 482 of the second error detection logic 460 (indicated by the signal TM2_MISMATCH_TEST as depicted in the example shown in the figure) is coupled to the self-test control logic 405. For example, the second input of the seventh logic gate 482 may be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input may be made valid in response to a self-test (e.g., a mismatch test) performed on the second comparator logic 404. For example, a mismatch test may be implemented by outputting logic one and logic zero from the self-test control logic 405 during the first cycle, respectively, using the second set of multiplexers 424, 426 and the fourth set of multiplexers 466, 468, to test whether one or more of the second logic gates 474, 476 remain fixed in and / or otherwise latched to a logic zero (or logic one) state. In such an example, the mismatch test can be performed by the second set of multiplexers 424, 426 and the fourth set of multiplexers 466, 468 outputting logic zero and logic one from the self-test control logic 405 during the second cycle to test whether one or more of the second logic gates 474, 476 remain fixed in and / or otherwise latched to the logic zero (or logic one) state.

[0099] In some examples, the second input of the ninth logic gate 486 of the second error detection logic 460 (which can be implemented by the signals !COMPARATOR2_ERROR_FORCING_MODE and COMPARATOR2_SELF-TEST_ERROR_FORCING_MODE as depicted in the example shown in the figure) is coupled to the self-test control logic 405. For example, the second input can be coupled to the output of the self-test control logic 405. In some examples, the signal at the second input is made valid in response to the second comparator logic 404 not operating in error-forced mode (which can be implemented by the signal !COMPARATOR2_ERROR_FORCING_MODE as depicted in the example shown in the figure) and the second comparator logic 404 performing a self-test (which can be implemented by the signal COMPARATOR2_SELF-TEST_ERROR_FORCING_MODE as depicted in the example shown in the figure).

[0100] In some examples, in response to the second comparator logic 404 operating in error-forced mode (which can be implemented by activating the signal COMPRATOR2_ERROR_FORCING_MODE depicted in the example in this illustration), the second comparator logic 404 can invert one of the functional outputs from the second bus 490. This may trigger a mismatch, which can be indicated by activating logic one of the fifth logic gate 478.

[0101] In the example operation, the self-test control logic 405 and / or more generally the dual comparator logic 400 can choose to test either the first comparator logic 402 or the second comparator logic 404. Figure 2 The lockstep function of the lockstep encapsulator 200. For example, self-test control logic 405 can select first comparator logic 402 to test the lockstep function. In such an example, self-test control logic 405 calls and / or otherwise instructs first set of multiplexers 420, 422 and third set of multiplexers 462, 464 to pass inputs from buses 489, 490 to first logic gates 428, 430. In some such examples, self-test control logic 405 can make a signal at the second input of the fifth logic gate 436 of the first error detection logic 418 valid to perform a test of the lockstep function. In some examples, in response to the first logic gates 428, 430 detecting that the inputs from buses 489, 490 are matched, the fifth logic gate 436 can output a logic low signal as the FUNC_COMPARE_ERROR1 signal. In some examples, in response to the first logic gates 428 and 430 detecting an input mismatch from buses 489 and 490, the fifth logic gate 436 can output a logic high-level signal as the FUNC_COMPARE_ERROR1 signal.

[0102] In example operation, self-test control logic 405 may select second comparator logic 404 to perform a self-test, which may include a match test and / or a mismatch test. In such an example, self-test control logic 405 may invoke and / or otherwise instruct second multiplexers 424, 426 and fourth multiplexers 466, 468 to pass inputs from self-test control logic 405 to second logic gates 470, 472. In some such examples, self-test control logic 405 may invalidate the signal at the second input of the fifth logic gate 436 of second error detection logic 460 to perform a self-test.

[0103] In some examples, self-test control logic 405 (i) outputs a logic zero (or logic one) to the second set of multiplexers 424, 426 and the fourth set of multiplexers 466, 468 to perform a match test, and (ii) makes TM2_MATCH_TEST valid. In response to the second logic gates 470, 472 not detecting at least one logic one from the second logic gates 470, 472, the sixth logic gate 480 can output a logic low signal to the tenth logic gate 488, indicating that the match test has passed. In response to the second logic gates 470, 472 detecting at least one logic one from the second logic gates 470, 472, the sixth logic gate 480 can output a logic high signal to the tenth logic gate 488, indicating that the match test has failed.

[0104] In some examples, the self-test control logic 405(i) outputs a logic 1 to the second set of multiplexers 424, 426 and a logic 0 to the fourth set of multiplexers 466, 468 during the first cycle, and outputs a logic 0 to the second set of multiplexers 424, 426 and a logic 1 to the fourth set of multiplexers 466, 468 during the second cycle (after the first cycle) to perform a mismatch test, and (ii) makes TM2_MISMATCH_TEST valid. In response to the second logic gates 470, 472 not detecting at least one logic 1 from the second logic gates 470, 472, the sixth logic gate 480 may output a logic low signal to the tenth logic gate 488, indicating that the mismatch test has passed or been successfully completed. In response to the detection of at least one logic 1 from the second logic gates 470 and 472, the sixth logic gate 480 may output a logic high-level signal to the tenth logic gate 488, indicating that the mismatch test has failed or has not been successfully completed.

[0105] In example operation, in response to at least one output logic one from the sixth logic gate 480, the seventh logic gate 482, or the ninth logic gate 486, the tenth logic gate 488 can activate logic one as the SELF-TEST_ERROR2 signal. In some such examples, the activation of the SELF-TEST_ERROR2 signal indicates the detection of a fault condition in the second comparator logic 402, and this indication can be stored as lockstep debugging data 220. Figure 2 In memory 218.

[0106] In the example operation, the self-test control logic 405 and / or more generally the dual comparator logic 400 can select (i) the second comparator logic 404 to test the lockstep function in response to the second comparator logic 404 completing the self-test (e.g., successfully completing the self-test), and select (ii) the first comparator logic 402 to perform the self-test. Advantageously, by testing at least one of the first comparator logic 402 or the second comparator logic 404 at a time, the other of the first comparator logic 402 or the second comparator logic 404 can remain online to test the lockstep function. Figure 2 Lockstep associated with main hardware 202 and auxiliary hardware 204.

[0107] Figure 5 It describes Figure 1 Example LCL 104 Figure 2 Lockstep comparison control logic 210 Figure 3 Comparator logic 300 and / or Figures 4A to 4B Timing diagram 500 for example operation of dual comparator logic 400. Timing diagram 500 includes example waveforms 502, 504, 506, 508, 510, 512, 514, and 516, including a first example waveform 502, a second example waveform 504, a third example waveform 506, a fourth example waveform 508, a fifth example waveform 510, a sixth example waveform 512, a seventh example waveform 514, and an eighth example waveform 516. Specifically, the first waveform 502, the second waveform 504, the third waveform 506, the fifth waveform 510, and / or the sixth waveform 512 may correspond to (i) a single comparator implementation (e.g., Figure 3 (i) Comparator logic 300) and (ii) Dual comparator implementation (e.g., Figures 4A to 4B The signals associated with both the dual comparator logic 400 and the second comparator (e.g., the second comparator in the dual comparator example). In some examples, the fourth waveform 508, the seventh waveform 514, and the eighth waveform 516 may correspond to the signals associated with the second comparator in the dual comparator example (e.g., the second comparator in the dual comparator example). Figures 4A to 4B The signals associated with the first comparator logic 402 and / or the second comparator logic 404 of the dual comparator logic 400.

[0108] The first waveform 502 implements a clock signal. For example, the first waveform 502 can implement a clock signal. Figure 3 The first latch 318, the second latch 320, the third latch 340, and / or the fourth latch 342 receive the clock signal (CLK). In some examples, the first waveform 502 can be implemented by... Figures 4A to 4B The clock signal (CLK) received by the first latch 406, the second latch 414, the third latch 416, the fourth latch 448, the fifth latch 456 and / or the sixth latch 458.

[0109] The second waveform 504 implements the self-test enable signal. For example, the self-test enable signal can be generated by... Figure 2 Self-test control logic 212 Figure 3 Self-test control logic 322 and / or Figures 4A to 4B The self-test control logic 405 is used for implementation. In some examples, the self-test enable signal can be implemented. Figure 3 The signal SELF-TEST_MODE is described in the diagram. In some examples, self-test control logic 212, self-test control logic 322, and / or self-test control logic 405 can enable the self-test enable signal to initiate and / or otherwise trigger the test. Figure 2 First comparator logic 214 and / or second comparator logic 216 Figure 3 Comparator logic 300 and / or Figures 4A to 4B Self-test of the first comparator logic 402 and / or the second comparator logic 404.

[0110] The third waveform 506 implements the first comparator logic (e.g., ...). Figure 2 First comparator logic 214 Figure 3 Comparator logic 300 and / or Figures 4A to 4B The first comparator logic 402 operates. The fourth waveform 508 implements the second comparator logic (e.g., Figure 2 The second comparator logic 216 Figure 3 Comparator logic 300 and / or Figures 4A to 4B The operation of the second comparator logic 404).

[0111] The fifth waveform 510 implements the first test mode matching signal (TM1_MATCH_TEST). In some examples, the fifth waveform 510 may implement... Figure 3 The MATCH_TEST signal and / or Figures 4A to 4B The TM1_MATCH_TEST signal. The sixth waveform 512 implements the first test mode mismatch signal (TM1_MISMATCH_TEST). In some examples, the sixth waveform 512 may implement... Figure 3 The MISMATCH_TEST signal and / or Figures 4A to 4B The TM1_MISMATCH_TEST signal.

[0112] The seventh waveform 514 implements the second test mode matching signal (TM2_MATCH_TEST). In some examples, the seventh waveform 514 may implement... Figure 3 The MATCH_TEST signal and / or Figures 4A to 4BThe TM2_MATCH_TEST signal. The eighth waveform 516 implements the second test mode mismatch signal (TM2_MISMATCH_TEST). In some examples, the seventh waveform 516 may implement... Figure 3 The MISMATCH_TEST signal and / or Figures 4A to 4B The TM2_MISMATCH_TEST signal.

[0113] exist Figure 5 In the timing diagram 500, at the first example time (T1) 518, the self-test control logic 212 can activate the second waveform 504, and at the second example time (T2) 520, it deactivates the second waveform 504. In response to this deactivation, the self-test control logic 212 activates the fifth waveform 510 to trigger a match test on the first comparator logic, thereby implementing test mode 1. For example, the self-test control logic 212 can... Figures 4A to 4B TM1_MATCH_TEST is enabled to perform a match test on the first comparator logic 402 from the second time 520 until the third example time (T3) 522, as described above. Figure 2 , Figure 3 and / or Figures 4A to 4B As described. Advantageously, the first comparator logic 402 can perform a match test on the first comparator logic 402 within two clock cycles of the first waveform 502.

[0114] At the third time 522, the self-test control logic 212 invalidates the fifth waveform 510 and enables the sixth waveform 512 to trigger a mismatch test on the first comparator logic. For example, the self-test control logic 212 can... Figures 4A to 4B TM1_MISMATCH_TEST is enabled to perform a mismatch test on the first comparator logic 402 from the third time 522 to the fourth example time (T4) 524, in order to implement test mode 1, as described above. Figure 2 , Figure 3 and / or Figures 4A to 4B As described. Advantageously, the first comparator logic 402 can perform a mismatch test on the first comparator logic 402 within two clock cycles of the first waveform 502. Advantageously, the first comparator logic 402 can perform a self-test (e.g., a match test and a mismatch test) on the first comparator logic 402 within four clock cycles of the first waveform 502.

[0115] At the fourth time 524, the self-test control logic 212 invalidates the sixth waveform 512 and enables the seventh waveform 514 to trigger a match test on the second comparator logic, thereby implementing test mode 2. In response to the invalidation of the sixth waveform 512, the self-test of the first comparator logic 402 is completed, and it can return to the function operation with the comparison function enabled. At the fourth time 524, the self-test control logic 212 can... Figures 4A to 4B TM2_MATCH_TEST is enabled to perform a match test on the second comparator logic 404 from the fourth time 524 until the fifth example time (T5) 526, as described above. Figure 2 , Figure 3 and / or Figures 4A to 4B As described. Advantageously, the second comparator logic 404 can perform a match test on the second comparator logic 404 within two clock cycles of the first waveform 502.

[0116] At time 526, the self-test control logic 212 invalidates the seventh waveform 514 and enables the eighth waveform 516 to trigger a mismatch test on the second comparator logic, thereby implementing test mode 2. For example, the self-test control logic 212 can... Figures 4A to 4B TM2_MISMATCH_TEST is enabled to perform a mismatch test on the second comparator logic 404 from the fifth time 526 to the sixth example time (T6) 528, as described above. Figure 2 , Figure 3 and / or Figures 4A to 4B As described. In response to the invalidation of the eighth waveform 516, the self-test of the second comparator logic 404 is completed, and it can return to the function operation with the comparator function enabled.

[0117] Advantageously, the second comparator logic 404 can perform a mismatch test on the second comparator logic 404 within two clock cycles of the first waveform 502. Advantageously, the second comparator logic 404 can perform a self-test (e.g., a match test and a mismatch test) on the second comparator logic 404 within four clock cycles of the first waveform 502. Advantageously, Figures 4A to 4B The dual comparator logic 400 can perform the entire self-test (e.g., match and mismatch test for the first comparator logic 402 and match and mismatch test for the second comparator logic 404) within eight clock cycles of the first waveform 502.

[0118] Figures 6 to 7 The diagram shows the representation used for implementation. Figure 1 Example LCL 104 Figure 2 Example lockstep package 200 or its(multiple) parts, Figure 3 Example comparator logic 300 and / or Figures 4A to 4BThe example flowcharts include example procedures, hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof for a dual comparator logic 400. The procedures and / or machine-readable instructions can be derived from, for example, the following combinations... Figure 8 The example processor platform 800 described herein refers to a computer processor and / or processor circuitry, such as processor 812, executing one or more executable programs or portions thereof. This program may be embodied as software associated with processor 812 stored on a non-transitory computer-readable storage medium; however, the entire program and / or portions thereof may alternatively be executed by devices other than processor 812 and / or embodied as firmware or dedicated hardware, such as CD-ROMs, floppy disks, hard disks, DVDs, Blu-ray discs, or memory. Further, although references... Figures 6 to 7 The flowchart shown illustrates an example program, but alternative implementations can be used. Figure 1 Example LCL 104 Figure 2 Example lockstep package 200 or its(multiple) parts, Figure 3 Example comparator logic 300 and / or Figures 4A to 4B The example dual comparator logic 400 can be implemented in many other ways. For example, the execution order of the blocks can be changed and / or some blocks in the described blocks can be changed, eliminated, or combined. Alternatively or additionally, any or all blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware. The processor circuit system can be distributed across different network locations and / or located locally on one or more devices (e.g., a multi-core processor in a single machine, multiple processors distributed across a server rack, etc.).

[0119] The machine-readable instructions described herein can be stored in one or more formats, such as compressed, encrypted, segmented, compiled, executable, and packaged formats. Machine-readable instructions as described herein can be stored as data or data structures (e.g., portions of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, at the edge, etc.) within a network or set of networks. Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, reassigned, compiled, etc., so that they can be directly read, interpreted, and / or executed by computing devices and / or other machines. For example, machine-readable instructions can be stored in multiple parts that are independently compressed, encrypted, and stored on separate computing devices, wherein these parts, when decrypted, decompressed, and combined, form a set of executable instructions that perform one or more functions, which together can form a program such as that described herein.

[0120] In another example, machine-readable instructions may be stored in a state where they can be read by the processor circuitry but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute these instructions on a specific computing device or other device. In yet another example, the machine-readable instructions may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed, wholly or partially. Therefore, as used herein, machine-readable media may include machine-readable instructions and / or ...

[0121] The machine-readable instructions described in this article can be represented using any past, present, or future instruction set, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0122] As described above, it can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on non-transitory computer and / or machine-readable media (such as hard disk drives, flash memory, read-only memory, optical discs, digital versatile optical discs, caches, random access memory, and / or any other storage device or disk capable of storing information for any duration (e.g., extended time periods, permanent, short-term, temporary caching, and / or caching of information)). Figures 6 to 7 Example process. As used herein, the term nontransitory computer-readable medium is explicitly defined to include any type of computer-readable storage device and / or storage disk, excluding propagating signals and transmission media.

[0123] "Including" and "comprising" (and all their forms and tenses) are used as open-ended terms. Therefore, any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) indicates that additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, the phrase "at least" is open-ended, as are the terms "comprising" and "including." The term "and / or," when used, for example, in the form of A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, and (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" refers to an implementation that includes any of the following: (1) at least one A; (2) at least one B; and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" refers to an implementation that includes any of the following: (1) at least one A; (2) at least one B; and (3) at least one A and at least one B. As used herein in the context of describing the conduct or execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" refers to an implementation that includes any of the following: (1) at least one A; (2) at least one B; and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the conduct or execution of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A; (2) at least one B; and (3) at least one A and at least one B.

[0124] As used herein, singular references (e.g., "a," "first," "second," etc.) do not exclude plural. As used herein, the term "a" refers to one or more of the same entity. The terms "a," "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or method actions may be implemented by, for example, a single unit or processor. Moreover, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that the combination of features is impractical and / or disadvantageous.

[0125] Figure 6 This is a flowchart representing example process 600, which can be implemented using executable machine-readable instructions and / or using methods configured to... Figure 1 LCL 104, Figure 2 Lockstep package 200 or its(multiple) parts, Figure 3 Comparator logic 300 and / or Figures 4A to 4B The dual comparator logic 400 is executed in hardware to detect errors associated with at least one comparator.

[0126] Process 600 begins at box 602, in which... Figure 3 Comparator logic 300 determines whether self-test is enabled. For example, selection logic 304 may determine that self-test is enabled in response to a signal indication from self-test control logic 322 indicating that a self-test will be performed.

[0127] If, in block 602, comparator logic 300 determines that self-test is not yet enabled, control proceeds to block 604 to compare the functional output from the hardware. For example, Figure 3 The first logic gates 332 and 334 can handle logic inputs from... Figure 2 The outputs of the main module 202 and the auxiliary module 204 are compared.

[0128] In block 606, comparator logic 300 determines whether the functional outputs are different. For example, in response to different inputs from the first bus 314 and the second bus 316, the fifth logic gate 344 can make the logic high active as... Figure 3 The FUNC_COMPARE_ERROR. In some examples, in response to the same inputs from the first bus 314 and the second bus 316, the fifth logic gate 344 can output a logic low level as FUNC_COMPARE_ERROR.

[0129] If, in box 606, comparator logic 300 determines that the functional outputs are not different, control returns to box 602 to determine whether self-test is enabled. If, in box 606, comparator logic 300 determines that the functional outputs are different, then in box 608, comparator logic 300 outputs a functional comparison error. For example, an indication of a fault condition responding to FUNC_COMPARE_ERROR being valid at a logic high can be stored... Figure 2 In memory 218. In some examples, Figure 2 The resources of the computing system 102 can generate alarms indicating fault conditions. For example, the user interface 124 can display the alarms, and the interface resource 114 can access them via... Figure 1 Network 126 transmits alarms to central facility 128, and / or combinations thereof. In response to a function comparison error in box 608, Figure 6 The process ends at 600.

[0130] If, in block 602, comparator logic 300 determines that self-test is enabled, control proceeds to block 610 to determine whether a match test is enabled. For example, selection logic 304 and / or error detection logic 312 may respond to a selection signal from self-test control logic 322 and / or to a signal from that self-test control logic. Figure 3 The validity of MATCH_TEST confirms that match testing is enabled.

[0131] If, in block 610, comparator logic 300 determines that a match test is not enabled, control proceeds to block 618 to determine whether a mismatch test is enabled. If, in block 610, comparator logic 300 determines that a match test is enabled, then in block 612, comparator logic 300 compares the output from the self-test logic. For example, self-test control logic 322 may output logic zero to multiplexers 324, 326, 328, and 330 during a first cycle, a first time period, etc. In such an example, first logic gates 332 and 334 may compare the outputs from multiplexers 324, 326, 328, and 330 to determine whether a match is detected. In some such examples, self-test control logic 322 may output logic one to multiplexers 324, 326, 328, and 330 during a second cycle (after the first cycle), a second time period (after the first time period), etc. In such an example, the first logic gates 332 and 334 can compare the outputs from multiplexers 324, 326, 328, and 330 to determine whether a match has been detected.

[0132] In block 614, comparator logic 300 determines whether a match is detected based on comparisons of these outputs. For example, third logic gate 336 may determine whether at least one logic 1 has been output from one or more first logic gates 332 and 334 during the first cycle. In such an example, in response to third logic gate 336 determining that at least one logic 1 has been output from one or more first logic gates 332 and 334, sixth logic gate 346 may output a logic high level to eighth logic gate 350. In some such examples, third logic gate 336 may determine whether at least one logic zero has been output from one or more first logic gates 332 and 334 during the second cycle. In such an example, in response to third logic gate 336 determining that at least one logic zero has been output from one or more first logic gates 332 and 334, sixth logic gate 346 may output a logic high level to eighth logic gate 350.

[0133] If, in block 614, comparator logic 300 determines a match has been detected based on a comparison of these outputs, control proceeds to block 618 to determine whether a mismatch test is enabled. If, in block 614, comparator logic 300 determines no match has been detected based on a comparison of these outputs, then in block 616, comparator logic 300 outputs a self-test error. For example, the eighth logic gate 350 can make logic high active as Figure 3 The SELF-TEST_ERROR output. In some examples, fault indications regarding self-test errors, program counter values ​​associated with self-test errors, etc., can be stored in memory 218 as lockstep debugging data 220. In some examples, Figure 2 The resources of the computing system 102 can generate alerts indicating self-test errors. For example, the user interface 124 can display the alerts, and the interface resource 114 can access them via... Figure 1 Network 126 transmits alarms to central facility 128, and / or combinations thereof.

[0134] In response to a self-test error output in block 616, comparator logic 300 in block 618 determines whether mismatch testing is enabled. For example, selection logic 304 and / or error detection logic 312 may respond to a selection signal from self-test control logic 322 and / or respond to a signal from that self-test control logic. Figure 3 The validity of MISMATCH_TEST confirms that mismatch testing is enabled.

[0135] If, at block 618, comparator logic 300 determines that mismatch testing is not enabled, control proceeds to block 626 to determine whether to continue monitoring the hardware. If, at block 618, comparator logic 300 determines that mismatch testing is enabled, then at block 620, comparator logic 300 compares the output from the self-test logic. For example, during the first cycle, self-test control logic 322 may output logic one to the first portion of multiplexers 324, 326, 328, and 330, and logic zero to the second portion of multiplexers 324, 326, 328, and 330. In such an example, first logic gates 332 and 334 may compare the outputs from multiplexers 324, 326, 328, and 330 to determine whether a mismatch has been detected. In some such examples, during a second cycle following the first cycle, the self-test control logic 322 can output logic zero to the first part of multiplexers 324, 326, 328, and 330, and logic one to the second part of multiplexers 324, 326, 328, and 330. In such examples, first logic gates 332 and 334 can compare the outputs from multiplexers 324, 326, 328, and 330 to determine whether a mismatch has been detected.

[0136] In block 622, comparator logic 300 determines whether a mismatch has been detected based on comparisons of these outputs. For example, a fourth logic gate 338 may determine whether at least one logic zero has been output from one or more first logic gates 332, 334 during a first cycle, a second cycle, etc. In such an example, in response to the fourth logic gate 338 determining that at least one logic zero has been output from one or more first logic gates 332, 334 during a first cycle, a seventh logic gate 348 may output a logic high level to an eighth logic gate 350.

[0137] If, in block 622, comparator logic 300 determines, based on the comparison of these outputs, that a mismatch has not yet been detected, control proceeds to block 626 to determine whether to continue monitoring the hardware. If, in block 622, comparator logic 300 determines, based on the comparison of these outputs, that a mismatch has been detected, then in block 624, comparator logic 300 outputs a self-test error. For example, the eighth logic gate 350 can make logic high active as... Figure 3 The SELF-TEST_ERROR output. In some examples, fault indications regarding self-test errors, program counter values ​​associated with self-test errors, etc., can be stored in memory 218 as lockstep debugging data 220. In some examples, Figure 2 The resources of the computing system 102 can generate alerts indicating self-test errors. For example, the user interface 124 can display the alerts, and the interface resource 114 can access them via... Figure 1Network 126 transmits alarms to central facility 128, and / or combinations thereof.

[0138] In response to comparator logic 300 outputting a self-test error in box 624, comparator logic 300 determines in box 626 whether to continue monitoring the hardware. If, in box 626, comparator logic 300 determines to continue monitoring the hardware, control returns to box 602 to determine whether self-test is enabled; otherwise... Figure 6 The process ends at 600.

[0139] Figure 7 This is another flowchart representing example process 700, which can be implemented using executable machine-readable instructions and / or using methods configured to... Figure 1 LCL 104, Figure 2 The lockstep package 200 or its(multiple) parts and / or Figures 4A to 4B The hardware executes a dual comparator logic 400 to detect errors associated with at least two comparators.

[0140] Process 700 begins at box 702, in which... Figures 4A to 4B The dual comparator logic 400 identifies the comparator that is performing a self-test. For example, the first selection logic 408 can respond to a signal from... Figures 4A to 4B The self-test control logic 405 identifies that the first comparator logic 402 is performing a self-test by a signal, which can instruct the first comparator logic 402 to perform a self-test (e.g., a match test, a mismatch test, etc.).

[0141] In block 704, dual comparator logic 400 uses a comparator that is not performing a self-test to compare the functional output from the hardware. For example, the second logic gate 470 can compare the output from... Figure 2 The outputs of the main module 202 and the auxiliary module 204 are compared.

[0142] In block 706, dual comparator logic 400 determines whether the functional outputs are different. For example, in response to different inputs from the first bus 489 and the second bus 490, the fifth logic gate 478 can make the logic high active as... Figures 4A to 4B FUNC_COMPARE_ERROR2. In some examples, in response to the same inputs from the first bus 489 and the second bus 490, the fifth logic gate 478 can output a logic low level as FUNC_COMPARE_ERROR2.

[0143] If, in block 706, the dual comparator logic 400 determines that the functional outputs are not different, control proceeds to block 710 to determine whether a match test is enabled. If, in block 706, the dual comparator logic 400 determines that the functional outputs are different, then in block 708, the dual comparator logic 400 outputs a functional comparison error from a comparator that is not performing a self-test. For example, an indication of a fault condition in response to FUNC_COMPARE_ERROR2 being valid at a logic high can be stored... Figure 2 In memory 218. In some examples, Figure 2 The resources of the computing system 102 can generate alarms indicating fault conditions. For example, the user interface 124 can display the alarms, and the interface resource 114 can access them via... Figure 1 Network 126 transmits alarms to central facility 128, and / or combinations thereof.

[0144] In response to a function comparison error output in block 708, control proceeds to block 710 to determine whether a match test is enabled. For example, first selection logic 408 and / or first error detection logic 418 may respond to a selection signal from self-test control logic 405 and / or respond to a signal from that self-test control logic. Figures 4A to 4B The validity of TM1_MATCH_TEST confirms that match testing is enabled.

[0145] If, in block 710, the dual comparator logic 400 determines that the match test is not enabled, control proceeds to block 718 to determine whether the mismatch test is enabled. If, in block 710, the dual comparator logic 400 determines that the match test is enabled, then in block 712, the dual comparator logic 400 compares the output from the self-test logic. For example, the self-test logic 405 may output logic zero to the first set of multiplexers 420, 422 and the third set of multiplexers 462, 464 during a first cycle, a first time period, etc. In such an example, the first logic gates 428, 430 may compare the outputs from the first set of multiplexers 420, 422 and the third set of multiplexers 462, 464 to determine whether a match is detected. In some such examples, the self-test logic 405 may output logic one to the first set of multiplexers 420, 422 and the third set of multiplexers 462, 464 during a second cycle after the first cycle, a second time period after the first time period, etc. In such an example, the first logic gates 428 and 430 can compare the outputs from the first set of multiplexers 420 and 422 and the third set of multiplexers 462 and 464 to determine whether a match is detected.

[0146] In block 714, dual comparator logic 400 determines whether a match has been detected based on comparisons of these outputs. For example, a third logic gate 432 can determine whether at least one logic 1 has been output from one or more of the first logic gates 428 and 430, which could indicate that a match has not yet been detected. In such an example, in response to the third logic gate 432 determining that at least one logic 1 has been output from one or more of the first logic gates 428 and 430, a sixth logic gate 438 can output a logic high level to a tenth logic gate 446.

[0147] If, in block 714, the dual comparator logic 400 determines a match has been detected based on a comparison of these outputs, control proceeds to block 718 to determine whether a mismatch test has been enabled. If, in block 714, the dual comparator logic 400 determines that a match has not yet been detected based on a comparison of these outputs, then in block 716, the dual comparator logic 400 outputs a self-test error from the comparator that is performing a self-test. For example, the tenth logic gate 446 can make the logic high active as Figure 3 The SELF-TEST_ERROR1 output. In some examples, fault indications regarding self-test errors, program counter values ​​associated with self-test errors, etc., can be stored in memory 218 as lockstep debugging data 220. In some examples, Figure 2 The resources of the computing system 102 can generate alerts indicating self-test errors. For example, the user interface 124 can display the alerts, and the interface resource 114 can access them via... Figure 1 Network 126 transmits alarms to central facility 128, and / or combinations thereof.

[0148] In response to a self-test error output from the comparator performing the self-test in block 716, dual comparator logic 400 in block 718 determines whether mismatch testing is enabled. For example, first selection logic 408 and / or first error detection logic 418 may respond to a selection signal from self-test control logic 405 and / or respond to a signal from that self-test control logic. Figures 4A to 4B The validity of TM1_MISMATCH_TEST confirms that mismatch testing is enabled.

[0149] If, at block 718, the dual comparator logic 400 determines that mismatch testing is not enabled, control proceeds to block 726 to determine whether to continue monitoring the hardware. If, at block 718, the dual comparator logic 400 determines that mismatch testing is enabled, then at block 720, the dual comparator logic 400 compares the output from the self-test logic. For example, the self-test logic 405 may output logic one to the first set of multiplexers 420, 422 and logic zero to the third set of multiplexers 462, 464 during a first cycle, a first time period, etc. In such an example, the first logic gates 428, 430 may compare the outputs from the first set of multiplexers 420, 422 and the third set of multiplexers 462, 464 to determine whether a mismatch has been detected. In some such examples, self-test logic 405 can output logic zero to the first set of multiplexers 420, 422 and logic one to the third set of multiplexers 462, 464 during a second period after the first period, a second time period after the first time period, etc. In such examples, first logic gates 428, 430 can compare the outputs from the first set of multiplexers 420, 422 and the third set of multiplexers 462, 464 to determine whether a mismatch has been detected.

[0150] In block 722, dual comparator logic 400 determines whether a mismatch has been detected based on comparisons of these outputs. For example, a fourth logic gate 434 can determine whether at least one logic zero has been output from one or more of the first logic gates 428 and 430, which could indicate a mismatch has been detected. In such an example, in response to the fourth logic gate 434 determining that at least one logic zero has been output from one or more of the first logic gates 428 and 430, a seventh logic gate 440 can output a logic high level to a tenth logic gate 446.

[0151] If, in block 722, the dual comparator logic 400 determines that no mismatch has been detected based on a comparison of these outputs, control proceeds to block 726 to determine whether to continue monitoring the hardware. If, in block 722, the dual comparator logic 400 determines that a mismatch has been detected based on a comparison of these outputs, then in block 724, the dual comparator logic 400 outputs a self-test error from the comparator that is performing a self-test. For example, the tenth logic gate 446 can make the logic high active as Figures 4A to 4B The SELF-TEST_ERROR1 output. In some examples, fault indications regarding self-test errors, program counter values ​​associated with self-test errors, etc., can be stored in memory 218 as lockstep debugging data 220. In some examples, Figure 2 The resources of the computing system 102 can generate alerts indicating self-test errors. For example, the user interface 124 can display the alerts, and the interface resource 114 can access them via... Figure 1 Network 126 transmits alarms to central facility 128, and / or combinations thereof.

[0152] In response to a self-test error output from the comparator performing the self-test in box 724, dual comparator logic 400 determines whether to continue monitoring the hardware. If, in box 726, dual comparator logic 400 determines to continue monitoring the hardware, control returns to box 702 to select a comparator for the self-test; otherwise... Figure 7 The process ends at 700.

[0153] Figure 8 This is a block diagram of an example processor platform 800, which is configured to execute... Figures 6 to 7 Instructions to be implemented Figure 1 LCL 104, Figure 2 Lockstep package 200 or its(multiple) parts, Figure 3 Comparator logic 300 and / or Figures 4A to 4B The dual comparator logic 400. The processor platform 800 can be, for example, a vehicle's electronic control unit, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a game console, or any other type of computing device.

[0154] The illustrated example processor platform 800 includes two processors 812. The two processors 812 in the illustrated example are hardware. For example, the processors 812 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processors can be semiconductor-based (e.g., silicon-based) devices.

[0155] The illustrated example processor 812 includes local memory 813 (e.g., cache). The illustrated example processor 812 communicates via bus 818 with main memory, including volatile memory 814 and non-volatile memory 816. Volatile memory 814 may consist of one or more flip-flops, synchronous dynamic random access memory (SDRAM), or dynamic random access memory (DRAM). Dynamic Random Access Memory It may be implemented using flash memory and / or any other type of random access memory device. The non-volatile memory 816 may be implemented using flash memory and / or any other desired type of memory device. Access to the main memory 814, 816 is controlled by the memory controller.

[0156] The illustrated example processor platform 800 also includes interface circuitry 820. Interface circuitry 820 can be implemented using any type of interface standard, such as an Ethernet interface, Universal Serial Bus (USB), etc. Interfaces, Near Field Communication (NFC) interfaces and / or PCI Fast Interfaces.

[0157] In the illustrated example, one or more input devices 822 are connected to interface circuitry 820. The input devices 822 allow users to input data and / or commands into processor 812. The input devices may be implemented as, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, equidistant point devices, and / or voice recognition systems.

[0158] One or more output devices 824 are also connected to the interface circuitry 820 of the illustrated example. The output devices 824 may be implemented, for example, by display devices (e.g., light-emitting diode (LED), organic light-emitting diode (OLED), liquid crystal display (LCD), cathode ray tube (CRT) display, flat panel display (IPS), touchscreen, etc.), haptic output devices, printers, and / or speakers. The interface circuitry 820 of the illustrated example may include a graphics driver card, a graphics driver chip, and / or a graphics driver processor.

[0159] The illustrated example interface circuit 820 also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external machines (e.g., any type of computing device) via network 826. Communication can be performed via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, line-to-line wireless systems, cellular telephone systems, etc.

[0160] The illustrated example processor platform 800 also includes one or more mass storage devices 828 for storing software and / or data. Examples of such mass storage devices 828 include floppy disk drives, hard disk drives, optical disk drives, Blu-ray disc drives, redundant array of independent disks (RAID) systems, and digital universal optical disc (DVD) drives.

[0161] Figures 6 to 7 The machine-executable instructions 832 can be stored in mass storage device 828, in volatile memory 814, in non-volatile memory 816 and / or on a removable, non-transitory computer-readable storage medium such as a CD or DVD.

[0162] Example LCL 834 is coupled via bus 818 to one or more of the following: processor 812, volatile memory 814, non-volatile memory 816, interface 820, and / or one or more mass storage devices 828. In some examples, LCL 834 may be... Figure 1LCL 104, Figure 2 Lockstep package 200 or its(multiple) parts, Figure 3 Comparator logic 300 and / or Figures 4A to 4B The dual comparator logic 400 is used for implementation. For example, the LCL 834 can test the lockstep of the processor 812. In some examples, as described herein, the LCL 834 can perform self-tests on one or more comparators included in the LCL 834 and / or otherwise implemented by the LCL.

[0163] As can be understood from the foregoing, example methods, apparatuses, and articles of art for implementing lockstep comparators have been described. Advantageously, the example methods, apparatuses, and articles of art described herein can implement dual comparators with online test sequencing. For example, the example methods, apparatuses, and articles of art described herein can implement intelligent redundancy of comparators for lockstep testing of two or more hardware resources. Advantageously, the example methods, apparatuses, and articles of art described herein can implement diagnostics to minimize the self-test time of the lockstep comparator and / or otherwise reduce the self-test time of the lockstep comparator to eight cycles, regardless of the number of signals being compared.

[0164] Advantageously, the example methods, apparatus, and artifacts described herein can freeze the comparison state of one or more lockstep comparators in response to the detection of a mismatched comparison, and can make the comparison state (along with other debug data, such as associated program counter values) readable and / or otherwise available to the application and / or other hardware resources. Advantageously, the example methods, apparatus, and artifacts described herein can enable lockstepping even during the self-test execution of one or more lockstep comparators. For example, the example methods, apparatus, and artifacts described herein can perform lockstep self-tests during application execution without compromising application integrity.

[0165] This document describes example methods, apparatuses, systems, and articles of art for implementing lockstep comparators. Further examples and combinations thereof include the following:

[0166] Example 1 includes an apparatus comprising: a self-test logic circuit system having a first output; and comparator logic including: selection logic having a first input and a second output, each of the first inputs being coupled to the first outputs; a first detection logic having a second input and a third output, the second inputs being coupled to the second outputs; a second detection logic having a third input and a fourth output, the third inputs being coupled to the third outputs; latching logic having a fifth input and a fifth output, the third output and the fourth output being coupled to the fifth inputs; and error detection logic having a sixth input coupled to the fifth inputs.

[0167] Example 2 includes the apparatus according to Example 1, wherein the selection logic includes a plurality of multiplexers, each of the plurality of multiplexers having a corresponding first input of the first inputs and a corresponding second output of the second outputs.

[0168] Example 3 includes the apparatus according to Example 2, the apparatus further comprising: a first latch having a seventh input and a sixth output, the seventh input being coupled to one or more seventh outputs of a first processor; and a second latch having an eighth input and an eighth output, the eighth input being coupled to one or more ninth outputs of a second processor, the first processor being configured to operate in a lockstep manner with the second processor.

[0169] Example 4 includes the apparatus according to Example 3, wherein the sixth output is coupled to a corresponding first input of a first group of multiplexers in the plurality of multiplexers, and the eighth output is coupled to a corresponding second input of a second group of multiplexers in the plurality of multiplexers, the first group being different from the second group.

[0170] Example 5 includes the apparatus according to Example 1, wherein the first detection logic includes a plurality of logic gates having the second inputs and the third outputs.

[0171] Example 6 includes the apparatus according to Example 5, wherein each of the plurality of logic gates is an XOR logic gate.

[0172] Example 7 includes the apparatus according to Example 1, wherein the latching logic includes: a first latch having a seventh input and a sixth output, the seventh input being coupled to the second detection logic and the sixth output being coupled to the error detection logic; and a second latch having an eighth input and a seventh output, the eighth input being coupled to the second detection logic and the seventh output being coupled to the error detection logic.

[0173] Example 8 includes the apparatus according to Example 7, wherein the second detection logic includes a first logic gate and a second logic gate, the first logic gate and the second logic gate having each of the third inputs a third output and the fourth outputs, the seventh input being coupled to the first logic gate through the first of the fourth outputs, and the eighth input being coupled to the second logic gate through the second of the fourth outputs.

[0174] Example 9 includes the apparatus according to Example 8, wherein the first logic gate is an OR logic gate and the second logic gate is a NAND logic gate.

[0175] Example 10 includes the apparatus according to Example 7, wherein the error detection logic includes: a first logic gate having a ninth input coupled to the sixth output; a second logic gate having a tenth input and a ninth output coupled to the sixth output; a third logic gate having an eleventh input and a tenth output coupled to the seventh output; and a fourth logic gate having a twelfth input and a thirteenth input coupled to the ninth output and the thirteenth input coupled to the tenth output.

[0176] Example 11 includes the apparatus according to Example 10, wherein the first logic gate, the second logic gate, and the third logic gate are AND logic gates, and the fourth logic gate is an OR logic gate.

[0177] Example 12 includes the apparatus according to Example 1, wherein the latching logic is a first latching logic, the apparatus further includes a second latching logic, the selection logic is coupled to a first processor and a second processor via the second latching logic, and the self-test logic circuitry is configured to: in response to a first control signal, instruct the error detection logic to test whether a first processor output from the first processor matches a second processor output from the second processor; and in response to a second control signal, instruct the error detection logic to perform a self-test on the first detection logic.

[0178] Example 13 includes the apparatus according to Example 12, wherein the self-test includes a first self-test and a second self-test, and the self-test logic circuitry is configured to: invoke the first self-test to execute within two clock cycles; and invoke the second self-test to execute within two clock cycles, wherein the first detection logic is configured to execute the self-test within four clock cycles based on the first self-test and the second self-test.

[0179] Example 14 includes the apparatus according to Example 12, wherein the error detection logic is configured to: identify a first fault condition in response to determining that the first processor output does not match the second processor output; identify a second fault condition in response to a self-test failure; and transmit lockstep debug data to a user interface in response to identifying at least one of the first fault condition or the second fault condition, the lockstep debug data including at least one of port information or program counter information associated with at least one of the first fault condition or the second fault condition.

[0180] Example 15 includes an apparatus comprising: first comparator logic configured to receive a first input from a first processor and a second input from a second processor; second comparator logic coupled to the first comparator logic and configured to receive the first input and the second input; and a self-test logic circuitry coupled to the first comparator logic and the second comparator logic, the self-test logic circuitry being configured to, in response to one or more first control signals, instruct the first comparator logic to compare the first input and the second input, and instruct the second comparator logic to perform a self-test on the second comparator logic.

[0181] Example 16 includes the apparatus according to Example 15, wherein the self-test logic circuitry is configured to, in response to generating one or more second control signals,: instruct the first comparator logic to perform a self-test on the first comparator logic; and instruct the second comparator logic to compare a third input of the first processor with a fourth input of the second processor, the first processor being configured to operate in a lockstep manner with the second processor.

[0182] Example 17 includes the apparatus according to Example 15, wherein the first comparator logic includes: selection logic; first detection logic coupled to the selection logic; second detection logic coupled to the first detection logic; a first latch coupled to the second detection logic; a second latch coupled to the second detection logic; and error detection logic coupled to the first latch and the second latch.

[0183] Example 18 includes the apparatus according to Example 17, wherein the selection logic is a first selection logic, and the second comparator logic includes a second selection logic coupled to the first detection logic.

[0184] Example 19 includes the apparatus according to Example 17, wherein the first latch has a first input and a first output, the second latch has a second input and a second output, and the error detection logic includes: a first logic gate having a third input and a third output, the third input being coupled to the first output; a second logic gate having a fourth input and a fourth output, the fourth input being coupled to the first output; a third logic gate having a fifth input and a fifth output, the fifth input being coupled to the second output; and a fourth logic gate having a sixth input, a seventh input, and a sixth output, the sixth input being coupled to the fourth output, and the seventh input being coupled to the fifth output.

[0185] Example 20 includes the apparatus according to Example 19, wherein at least one of the third output or the sixth output is coupled to a memory.

[0186] Example 21 includes a system comprising: first processor hardware having a first output; second processor hardware having a second output; and lockstep control logic comprising: first comparator logic having a third input and a fourth input coupled to the first output; second comparator logic having a fifth input and a sixth input coupled to the second output; and self-test control logic having a third output and a fourth output coupled to the fourth input, the fourth output being coupled to the sixth input.

[0187] Example 22 includes the system according to Example 21, wherein the self-test control logic is configured to: perform a first self-test on the first comparator logic over two clock cycles; perform a second self-test on the first comparator logic over two clock cycles; perform the first self-test on the second comparator logic over two clock cycles; and perform the second self-test on the second comparator logic over two clock cycles.

[0188] Example 23 includes the system according to Example 21, wherein the self-test control logic is configured to generate one or more control signals to instruct the first comparator logic to compare the first outputs and the second outputs, and to instruct the second comparator logic to perform a self-test on the second comparator logic.

[0189] Example 24 includes the system according to Example 23, wherein the one or more control signals are one or more first control signals, and the self-test control logic is configured to generate one or more second control signals to instruct the first comparator logic to perform a self-test on the first comparator logic, and to instruct the second comparator logic to compare a fifth output of the first processor hardware with a sixth output of the second processor hardware, the first processor hardware being configured to operate in a lockstep manner with the second processor hardware.

[0190] Example 25 includes the system according to Example 23, wherein the first comparator logic is configured to: identify a first fault condition in response to determining that one or more of the first outputs do not match one or more of the second outputs; and in response to identifying the first fault condition, transmit first lockstep debug data to a user interface, the first lockstep debug data including at least one of first port information or first program counter information associated with the first fault condition; and the second comparator logic is configured to: identify a second fault condition in response to a self-test failure; and in response to identifying the second fault condition, transmit second lockstep debug data to the user interface, the second lockstep debug data including at least one of second port information or second program counter information associated with the second fault condition.

[0191] While some example methods, apparatuses, and articles have been described, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles that fall entirely within the scope of the claims of this patent.

[0192] The following claims are hereby incorporated into this specific embodiment by reference, wherein each claim exists independently as a separate embodiment herein.

Claims

1. An apparatus comprising: A self-test logic circuit system, wherein the self-test logic circuit system has a first output; as well as Comparator logic, the comparator logic including: Selection logic having a first input and a second output, wherein each of the first inputs is coupled to the first output; A first detection logic, the first detection logic having a second input and a third output, the second input being coupled to the second output; A second detection logic having a third input and a fourth output, wherein the third input is coupled to the third output; Latching logic having a fifth input and a fifth output, wherein the third output and the fourth output are coupled to the fifth input; and Error detection logic, the error detection logic having a sixth input coupled to the fifth input.

2. The apparatus according to claim 1, wherein, The selection logic includes multiple multiplexers, each of which has a corresponding first input among the first inputs and a corresponding second output among the second outputs.

3. The apparatus according to claim 2, further comprising: A first latch has a seventh input and a sixth output, the seventh input being coupled to one or more seventh outputs of a first processor; as well as A second latch having an eighth input and an eighth output, the eighth input being coupled to one or more ninth outputs of a second processor, the first processor being configured to operate in a lockstep manner with the second processor.

4. The apparatus according to claim 3, wherein, The sixth output is coupled to each of the first inputs of the first group of multiplexers in the plurality of multiplexers, and the eighth output is coupled to each of the second inputs of the second group of multiplexers in the plurality of multiplexers, the first group being different from the second group.

5. The apparatus according to claim 1, wherein, The first detection logic includes multiple logic gates, each having the second input and the third output.

6. The apparatus according to claim 5, wherein, Each of the plurality of logic gates is an XOR logic gate.

7. The apparatus according to claim 1, wherein, The latching logic includes: A first latch, having a seventh input and a sixth output, the seventh input being coupled to the second detection logic and the sixth output being coupled to the error detection logic; and A second latch has an eighth input and a seventh output, the eighth input being coupled to the second detection logic and the seventh output being coupled to the error detection logic.

8. The apparatus according to claim 7, wherein, The second detection logic includes a first logic gate and a second logic gate. The first logic gate and the second logic gate have each of the third inputs and the fourth output. The seventh input is coupled to the first logic gate through the first fourth output, and the eighth input is coupled to the second logic gate through the second fourth output.

9. The apparatus according to claim 8, wherein, The first logic gate is an OR logic gate, and the second logic gate is a NAND logic gate.

10. The apparatus according to claim 7, wherein, The error detection logic includes: A first logic gate, the first logic gate having a ninth input, the ninth input being coupled to the sixth output; A second logic gate having a tenth input and a ninth output, the tenth input being coupled to the sixth output; A third logic gate, the third logic gate having an eleventh input and a tenth output, the eleventh input being coupled to the seventh output; and The fourth logic gate has a twelfth input and a thirteenth input, the twelfth input being coupled to the ninth output and the thirteenth input being coupled to the tenth output.

11. The apparatus according to claim 10, wherein, The first logic gate, the second logic gate, and the third logic gate are AND logic gates, and the fourth logic gate is an OR logic gate.

12. The apparatus according to claim 1, wherein, The latching logic is a first latching logic, the device further includes a second latching logic, the selection logic is coupled to a first processor and a second processor through the second latching logic, and the self-test logic circuit system is used for: In response to a first control signal, the error detection logic is instructed to test whether a first processor output from the first processor matches a second processor output from the second processor; and In response to the second control signal, the error detection logic is instructed to perform a self-test on the first detection logic.

13. The apparatus according to claim 12, wherein, The self-test includes a first self-test and a second self-test, and the self-test logic circuit system is used for: The first self-test is invoked to execute over two clock cycles; as well as The second self-test is invoked to execute over two clock cycles, and the first detection logic is used to execute the self-test over four clock cycles based on the first self-test and the second self-test.

14. The apparatus according to claim 12, wherein, The error detection logic is used for: In response to determining that the output of the first processor does not match the output of the second processor, a first fault condition is identified; In response to a failure in the self-test, a second failure condition is identified; as well as In response to identifying at least one of the first fault condition or the second fault condition, lockstep debugging data is transmitted to the user interface, the lockstep debugging data including at least one of port information or program counter information associated with at least one of the first fault condition or the second fault condition.

15. An apparatus comprising: A first comparator logic, configured to receive a first input from a first processor and a second input from a second processor; A second comparator logic, coupled to the first comparator logic, is configured to receive the first input and the second input; as well as A self-test logic circuit system, coupled to the first comparator logic and the second comparator logic, is configured to respond to one or more first control signals as follows: Instruct the first comparator logic to compare the first input and the second input; and Instruct the second comparator logic to perform a self-test on the second comparator logic.

16. The apparatus according to claim 15, wherein, The self-test logic circuit system is configured to respond to the generation of one or more second control signals as follows: Instruct the first comparator logic to perform a self-test on the first comparator logic; and The second comparator logic is instructed to compare the third input of the first processor with the fourth input of the second processor, wherein the first processor is configured to operate in a lockstep manner with the second processor.

17. The apparatus according to claim 15, wherein, The first comparator logic includes: Selection logic; A first detection logic, which is coupled to the selection logic; The second detection logic is coupled to the first detection logic; A first latch, which is coupled to the second detection logic; A second latch, the second latch being coupled to the second detection logic; and Error detection logic, which is coupled to the first latch and the second latch.

18. The apparatus according to claim 17, wherein, The selection logic is a first selection logic, and the second comparator logic includes a second selection logic, which is coupled to the first detection logic.

19. The apparatus according to claim 17, wherein, The first latch has a first input and a first output, the second latch has a second input and a second output, and the error detection logic includes: A first logic gate, the first logic gate having a third input and a third output, the third input being coupled to the first output; A second logic gate having a fourth input and a fourth output, the fourth input being coupled to the first output; A third logic gate, the third logic gate having a fifth input and a fifth output, the fifth input being coupled to the second output; and A fourth logic gate having a sixth input, a seventh input, and a sixth output, wherein the sixth input is coupled to the fourth output and the seventh input is coupled to the fifth output.

20. The apparatus according to claim 19, wherein, At least one of the third output or the sixth output is coupled to the memory.

21. A system comprising: First processor hardware, the first processor hardware having a first output; Second processor hardware, the second processor hardware having a second output; as well as Lockstep control logic, the lockstep control logic including: A first comparator logic having a third input and a fourth input, the third input being coupled to the first output; A second comparator logic having a fifth input and a sixth input, the fifth input being coupled to the second output; and The self-test control logic has a third output and a fourth output, the third output being coupled to the fourth input, and the fourth output being coupled to the sixth input.

22. The system according to claim 21, wherein, The self-test control logic is used for: Perform a first self-test on the first comparator logic over two clock cycles; A second self-test is performed on the first comparator logic over two clock cycles; The first self-test is performed on the second comparator logic over two clock cycles; and The second self-test is performed on the second comparator logic over two clock cycles.

23. The system according to claim 21, wherein, The self-test control logic is used to generate one or more control signals to: Instruct the first comparator logic to compare the first output and the second output; and Instruct the second comparator logic to perform a self-test on the second comparator logic.

24. The system according to claim 23, wherein, The one or more control signals are one or more first control signals, and the self-test control logic is used to generate one or more second control signals to: Instruct the first comparator logic to perform a self-test on the first comparator logic; and The second comparator logic is instructed to compare the fifth output of the first processor hardware with the sixth output of the second processor hardware, the first processor hardware being configured to operate in a lockstep manner with the second processor hardware.

25. The system according to claim 23, wherein: The first comparator logic is used for: In response to determining that one or more of the first outputs in the first outputs do not match one or more of the second outputs in the second outputs, a first fault condition is identified; as well as In response to identifying the first fault condition, first lockstep debugging data is transmitted to the user interface, the first lockstep debugging data including at least one of first port information or first program counter information associated with the first fault condition; and The second comparator logic is used for: In response to a failure in the self-test, a second failure condition is identified; and In response to identifying the second fault condition, second lockstep debugging data is transmitted to the user interface, the second lockstep debugging data including at least one of second port information or second program counter information associated with the second fault condition.

Images