Chip verification method supporting automatic area reset
By defining two macros to achieve automated region reset of submodules in the UVM environment, the problem of submodule reset in chip simulation design is solved, efficiency is improved and synchronous maintenance steps are simplified, and it has high flexibility and reusability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG SINOCHIP SEMICON CO LTD
- Filing Date
- 2023-04-28
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies cannot meet the requirement of resetting only sub-modules in complex subsystems or whole-chip-level verification environments during chip simulation design, resulting in wasted test resources and low work efficiency. At the same time, it is necessary to maintain the reset operation of UVM components simultaneously, which increases the workload.
Two macros are defined to register verification and reset information in the UVM environment, enabling automated regional reset of submodules. This eliminates the need to synchronously maintain other components in the testbench that require reset. By constructing the UVM tb architecture and signal transmission, independent reset of submodules is achieved.
It enables automated reset of one or more sub-modules, eliminating tedious synchronization maintenance steps, improving work efficiency, and providing high flexibility and reusability.
Smart Images
Figure CN116755927B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip simulation design, and more specifically to a chip verification method that supports automatic region reset. Background Technology
[0002] In chip design, verification personnel typically perform reset scenario tests. The main scenario involves resetting the chip during simulation to verify whether the DUT (Device Under Test) functions correctly after a restart. In the UVM environment, a common testing method is to call the `jump` method to jump to the `reset_phase` stage, resetting the entire verification environment before sending normal stimuli.
[0003] However, this reset method has the following drawbacks: While the jump method in phase is simple and easy to operate, it can only reset the entire environment. In complex subsystems or whole-chip verification environments, there may be application scenarios where it is not necessary to reset the entire environment, but only one or more sub-modules. The phase jump method described above cannot cover such application scenarios. If the entire environment is forcibly reset every time, it will lead to a waste of test resources and greatly reduce work efficiency.
[0004] In addition, during the reset process, in addition to resetting the RTL, the UVC also needs to perform a corresponding reset operation. Otherwise, unexpected errors may occur, such as the queue or array used to cache data in the reference model not being reset, or the cache queue in the monitor. If it is not reset, it will cause the scoreboard to fail to match. Therefore, the existing phase jump reset method also needs to maintain the reset_phase in the UVM component at the same time, which increases the workload. Summary of the Invention
[0005] The purpose of this invention is to provide a regional reset method that can not only reset submodules individually, but also eliminates the step of synchronously maintaining other components in the testbench that need to be reset.
[0006] To achieve the above objectives, the present invention employs the following technical solution:
[0007] A chip verification method supporting region automatic reset includes:
[0008] Define two macros. The first macro contains registration verification information, which is used to register the received reset signal and the cache units such as arrays and queues in tb used for caching data to the factory. The second macro contains reset information, which is used to retrieve the reset unit in the factory and perform a reset.
[0009] Construct the TB architecture of UVM, and instantiate multiple sub-module environments in each subsystem environment;
[0010] At the top level of tb, uvm_config_db is called to pass the reset signal connected to RTL to the corresponding environment;
[0011] Each submodule environment receives the reset signal transmitted from the top layer of tb;
[0012] The first macro is called to register the received signal with the factory. At simulation time, the second macro is called to pass in the information that needs to be reset, and the submodule environment is reset.
[0013] Resend the incentive.
[0014] Preferably, when the received signal is registered to the factory by calling the first macro, the relevant component cache units that need to be synchronously reset are also registered to the factory by calling the first macro.
[0015] The registration verification information for the first macro includes at least five parameters, namely:
[0016] The first parameter specifies the name of the parameter to be registered;
[0017] The second parameter specifies the type of parameter to be registered;
[0018] The third parameter specifies whether it is an interface signal;
[0019] The fourth parameter is defined when the third parameter determines that it is an interface signal, specifying whether the signal is active low or active high.
[0020] The fifth parameter specifies the parent class.
[0021] The reset information of the second macro includes at least two parameters, namely:
[0022] The first parameter specifies the env pointer to be reset;
[0023] The second parameter specifies the duration the reset needs to be maintained.
[0024] After registering the received signal to the factory by calling the first macro, it also specifies the parent class of the signal receiving submodule's environment as its respective env.
[0025] The relevant components include reference model, monitor, and scoreboard, which are registered in the factory by calling the first macro and specifying their parent class.
[0026] The advantages of this invention are: it solves the problem of resetting one or more submodules within the same testbench; it enables the reset of any submodule or subsystem, while eliminating the cumbersome steps of synchronously maintaining cached queues or arrays in the testbench during chip reset. By registering the first macro defined in this invention and calling the second macro, the RTL can be reset while automatically resetting the relevant content of the testbench. The two macros related to automatic, regional reset also have universality, facilitating portability to other verification environments and possessing high flexibility and reusability. Attached Figure Description
[0027] Figure 1 This is a flowchart of the present invention;
[0028] Figure 2 This is a schematic diagram of the env environment in an embodiment of the present invention. Detailed Implementation
[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0030] This invention achieves regional, automated reset by defining two macros. The first macro includes at least the following five parameters:
[0031] The first parameter specifies the name of the parameter to be registered;
[0032] The second parameter specifies the type of parameter to be registered (mainly including string, int, bit, byte, array, queue, logic, etc.);
[0033] The third parameter specifies whether it is an interface signal; 1 represents an interface signal, and 0 represents no.
[0034] The fourth parameter, when it is an interface signal, needs to be defined as an input parameter. It mainly specifies whether this reset signal is active low or active high. 1 represents active high and 0 represents active low.
[0035] The fifth parameter specifies the parent class.
[0036] The second macro contains at least two parameters: the first parameter specifies a pointer to the env to be reset; the second parameter specifies the duration the reset needs to be maintained.
[0037] The function of the macro is as follows: when the first macro is called, it registers the corresponding parameter name, type and other attributes to the factory and specifies its parent class; when the second macro is called, it retrieves the parameters related to reset under this environment and registered in the factory according to the passed-in env pointer, and then asserts the interface signal under this environment (as specified by the fourth parameter when the first macro is called). At the same time, it resets the other types of parameters registered to this environment, and after a period of time, it performs de-assert (as specified by the time when the first macro is called).
[0038] For details on the implementation method, please refer to [link / reference]. Figure 1 After defining two macros, construct the TB architecture of UVM. Instantiate multiple submodule environments within a subsystem environment. Please refer to [link / reference]. Figure 2 It includes three sub-module environments: A, B, and C. In the top layer of tb, the reset signal connected to the RTL sub-module environment is passed to different sub-module environments through uvm_config_db. That is, the reset signals of modules A, B, and C in DUT are sent to Env_A, Env_B, and Env_C respectively, and each sub-environment receives the reset signal passed from the top layer of tb.
[0039] The first macro defined above is called to register the received signal to the factory, specifying its parent class as its respective env. As shown in the figure, RESET_A is received in Env_A and registered to the factory, with its parent class being Env_A. Similarly, RESET_B and RESET_C are registered in the same way.
[0040] In each sub-environment's UVC, the cache units that need to be synchronously reset during reset are registered to the factory by calling the first macro. For example, in the diagram, Env_A, Env_B, and Env_C all have queues for caching in their mon and scb functions. At any simulation moment in the test, the second macro is called, passing in the pointer to the sub-environment that needs to be reset and the duration, to reset the sub-environment, and finally, the stimulus is resent.
[0041] It should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A chip verification method supporting region automatic reset, characterized in that, include: Define two macros. The first macro contains registration verification information, which is used to register the received reset signal and the cache unit in tb used for caching data to the factory. The second macro contains reset information, which is used to retrieve the reset unit in the factory and perform a reset. Construct the TB architecture of UVM, and instantiate multiple sub-module environments in each subsystem environment; At the top level of tb, uvm_config_db is called to pass the reset signal connected to RTL to the corresponding environment; Each submodule environment receives the reset signal transmitted from the top layer of tb; The first macro is called to register the received signal with the factory. At simulation time, the second macro is called to pass in the information that needs to be reset, and the submodule environment is reset. Resend the incentive.
2. The chip verification method supporting region automatic reset according to claim 1, characterized in that, When the first macro is called to register the received signal to the factory, the relevant component cache units that need to be synchronously reset are also registered to the factory by calling the first macro.
3. The chip verification method supporting region automatic reset according to claim 1, characterized in that, The registration verification information for the first macro includes at least five parameters, namely: The first parameter specifies the name of the parameter to be registered; The second parameter specifies the type of parameter to be registered; The third parameter specifies whether it is an interface signal; The fourth parameter is defined when the third parameter determines that it is an interface signal, specifying whether the signal is active low or active high. The fifth parameter specifies the parent class.
4. The chip verification method supporting region automatic reset according to claim 1, characterized in that, The reset information of the second macro includes at least two parameters, namely: The first parameter specifies the env pointer to be reset; The second parameter specifies the duration the reset needs to be maintained.
5. The chip verification method supporting region automatic reset according to claim 3, characterized in that, After registering the received signal to the factory by calling the first macro, the parent class of the signal receiving submodule environment is also specified as their respective env.
6. The chip verification method supporting region automatic reset according to claim 2, characterized in that, The relevant components include reference model, monitor, and scoreboard, which are registered in the factory by calling the first macro and specifying their parent class.