Display module, control method thereof, and display device

Abstract

The present disclosure provides a display module and a control method thereof, and a display device, and relates to the technical field of display. The scan driving circuit comprises an output sub-circuit, the output sub-circuit being electrically connected with a clock signal end, an output end and a pull-up node, a level conversion unit being electrically connected with the pull-up node, and the working process of the level conversion unit after power failure of the display module comprising a first time, a second time and a third time in sequence. The level conversion unit is configured to: at the first time, pull up the level of the pull-up node to a first level and pull up the level of the clock signal end to a second level; the first level is configured to control the output sub-circuit to write the second level into the output end, and the second level is configured to control the pixel driving circuit to release a data signal; at the second time, pull down the level of the pull-up node to a third level; the third level is less than the first level; and at the third time, pull down the level of the clock signal end to a fourth level, and the fourth level is configured to control the pixel driving circuit to be closed.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display module and its control method, and a display device. Background Technology

[0002] Image retention is prone to occur in display modules after power loss because data signals in the pixel drive circuit cannot be fully released, especially when the transistors in the display panel are oxide transistors, and / or after reliability testing. Oxide transistors have lower leakage current, which is detrimental to data signal release. After reliability testing, transistors in the shift register may experience characteristic shifts due to prolonged operation, also hindering data signal release. Summary of the Invention

[0003] The embodiments of this disclosure provide a display module and its control method, as well as a display device, which improves the problem of image retention on the display panel after abnormal power failure.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a display module is provided, including a scan driving circuit and a level conversion unit. The scan driving circuit includes an output sub-circuit, which is electrically connected to a clock signal terminal, an output terminal, and a pull-up node. The level conversion unit is electrically connected to the pull-up node. After the display module is powered off, the operation process of the level conversion unit includes a first moment, a second moment, and a third moment in sequence. The level conversion unit is configured as follows:

[0006] At the first moment, the level of the pull-up node is pulled up to a first level, and the level of the clock signal terminal is pulled up to a second level; the first level is configured to control the output sub-circuit to write the second level to the output terminal, and the second level is configured to control the pixel driving circuit to release the data signal;

[0007] At the second moment, the level of the pull-up node is pulled down to a third level; the third level is lower than the first level.

[0008] At the third moment, the level of the clock signal terminal is pulled down to a fourth level, which is configured to control the pixel driving circuit to turn off.

[0009] In some embodiments, the display module further includes a voltage line and a power management chip, the voltage line being electrically connected to the power management chip and the level conversion unit, the level conversion unit being configured to pull down the level of the pull-up node to the third level when the level of the voltage line drops to a second threshold.

[0010] In some embodiments, the display module further includes a second detection unit electrically connected to the voltage line and the level conversion unit. The second detection unit is configured to control the level conversion unit to pull down the level of the pull-up node to the third level when the level of the voltage line drops to a second threshold.

[0011] In some embodiments, the display module further includes a power line electrically connected to the power management chip to provide a voltage level to the power management chip, and the level conversion unit is configured to pull down the voltage level of the pull-up node to the third voltage level when the voltage level of the power line drops to a fourth threshold.

[0012] In some embodiments, the display module further includes a second detection unit electrically connected to the power line and the level conversion unit. The second detection unit is configured to control the level conversion unit to pull down the level of the pull-up node to the third level when the level of the power line drops to a fourth threshold.

[0013] In some embodiments, the display module further includes a first monitoring unit and a third monitoring unit.

[0014] The first monitoring unit is electrically connected to the power line and the level conversion unit. The first monitoring unit is configured to: when the level of the power line drops to the first threshold, control the level conversion unit to pull up the level of the pull-up node to the first level and pull up the level of the clock signal terminal to the second level.

[0015] The third monitoring unit is electrically connected to the voltage line and the level conversion unit. The third monitoring unit is configured to: when the level of the voltage line drops to the third threshold, control the level conversion unit to pull down the level of the pull-up node to the fourth level.

[0016] The first threshold, the second threshold, and the third threshold decrease sequentially.

[0017] In some embodiments, the output sub-circuit includes a third transistor, the control terminal of which is electrically connected to the pull-up node, the first terminal of which is electrically connected to the clock signal terminal, and the second terminal of which is electrically connected to the output terminal.

[0018] In some implementations, the third level is configured to control the third transistor to turn off.

[0019] On the other hand, a control method for a display module is provided. The display module includes a scan driving circuit and a level conversion unit. The scan driving circuit includes an output sub-circuit, which is electrically connected to a clock signal terminal, an output terminal, and a pull-up node. The level conversion unit is electrically connected to the pull-up node. After the display module is powered off, the operation process of the level conversion unit sequentially includes a first moment, a second moment, and a third moment. The control method includes:

[0020] At the first moment, the level conversion unit is controlled to pull up the level of the pull-up node to a first level and pull up the level of the clock signal terminal to a second level; the first level is configured to control the output sub-circuit to write the second level to the output terminal, and the second level is configured to control the pixel driving circuit to release the data signal;

[0021] At the second moment, the level conversion unit is controlled to pull down the level of the pull-up node to a third level; the third level is lower than the first level.

[0022] At the third moment, the level conversion unit is controlled to pull down the level of the clock signal terminal to a fourth level, which is configured to control the pixel driving circuit to turn off.

[0023] In another aspect, a display device is provided, including the aforementioned display module.

[0024] The display module provided in this embodiment can have a level conversion unit that pulls up the level of the pull-up node to a first level and pulls up the clock signal to a second level at a first moment, thereby causing the output sub-circuit to output a second level, and the pixel driving circuit to release the data signal under the control of the second level. Furthermore, the level conversion unit can pull down the level of the pull-up node to a third level at a second moment, thereby preventing the transistors in the output sub-circuit from experiencing characteristic drift under the prolonged high level of the pull-up node. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 The diagram schematically illustrates the frontal view of a display device;

[0027] Figure 2 A schematic diagram of a display panel is shown.

[0028] Figure 3 A schematic diagram illustrating the connection between a pixel driving circuit and a shift register is shown.

[0029] Figure 4 A partial structural block diagram of a display module is schematically shown.

[0030] Figure 5 The timing diagram of each signal after the small-sized display module loses power is schematically shown;

[0031] Figure 6 The timing diagram of each signal after power failure is schematically shown for medium and large-sized display modules;

[0032] Figure 7 A circuit diagram of a shift register is shown schematically.

[0033] Figure 8 A partial structural block diagram of a display module is schematically shown.

[0034] Figure 9 The timing diagram of the output signal of the level conversion unit after the display module is powered off is shown;

[0035] Figure 10 A partial structural block diagram of a display module is schematically shown.

[0036] Figure 11 The circuit diagram of the second detection unit is shown schematically;

[0037] Figure 12 The circuit diagram of the first monitoring unit is shown schematically;

[0038] Figure 13 The circuit diagram of the third monitoring unit is shown schematically;

[0039] Figure 14 A flowchart illustrating the steps of a control method for a display module is shown.

[0040] Figure label: Detailed Implementation

[0041] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0042] In the embodiments of this disclosure, the terms "first," "second," "third," and "fourth" are used to distinguish identical or similar items with essentially the same function and effect, solely for the purpose of clearly describing the technical solutions of the embodiments of this disclosure, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0043] In embodiments of this disclosure, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0044] In the embodiments of this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0045] Figure 1 The diagram schematically illustrates the frontal view of a display device. For example... Figure 1 As shown, some embodiments of this disclosure provide a display device 100, which can be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). For example, the display device 100 can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, display of camera view (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, architectural structure, packaging and aesthetic structure (e.g., display of an image of a piece of jewelry), etc. Figure 1 The illustration uses a display device 100 as an example.

[0046] The display device 100 includes a display module, which includes a display panel 110. The display panel 110 can be a liquid crystal display (LCD); it can also be an electroluminescent display panel or a photoluminescent display panel. When the display panel 110 is an electroluminescent display panel, it can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. When the display panel 110 is a photoluminescent display panel, the photoluminescent display device can be a quantum dot photoluminescent display panel.

[0047] Figure 2 A schematic diagram of a display panel is shown. For example, as shown... Figure 2 As shown, the display panel 110 includes a substrate 111 and multiple sub-pixels P, multiple gate lines GL, and multiple data lines DL disposed on one side of the substrate 111.

[0048] The display panel 110 may have a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA may be located on one, two, or three sides of the display area AA, or the non-display area NA may be arranged around the display area AA. Multiple sub-pixels P, multiple gate lines, and multiple data lines may be located within the display area AA.

[0049] For example, multiple subpixels P can be arranged in an array. For instance, multiple subpixels P arranged in an array form multiple subpixel rows and multiple subpixel columns. Multiple subpixels P in a subpixel row are arranged along a first direction X, and multiple subpixels P in a subpixel column are arranged along a second direction Y.

[0050] In this configuration, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the included angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°, etc.

[0051] When the display panel is an OLED display panel, the sub-pixel P may include a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit. When the display panel is an LCD display panel, the sub-pixel P may include a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit.

[0052] Figure 3 A schematic diagram illustrating the connection between a pixel driving circuit and a shift register is shown. For example, as shown... Figure 3As shown, the pixel driving circuit includes a driving transistor. The gate of the driving transistor is electrically connected to the output terminal of the shift register 112. The first electrode of the driving transistor is electrically connected to the data signal terminal Data. The second electrode of the driving transistor is electrically connected to the pixel electrode Electrode.

[0053] For example, multiple pixel driving circuits in the same sub-pixel column can be electrically connected to the same data line, and multiple pixel driving circuits in the same sub-pixel row can be electrically connected to the same gate line.

[0054] A scan driving circuit is also provided on one side of the substrate 111, which includes multiple cascaded shift registers 112. When the scan driving circuit is working, the multiple cascaded shift registers 112 output control signals step by step through their output terminals. The output terminals of the shift registers 112 can be electrically connected to the gate lines so that the shift registers 112 provide scan signals to the pixel driving circuit through the gate lines.

[0055] For example, the scan driving circuit is located in the non-display area NA. Of course, in actual applications, in order to reduce the bezel size of the display panel 110, at least a portion of the structure of the scan driving circuit can also be located in the display area AA.

[0056] Figure 4 A schematic diagram of the structure of a display module is shown. For example... Figure 4 As shown, the display module may also include a power management chip 114 (Power Management IC, PMIC), a level shifting unit 113 (Level Shift, L / S), a power line VCC, and a voltage line VGH.

[0057] The power supply line VCC is electrically connected to the power management chip 114 to provide a power level to the power management chip 114. For example, one end of the power supply line VCC is electrically connected to the power management chip 114, and the other end of the power supply line VCC is electrically connected to the power module of the display device 100.

[0058] The voltage line VGH is electrically connected to the power management chip 114 and the level conversion unit 113, so that the power management chip 114 provides a voltage level to the level conversion unit 113 through the voltage line VGH. For example, during normal display of the display module, a constant high-level signal is connected to the voltage line VGH.

[0059] Level conversion unit 113 is electrically connected to shift register 112 to provide a level to shift register 112. Exemplarily, the display module also includes a timing controller (Tcon), which is electrically connected to level conversion unit 113 so that level conversion unit 113 outputs a level to shift register 112 according to the signal from timing controller and the level of voltage line VGH.

[0060] Image retention is prone to occur after the display module is powered off because the data signals in the pixel drive circuit cannot be fully released, especially when the transistors in the display panel 110 are oxide transistors, and / or after reliability testing. Because oxide transistors have low leakage current, they are not conducive to the release of data signals. After reliability testing, the transistors in the shift register 112 undergo characteristic shifts due to long-term operation, which is also not conducive to the release of data signals.

[0061] The power loss of the display module is divided into normal power loss and abnormal power loss. During normal power loss, the power supply line VCC level is detected. When the power supply line VCC level drops, it enters Xon mode to release the data signal. Figure 5 The timing diagram of each signal after the small-sized display module is powered off is shown schematically. Figure 6 The timing diagram of each signal after power failure is schematically shown for medium to large-sized display modules. Figure 5 and Figure 6 It is known that the timing controller of the small-sized display panel 110 can effectively control the power-down process, resulting in a less noticeable image retention phenomenon. However, in the medium-to-large-sized display panel 110, the data signal release effect is reduced due to the gradual decrease in the level signal. For example, each signal is maintained by the capacitance formed by the voltage line VGH and other conductive structures, and the gradual discharge of the capacitor causes the level to decrease. During abnormal power loss, the data driver chip cannot output a black screen in time. The data signal in the pixel driver circuit before entering Xon mode is the data signal of the previous frame image. Especially after reliability testing, this can easily lead to complete retention of the previous frame image. The embodiments of this disclosure can be applied to medium-to-large-sized display modules, such as tablet computers, laptops, desktop computer monitors, and televisions.

[0062] Figure 7 A circuit diagram of a shift register 112 is schematically shown. Taking oxide transistors in the display panel 110 as an example, to solve the image retention caused by abnormal power loss after reliability testing of the 8585 product with a refresh rate of 90Hz, a fourteenth transistor M14 is added, resulting in... Figure 7The shift register 112 is shown. STV0 is electrically connected to the gate of the fourteenth transistor M14. When power is off, STV0 generates an Xon signal (STV0 is a high-level signal), causing the fourteenth transistor M14 to conduct, thus outputting the high-level signal in VGL through the output terminal OUT. However, after the reliability test of a 120Hz product, the characteristics of M13A, M13B, and M14 drift significantly, resulting in image retention still present on the display panel 110.

[0063] Figure 8 A partial structural block diagram of a display module is schematically shown. For example... Figure 8 As shown, the scan driving circuit in this embodiment includes an output sub-circuit. The output sub-circuit is electrically connected to the clock signal terminal CLK, the output terminal OUT, and the pull-up node PU. The output sub-circuit is also electrically connected to the pixel driving circuit to output a scan signal to the pixel driving circuit. The level conversion unit 113 is electrically connected to the pull-up node PU to control the output sub-circuit.

[0064] For example, when the level conversion unit 113 pulls up the node PU to output a high level, the clock signal terminal CLK and the output terminal OUT are connected, and the level of the clock signal terminal CLK is written to the output terminal OUT; when the level conversion unit 113 pulls up the node PU to output a low level, the clock signal terminal CLK and the output terminal OUT are not connected.

[0065] The output sub-circuit may include a third transistor M3. The control terminal of the third transistor M3 is electrically connected to the pull-up node PU, the first terminal of the third transistor M3 is electrically connected to the clock signal terminal CLK, and the second terminal of the third transistor M3 is electrically connected to the output terminal OUT.

[0066] For example, the third transistor M3 is an N-type transistor. When the level of the pull-up node PU is high, the third transistor M3 is turned on, and when the level of the pull-up node PU is low, the third transistor M3 is turned off.

[0067] For example, continue to refer to Figure 7 The level conversion unit 113 is electrically connected to the pull-up node PU via M8A. When the display module is powered off, the level of VDD_A is pulled high, thereby turning on M8A.

[0068] Figure 9 The timing diagram of the output signal of the level conversion unit 113 after the display module is powered off is shown. Figure 9 As shown, after the display module is powered off, the operation process of the level conversion unit 113 includes the first time t1, the second time t2, and the third time t3 in sequence.

[0069] At the first moment t1, the level conversion unit 113 pulls up the level of the pull-up node PU to the first level and pulls up the level of the clock signal terminal CLK to the second level. The first level can control the output sub-circuit, enabling conduction between the clock signal terminal CLK and the output terminal OUT, thereby writing the second level of the clock signal terminal CLK to the output terminal OUT. After the second level is written from the output terminal OUT to the pixel driving circuit, it can control the pixel driving circuit to release the data signal.

[0070] For example, when the first level is high, the output sub-circuit enables the clock signal terminal CLK and the output terminal OUT to conduct under the control of the high level.

[0071] For example, the pixel driving circuit includes a driving transistor DTFT, which is an N-type transistor. The second level is a high level, which can control the driving transistor DTFT to turn on, thereby releasing the data signal.

[0072] At the first moment t1, the level of the pull-up node PU is pulled high, causing the third transistor M3 to remain in a high-level state for an extended period, which can easily lead to characteristic drift in the third transistor M3. For example, if a capacitor is connected between the control electrode and the second electrode of the third transistor M3, the high-level signal will be stored in the capacitor, thus causing the third transistor M3 to remain in a high-level state for a long time.

[0073] At the second time t2, the level conversion unit 113 pulls down the level of the pull-up node PU to a third level, which is lower than the first level. Pulling down the level of the pull-up node PU to the third level can lower the level of the control electrode of the third transistor M3, preventing the characteristics of the third transistor M3 from drifting due to the control electrode of the third transistor M3 being in a high-level state for a long time.

[0074] For example, level shifting unit 113 pulls down the level of pull-up node PU to ground level GND.

[0075] At the third moment t3, the level conversion unit 113 pulls down the clock signal terminal CLK to the fourth level, which is configured to control the pixel driving circuit to turn off. When the clock signal terminal CLK is at the fourth level, the output level of the output sub-circuit can also be the fourth level.

[0076] For example, the driving transistor DTFT is an N-type transistor, the fourth level is low, and the output terminal OUT outputs a low level, which can turn off the driving transistor DTFT.

[0077] It should be noted that from the first time t1 to the second time t2, the voltage levels of the power supply line VCC, the voltage line VGH, the clock signal terminal CLK, and the first pull-up node PU gradually decrease. From the second time t2 to the third time t3, the voltage levels of the power supply line VCC, the voltage line VGH, and the clock signal terminal CLK gradually decrease, while the voltage level of the pull-up node PU remains unchanged.

[0078] The display module provided in this embodiment allows the level conversion unit 113 to pull up the level of the pull-up node PU to a first level and pull up the clock signal terminal CLK to a second level at a first time t1, thereby causing the output sub-circuit to output a second level. Under the control of the second level, the pixel driving circuit releases the data signal, improving the image retention problem. Furthermore, the level conversion unit 113 can pull down the level of the pull-up node PU to a third level at a second time t2, thereby preventing the transistors in the output sub-circuit from experiencing characteristic drift under the prolonged high level of the pull-up node PU.

[0079] The second moment t2 can be determined based on the voltage level of the voltage line VGH or the power supply level of the power line VCC.

[0080] Optionally, when the voltage line VGH level drops to the second threshold v3, the level conversion unit 113 pulls down the level of the pull-up node PU to the third level.

[0081] For example, when the second threshold v3 equals 8V, and the voltage line VGH drops to 8V, the level conversion unit 113 pulls down the level of the pull-up node PU to ground. Between the first time t1 and the second time t2, the voltage line VGH is greater than 8V, allowing the level conversion unit 113 to output a level greater than 8V to the clock signal terminal CLK. The time from the first time t1 to the second time t2 is 50ms, thereby controlling the pixel driving circuit to release the data signal.

[0082] For example, when the voltage line VGH is 8V, STV0 / VDDO / VDDE are all 8V, and the pull-up node PU can be easily pulled down to ground level through M5 / M8A / M8B.

[0083] Figure 10 A partial structural block diagram of a display module is schematically shown. For example... Figure 10 As shown, the display module may also include a second detection unit 116, which is electrically connected to the voltage line VGH and the level conversion unit 113. The second detection unit 116 is configured to control the level conversion unit 113 to pull down the level of the pull-up node PU to a third level when the level of the voltage line VGH drops to the second threshold v3. Figure 11The circuit diagram of the second detection unit 116 is shown schematically.

[0084] Optionally, when the power supply line VCC level drops to the fourth threshold, the level of the pull-up node PU is pulled down to the third level. The fourth threshold can be flexibly set according to actual conditions, as long as the driving transistor can be turned on and release the data signal before the power supply line VCC level drops to the fourth threshold.

[0085] At this time, the second detection unit 116 is electrically connected to the power line VCC and the level conversion unit 113. The second detection unit 116 is configured to control the level conversion unit 113 to pull down the level of the pull-up node PU to the third level when the level of the power line VCC drops to the fourth threshold.

[0086] Continue to refer to Figure 10 The display module also includes a first monitoring unit 115 and a third monitoring unit 117.

[0087] The first monitoring unit 115 is electrically connected to the power supply line VCC and the level conversion unit 113. The first monitoring unit 115 is configured to: when the level of the power supply line VCC drops to a first threshold v1, control the level conversion unit 113 to pull up the level of the pull-up node PU to a first level and pull up the level of the clock signal terminal CLK to a second level. The circuit diagram of the first monitoring unit 115 is shown below. Figure 12 As shown.

[0088] For example, the display module is 3.3V when it is working normally, and the first threshold v1 can be set to 2.4V.

[0089] The third monitoring unit 117 is electrically connected to the voltage line VGH and the level conversion unit 113. The third monitoring unit 117 is configured to control the level conversion unit 113 to pull down the level of the pull-up node PU to the fourth level when the level of the voltage line VGH drops to the third threshold v2. Figure 13 As shown.

[0090] Among them, the first threshold v1, the second threshold v3, and the third threshold v2 decrease sequentially.

[0091] This disclosure also provides a control method for a display module, used to control the display module after power failure. Figure 14 A flowchart illustrating the steps of a control method for a display module is shown, as follows: Figure 14 As shown, the control method for the display module includes the following steps.

[0092] S100, at the first moment, the control level conversion unit pulls up the level of the pull-up node to the first level and pulls up the level of the clock signal terminal to the second level.

[0093] The first level is configured to control the output sub-circuit to write the second level to the output terminal, and the second level is configured to control the drive transistor to turn on.

[0094] For example, the first monitoring unit monitors the power line level. When the power line level drops to a first threshold, the first monitoring unit sends a signal to the level conversion unit to control the level conversion unit to pull up the level of the pull-up node to a first level and pull up the level of the clock signal terminal to a second level.

[0095] S200, at the second moment, the control level conversion unit pulls down the level of the pull-up node to the third level.

[0096] The third level is lower than the first level. For example, the third level is the ground level GND.

[0097] For example, the second detection unit monitors the level of the power line or voltage line. When the level of the power line drops to the fourth threshold or the level of the voltage line drops to the second threshold, the second detection unit sends a signal to the level conversion unit to control the level conversion unit to pull down the level of the pull-up node to the third level.

[0098] S300, at the third moment, the control level conversion unit pulls down the level of the clock signal terminal to the fourth level.

[0099] The fourth level is configured to control the pixel driving circuit to turn off.

[0100] For example, the third monitoring unit monitors the power line level. When the power line level drops to a third threshold, the third monitoring unit sends a signal to the level conversion unit to control the level conversion unit to output a fourth level to the clock signal terminal.

[0101] The control method for the display module provided in this embodiment allows the level shifting unit to pull up the level of the pull-up node to a first level and pull up the clock signal to a second level at a first moment, thereby causing the output sub-circuit to output a second level, and the pixel driving circuit to release the data signal under the control of the second level. Furthermore, the level shifting unit can pull down the level of the pull-up node to a third level at a second moment, thereby preventing the transistors in the output sub-circuit from experiencing characteristic drift under the prolonged high level of the pull-up node.

[0102] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display module, characterized in that, The system includes a scan driving circuit and a level conversion unit. The scan driving circuit includes an output sub-circuit, which is electrically connected to a clock signal terminal, an output terminal, and a pull-up node. The level conversion unit is electrically connected to the pull-up node. After the display module is powered off, the operation of the level conversion unit includes a first moment, a second moment, and a third moment. The level conversion unit is configured as follows: At the first moment, the level of the pull-up node is pulled up to a first level, and the level of the clock signal terminal is pulled up to a second level; the first level is configured to control the output sub-circuit to write the second level to the output terminal, and the second level is configured to control the pixel driving circuit to release the data signal; At the second moment, the level of the pull-up node is pulled down to the third level; The third level is lower than the first level; At the third moment, the level of the clock signal terminal is pulled down to a fourth level, which is configured to control the pixel driving circuit to turn off.

2. The display module according to claim 1, characterized in that, The display module also includes a voltage line and a power management chip. The voltage line is electrically connected to the power management chip and the level conversion unit. The level conversion unit is configured to pull down the level of the pull-up node to the third level when the level of the voltage line drops to the second threshold.

3. The display module according to claim 2, characterized in that, The display module further includes a second detection unit, which is electrically connected to the voltage line and the level conversion unit. The second detection unit is configured to control the level conversion unit to pull down the level of the pull-up node to the third level when the level of the voltage line drops to the second threshold.

4. The display module according to claim 2, characterized in that, The display module also includes a power line, which is electrically connected to the power management chip to provide a voltage level to the power management chip. The level conversion unit is configured to pull down the voltage level of the pull-up node to the third voltage level when the voltage level of the power line drops to the fourth threshold.

5. The display module according to claim 4, characterized in that, The display module further includes a second detection unit, which is electrically connected to the power line and the level conversion unit. The second detection unit is configured to control the level conversion unit to pull down the level of the pull-up node to the third level when the level of the power line drops to the fourth threshold.

6. The display module according to claim 5, characterized in that, The display module also includes a first monitoring unit and a third monitoring unit. The first monitoring unit is electrically connected to the power line and the level conversion unit. The first monitoring unit is configured to: when the level of the power line drops to a first threshold, control the level conversion unit to pull up the level of the pull-up node to the first level and pull up the level of the clock signal terminal to the second level. The third monitoring unit is electrically connected to the voltage line and the level conversion unit. The third monitoring unit is configured to: when the level of the voltage line drops to the third threshold, control the level conversion unit to pull down the level of the pull-up node to the fourth level. The first threshold, the second threshold, and the third threshold decrease sequentially.

7. The display module according to claim 1, characterized in that, The output sub-circuit includes a third transistor, the control electrode of which is electrically connected to the pull-up node, the first electrode of which is electrically connected to the clock signal terminal, and the second electrode of which is electrically connected to the output terminal.

8. The display module according to claim 7, characterized in that, The third level is configured to control the third transistor to turn off.

9. A control method for a display module, characterized in that, The display module includes a scan driving circuit and a level conversion unit. The scan driving circuit includes an output sub-circuit, which is electrically connected to a clock signal terminal, an output terminal, and a pull-up node. The level conversion unit is electrically connected to the pull-up node. After the display module is powered off, the operation process of the level conversion unit includes a first moment, a second moment, and a third moment in sequence. The control method includes: At the first moment, the level conversion unit is controlled to pull up the level of the pull-up node to a first level and pull up the level of the clock signal terminal to a second level; the first level is configured to control the output sub-circuit to write the second level to the output terminal, and the second level is configured to control the pixel driving circuit to release the data signal; At the second moment, the level conversion unit is controlled to pull down the level of the pull-up node to a third level; the third level is lower than the first level. At the third moment, the level conversion unit is controlled to pull down the level of the clock signal terminal to a fourth level, which is configured to control the pixel driving circuit to turn off.

10. A display device, characterized in that, Includes the display module as described in any one of claims 1 to 8.

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