Method and apparatus for constructing quantum circuit, and storage medium

Abstract

The application provides a quantum circuit construction method and device and a storage medium, and solves the technical problem of how to generate a corresponding quantum circuit by matrix encoding in the related art. The quantum circuit construction method comprises the following steps: determining a to-be-decomposed matrix A and a set of non-zero elements in the to-be-decomposed matrix A; converting the non-zero element indexes in the to-be-decomposed matrix A into a binary representation form; expanding and re-representing each term in the to-be-decomposed matrix A as a matrix A' according to the binary representation form of the non-zero element indexes in the to-be-decomposed matrix A; determining the logical gate type corresponding to each subterm in each term of the matrix A' according to the values of the subterms in each term of the matrix A'; determining a quantum subcircuit and a coefficient corresponding to the quantum subcircuit according to the logical gate type corresponding to each subterm in each term of the matrix A'; wherein the quantum subcircuit corresponds to a non-zero element; and constructing a quantum circuit according to the coefficient and the quantum subcircuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and particularly relates to a quantum circuit construction method and device and a storage medium. BACKGROUND

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and computes quantum information and runs quantum algorithms, it is a quantum computer. Therefore, a quantum computer has a higher efficiency in processing mathematical problems than a general computer.

[0003] At present, quantum computing algorithms are usually represented by quantum circuits, and the quantum circuit includes quantum logic gate operations. The process of solving a problem using quantum computing can be understood as follows: the problem is converted into a function form description, and then a matrix code is introduced into the quantum circuit to perform the quantum circuit for solving.

[0004] Therefore, how to generate a corresponding quantum circuit from a matrix code has been a hot topic in the field and needs to be solved urgently. SUMMARY

[0005] The embodiments of the present application provide a quantum circuit construction method, device and storage medium to solve the technical problem of how to generate a corresponding quantum circuit from a matrix code in the related art, which can generate a corresponding quantum circuit from a square matrix in a matrix.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] In a first aspect, a quantum circuit construction method is provided, and the method comprises:

[0008] determining a to-be-decomposed matrix A and a set of non-zero elements in the to-be-decomposed matrix A; wherein the to-be-decomposed matrix A is a square matrix and the element type in the square matrix is a complex number;

[0009] converting the non-zero element index in the to-be-decomposed matrix A into a binary representation form;

[0010] expanding and re-representing each term in the to-be-decomposed matrix A as a matrix A' according to the binary representation form of the non-zero element index in the to-be-decomposed matrix A;

[0011] determining the logic gate type corresponding to each subterm in each term of the matrix A' according to the value of each subterm in each term of the matrix A';

[0012] determining a quantum sub-circuit and a coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to each subterm in each term of the matrix A'; wherein the quantum sub-circuit corresponds to a non-zero element;

[0013] According to the coefficient and the quantum sub-circuit, a quantum circuit is constructed.

[0014] Optionally, the non-zero elements in the matrix A to be decomposed are A kj , k and j correspond to the row index and the column index respectively, S is a set of non-zero elements in the matrix A to be decomposed, and s is an iteration index of the non-zero elements in the matrix A to be decomposed; the binary representation of the non-zero element index in the matrix A to be decomposed is:

[0015]

[0016]

[0017] The matrix A to be decomposed is represented as:

[0018] The matrix A' is represented as:

[0019]

[0020] wherein n is the number of bits after converting the decimal row index or the decimal column index into binary, and m is an integer between 1 and n.

[0021] Optionally, the value of each sub-item in each item of the matrix A' is one of |0><0|, |0><1|, |1><0|, and |1><1|.

[0022] The value of each sub-item in each item of the matrix A' is determined according to the value of each sub-item in each item of the matrix A', and the type of the logic gate corresponding to each sub-item in each item of the matrix A' is determined.

[0023]

[0024]

[0025]

[0026]

[0027] wherein X is a Pauli X gate, Y is a Pauli Y gate, Z is a Pauli Z gate, I is an I gate, and i is an imaginary number.

[0028] Optionally, the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit are determined according to the type of the logic gate corresponding to each sub-item in each item of the matrix A'.

[0029] The quantum sub-circuit is determined according to the type of the logic gate corresponding to each sub-item in each item of the matrix A'.

[0030] The coefficient corresponding to the quantum sub-circuit is determined according to the value of the matrix corresponding to the quantum sub-circuit and the value of the non-zero element.

[0031] Optionally, the determining the coefficient corresponding to the quantum sub-circuit according to the value of the quantum sub-circuit corresponding matrix and the value of the non-zero element comprises:

[0032] dividing the value of the non-zero element by the value of the quantum sub-circuit corresponding matrix, and the calculation result is the coefficient corresponding to the quantum sub-circuit.

[0033] Optionally, the determining the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the type of the logical gate corresponding to each sub-term in each term in the matrix A' further comprises:

[0034] determining that there is the same quantum sub-circuit;

[0035] merging the same quantum sub-circuit into one term; wherein the coefficient of the merged quantum sub-circuit is the sum of the coefficients of the quantum sub-circuits before merging.

[0036] In a second aspect, a device for constructing a quantum circuit is provided, and the device comprises:

[0037] a first determining module configured to determine a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed; wherein the matrix A to be decomposed is a square matrix and the element type in the square matrix is a complex number;

[0038] a converting module configured to convert the subscript of the non-zero element in the matrix A to be decomposed into a binary representation;

[0039] a decomposing module configured to expand and re-represent each term in the matrix A to be decomposed as a matrix A' according to the binary representation of the subscript of the non-zero element in the matrix A to be decomposed;

[0040] a second determining module configured to determine the type of the logical gate corresponding to each sub-term in each term in the matrix A' according to the value of each sub-term in each term in the matrix A';

[0041] a third determining module configured to determine the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the type of the logical gate corresponding to each sub-term in each term in the matrix A'; wherein the quantum sub-circuit corresponds to the non-zero element;

[0042] a constructing module configured to construct a quantum circuit according to the coefficient and the quantum sub-circuit.

[0043] Optionally, the non-zero element in the matrix A to be decomposed is A kj , k and j respectively correspond to the row subscript and the column subscript, S is the set of non-zero elements in the matrix A to be decomposed, and s is the iteration index of the non-zero element in the matrix A to be decomposed; the binary representation of the subscript of the non-zero element in the matrix A to be decomposed is:

[0044]

[0045]

[0046] The to-be-decomposed matrix A is represented as:

[0047] The matrix A' is represented as:

[0048]

[0049] wherein n is a decimal row index or a number of bits converted from a decimal column index to binary, and m is an integer between 1 and n.

[0050] Optionally, a value of each subterm in each term of the matrix A' is one of |0><0|, |0><1|, |1><0| and |1><1|.

[0051] The second determining module determines a type of a logic gate corresponding to each subterm in each term in the matrix A' according to the following rules:

[0052]

[0053]

[0054]

[0055]

[0056] wherein X is a Pauli X gate, Y is a Pauli Y gate, Z is a Pauli Z gate, I is an I gate, and i is an imaginary number.

[0057] Optionally, the second determining module comprises:

[0058] A first determining unit is configured to determine a quantum sub-circuit according to the type of the logic gate corresponding to each subterm in each term in the matrix A'.

[0059] A second determining unit is configured to determine a coefficient corresponding to the quantum sub-circuit according to a value of a matrix corresponding to the quantum sub-circuit and a value of a non-zero element.

[0060] Optionally, the second determining unit is further configured to:

[0061] divide the value of the non-zero element by the value of the matrix corresponding to the quantum sub-circuit, and the calculation result is the coefficient corresponding to the quantum sub-circuit.

[0062] Optionally, the second determining module further comprises:

[0063] A third determining unit is configured to determine that there is a same quantum sub-circuit.

[0064] The merging unit is configured to merge the same quantum sub-circuits into one item, and coefficients of the merged quantum sub-circuits are the sum of the corresponding coefficients of the quantum sub-circuits before merging.

[0065] In a third aspect, an electronic device is provided, which includes a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the method of any one of the first aspect.

[0066] In a fourth aspect, a storage medium is provided, which stores a computer program, and the computer program is configured to execute the method of any one of the first aspect when running.

[0067] In a fifth aspect, a quantum computer operating system is provided, which implements construction of a quantum circuit according to the method of any one of the first aspect.

[0068] In a sixth aspect, a quantum computer is provided, which includes the quantum computer operating system of the fifth aspect.

[0069] Based on the construction method, device and storage medium of the quantum circuit, the non-zero element index in the to-be-decomposed matrix is converted into a binary representation form, and based on this, the quantum sub-circuit and the corresponding coefficient of the quantum sub-circuit are determined according to the logic gate type corresponding to each item of the to-be-decomposed matrix after expansion, and then the quantum circuit can be constructed. Since this method only requires the matrix to be a square matrix, without other requirements such as the matrix being a density matrix or an Ermi matrix, the technical problem of how to encode the matrix to generate a corresponding quantum circuit is solved. BRIEF DESCRIPTION OF DRAWINGS

[0070] Figure 1 FIG. 1 is a hardware structure block diagram of a computer terminal for a quantum circuit construction method according to an example embodiment of the present application;

[0071] Figure 2 FIG. 2 is a schematic diagram of a quantum circuit display mode according to an example embodiment of the present application;

[0072] Figure 3 FIG. 3 is a flowchart of a quantum circuit construction method according to an example embodiment of the present application;

[0073] Figure 4 FIG. 4 is a schematic block diagram of a quantum circuit construction device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0074] The embodiments described below with reference to the drawings are exemplary and are used only to explain the present application and cannot be explained as a limitation of the present application.

[0075] The embodiment of the present application first provides a construction method of a quantum circuit, which can be applied to an electronic device, such as a computer terminal, specifically, a common computer, a quantum computer, and the like.

[0076] The construction method of the quantum circuit provided by the embodiment of the present application is described in detail below by taking a computer terminal as an example. Figure 1 A hardware structure block diagram of a computer terminal of the construction method of the quantum circuit provided by the embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the computer terminal 10 can include one or more (only one is shown in the figure) processors 102 (the processor 102 can include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Optionally, the above computer terminal can further include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that the structure shown in the figure is only schematic, which does not limit the structure of the above computer terminal. For example, the computer terminal 10 can further include more or less components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 Figure 1 The computer terminal 10 can further include a bus 101 for interconnecting the above components. The bus 101 can be implemented by a system bus, a point-to-point connection, or any other suitable type of communication link. Figure 1 Figure 1 Figure 1

[0077] The memory 104 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the construction method of the quantum circuit in the embodiment of the present application. The processor 102 performs various function applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the above method. The memory 104 can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, a flash memory, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the computer terminal 10 through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0078] ​​​​The transmission device 106 is configured to receive or send data via a network. The network can include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network interface controller (NIC) that can connect to other network devices through a base station to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0079] It should be noted that a real quantum computer is a hybrid structure, which includes two parts: one part is a classical computer responsible for performing classical computation and control; the other part is a quantum device responsible for running a quantum program to implement quantum computation. The quantum program is a sequence of instructions written in a quantum language such as QRunes language that can run on a quantum computer, which supports quantum logic gate operations and ultimately realizes quantum computation. Specifically, the quantum program is a sequence of instructions for operating quantum logic gates in a certain time sequence.

[0080] In practical applications, due to the limitations of the development of quantum device hardware, quantum computation simulation is usually needed to verify quantum algorithms, quantum applications, and the like. Quantum computation simulation is a process of simulating the running of a quantum program corresponding to a specific problem by means of a virtual architecture (i.e., a quantum virtual machine) built by an ordinary computer. Generally, a quantum program corresponding to a specific problem needs to be constructed. The quantum program referred to in the embodiments of the present application is a program written in a classical language representing quantum bits and their evolution, in which quantum bits, quantum logic gates, and the like related to quantum computation are represented by corresponding classical codes.

[0081] As an embodiment of a quantum program, a quantum circuit, also known as a quantum logic circuit, is the most commonly used general quantum computation model, which represents a circuit for operating quantum bits in an abstract concept, and its composition includes quantum bits, a circuit (a time line), and various quantum logic gates, and finally the result needs to be read out through a quantum measurement operation.

[0082] The quantum circuit can be a sequence of quantum logic gates arranged in a certain time sequence. Specifically, for example:

[0083] q0: RX(q0), H(q0), CNOT(q0, q2), X(q0)

[0084] q1: X(q1), RY(q1), H(q1), CNOT(q2, q1)

[0085] q2: H(q2), X(q2), CNOT(q0, q2), CNOT(q2, q1), RZ(q2)

[0086] A more visual representation of the quantum circuit corresponding to the above sequence of quantum logic gates is shown in FIG. 2. Figure 2

[0087] Unlike traditional circuits, which are connected by metal wires to pass voltage signals or current signals, in quantum circuits, the wires can be seen as connected by time, i.e., the states of the qubits evolve naturally over time, in the process of which they are operated on according to the instructions of the Hamiltonian operator, until they encounter quantum logic gates.

[0088] A quantum program as a whole corresponds to a total quantum circuit, and the quantum program described in the present application refers to the total quantum circuit, wherein the total number of qubits in the total quantum circuit is the same as the total number of qubits of the quantum program. It can be understood that a quantum program can be composed of a quantum circuit, measurement operations on the qubits in the quantum circuit, registers for storing measurement results, and control flow nodes (jump instructions). A quantum circuit can contain tens, hundreds, or even thousands of quantum logic gate operations. The execution process of a quantum program is the process of executing all quantum logic gates in a certain time sequence. It should be noted that the time sequence refers to the time order in which individual quantum logic gates are executed.

[0089] It should be noted that in classical computing, the most basic unit is a bit, and the most basic control mode is a logic gate, which can be combined to achieve the purpose of controlling the circuit. Similarly, the way to handle qubits is quantum logic gates. Using quantum logic gates, the quantum state can evolve, and quantum logic gates are the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, etc., and multi-bit quantum logic gates such as CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. Quantum logic gates are generally represented by unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the quantum state right vector by the unitary matrix on the left.

[0090] ​The logic state of a quantum state, i.e., a quantum bit, is represented in binary in a quantum algorithm (or quantum program). For example, a set of quantum bits q0, q1, q2 represents the 0th, 1st, and 2nd quantum bits, and the quantum state corresponding to the set of quantum bits q2q1q0 from high to low is 2n, where n is the total number of quantum bits, and there are 8 eigenstates (determined states): |000>, |001>, |010>, |011>, |100>, |101>, |110>, and |111>. Each bit of each quantum state corresponds to a quantum bit, for example, the |000> state corresponds to q2q1q0 from high to low, and |> is the Dirac symbol.

[0091] Taking a single quantum bit as an example, the logic state of the single quantum bit ψ can be in the |0> state, the |1> state, or a superposition state (an uncertain state) of the |0> state and the |1> state, and can be specifically represented as ψ = a|0> + b|1>, where a and b are complex numbers representing the amplitude (probability amplitude) of the quantum state, the square of the amplitude represents the probability, a 2 , b 2 represent the probabilities of the logic state being in the |0> state and the |1> state, respectively, a 2 +b 2 = 1. In short, a quantum state is a superposition state of eigenstates, and when the probability of other states is 0, it is in a uniquely determined eigenstate.

[0092] The construction method of the quantum circuit provided in the embodiments of the application will be further described and explained below.

[0093] Referring to Figure 3 , Figure 3 is a flowchart of a construction method of a quantum circuit provided in an example embodiment of the application, including steps S310 to S360, wherein:

[0094] S310, determining a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed.

[0095] The matrix A to be decomposed is a square matrix, and the element type in the square matrix is a complex number. That is, for any given square matrix (the element type is a complex number, and the form is a+bi), the scheme of the application can decompose the square matrix into a linear combination of real numbers (corresponding to floating-point numbers in calculation) and quantum circuits. The logic gates in the quantum circuit only include the following types: Pauli X gate, Pauli Y gate, Pauli Z gate, and I gate (2-order unit matrix).

[0096] The matrix A to be decomposed can be defined as follows: the matrix A to be decomposed is an N×N square matrix, and the non-zero elements are A kj, k, j are corresponding row index and column index respectively, S is the set of non-zero elements in the matrix A to be decomposed or can also be understood as the number of terms of linear combination before the merged coefficient, s is the iteration index of non-zero element in the matrix A to be decomposed or can also be understood as the number of the non-zero element, then the matrix A to be decomposed is expressed as follows:

[0097]

[0098] After determining the matrix A to be decomposed and the set of non-zero elements in the matrix A to be decomposed, step S320 is performed.

[0099] S320, converting the non-zero element index in the matrix A to be decomposed into binary representation.

[0100] For an N×N matrix A to be decomposed, the binary representation of the non-zero element index in the matrix A to be decomposed is as follows:

[0101]

[0102]

[0103] After converting the non-zero element index in the matrix A to be decomposed into binary representation, step S330 is performed.

[0104] S330, according to the binary representation of the non-zero element index in the matrix A to be decomposed, each term in the matrix A to be decomposed is expanded and represented as a matrix A'.

[0105] After the matrix A to be decomposed is decomposed into each term expansion, the representation of the represented matrix A' is as follows:

[0106]

[0107] Wherein, n is the number of bits after converting the decimal row index or the decimal column index into binary, and m is an integer between 1 and n.

[0108] S340, according to the value of the subterm in each term of the matrix A', determine the type of the logic gate corresponding to the subterm in each term of the matrix A'.

[0109] According to the representation of the matrix A', wherein, The value of only can be 0 or 1, The value of only can be 0 or 1. That is, for the subterm The value of only can be one of |0><0|, |0><1|, |1><0|, |1><1|.

[0110] According to the value of the subterm in each term in the matrix A', each value corresponds to a type of logic gate formed by a combination of Pauli gates and I gates. The corresponding relationship is shown as follows:

[0111]

[0112]

[0113]

[0114]

[0115] wherein i represents an imaginary number.

[0116] After determining the type of logic gate corresponding to the subterm in each term in the matrix A', step S350 is performed.

[0117] S350, according to the type of logic gate corresponding to the subterm in each term in the matrix A', determining the quantum subcircuit and the coefficient corresponding to the quantum subcircuit.

[0118] wherein the quantum subcircuit corresponds to a non-zero element.

[0119] Specifically, step S350 can include the following steps:

[0120] S3501, according to the type of logic gate corresponding to the subterm in each term in the matrix A', determining the quantum subcircuit;

[0121] Defining a quantum bit to be acted on by a finite number of quantum logic gates, according to the type of logic gate corresponding to the subterm in each term in the matrix A', the logic gates in the logic gate type are sequentially applied to the quantum bit to construct a quantum circuit.

[0122] The matrix A'' corresponding to the constructed quantum circuit is represented as follows:

[0123]

[0124] wherein L is a set of Pauli operator subcircuits, l is an iteration index of the Pauli operator subcircuit, and ω is a subcircuit.

[0125] S3502, according to the value of the matrix corresponding to the quantum subcircuit and the value of the non-zero element, determining the coefficient corresponding to the quantum subcircuit.

[0126] The coefficient corresponding to the quantum subcircuit can be determined by dividing the value of the non-zero element by the value of the matrix corresponding to the quantum subcircuit to obtain the quantum subcircuit and the coefficient corresponding to the non-zero element.

[0127] Since the basic properties of the set include independence, uniqueness and disorder. That is, for all elements in the set, there are no two identical elements. Therefore, optionally, step S350 can further include the following steps:

[0128] S3503, determining that there is a same quantum sub-circuit.

[0129] That is, after step S3502 is performed, it is necessary to determine whether there is a same quantum sub-circuit. If there is a same quantum sub-circuit, step S3504 is performed. If there is no same quantum sub-circuit, step S360 is performed.

[0130] S3504, merging the same quantum sub-circuit into one.

[0131] Wherein, the coefficient of the merged quantum sub-circuit is the sum of the corresponding coefficients of each quantum circuit before merging.

[0132] After determining the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit, step S360 can be performed, and the quantum circuit is constructed according to the coefficient and the quantum sub-circuit.

[0133] The quantum circuit can be constructed by encoding the coefficient into the quantum sub-circuit and connecting each quantum sub-circuit in time sequence.

[0134] Compared with the prior art, based on the quantum circuit construction method shown in Figure 3 The quantum circuit construction method shown in the figure, based on the binary representation of the non-zero element index in the matrix to be decomposed, determines the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the logical gate type corresponding to each sub-item of the expanded item in the matrix to be decomposed, and then constructs the quantum circuit. Since this method only requires the matrix to be a square matrix, it does not have other requirements such as the matrix being a density matrix or an Ermi matrix, thereby realizing the Pauli operator decomposition of any square matrix type complex matrix, and solving the technical problem of how to encode the matrix to generate the corresponding quantum circuit in the related art.

[0135] The above Figure 3 The quantum circuit construction method provided by the embodiment of the application is described in detail. The following Figure 4 The device for executing the quantum circuit construction method provided by the embodiment of the application is described in detail.

[0136] Exemplarily, referring to Figure 4 , Figure 4 A schematic block diagram of a quantum circuit construction device provided by an exemplary embodiment of the application, corresponding to the flow shown in Figure 3 The quantum circuit construction device 400 includes:

[0137] The first determining module 410 is configured to determine a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed; wherein the matrix A to be decomposed is a square matrix and the element type in the square matrix is a complex number.

[0138] The conversion module 420 is configured to convert the non-zero element index in the matrix A to be decomposed into a binary representation.

[0139] The decomposition module 430 is configured to expand and re-represent each term in the matrix A to be decomposed as a matrix A' according to the binary representation of the non-zero element index in the matrix A to be decomposed.

[0140] The second determining module 440 is configured to determine the logic gate type corresponding to each subterm in each term of the matrix A' according to the value of each subterm in each term of the matrix A'.

[0141] The third determining module 450 is configured to determine a quantum sub-circuit and a coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to each subterm in each term of the matrix A'; wherein the quantum sub-circuit corresponds to a non-zero element.

[0142] The construction module 460 is configured to construct a quantum circuit according to the coefficient and the quantum sub-circuit.

[0143] Optionally, the non-zero element in the matrix A to be decomposed is A kj , k and j respectively correspond to a row index and a column index, S is a set of non-zero elements in the matrix A to be decomposed, and s is an iteration index of the non-zero element in the matrix A to be decomposed; the binary representation of the non-zero element index in the matrix A to be decomposed is:

[0144]

[0145]

[0146] The matrix A to be decomposed is represented as:

[0147] The matrix A' is represented as:

[0148]

[0149] wherein n is the number of bits after converting a decimal row index or a decimal column index into binary, and m is an integer between 1 and n.

[0150] Optionally, the value of each subterm in each term of the matrix A' is one of |0><0|, |0><1|, |1><0|, and |1><1|.

[0151] The second determining module 450 determines the logic gate type corresponding to each subterm in each term of the matrix A' according to the following rules:

[0152]

[0153]

[0154]

[0155]

[0156] Where X is the Pauli X gate, Y is the Pauli Y gate, Z is the Pauli Z gate, I is the I gate, and i is the imaginary number.

[0157] Optionally, the second determining module 450 includes:

[0158] The first determining unit is used to determine the quantum circuit based on the logic gate type corresponding to each sub-item in matrix A′;

[0159] The second determining unit is used to determine the coefficients corresponding to the quantum circuit based on the values ​​of the matrix corresponding to the quantum circuit and the values ​​of the non-zero elements.

[0160] Optionally, the second determining unit is further configured to:

[0161] The value of a non-zero element is divided by the value of the matrix corresponding to the quantum circuit, and the result of the calculation is the coefficient corresponding to the quantum circuit.

[0162] Optionally, the second determining module further includes:

[0163] The third determining unit is used to determine whether identical quantum circuits exist;

[0164] A merging unit is used to merge identical quantum circuits into one term; wherein the coefficient of the merged quantum circuit is the sum of the coefficients of the individual quantum circuits before merging.

[0165] Compared with existing technologies, based on Figure 4 The quantum circuit construction device shown converts the non-zero element indices in the matrix to be decomposed into binary representations. Based on this, it determines the quantum sub-circuit and its corresponding coefficients according to the logic gate type of each sub-item after expansion in the matrix to be decomposed. Thus, a quantum circuit can be constructed. Since this method only requires the matrix to be a square matrix, without other requirements such as the matrix being a density matrix or a Hermitian matrix, it realizes the Pauli operator decomposition of complex matrices of arbitrary square matrix types. After decomposition, a quantum circuit can be constructed to simulate the evolution of Hamiltonians, solving the technical problem in related technologies of how to encode a matrix to generate the corresponding quantum circuit.

[0166] The embodiment of the present application further provides a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to execute the steps in any one of the method embodiments.

[0167] Specifically, in the embodiment, the storage medium can be configured to store a computer program for executing the following steps:

[0168] S310, determining a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed.

[0169] S320, converting the indexes of the non-zero elements in the matrix A to be decomposed into a binary representation.

[0170] S330, expanding and re-representing each item in the matrix A to be decomposed as a matrix A' according to the binary representation of the indexes of the non-zero elements in the matrix A to be decomposed.

[0171] S340, determining the type of a logic gate corresponding to each sub-item in each item of the matrix A' according to the value of each sub-item in each item of the matrix A'.

[0172] S350, determining a quantum sub-circuit and a coefficient corresponding to the quantum sub-circuit according to the type of the logic gate corresponding to each sub-item in each item of the matrix A'.

[0173] S360, constructing a quantum circuit according to the coefficient and the quantum sub-circuit.

[0174] Specifically, in the embodiment, the storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk and various storage media that can store a computer program.

[0175] The embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to execute the steps in any one of the method embodiments.

[0176] Specifically, the electronic device can further include a transmission device and an input-output device, wherein the transmission device is connected to the processor, and the input-output device is connected to the processor.

[0177] Specifically, in the embodiment, the processor can be configured to execute the following steps through the computer program:

[0178] S310, determining a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed.

[0179] S320, converting the non-zero element index in the matrix A to be decomposed into a binary representation.

[0180] S330, expanding and re-representing each item in the matrix A to be decomposed into a matrix A' according to the binary representation of the non-zero element index in the matrix A to be decomposed.

[0181] S340, determining the logic gate type corresponding to each sub-item in each item of the matrix A' according to the value of each sub-item in each item of the matrix A'.

[0182] S350, determining the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit according to the logic gate type corresponding to each sub-item in each item of the matrix A'.

[0183] S360, constructing a quantum circuit according to the coefficient and the quantum sub-circuit.

[0184] Optionally, the processor in the electronic device can be one or more. The processor can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented by software, the processor can be a general-purpose processor, which realizes by reading software codes stored in a memory.

[0185] Optionally, the memory in the electronic device can also be one or more. The memory can be integrated with the processor or set separately from the processor, which is not limited in the present application. For example, the memory can be a non-transient processor, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or set separately on different chips, and the type of the memory and the setting mode of the memory and the processor are not limited in the present application.

[0186] The electronic device can be, for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD) or other integrated circuits.

[0187] It should be understood that the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0188] It should also be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, but not by way of limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0189] The embodiments of the present application also provide a quantum computer operating system, which is used to implement the construction of a quantum circuit according to any one of the above method embodiments provided in the embodiments of the present application.

[0190] The embodiments of the present application also provide a quantum computer, which includes the above quantum computer operating system.

[0191] The above-described embodiments can be implemented in part or in whole through software, hardware (e.g., circuitry), firmware, or any combination thereof. When implemented in software, the above-described embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When loaded and executed by a computer, the computer instructions or computer programs can produce the processes or functions described above in accordance with the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, such as from a website site, a computer, a server, or a data center to another website site, a computer, a server, or a data center through a wired (e.g., infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium or a collection of medium accessible by a computer or a data storage device such as a server, a data center, etc. containing one or more available medium. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state disk.

[0192] It should be understood that the term "and / or" in this document is merely used to describe an associated relationship between associated objects, and can represent three relationships, for example, A and / or B can represent three cases of A alone, A and B together, and B alone, where A and B can be singular or plural. In addition, the character " / " in this document generally represents an "or" relationship between the front and rear associated objects, but can also represent an "and / or" relationship. The specific meaning can be understood according to the context before and after.

[0193] In this application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or similar expressions means any combination of the items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0194] It should be understood that in various embodiments of the present application, the size of the sequence number of the above-described processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0195] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0196] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0197] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0198] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0199] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0200] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0201] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of constructing a quantum circuit, characterized by, The method comprises: determining a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed; wherein the matrix A to be decomposed is a square matrix and the element type in the square matrix is a complex number; The non-zero element index in the matrix A to be decomposed is converted into a binary representation, wherein the non-zero element The row index and the column index of the non-zero element are respectively represented in binary as follows: and The matrix A to be decomposed is represented as follows: S is a set of non-zero elements in the matrix A to be decomposed, and s is an iteration index of the non-zero element in the matrix A to be decomposed. According to the binary representation of the non-zero element index in the matrix A to be decomposed, each item in the matrix A to be decomposed is expanded and represented as a matrix wherein, … … n is the number of bits converted from the decimal row index or the decimal column index to binary, and m is an integer between 1 and n. According to the value of each subterm of each term of the matrix , determine the type of logic gate corresponding to each subterm of each term of the matrix , wherein the value of the subterm is one of , , , , and the type of logic gate corresponding is , , , , X is a Pauli X gate, Y is a Pauli Y gate, Z is a Pauli Z gate, I is an I gate, is a dummy gate; According to the matrix a type of logic gate corresponding to each sub-item in each item, a quantum sub-circuit and a coefficient corresponding to the quantum sub-circuit; wherein the quantum sub-circuit corresponds to a non-zero element, and the coefficient corresponding to the quantum sub-circuit is determined by dividing the value of the non-zero element by the value of the matrix corresponding to the quantum sub-circuit. constructing a quantum circuit according to the coefficient and the quantum sub-circuit.

2. The method of claim 1, wherein, The matrix The type of logic gate corresponding to each sub-item in each item in the matrix, determines the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit, comprising: According to the matrix The quantum sub-circuit is determined according to the type of the logic gate corresponding to each sub-item in each item in the matrix. determining the coefficient corresponding to the quantum sub-circuit according to the value of the matrix corresponding to the quantum sub-circuit and the value of the non-zero element.

3. The method of claim 2, wherein, The matrix The type of logic gate corresponding to each sub-item in each item in the matrix, the quantum sub-circuit and the coefficient corresponding to the quantum sub-circuit are determined by the following steps. determining that there is the same quantum sub-circuit; merging the same quantum sub-circuit into one item; wherein the coefficient of the quantum sub-circuit after merging is the sum of the coefficients corresponding to each quantum sub-circuit before merging.

4. A device for constructing a quantum circuit, characterized by The device comprises: a first determining module configured to determine a matrix A to be decomposed and a set of non-zero elements in the matrix A to be decomposed; wherein the matrix A to be decomposed is a square matrix and the element type in the square matrix is a complex number; A conversion module is configured to convert the non-zero element index in the matrix A to be decomposed into a binary representation, wherein the binary representations of the row index and the column index of the non-zero element are respectively: and The matrix A to be decomposed is represented as: S is a set of non-zero elements in the matrix A to be decomposed, and s is an iteration index of the non-zero elements in the matrix A to be decomposed.​​​ a decomposition module, configured to expand and re-express each item in the matrix A to be decomposed into a matrix according to a binary representation of a non-zero element subscript in the matrix A to be decomposed wherein, … … n is a decimal row subscript or a number of bits after conversion of a decimal column subscript into binary, and m is an integer between 1 and n; The second determining module is used to determine the matrix. The value of each sub-item in each term determines the matrix. The logic gate type corresponding to each sub-item in each item, where the value of the sub-item is... , , , One of them, the logic gate type corresponds to , , , X is the Pauli X-gate, Y is the Pauli Y-gate, Z is the Pauli Z-gate, and I is the I-gate. It is an imaginary number; a third determining module, configured to determine a quantum sub-circuit and a coefficient corresponding to the quantum sub-circuit according to a logic gate type corresponding to each sub-item in each item in the matrix a third determining module, configured to determine a quantum sub-circuit and a coefficient corresponding to the quantum sub-circuit according to a logic gate type corresponding to each sub-item in each item in the matrix a constructing module configured to construct a quantum circuit according to the coefficient and the quantum sub-circuit. 5.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to run the computer program to execute the method in any one of claims 1 to 3.

6. A storage medium, characterized by The storage medium stores a computer program, wherein the computer program is configured to execute the method in any one of claims 1 to 3 when running.

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