Display panel and display device

Abstract

The display panel and the display device belong to the technical field of display. The pixel driving circuit of the display panel comprises a threshold compensation transistor, and the display panel further comprises a threshold compensation bottom wire and a threshold compensation top wire for loading the threshold compensation signal. The threshold compensation bottom wire is located on the side of the channel region of the threshold compensation transistor close to the substrate, and the threshold compensation top wire is located on the side of the channel region of the threshold compensation transistor away from the substrate. The threshold compensation bottom wire has an enlarged part overlapping with the channel region of the threshold compensation transistor, and the threshold compensation top wire has a channel definition part overlapping with the channel region of the threshold compensation transistor; the orthographic projection of the channel definition part of the threshold compensation top wire on the substrate is located in the orthographic projection of the enlarged part of the threshold compensation bottom wire on the substrate. The display panel can improve the uniformity of display.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] LTPO (Low Temperature Poly-silicon Transistor + Metal Oxide Transistor) technology is applied to a display panel, which can reduce power consumption of the display panel and improve low-frequency display effect. However, the display panel applying the LTPO technology is prone to periodic bright and dark stripes, which reduces the quality and yield of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The present disclosure aims to overcome the deficiencies of the prior art, and provide a display panel and a display device to improve the brightness uniformity of the display panel.

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a substrate substrate, a driving circuit layer and a pixel layer which are sequentially stacked; the pixel layer is provided with a sub-pixel; the driving circuit layer is provided with a pixel driving circuit for driving the sub-pixel;

[0006] The pixel driving circuit comprises a threshold compensation transistor, a storage capacitor and a driving transistor for generating a driving current; the drain electrode of the threshold compensation transistor, the gate electrode of the driving transistor and the first electrode plate of the storage capacitor are electrically connected to a first node, and the source electrode of the threshold compensation transistor and the drain electrode of the driving transistor are electrically connected to a second node; the threshold compensation transistor is a metal oxide transistor, which is used to compensate the threshold voltage of the driving transistor in response to a threshold compensation signal;

[0007] The driving circuit layer further comprises a threshold compensation bottom trace and a threshold compensation top trace for loading the threshold compensation signal; the threshold compensation bottom trace is located on the side of the channel region of the threshold compensation transistor close to the substrate substrate, and the threshold compensation top trace is located on the side of the channel region of the threshold compensation transistor away from the substrate substrate;

[0008] The threshold compensation bottom trace has an enlarged portion overlapping the channel region of the threshold compensation transistor, and the threshold compensation top trace has a channel definition portion overlapping the channel region of the threshold compensation transistor;

[0009] The orthogonal projection of the channel definition portion of the threshold compensation top trace on the substrate substrate is located within the orthogonal projection of the enlarged portion of the threshold compensation bottom trace on the substrate substrate.

[0010] According to an embodiment of the present disclosure, the pixel driving circuit further comprises a data writing transistor, a drain of the data writing transistor and a source of the driving transistor are electrically connected with the third node; the data writing transistor is configured to load a data voltage to the third node in response to a data scanning signal; the data writing transistor is a polysilicon transistor; the driving circuit layer further comprises a data scanning wire configured to load the data scanning signal; along an extension direction of a channel region of the data writing transistor, a size of a portion of the data scanning wire overlapping with the channel region of the data writing transistor is a third size;

[0011] Along an extension direction of a channel region of the threshold compensation transistor, a size of a channel defining portion of the threshold compensation top wire is a first top size, and a size of the bulging portion of the threshold compensation bottom wire is a first bottom size; a difference between the first bottom size and the first top size is 0.5-0.75 times of the third size.

[0012] According to an embodiment of the present disclosure, along an extension direction of a channel region of the threshold compensation transistor, a size of a channel defining portion of the threshold compensation top wire is a first top size, and a size of the bulging portion of the threshold compensation bottom wire is a first bottom size.

[0013] The first bottom size is 1.3-2 times of the first top size.

[0014] According to an embodiment of the present disclosure, the first bottom size is 1.4-1.7 times of the first top size.

[0015] According to an embodiment of the present disclosure, along an extension direction of a channel region of the threshold compensation transistor, a size of a channel defining portion of the threshold compensation top wire is a first top size, and a size of the bulging portion of the threshold compensation bottom wire is a first bottom size.

[0016] The first bottom size is at least 1.5 microns larger than the first top size.

[0017] According to an embodiment of the present disclosure, the first bottom size is 2-3 microns larger than the first top size.

[0018] According to an embodiment of the present disclosure, along an extension direction of a channel region of the threshold compensation transistor, a boundary of a normal projection of the bulging portion of the threshold compensation bottom wire on the substrate is at least 0.2 microns beyond a boundary of a normal projection of the channel defining portion of the threshold compensation top wire on the substrate.

[0019] According to an embodiment of the present disclosure, the driving circuit layer comprises a first source-drain metal layer, a first planarization layer, and a second source-drain metal layer arranged in sequence.

[0020] The first source-drain metal layer is provided with a first conductive structure and a second conductive structure; the second source-drain metal layer is provided with a data voltage trace for loading a data voltage and a driving voltage trace for loading a driving voltage; the first conductive structure is electrically connected to the source of the data writing transistor and the data voltage trace through a via; and the second conductive structure is electrically connected to the second electrode plate of the storage capacitor and the driving voltage trace through a via.

[0021] The second conductive structure has a parasitic capacitance adjusting portion extending along the column direction, and the parasitic capacitance adjusting portion is arranged to overlap the data voltage trace.

[0022] According to an embodiment of the present disclosure, the second conductive structure is electrically connected between two adjacent second conductive structures.

[0023] According to an embodiment of the present disclosure, the driving circuit layer further comprises a first buffer layer, a polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, a second buffer layer, a second gate layer, a second gate insulating layer, a metal-oxide semiconductor layer, a third gate insulating layer, a third gate layer, and an interlayer dielectric layer arranged in sequence between the substrate and the first source-drain metal layer.

[0024] The channel region of the driving transistor and the channel region of the data writing transistor are arranged in the polysilicon semiconductor layer, and the first electrode plate of the storage capacitor is arranged in the first gate layer; the first gate layer covers the channel region of the driving transistor.

[0025] The threshold compensation bottom trace and the second electrode plate of the storage capacitor are arranged in the second gate layer, and the threshold compensation top trace is arranged in the third gate layer; and the channel region of the threshold compensation transistor is arranged in the metal-oxide semiconductor layer.

[0026] According to another aspect of the present disclosure, a display device is provided, comprising the display panel described above.

[0027] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1-1 This is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0030] Figure 1-2 This is a cross-sectional view of a display panel according to one embodiment of the present disclosure.

[0031] Figure 2 This is a schematic diagram of the core module of the pixel driving circuit in one embodiment of the present disclosure.

[0032] Figure 3 This is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0033] Figure 4 This is a cross-sectional structural diagram of a threshold compensation transistor in related technologies.

[0034] Figure 5 This is a cross-sectional view of a threshold compensation transistor in one embodiment of the present disclosure.

[0035] Figure 6 This is a cross-sectional view of a capacitor reset transistor in one embodiment of the present disclosure.

[0036] Figure 7 This is a schematic diagram of the stacked structure of a polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source / drain metal layer in a circuit layout area according to one embodiment of this disclosure.

[0037] Figure 8 This is an enlarged schematic diagram of a partial stacked structure of a polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, and a third gate layer in a circuit layout area according to an embodiment of this disclosure.

[0038] Figure 9 This is an enlarged schematic diagram of a partial stacked structure of the second gate layer in a circuit layout area according to one embodiment of this disclosure.

[0039] Figure 10 This is an enlarged schematic diagram of a partial stacked structure of the third gate layer in a circuit layout area according to an embodiment of this disclosure.

[0040] Figure 11This is a partial structural diagram of a metal light-shielding layer in one embodiment of the present disclosure.

[0041] Figure 12 This is a partial structural schematic diagram of a polycrystalline silicon semiconductor layer in one embodiment of the present disclosure.

[0042] Figure 13 This is a partial structural diagram of the first gate layer in one embodiment of the present disclosure.

[0043] Figure 14 This is a partial structural diagram of the second gate layer in one embodiment of the present disclosure.

[0044] Figure 15 This is a partial structural schematic diagram of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0045] Figure 16 This is a partial structural diagram of the third gate layer in one embodiment of the present disclosure.

[0046] Figure 17 This is a partial structural diagram of the first source / drain metal layer in one embodiment of the present disclosure.

[0047] Figure 18 This is a schematic diagram of the stacked structure of the second gate layer, the metal oxide semiconductor layer, the third gate layer and the first source / drain metal layer in one embodiment of the present disclosure.

[0048] Figure 19 This is a schematic diagram of the structure of the second source / drain metal layer in one embodiment of the present disclosure. Detailed Implementation

[0049] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0050] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0051] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0052] In this disclosure, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the area through which current primarily flows. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchangeable. Therefore, in this specification, "source" and "drain" are interchangeable and relative concepts.

[0053] In this disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are disposed on different film layers, and the orthographic projection of structure A on the substrate overlaps with the orthographic projection of structure B on the substrate.

[0054] In this disclosure, the overlapping portion of structure C and structure D refers to a specific portion C1 in structure C; the orthographic projection of this specific portion C1 on the substrate is the overlapping portion of the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate.

[0055] In this disclosure, structural layer E is located on the side of structural layer F away from the substrate. This can be understood as structural layer E being formed on the side of structural layer F away from the substrate. When structural layer F is a patterned structure, some structures of structural layer E may also be located at the same physical height as structural layer E or below the physical height of structural layer E, wherein the substrate serves as the height reference.

[0056] This disclosure provides a display panel, see [link]Figure 1-1 The display panel includes a display area AA and a peripheral area BB surrounding the display area AA. Within the display area AA, the display panel is provided with sub-pixels (e.g., Figure 1-1 The display panel consists of an organic light-emitting diode (OLED) and a pixel drive circuit (PDC) that drives the sub-pixels. Under the drive of the PDC, each sub-pixel emits light independently, enabling the display panel to display an image.

[0057] Figure 1-2 A cross-sectional view of a display panel according to an embodiment of this disclosure is illustrated. See also Figure 1-2 The display panel includes a substrate BP, a driving circuit layer FA, and a pixel layer FB stacked in sequence.

[0058] The substrate BP can be made of inorganic or organic materials. For example, in one embodiment of this disclosure, the substrate BP can be made of glass materials such as soda-lime glass, quartz glass, or sapphire glass, or metal materials such as stainless steel, aluminum, or nickel. In another embodiment of this disclosure, the substrate BP can be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or combinations thereof. In another embodiment of this disclosure, the substrate BP can also be a flexible substrate BP, for example, the substrate BP can be made of polyimide (PI). The substrate BP can also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate BP may include a bottom film, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.

[0059] As an example, in Figure 1-2 In this design, the substrate BP is made of polyimide to enable the display panel to be a flexible display panel. (See also...) Figure 1-2 The display panel can be first formed on a support substrate SBP, and the support substrate SBP can be peeled off after fabrication. In this way, the support substrate SBP can provide support for the display panel during the manufacturing process.

[0060] The driver circuit layer (FA) contains pixel driver circuits for driving sub-pixels. Within the driver circuit layer (FA), any pixel driver circuit may include a transistor and a storage capacitor. See also... Figure 1-2 The driving circuit layer is provided with a polycrystalline silicon semiconductor layer SEMI1 and a metal oxide semiconductor layer SEMI2, such that the transistors in the driving circuit layer include at least metal oxide transistors and polycrystalline silicon transistors (e.g., low-temperature polycrystalline silicon transistors). Further, these transistors can be thin-film transistors. Of course, in other embodiments of this disclosure, the polycrystalline silicon transistors can also be amorphous silicon transistors; correspondingly, the polycrystalline silicon semiconductor layer SEMI1 of the driving circuit layer can be replaced with an amorphous silicon semiconductor layer.

[0061] In this disclosure, the polysilicon transistor can be a top-gate thin-film transistor, a bottom-gate thin-film transistor, or a dual-gate thin-film transistor, depending on its ability to effectively control the transistor. The metal-oxide transistor is a dual-gate thin-film transistor, meaning that the channel region of the transistor is sandwiched between the top gate (the gate on the side away from the substrate) and the bottom gate (the gate on the side closer to the substrate). In this way, the bottom gate can block light from the substrate side, preventing light from shining into the channel region of the transistor and causing abnormal transistor operation.

[0062] In some embodiments of this disclosure, the gate of the polysilicon transistor can be disposed in the same layer as a gate of the metal-oxide transistor; for example, the gate of the polysilicon transistor and the bottom gate of the metal-oxide transistor can be disposed in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top and bottom gates of the metal-oxide transistor can be disposed in different gate layers.

[0063] As an example, see Figure 1-2 The driving circuit layer includes a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, and a third gate layer GT3, which are sequentially stacked on one side of the substrate BP. The polysilicon semiconductor layer SEMI1 contains the active region of a polysilicon transistor, and the first gate layer GT1 contains the gate of the polysilicon transistor. The metal oxide semiconductor layer SEMI2 contains the active region of a metal oxide transistor; the second gate layer GT2 contains the bottom gate of the metal oxide transistor; and the third gate layer GT3 contains the top gate of the metal oxide transistor. In this disclosure, the active region of the transistor includes a channel region of the transistor and source and drain electrodes located on both sides of the channel region; wherein the channel region maintains semiconductor characteristics, and the source and drain electrodes are conductive.

[0064] In the disclosure, the display panel also has control traces for loading control signals to the gates of transistors. These control traces may extend substantially along the row direction and be electrically connected to the gates of the driven transistors. Further, the control traces and the gates of the driven transistors are disposed on the same gate layer. Exemplarily, the control traces may overlap with the channel region of the driven transistor, such that the overlapping portion is multiplexed as the gate of the transistor. See, as an example... Figure 1-1 The control traces of the display panel include one or more of the following: pixel electrode reset trace RPL for loading the pixel electrode reset signal RP; data scan trace GPL for loading the data scan signal GP; threshold compensation trace GN1L for loading the threshold compensation signal GN1; capacitor reset trace GN2L for loading the capacitor reset signal GN2; and light emission control trace EML for loading the light emission control signal EM. Among these, in... Figure 1-1 In the example, the data scan trace GPL and the pixel electrode reset trace RPL can be reused as the same trace; in other embodiments of this disclosure, the data scan trace GPL and the pixel electrode reset trace RPL can also be two different traces. It is understood that the type and number of control traces can differ in different display panels, especially in display panels with different pixel drive circuits (PDCs).

[0065] In embodiments of this disclosure, the driving circuit layer further includes a source / drain metal layer located on the side of each gate layer and semiconductor layer away from the substrate BP. The source / drain metal layer is provided with a data voltage trace DataL for loading a data voltage Data and a driving voltage trace VDDL for loading a driving voltage VDD. The data voltage trace DataL is used to load the data voltage Data to the pixel driving circuit PDC, so that the pixel driving circuit PDC controls the brightness of the sub-pixels according to the voltage value of the data voltage Data. In this disclosure, the source / drain metal layer can be one layer, two layers, or three layers. Figure 1-2 In the example, the source and drain metal layers are two layers, including a first source and drain metal layer SD1 and a second source and drain metal layer SD2 stacked together; an interlayer dielectric layer ILD is disposed on the surface of the first source and drain metal layer SD1 near the substrate BP; a first planarization layer PLN1 is disposed between the first source and drain metal layer SD1 and the second source and drain metal layer SD2; and a second planarization layer PLN2 is disposed on the side of the second source and drain metal layer SD2 away from the substrate BP.

[0066] Optionally, the driving circuit layer FA may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer away from the substrate BP, in order to protect the source / drain metal layer.

[0067] Optionally, the driving circuit layer FA may further include a first buffer layer Buff1 disposed between the substrate BP and the semiconductor layer, wherein the semiconductor layer and the gate layer are both located on the side of the first buffer layer Buff1 away from the substrate BP. The material of the first buffer layer Buff1 may be an inorganic insulating material such as silicon oxide or silicon nitride. The first buffer layer Buff1 may be a single inorganic material layer or a multilayer stacked inorganic material layer.

[0068] Optionally, the driving circuit layer FA may further include a metal light-shielding layer LS located between the first buffer layer Buff1 and the substrate BP, the metal light-shielding layer LS being able to shield at least a portion of the transistor's channel region. Further, in some embodiments, the metal light-shielding layer LS may be electrically connected to the source / drain metal layers via vias, thus allowing the metal light-shielding layer LS to perform signal transmission, signal shielding, or other functions as needed. For example, a common electrode voltage may be applied to the metal light-shielding layer LS to enable it to achieve signal shielding. As another example, a portion of the metal light-shielding layer LS may be patterned as conductive lines so that the conductive lines located on the metal light-shielding layer LS can be used to transmit signals, such as touch signals.

[0069] Optionally, an inorganic barrier layer Barr can be provided between the metal light-shielding layer LS and the first buffer layer Buff1 to prevent the material in the substrate BP from penetrating into the driving circuit layer.

[0070] The pixel layer (FB) is provided with an array of light-emitting elements, and each light-emitting element emits light under the control of the pixel driving circuit. These light-emitting elements can serve as sub-pixels in embodiments of this disclosure. In this disclosure, the light-emitting elements can be organic light-emitting diodes (OLEDs), micro light-emitting diodes (Micro LEDs), quantum dot-organic light-emitting diodes (QD-OLEDs), quantum dot light-emitting diodes (QLEDs), or other types of light-emitting elements. For example, see [link to relevant documentation]. Figure 1-1 In one embodiment of this disclosure, the light-emitting element is an organic light-emitting diode (OLED), and the display panel is an OLED display panel. Below, taking an organic light-emitting diode as an example, a feasible structure of the pixel layer is described exemplarily.

[0071] In this example, the pixel layer FB can be disposed on the side of the driving circuit layer FA away from the substrate BP. It may include a pixel electrode layer ANL, a pixel definition layer PDL, a support pillar layer PS, an organic light-emitting functional layer EL, and a common electrode layer COML, stacked sequentially. The pixel electrode layer ANL has multiple pixel electrodes in the display area of ​​the display panel. The pixel definition layer PDL has multiple through-holes in the display area, each corresponding to one of the pixel electrodes, with each pixel opening exposing at least a portion of the corresponding pixel electrode. The support pillar layer PS includes multiple support pillars in the display area, located on the surface of the pixel definition layer PDL away from the substrate BP, to support a fine metal mask (FMM) during the evaporation process. The organic light-emitting functional layer EL at least covers the pixel electrodes exposed by the pixel definition layer PDL. The organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. The individual layers of the organic light-emitting functional layer (EL) can be fabricated using a vapor deposition process, and the pattern of each layer can be defined using a fine metal mask or an open mask during vapor deposition. A common electrode layer (COML) can cover the EL in the display area. Thus, the pixel electrode, the common electrode layer (COML), and the EL located between the pixel electrode and the common electrode layer (COML) form an organic light-emitting diode (OLED) F300D, and any one of these OLEDs can serve as a sub-pixel of the display panel.

[0072] In some embodiments, the pixel layer FB may also include a light extraction layer located on the side of the common electrode layer COML away from the substrate BP, to enhance the light extraction efficiency of the organic light-emitting diode.

[0073] Optionally, the display panel may further include a thin-film encapsulation layer (TFE). The TFE is disposed on the surface of the pixel layer FB away from the substrate BP, and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer (EL) and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the substrate BP.

[0074] Optionally, the display panel may also include a touch function layer, which is located on the side of the thin film encapsulation layer TFE away from the substrate BP, and is used to realize touch operation of the display panel.

[0075] Optionally, the display panel may further include an anti-reflection layer, which may be disposed on the side of the thin-film encapsulation layer (TFE) away from the pixel layer (FB) to reduce the reflection of ambient light by the display panel, thereby reducing the impact of ambient light on the display effect. In one embodiment of this disclosure, the anti-reflection layer may include a color filter layer and a black matrix layer stacked together, thus improving the color gamut of the display panel while reducing ambient light interference. In another embodiment of this disclosure, the anti-reflection layer may be a polarizer, such as a patterned coated circular polarizer. Further, the anti-reflection layer may be disposed on the side of the touch functional layer away from the substrate (BP).

[0076] In the display panel provided in this disclosure, the pixel driving circuit PDC includes a storage capacitor Cst and a plurality of transistors, wherein a portion of the transistors are polysilicon transistors and another portion are metal-oxide transistors. The pixel driving circuit PDC may include a core module for providing drive current. See also Figure 2 The core module may include a storage capacitor Cst, a threshold compensation transistor T2, and a driving transistor T3. The drain of the threshold compensation transistor T2, the gate of the driving transistor T3, and the first electrode plate CP1 of the storage capacitor Cst are electrically connected to a first node N1. The source of the threshold compensation transistor T2 and the drain of the driving transistor T3 are electrically connected to a second node N2. The threshold compensation transistor T2 is a metal-oxide-semiconductor transistor used to compensate the threshold voltage of the driving transistor T3 in response to a threshold compensation signal GN1. The driving transistor T3 is a polysilicon transistor that can generate a driving current under the control of the first node N1.

[0077] At the initial moment of the data writing stage of the pixel driver circuit PDC, the first node N1 has been pre-reset (at a negative voltage), causing the driving transistor T3 to be turned on. After entering the data writing stage, the data voltage Data is written to the first node N1; the threshold compensation transistor T2 is turned on under the control of the threshold compensation signal GN1, making the first node N1 and the second node N2 electrically connected. At this time, the third node N3 can charge the first node N1 through the driving transistor T3 and the threshold compensation transistor T2, so that the voltage of the first node N1 rises to the point that the driving transistor T3 is turned off. The voltage difference between the voltage of the first node N1 and the voltage of the third node N3 is the threshold voltage of the driving transistor T3. In this way, after the data writing stage, the voltage of the first node N1 is related to the threshold voltage of the driving transistor T3 and the data voltage Data, overcoming the problem of uneven threshold voltage of the driving transistor T3 due to process reasons. Of course, in the display panel disclosed herein, the pixel driver circuit PDC, in addition to the core module mentioned above, also needs to include other transistors to realize the functions of resetting the pixel driver circuit PDC, writing the data voltage Data, and controlling the light emission of sub-pixels.

[0078] Figure 3 A pixel drive circuit (PDC) is provided as an example. See also Figure 3 In addition to the core modules described above, the exemplary pixel driving circuit PDC also includes transistors such as capacitor reset transistor T1, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and pixel electrode reset transistor T7. It is understood that in other examples of this disclosure, the pixel driving circuit PDC may also include other transistors or storage capacitor Cst, or may have fewer transistors; the electrical connections between the transistors, the applied signals, and the timing of the applied signals may also be... Figure 3 The pixel drive circuit PDC in the example is different; the one with the above-mentioned core module shall prevail.

[0079] As follows, Figure 3 Taking the example of the pixel driving circuit PDC, the structure, principle and effect of the display panel of the present disclosure embodiment will be further introduced and explained.

[0080] exist Figure 3In the example pixel driving circuit PDC, the first electrode plate of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate of the storage capacitor Cst is used to load the driving voltage VDD. Thus, the voltage loaded on the second electrode plate of the storage capacitor Cst is stable. In other embodiments of this disclosure, the second electrode plate of the storage capacitor Cst can be loaded with other power supply voltages, such as the same common voltage loaded on the common electrode layer. Of course, in other embodiments of this disclosure, the voltage of the second electrode plate of the storage capacitor may not be constant; for example, the drain of the capacitor reset transistor and the drain of the data write transistor are electrically connected to the second electrode plate of the storage capacitor; the capacitor reset transistor is used to reset the voltage of the second electrode plate of the storage capacitor, and the data write transistor is used to load the data voltage onto the second electrode plate of the storage capacitor; through coupling, the voltage of the first node can be adjusted as the voltage of the second electrode plate of the storage capacitor is adjusted.

[0081] exist Figure 3 In the example pixel driving circuit PDC, the PDC further includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The source of the first light-emitting control transistor T5 is used to load a driving voltage VDD, for example, it is electrically connected to a driving voltage trace VDDL used to load the driving voltage VDD. The drain of the first light-emitting control transistor T5 is electrically connected to a third node N3. The source of the second light-emitting control transistor T6 is electrically connected to a second node N2, and the drain of the second light-emitting control transistor T6 is electrically connected to a fourth node N4. The fourth node N4 is also electrically connected to the pixel electrode of the sub-pixel. The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to load a light-emitting control signal EM, for example, they are electrically connected to a light-emitting control trace EML used to load the light-emitting control signal EM. When the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on in response to the light-emitting control signal EM, the driving current generated by the driving transistor T3 can flow to the sub-pixel, thereby driving the sub-pixel to emit light. Further, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are polysilicon transistors. Of course, in other embodiments of this disclosure, the pixel driving circuit PDC may include only one of the first light-emitting control transistor T5 and the second light-emitting control transistor T6.

[0082] exist Figure 3In the example pixel driving circuit PDC, the pixel driving circuit PDC also includes a capacitor reset transistor T1 and a data writing transistor T4. The source of the capacitor reset transistor T1 is used to load a first initialization voltage Vinit1, and the drain of the capacitor reset transistor T1 is electrically connected to the first node N1. The capacitor reset transistor T1 is used to load the first initialization voltage Vinit1 to the first node N1 in response to the capacitor reset signal GN2, thereby resetting the first node N1. In this example, the capacitor reset transistor T1 is a metal-oxide-semiconductor transistor; in other examples of this disclosure, the capacitor reset transistor T1 can also be a polysilicon transistor. The data writing transistor T4 is a polysilicon transistor. The source of the data writing transistor T4 is used to load a data voltage Data, for example, electrically connected to a data voltage trace DataL used to load the data voltage Data; the drain of the data writing transistor T4 is electrically connected to the third node N3; the data writing transistor T4 is used to load the data voltage Data to the third node N3 in response to the data scan signal GP.

[0083] Understandable, Figure 3 In the example pixel drive circuit PDC, the capacitor reset transistor T1 is electrically connected to the first node N1 and the data write transistor T4 is electrically connected to the third node N3. In other embodiments of this disclosure, the data write transistor T4 and the capacitor reset transistor T1 may also have other connection arrangements, such as the drain of the data write transistor T4 and the drain of the capacitor reset transistor T1 being electrically connected to the second electrode plate of the storage capacitor Cst.

[0084] exist Figure 3 In the example pixel driving circuit PDC, the pixel driving circuit PDC further includes a pixel electrode reset transistor T7, which is a polysilicon transistor. The source of the pixel electrode reset transistor T7 is used to apply a second initialization voltage Vinit2, for example, by being electrically connected to a second initialization voltage trace Vinit2L used to apply the second initialization voltage Vinit2. The drain of the pixel electrode reset transistor T7 is electrically connected to a fourth node N4. The pixel electrode reset transistor T7 is used to apply the second initialization voltage Vinit2 to the fourth node N4 in response to the pixel electrode reset signal RP, thereby resetting the pixel electrode of the sub-pixel. Of course, in other embodiments of this disclosure, the pixel driving circuit PDC may not include the pixel electrode reset transistor T7, or the pixel electrode reset transistor T7 may be a metal-oxide-slim film transistor.

[0085] exist Figure 3In the example pixel drive circuit PDC, the first initialization voltage Vinit1 applied to the source of capacitor reset transistor T1 and the second initialization voltage Vinit2 applied to the source of pixel electrode reset transistor T7 can be different voltage signals, for example, they can be voltage signals from different traces (the magnitude of the voltage can be the same). In other examples of this disclosure, the first initialization voltage Vinit1 applied to the source of capacitor reset transistor T1 and the second initialization voltage Vinit2 applied to the source of pixel electrode reset transistor T7 can also be the same signal, for example, a signal from the same trace.

[0086] exist Figure 3 In the example display panel, a switch SW can be provided between the source driving circuit of the display panel and the data voltage traces DataL, meaning that one source driving circuit can drive multiple data voltage traces DataL. When driving the pixel driving circuit PDC, by controlling the sequential conduction of each switch SW, the required data voltage Data for each data voltage trace DataL can be pre-written onto each data voltage trace DataL; then, a data scan signal GP is applied to the gate of the data writing transistor T4 of the same row of pixel driving circuits PDC, so that the data voltage Data on each data voltage trace DataL is simultaneously written into the electrically connected pixel driving circuit PDC. Of course, in other embodiments of this disclosure, each source driving circuit can drive one data voltage trace DataL.

[0087] In the display panel disclosed herein, Figure 3 The pixel driving circuit PDC shown can operate sequentially according to the following timing sequence. During the capacitor reset phase, the gate of the capacitor reset transistor T1 is turned on by the capacitor reset signal GN2, causing the first node N1 to be reset to the first initialization voltage Vinit1. At this time, under the control of the first node N1, the driving transistor T3 is turned on. The threshold compensation transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the data writing transistor T4, and the pixel electrode reset transistor T7 remain off.

[0088] During the data writing phase, the gate of the data writing transistor T4 is loaded with the data scan signal GP, causing T4 to conduct and the data voltage Data to be written to the third node N3. The gate of the threshold compensation transistor T2 is loaded with the threshold compensation signal GN1, causing T2 to conduct. The capacitor reset transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 remain off. Thus, the third node N3 can charge the first node N1, causing its voltage to rise until it reaches a level that turns off the driving transistor T3. In this way, the data voltage Data and the threshold voltage of the driving transistor T3 are written to the first node N1, where the voltage of the first node N1 is VData + Vth3, where Vth3 is the threshold voltage of the driving transistor T3 and VData is the value of the data voltage Data. Therefore, during the data writing phase, both data writing and threshold compensation of the driving transistor T3 are simultaneously achieved.

[0089] During the pixel electrode reset phase, the pixel electrode reset transistor T7 is turned on by loading the pixel electrode reset signal RP onto its gate, thereby applying the second initialization voltage Vinit2 to the fourth node N4. In some embodiments, the pixel electrode reset signal RP of the previous row pixel driving circuit PDC and the data scan signal GP of the next row pixel driving circuit PDC are the same signal, which means that when the previous row pixel driving circuit PDC is in the pixel electrode reset phase, the next row pixel driving circuit PDC is in the data writing phase. Of course, in other examples of this disclosure, the pixel electrode reset signal RP and the data scan signal GP of the same row pixel driving circuit PDC can be the same signal, and the pixel electrode reset phase and the data writing phase of that row pixel driving circuit PDC are the same phase, that is, the data writing transistor T4 and the pixel electrode reset transistor T7 are synchronously turned on or off.

[0090] During the light-emitting stage, the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are loaded with the light-emitting control signal EM, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to conduct. In this way, the driving voltage VDD is applied to the third node N3, and the second node N2 is electrically connected to the sub-pixel; the driving transistor T3 outputs a driving current under the control of the first node N1, thereby driving the sub-pixel to emit light.

[0091] It is understood that the 7T1C (7 transistors and 1 storage capacitor) pixel driving circuit PDC of the above example of this disclosure is merely one exemplary pixel driving circuit PDC for the display panel of this disclosure, and not a specific limitation on the pixel driving circuit PDC used in the display panel of this disclosure. In other embodiments of this disclosure, the pixel driving circuit PDC may include more or fewer transistors, such as 8 transistors, 9 transistors, etc., and one or more of the transistors shown in the example of 7T1C above may also be configured as multiple sub-transistors connected in series. In other embodiments of this disclosure, the pixel driving circuit PDC may include more storage capacitors Cst, such as two or three storage capacitors.

[0092] In the display panel disclosed herein, the pixel driving circuit PDC reduces leakage current at the first node N1 by setting the threshold compensation transistor T2 as a metal-oxide-semiconductor transistor, thereby improving the voltage holding capability of the pixel driving circuit PDC, reducing the risk of flickering under low-frequency driving, and reducing the power consumption of the display panel. However, in actual testing, it was found that some display panels exhibit noticeable (visible to the naked eye) grayscale lines during display, such as periodic stripes with alternating bright and dark areas when displaying a solid color image. After extensive analysis of the structure and manufacturing process of the display panel, the inventors discovered that the appearance of these grayscale lines is related to structural fluctuations in the threshold compensation transistor T2.

[0093] See Figure 4The threshold compensation transistor T2 typically includes a top gate T2GU located above the channel region T2Act (away from the substrate BP) and a bottom gate T2GD located below the channel region T2Act (closer to the substrate BP). In design, the bottom gate T2GD is generally made slightly larger than the top gate T2GU to stabilize the characteristics of the channel region T2Act. Since the threshold compensation transistor T2 functions as a switch and the voltage applied to it is either high or low, the purpose of the bottom gate T2GD in stabilizing the channel region T2Act is to reduce the leakage current of the threshold compensation transistor T2. To improve the resolution of the display panel and reduce the layout area of ​​the pixel drive circuit PDC, it is generally necessary to compress the size of each structure as much as possible. Therefore, in existing designs, the bottom gate T2GD of the threshold compensation transistor T2 is generally made slightly larger than the top gate T2GU of the threshold compensation transistor T2, and is as narrow as possible while satisfying this condition. However, after extensive analysis of display panels with grayscale lines, the inventors discovered that the size of the bottom gate T2GD of the threshold compensation transistor T2 affects the display effect of the display panel. Specifically, the inventors found that when the edge of the channel region T2Act of the threshold compensation transistor T2 is close to the edge of the bottom gate T2GD of the threshold compensation transistor T2 due to process deviations, the threshold voltage of the threshold compensation transistor T2 will change, and the change in the threshold voltage of the threshold compensation transistor T2 leads to a change in the voltage of the first node N1, which in turn causes grayscale lines to appear on the display panel. Based on this discovery, the inventors provide the following explanation for the generation mechanism of grayscale lines on the display panel.

[0094] See Figure 4 When the edge of the channel region T2Act of the threshold compensation transistor T2 approaches the edge of the bottom gate T2GD of the threshold compensation transistor T2, the threshold voltage of the threshold compensation transistor T2 will shift, that is, the threshold voltage of the threshold compensation transistor T2 will become Vth. 20 +△Vth2; where Vth 20Vth is the threshold voltage of threshold compensation transistor T2 under normal conditions; ΔVth2 is the offset of the threshold voltage of threshold compensation transistor T2. During the data writing phase (also the threshold compensation phase), when the driving transistor T3 is off, the voltage of the first node N1 is VData + Vth3. When the threshold compensation transistor T2 changes from the on state to the off state, electrons in the channel region T2Act of the threshold compensation transistor T2 will be conducted to the first node N1, generating a kickback effect. This causes the voltage of the first node N1 to become VData + Vth - Vk, where Vk is the voltage change caused by the kickback effect on the first node N1.

[0095] Where Vk = 0.5 * Cgi * (VGH + Vth2) / (Cst0 + Cgd). Cgi is the capacitance between the gate and channel regions of the threshold compensation transistor T2; VGH is the voltage applied to the gate of the threshold compensation transistor T2 when it is turned off; Vth2 is the threshold voltage of the threshold compensation transistor T2; Cst0 is the capacitance of the storage capacitor Cst; and Cgd is the capacitance between the gate and drain of the threshold compensation transistor T2.

[0096] Based on the inventor's understanding of the voltage of the first node N1, it can be found that Vk is related to the threshold voltage of the threshold compensation transistor T2. When the threshold voltage of the threshold compensation transistor T2 fluctuates due to the setting of the bottom gate T2GD, Vk will fluctuate, which in turn causes the voltage of the first node N1 to fluctuate, resulting in grayscale lines appearing on the display panel.

[0097] In the display panel of this embodiment, see Figures 7-10The driving circuit layer includes a threshold compensation bottom trace GN1DL and a threshold compensation top trace GN1UL for loading the threshold compensation signal GN1. The threshold compensation bottom trace GN1DL is located on the side of the channel region T2Act of the threshold compensation transistor T2 closer to the substrate BP, and the threshold compensation top trace GN1UL is located on the side of the channel region T2Act of the threshold compensation transistor T2 away from the substrate BP. The threshold compensation bottom trace GN1DL has a bulge GN1DLP that overlaps with the channel region T2Act of the threshold compensation transistor T2, and the portion of the bulge GN1DLP that overlaps with the channel region T2Act of the threshold compensation transistor T2 serves as the bottom gate T2GD of the threshold compensation transistor T2. The threshold compensation top trace GN1UL has a channel definition portion GN1ULP that overlaps with the channel region T2Act of the threshold compensation transistor T2. The portion of the channel definition portion GN1ULP of the threshold compensation top trace GN1UL and the channel region T2Act of the threshold compensation transistor T2 overlaps to form the top gate T2GU of the threshold compensation transistor T2. The orthographic projection of the channel definition portion GN1ULP onto the substrate BP is located within the orthographic projection of the enlarged portion GN1DLP onto the substrate BP.

[0098] In this way, the display panel disclosed herein allows the top gate T2GU of the threshold compensation transistor T2 to be completely located within the range of the bottom gate T2GD of the threshold compensation transistor T2. During the fabrication of the display panel, the top gate T2GU of the threshold compensation transistor T2 can be used to define the channel region T2Act of the threshold compensation transistor T2. This ensures that the channel region T2Act of the threshold compensation transistor T2 is completely shielded by the bottom gate T2GD of the threshold compensation transistor T2, preventing light from the substrate BP side from illuminating the channel region T2Act of the threshold compensation transistor T2 and causing threshold voltage fluctuations in the threshold compensation transistor T2. This, in turn, avoids voltage fluctuations at the first node N1, eliminates grayscale lines in the display panel, and improves the yield and quality of the display panel.

[0099] In embodiments of this disclosure, see Figures 8-10 , and see Figure 5Along the extension direction of the channel region T2Act of the threshold compensation transistor T2, the dimension of the channel definition portion GN1ULP of the threshold compensation top trace GN1UL is a first top dimension S1U, and the dimension of the enlarged portion GN1DLP of the threshold compensation bottom trace GN1DL is a first bottom dimension S1D. In some embodiments of this disclosure, the first bottom dimension S1D is 1.3 to 2 times the first top dimension S1U. In this way, while reducing the size of the threshold compensation transistor T2, especially reducing the size of the enlarged portion GN1DLP of the threshold compensation bottom trace GN1DL, the process window of the threshold compensation transistor T2 can be increased as much as possible, ensuring that the channel region T2Act of the threshold compensation transistor T2 is completely within the range of the bottom gate T2GD of the threshold compensation transistor T2 (i.e., the orthogonal projection of the channel region T2Act on the second gate layer is completely within the bottom gate T2GD). When designing the display panel, along the extension direction of the channel region T2Act of the threshold compensation transistor T2, the centers of the bottom gate T2GD and the top gate T2GU of the threshold compensation transistor T2 can be substantially coincident. At the design level, the edge of the bottom gate T2GD of the threshold compensation transistor T2 can extend beyond the size of the top gate T2GU of the threshold compensation transistor T2 by at least 0.15 times the first top dimension S1U. This extension can essentially eliminate the influence of process deviations (such as alignment deviations) during the manufacturing process of the display panel, ensuring that the edge of the top gate T2GU of the threshold compensation transistor T2 in the actual manufactured display panel will not extend beyond the edge of the bottom gate T2GD of the threshold compensation transistor T2. On the other hand, at the design level, the edge of the bottom gate T2GD of the threshold compensation transistor T2 can extend beyond the size of the top gate T2GU of the threshold compensation transistor T2 by no more than 0.5 times the first top dimension S1U. This avoids the excessive width of the bulge portion GN1DLP of the threshold compensation bottom trace GN1DL, which would lead to an increase in the layout area of ​​the pixel driving circuit PDC. In other words, this embodiment of the present disclosure balances the design dimensions of the display panel, the manufacturing process deviations of the display panel, the losses caused by the increased layout area of ​​the pixel driving circuit PDC in the display panel, and the gains from the sacrificed layout area to eliminate grayscale lines in the display panel. It determines the design methods for the threshold compensation bottom trace GN1DL and the threshold compensation top trace GN1UL, and the specific form of the actual display panel after the design method is transformed into the actual display panel through the manufacturing process. Furthermore, the first bottom dimension S1D is 1.4 to 1.7 times the first top dimension S1U. This allows for an optimal balance between the gains obtained by the display panel in eliminating grayscale defects and the losses caused by increasing the layout area of ​​the pixel driving circuit PDC.

[0100] In some other embodiments of this disclosure, the first bottom dimension S1D is at least 1.5 micrometers larger than the first top dimension S1U. When designing the display panel, along the extension direction of the channel region T2Act of the threshold compensation transistor T2, the centers of the bottom gate T2GD and the top gate T2GU of the threshold compensation transistor T2 can be substantially coincident. Thus, at the design level, the edge of the bottom gate T2GD of the threshold compensation transistor T2 can extend beyond the top gate T2GU of the threshold compensation transistor T2 by at least 0.75 micrometers. This extension can substantially eliminate the influence of process deviations (e.g., alignment deviations) during the fabrication of the display panel.

[0101] Furthermore, the first bottom dimension S1D is at least 2.0 micrometers larger than the first top dimension S1U. When designing the display panel, along the extension direction of the channel region T2Act of the threshold compensation transistor T2, the centers of the bottom gate T2GD and the top gate T2GU of the threshold compensation transistor T2 can be substantially coincident. Thus, at the design level, the edge of the bottom gate T2GD of the threshold compensation transistor T2 can extend beyond the top gate T2GU of the threshold compensation transistor T2 by at least 1.0 micrometer. This extension can largely eliminate the influence of process deviations (e.g., alignment deviations) during the fabrication of the display panel.

[0102] Furthermore, the size by which the first bottom dimension S1D is larger than the first top dimension S1U is no more than 3 micrometers. This avoids the excessive width of the bulge portion GN1DLP of the threshold compensation bottom trace GN1DL, which would otherwise increase the layout area of ​​the pixel driving circuit PDC.

[0103] As an example, the first bottom dimension S1D is 2 to 3 micrometers larger than the first top dimension S1U. In this way, under mainstream process conditions (e.g., process conditions with an alignment deviation of 1 to 1.5 micrometers), an optimal balance can be achieved between the gains in eliminating grayscale defects in the display panel and the losses caused by increasing the layout area of ​​the pixel drive circuit PDC.

[0104] In one embodiment of this disclosure, along the extending direction of the channel region T2Act of the threshold compensation transistor T2, the boundary of the orthogonal projection of the enlarged portion GN1DLP of the threshold compensation bottom trace GN1DL onto the substrate BP extends at least 0.2 micrometers beyond the boundary of the orthogonal projection of the channel definition portion GN1ULP of the threshold compensation top trace GN1UL onto the substrate BP. This further reduces the influence of light from the substrate BP side on the channel region T2Act of the threshold compensation transistor T2, further eliminating fluctuations in the threshold voltage of the threshold compensation transistor T2.

[0105] In one embodiment of this disclosure, see Figure 3 , Figures 7-10 The pixel driving circuit PDC further includes a data writing transistor T4, the drain of which and the source of the driving transistor T3 are electrically connected to the third node N3. The data writing transistor T4 is used to load a data voltage Data onto the third node N3 in response to a data scan signal GP. The data writing transistor T4 is a polysilicon transistor. The driving circuit layer also includes a data scan trace GPL for loading the data scan signal GP. Along the extension direction of the channel region of the data writing transistor T4, the dimension of the portion where the data scan trace GPL overlaps with the channel region of the data writing transistor T4 is a third dimension S3. In other words, see [link to documentation]. Figure 8 The portion of the data scan trace GPL that overlaps with the channel region of the data write transistor T4 serves as the gate T4G of the data write transistor T4. Along the extension direction of the channel region of the data write transistor T4, the gate T4G of the data write transistor T4 has a third dimension S3. The difference between the first bottom dimension S1D and the first top dimension S1U is 0.5 to 0.75 times the third dimension S3.

[0106] In the pixel drive circuit PDC of this embodiment, the data writing transistor T4 is used to load the data voltage Data onto the first node N1, so it only needs to function as a switch. Based on this, a smaller-sized data writing transistor T4 can be selected to reduce the layout area of ​​the pixel drive circuit PDC, depending on the conditions of the display panel fabrication process. Thus, the length of the gate T4G of the data writing transistor T4 (i.e., the third dimension S3) is related to the process deviation during display panel fabrication. In this example, making the difference between the first bottom dimension S1D and the first top dimension S1U 0.5 to 0.75 times the third dimension S3 ensures that the channel region T2Act of the threshold compensation transistor T2 in the actually fabricated display panel is completely within the range of the bottom gate T2GD of the threshold compensation transistor T2. As an example, when the alignment deviation during display panel fabrication is in the range of 1 to 1.5 micrometers, the third dimension S3 can be 2.7 to 3.7 micrometers; the difference between the first bottom dimension S1D and the first top dimension S1U can be approximately 2 micrometers.

[0107] In some embodiments of this disclosure, other metal-oxide transistors can also employ a design similar to the threshold compensation transistor T2 to maintain a stable threshold voltage. For example, a pixel driver circuit PDC has a capacitor reset transistor T1 for resetting the first node N1; the capacitor reset transistor T1 is a metal-oxide transistor. It can then employ a design similar to the threshold compensation transistor T2 to maintain a stable threshold voltage. See also Figures 6-10 The driving circuit layer further includes a capacitor reset bottom trace GN2DL and a capacitor reset top trace GN2UL for loading the capacitor reset signal GN2. The capacitor reset bottom trace GN2DL is located on the side of the channel region T1Act of the capacitor reset transistor T1 closer to the substrate BP, and the capacitor reset top trace GN2UL is located on the side of the channel region T1Act of the capacitor reset transistor T1 away from the substrate BP. The capacitor reset bottom trace GN2DL has an enlarged portion GN2DLP that overlaps with the channel region T1Act of the capacitor reset transistor T1, and the capacitor reset top trace GN2UL has a channel defining portion GN2ULP that overlaps with the channel region T1Act of the capacitor reset transistor T1. The orthographic projection of the channel defining portion GN2ULP on the substrate BP is located within the orthographic projection of the enlarged portion GN2DLP on the substrate BP. Along the extension direction of the channel region T1Act of the capacitor reset transistor T1, the dimension of the channel definition portion GN2ULP is the second top dimension S2U, and the dimension of the enlarged portion GN2DLP is the second bottom dimension S2D.

[0108] In one example, the difference between the second bottom dimension S2D and the second top dimension S2U is 0.5 to 0.75 times the third dimension S3.

[0109] In one example, the second base dimension S2D is 1.3 to 2 times the second top dimension S2U. Further, the second base dimension S2D is 1.4 to 1.7 times the second top dimension S2U.

[0110] In one example, the second bottom dimension S2D is at least 1.5 micrometers larger than the second top dimension S2U. Further, the second bottom dimension S2D is 2 to 3 micrometers larger than the second top dimension S2U.

[0111] In one example, along the extension direction of the channel region T1Act of the capacitor reset transistor T1, the boundary of the orthogonal projection of the enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL onto the substrate BP exceeds the boundary of the orthogonal projection of the channel definition portion GN2ULP of the capacitor reset top trace GN2UL onto the substrate BP by at least 0.2 micrometers.

[0112] In one embodiment of this disclosure, the second top dimension S2U and the first top dimension S1U are substantially the same, and the second bottom dimension S2D and the first bottom dimension S1D are substantially the same.

[0113] In one embodiment of this disclosure, see Figure 1-2 and Figure 3 The driving circuit layer includes a first source-drain metal layer SD1, a first planarization layer PLN1, and a second source-drain metal layer SD2, which are stacked sequentially. The pixel driving circuit PDC also includes a data writing transistor T4, the drain of the data writing transistor T4 and the source of the driving transistor T3 being electrically connected to the third node N3. See also Figures 7-19 The first source / drain metal layer SD1 is provided with a first conductive structure ML1 and a second conductive structure ML2; the second source / drain metal layer SD2 is provided with a data voltage trace DataL and a drive voltage trace VDDL; the first conductive structure ML1 is electrically connected to the source of the data writing transistor T4 and the data voltage trace DataL through vias; the second conductive structure ML2 is electrically connected to the second electrode plate CP2 of the storage capacitor Cst and the drive voltage trace VDDL through vias. The second conductive structure ML2 has a parasitic capacitance adjustment section extending along the column direction, which overlaps with the data voltage trace DataL. This increases the parasitic capacitance C_Data of the data voltage trace DataL. When the data voltage Data is applied to the data voltage trace DataL, the data voltage Data can be maintained on the data voltage trace DataL for a longer period of time without significant voltage drop. When the data writing transistor T4 is turned on to charge the first node N1, the large parasitic capacitance of the data voltage trace DataL can ensure the charging rate of the first node N1, avoiding insufficient charging rate that could affect the normal display of the display panel, such as avoiding image distortion due to insufficient charging.

[0114] In one embodiment of this disclosure, two adjacent second conductive structures ML2 are connected to each other, so that two adjacent driving voltage traces VDDL are electrically connected through the second conductive structures ML2. This gridded distribution of the driving voltage VDD in the display area AA of the display panel improves the signal uniformity of the driving voltage VDD, thereby preventing uneven display on the display panel due to voltage drop or current unevenness of the driving voltage VDD.

[0115] The following description, in conjunction with the accompanying drawings, introduces and explains the specific layout of the pixel driving circuit PDC of the 7T1C in the display panel of the above example. It is understood that the 7T1C in the embodiments of this disclosure can also be presented in other layout configurations, and the display panel of this disclosure can also employ other pixel driving circuit PDCs. When other pixel driving circuit PDC structures are used, the layout configuration of the pixel driving circuit PDC in the display panel of this disclosure can be adjusted accordingly.

[0116] See Figure 1-2 In this example display panel, the driving circuit layer FA includes, in sequence, a metal light-shielding layer LS, an inorganic barrier layer Barr, a first buffer layer Buff1, a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, and a second planarization layer PLN2, all stacked on one side of the substrate BP. It is understood that in some other embodiments of the display panel disclosed herein, the metal light-shielding layer LS may not be provided.

[0117] In the display area AA, the main area where the pixel driver circuit PDC is set can be defined as the circuit layout area PDCA corresponding to that pixel driver circuit PDC. In this way, the main or most of the transistors and storage capacitors Cst of the pixel driver circuit PDC are located in the corresponding circuit layout area PDCA. See also Figure 7 The circuit layout area PDCA can be rectangular. In two adjacent rows of pixel driving circuit PDCs, the pixel electrode reset transistor T7 of the previous row of pixel driving circuit PDCs can be placed in the circuit layout area PDCA of the next row of pixel driving circuit PDCs. In other words, the capacitor reset transistors T1 to T6 and the storage capacitor Cst of the pixel driving circuit PDCs are placed in the circuit layout area PDCA of that pixel driving circuit PDC, and the pixel electrode reset transistor T7 of the pixel driving circuit PDCs is placed in the circuit layout area PDCA of the next row. In the example of this disclosure, the layout of two adjacent pixel driving circuit PDCs can be mirrored. Of course, in other embodiments of this disclosure, the layout of two adjacent pixel driving circuit PDCs can also be the same rather than mirrored.

[0118] Figure 11 A partial structural schematic diagram of the metallic light-shielding layer LS of a display panel according to an example of this disclosure is shown. See also Figure 11In the circuit layout area PDCA, the metal light-shielding layer LS consists of metal light-shielding portions LSP and connecting traces LSL; adjacent metal light-shielding portions LSP in the same row and adjacent in the same column are connected by connecting traces LSL. Thus, the metal light-shielding layer LS forms a grid, which can shield external signals and prevent signals from outside the display panel from affecting the normal display. The metal light-shielding portions LSP need to be relatively large to block light shining on the channel region of the driving transistor T3, ensuring the stable characteristics of the driving transistor T3.

[0119] Figure 12 A partial structural schematic diagram of the polysilicon semiconductor layer SEMI1 of the display panel of this disclosure example is shown. Figure 13 A partial structural schematic diagram of the first gate layer GT1 of a display panel according to an example of this disclosure is shown. See also Figure 12 The polysilicon semiconductor layer SEMI1 has polysilicon patterns corresponding one-to-one with each pixel driving circuit PDC. These polysilicon patterns form the channel region T3Act of the driving transistor T3, the channel region T4Act of the data writing transistor T4, the channel region T5Act of the first light-emitting control transistor T5, the channel region T6Act of the second light-emitting control transistor T6, and the channel region T7Act of the pixel electrode reset transistor T7, all possessing semiconductor characteristics. Furthermore, it forms a first polysilicon strip PL1, a second polysilicon strip PL2, a third polysilicon strip PL3, a fourth polysilicon strip PL4, a fifth polysilicon strip PL5, and a sixth polysilicon strip PL6 that have been conductiveized. The first polysilicon strip PL1, the second polysilicon strip PL2, the third polysilicon strip PL3, the fourth polysilicon strip PL4, the fifth polysilicon strip PL5, and the sixth polysilicon strip PL6 may be conductiveized after the first gate layer GT1 has been patterned. See also... Figure 12The first polysilicon strip PL1 is electrically connected to one end of the channel region T4Act of the data writing transistor T4, serving as the source of the data writing transistor T4. The second polysilicon strip PL2 is electrically connected to the other end of the channel region T4Act of the data writing transistor T4, one end of the channel region T3Act of the driving transistor T3, and one end of the channel region T5Act of the first light-emitting control transistor T5, serving as part of the third node N3, and simultaneously serving as the drain of the data writing transistor T4, the source of the driving transistor T3, and the drain of the first light-emitting control transistor T5. The third polysilicon strip PL3 is electrically connected to the other end of the channel region T5Act of the first light-emitting control transistor T5, serving as the source of the first light-emitting control transistor T5. The fourth polysilicon strip PL4 is electrically connected to the other end of the channel region T3Act of the driving transistor T3 and one end of the channel region T6Act of the second light-emitting control transistor T6, serving as part of the second node N2, and simultaneously serving as the drain of the driving transistor T3 and the source of the second light-emitting control transistor T6. The fifth polysilicon strip PL5 is electrically connected to the other end of the channel region T6Act of the second light-emitting control transistor T6 and one end of the channel region T7Act of the pixel electrode reset transistor T7, thus forming part of the fourth node N4, and simultaneously serving as the drain of both the second light-emitting control transistor T6 and the pixel electrode reset transistor T7. The sixth polysilicon strip PL6 is electrically connected to the other end of the channel region T7Act of the pixel electrode reset transistor T7, thus serving as the source of the pixel electrode reset transistor T7. See also Figure 12 The channel region T7Act, the sixth polysilicon strip PL6, and a portion of the fifth polysilicon strip PL5 of the pixel electrode reset transistor T7 of the polysilicon pattern corresponding to the pixel driving circuit PDC can be arranged in the circuit layout area PDCA corresponding to the next row of pixel driving circuit PDC; correspondingly, the channel region T7Act, the sixth polysilicon strip PL6, and a portion of the fifth polysilicon strip PL5 of the pixel electrode reset transistor T7 of the previous row of pixel driving circuit PDC are arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC.

[0120] See Figure 7 The channel region T3Act of the driving transistor T3 is bent to give it a longer length, for example, 15-25 micrometers. Furthermore, the area where the channel region T3Act of the driving transistor T3 is distributed, projected onto the metal light-shielding layer LS, can be completely located within the metal light-shielding portion LSP. In this way, the metal light-shielding portion LSP can shield the channel region T3Act of the driving transistor T3 from light. See also... Figure 13 and Figure 12The first gate layer GT1 is provided with a first electrode plate CP1 of the storage capacitor Cst, which completely covers the channel region T3Act of the driving transistor T3; that is, the orthogonal projection of the channel region T3Act of the driving transistor T3 onto the first gate layer GT1 is located within the range of the first electrode plate CP1 of the storage capacitor Cst. Thus, the first electrode plate CP1 of the storage capacitor Cst can serve as the gate of the driving transistor T3.

[0121] See Figure 7 The channel region T4Act of the data write transistor T4 in the next row of the pixel drive circuit PDC is adjacent to the channel region T7Act of the pixel electrode reset transistor T7 in the previous row of the pixel drive circuit PDC. See here. Figure 13 and Figure 7 The first gate layer GT1 has a data scan trace GPL that extends substantially along the row direction for loading the data scan signal GP. The data scan trace GPL overlaps with the channel region T4Act of the data write transistor T4. The overlapping portion of the data scan trace GPL and the channel region T4Act of the data write transistor T4 can be reused as the gate T4G of the data write transistor T4. The data scan trace GPL also overlaps with the channel region T7Act of the pixel electrode reset transistor T7. Thus, the overlapping portion of the data scan trace GPL and the channel region T7Act of the pixel electrode reset transistor T7 can be reused as the gate of the pixel electrode reset transistor T7. The data scan signal GP loaded on the data scan trace GPL can also serve as the pixel electrode reset signal RP, allowing the data scan trace GPL to be reused as the pixel electrode reset trace RPL.

[0122] See Figure 12 , Figure 13 and Figure 14 The channel region T5Act of the first light-emitting control transistor T5 and the channel region T6Act of the second light-emitting control transistor T6 are arranged in the same or substantially in the same direction. The first gate layer GT1 is provided with a light-emitting control trace EML for loading the light-emitting control signal EM and extending substantially along the row direction. The light-emitting control trace EML overlaps with the channel region T5Act of the first light-emitting control transistor T5 and the channel region T6Act of the second light-emitting control transistor T6; the portion of the light-emitting control trace EML overlapping with the channel region T5Act of the first light-emitting control transistor T5 is multiplexed as the gate of the first light-emitting control transistor T5, and the portion of the light-emitting control trace EML overlapping with the channel region T6Act of the second light-emitting control transistor T6 is multiplexed as the gate of the second light-emitting control transistor T6.

[0123] Figure 15 A partial structural schematic diagram of the second gate layer GT2 of the display panel of this disclosure example is shown. Figure 16A partial structural schematic diagram of the metal oxide semiconductor layer SEMI2 of the display panel of this disclosure example is shown. Figure 15 A partial structural schematic diagram of the third gate layer GT3 of the display panel of the present disclosure example is shown.

[0124] See Figure 7 The metal-oxide-semiconductor layer SEMI2 has metal-oxide patterns corresponding one-to-one with each pixel driver circuit PDC. The metal-oxide pattern of each pixel driver circuit PDC is completely located within the circuit layout area PDCA corresponding to that pixel driver circuit PDC. The orthogonal projections of the metal-oxide pattern of the pixel driver circuit PDC and the polysilicon pattern on the substrate BP do not overlap. The metal-oxide pattern of the pixel driver circuit PDC includes the channel region T1Act of the capacitor reset transistor T1 and the channel region T2Act of the threshold compensation transistor T2, which maintain semiconductor characteristics, and the conductor-conductive first metal-oxide portion OL1, second metal-oxide portion OL2, and third metal-oxide portion OL3. The first metal-oxide portion OL1, second metal-oxide portion OL2, and third metal-oxide portion OL3 can be conductor-conductive after the third gate layer GT3 is patterned. The second metal oxide portion OL2 is electrically connected to one end of the channel region T1Act of the capacitor reset transistor T1 and one end of the channel region T2Act of the threshold compensation transistor T2, thus serving as part of the first node N1, and simultaneously serving as the drain of both the capacitor reset transistor T1 and the threshold compensation transistor T2. The first metal oxide portion OL1 is electrically connected to the other end of the channel region T1Act of the capacitor reset transistor T1, thus serving as the source of the capacitor reset transistor T1; the third metal oxide portion OL3 is electrically connected to the other end of the channel region T2Act of the threshold compensation transistor T2, thus serving as the source of the threshold compensation transistor T2.

[0125] See Figure 15 and Figure 7The third gate layer GT3 is provided with a capacitor reset top trace GN2UL and a threshold compensation top trace GN1UL extending substantially along the longitudinal direction. The capacitor reset top trace GN2UL is used to load the capacitor reset signal GN2, and has a channel definition portion GN2ULP that overlaps with the channel region T1Act of the capacitor reset transistor T1. The portion of the channel definition portion GN2ULP of the capacitor reset top trace GN2UL that overlaps with the channel region T1Act of the capacitor reset transistor T1 is multiplexed as the top gate T1GU of the capacitor reset transistor T1, and is used to define the boundary of the channel region T1Act of the capacitor reset transistor T1 in its length direction. The threshold compensation top trace GN1UL is used to load the threshold compensation signal GN1, and has a channel definition portion GN1ULP that overlaps with the channel region T2Act of the threshold compensation transistor T2. The portion of the channel definition portion GN1ULP of the threshold compensation top trace GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2 is multiplexed as the top gate T2GU of the threshold compensation transistor T2, and is used to define the boundary of the channel region T2Act of the threshold compensation transistor T2 in the length direction.

[0126] See Figure 14 and Figure 7The second gate layer GT2 is provided with a capacitor reset bottom trace GN2DL extending substantially along the row direction, a threshold compensation bottom trace GN1DL, and a second electrode plate CP2 provided with storage capacitors Cst corresponding one-to-one with each pixel driving circuit PDC. The capacitor reset bottom trace GN2DL is used to load the capacitor reset signal GN2, and has an enlarged portion GN2DLP that overlaps with the channel region T1Act of the capacitor reset transistor T1. The channel definition portion GN2ULP of the capacitor reset top trace GN2UL is projected onto the second gate layer GT2 and is completely within the enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL. This ensures that the projected portion of the channel region T1Act of the capacitor reset transistor T1 is completely within the enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL. In this way, the enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL can both load the capacitor reset signal GN2 onto the channel region T1Act of the capacitor reset transistor T1 to eliminate the floating body effect of the capacitor reset transistor T1, and shield the light from the substrate BP side, thus keeping the channel region T1Act of the capacitor reset transistor T1 stable. The threshold compensation bottom trace GN1DL is used to load the threshold compensation signal GN1, and has an enlarged portion GN1DLP that overlaps with the channel region T2Act of the threshold compensation transistor T2. The channel definition portion GN1ULP of the threshold compensation top trace GN1UL is projected onto the second gate layer GT2 and is completely within the enlarged portion GN1DLP of the threshold compensation bottom trace GN1DL. This ensures that the projected portion of the channel region T2Act of the threshold compensation transistor T2 is completely within the enlarged portion GN1DLP of the threshold compensation bottom trace GN1DL. In this way, the enlarged portion GN1DLP of the threshold compensation bottom trace GN1DL can both load the threshold compensation signal GN1 onto the channel region T2Act of the threshold compensation transistor T2 to eliminate the floating body effect of the threshold compensation transistor T2, and shield the light on the substrate BP side so that the channel region T2Act of the threshold compensation transistor T2 can maintain stable performance.

[0127] See Figure 13 and Figure 14 , Figure 14 The second electrode plate CP2 of the storage capacitor Cst overlaps with the first electrode plate CP1 of the storage capacitor Cst to form the storage capacitor Cst. The second electrode plate CP2 of the storage capacitor Cst has a notch CP2G that exposes a portion of the first electrode plate CP1 of the storage capacitor Cst, allowing the first electrode plate CP1 of the storage capacitor Cst to be connected to the first source / drain metal layer SD1 through a via located in the notch CP2G. See also... Figure 17The second gate layer GT2 may also be provided with a first initialization voltage trace Vinit1L for loading the first initialization voltage Vinit1, which extends substantially along the row direction. Furthermore, the capacitor reset bottom trace GN2DL is located between the threshold compensation bottom trace GN1DL and the first initialization voltage trace Vinit1L.

[0128] Figure 18 A partial structural schematic diagram of the first source / drain metal layer SD1 of a display panel according to an example of this disclosure is shown. Figure 19 A partial structural schematic diagram of the second gate layer GT2, the metal oxide semiconductor layer SEMI2, the third gate layer GT3, and the first source / drain metal layer SD1 of the display panel of this disclosure example is shown. Figure 18 A partial structural schematic diagram of the second source / drain metal layer SD2 of the display panel of this disclosure example is shown.

[0129] See Figure 7 The second source / drain metal layer SD2 has data voltage traces (DataL) and drive voltage traces (VDDL) extending along the column direction, as well as a pixel transition structure (PA). See also Figure 17 , Figure 18 and Figure 7 In the circuit layout area PDCA, the first source-drain metal layer SD1 is provided with a first conductive structure ML1 to a sixth conductive structure ML6, and a second initialization voltage trace Vinit2L extending substantially along the row direction for loading the second initialization voltage Vinit2. The second initialization voltage trace Vinit2L can be bent in the circuit layout area PDCA to avoid other conductive structures.

[0130] The first conductive structure ML1 overlaps with the first polysilicon strip PL1 and is electrically connected via a via. The first conductive structure ML1 also overlaps with the data voltage trace DataL and is electrically connected via a via. In this way, the data voltage Data applied on the data voltage trace DataL can be applied to the first polysilicon strip PL1, which serves as the source of the data write transistor T4, through the first conductive structure ML1.

[0131] The second conductive structure ML2 overlaps with the third polysilicon strip PL3 and is electrically connected via a via. It also overlaps with the second electrode plate CP2 of the storage capacitor Cst and is electrically connected via a via, and further overlaps with the driving voltage trace VDDL and is electrically connected via a via. Thus, the driving voltage VDD applied to the driving voltage trace VDDL can be applied through the second conductive structure ML2 to the second electrode plate CP2 of the storage capacitor Cst and the third polysilicon strip PL3, which serves as the source of the first light-emitting control transistor T5. (See also...) Figure 17 and ​The second conductive structure ML2 has a parasitic capacitance adjustment section extending along the column direction, which overlaps with the data voltage trace DataL. This increases the parasitic capacitance of the data voltage trace DataL, thereby improving its voltage holding capability and charging capability.

[0132] The third conductive structure ML3 overlaps with the second metal oxide portion OL2 and is electrically connected via a via. It also overlaps with the first electrode plate CP1 of the storage capacitor Cst and is electrically connected via a via. The via between the third conductive structure ML3 and the first electrode plate CP1 of the storage capacitor Cst can pass through a notch CP2G. Thus, the second metal oxide portion OL2, which serves as the drain of the threshold compensation transistor T2, the drain of the capacitor reset transistor T1, and part of the first node N1, is electrically connected to the second electrode plate CP2 of the storage capacitor Cst via the third conductive structure ML3.

[0133] The fourth conductive structure ML4 overlaps with the first initialization voltage trace Vinit1L and is electrically connected via a via, and also overlaps with the first metal oxide portion OL1 and is electrically connected via a via. Thus, the first metal oxide portion OL1, which serves as the source of the capacitor reset transistor T1, is electrically connected to the first initialization voltage trace Vinit1L via the fourth conductive structure ML4, and the first initialization voltage Vinit1 applied to the first initialization voltage trace Vinit1L can be applied to the source of the capacitor reset transistor T1.

[0134] The fifth conductive structure ML5 is overlapped and electrically connected to the third metal oxide portion OL3, and also overlapped and electrically connected to the fourth polysilicon strip PL4. In this way, the third metal oxide portion OL3, which serves as the source of the threshold compensation transistor T2, and the fourth polysilicon strip PL4, which serves as the drain of the driving transistor T3, the source of the second light-emitting control transistor T6, and a part of the second node N2, are electrically connected through the fifth conductive structure ML5.

[0135] The sixth conductive structure ML6 overlaps with the fifth polysilicon strip PL5 and is electrically connected through a via, and also overlaps with the pixel transition structure PA and is electrically connected through a via. Thus, the fifth polysilicon strip PL5, which serves as the drain of the second light-emitting control transistor T6, the drain of the pixel electrode reset transistor T7, and part of the fourth node N4, is electrically connected to the pixel transition structure PA through the sixth conductive structure ML6. The pixel transition structure PA is used to electrically connect to the pixel electrode of the sub-pixel.

[0136] This disclosure also provides a display device, which includes any of the display panels described in the above-described display panel embodiments. The display device can be a smartphone screen, a smartwatch screen, or other types of display devices. Since this display device has any of the display panels described in the above-described display panel embodiments, it has the same beneficial effects, and will not be repeated here.

[0137] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a substrate, a driving circuit layer, and a pixel layer stacked sequentially; the pixel layer having sub-pixels; and the driving circuit layer having a pixel driving circuit for driving the sub-pixels; The pixel driving circuit includes a threshold compensation transistor, a storage capacitor, and a driving transistor for generating driving current. The drain of the threshold compensation transistor, the gate of the driving transistor, and the first electrode plate of the storage capacitor are electrically connected to the first node, and the source of the threshold compensation transistor and the drain of the driving transistor are electrically connected to the second node; the threshold compensation transistor is a metal-oxide transistor, used to compensate the threshold voltage of the driving transistor in response to a threshold compensation signal; The driving circuit layer further includes a threshold compensation bottom trace and a threshold compensation top trace for loading the threshold compensation signal; the threshold compensation bottom trace is located on the side of the channel region of the threshold compensation transistor closer to the substrate, and the threshold compensation top trace is located on the side of the channel region of the threshold compensation transistor away from the substrate. The threshold compensation bottom trace has an enlarged portion that overlaps with the channel region of the threshold compensation transistor, and the threshold compensation top trace has a channel definition portion that overlaps with the channel region of the threshold compensation transistor. The orthographic projection of the channel definition portion of the threshold compensation top trace on the substrate is located within the orthographic projection of the enlarged portion of the threshold compensation bottom trace on the substrate. The driving circuit layer includes a first source-drain metal layer, a first planarization layer, and a second source-drain metal layer stacked sequentially; the pixel driving circuit also includes a data writing transistor, the drain of the data writing transistor and the source of the driving transistor are electrically connected to the third node; The first source / drain metal layer is provided with a first conductive structure and a second conductive structure; the second source / drain metal layer is provided with a data voltage trace for loading a data voltage and a drive voltage trace for loading a drive voltage; the first conductive structure is electrically connected to the source of the data writing transistor and the data voltage trace through vias; the second conductive structure is electrically connected to the second electrode plate of the storage capacitor and the drive voltage trace through vias. The second conductive structure has a parasitic capacitance adjustment section extending along the column direction, which overlaps with the data voltage trace.

2. The display panel according to claim 1, wherein, The data writing transistor is used to apply a data voltage to the third node in response to a data scan signal; the data writing transistor is a polysilicon transistor; the driving circuit layer also includes a data scan trace for loading the data scan signal; along the extension direction of the channel region of the data writing transistor, the dimension of the portion where the data scan trace overlaps with the channel region of the data writing transistor is the third dimension; Along the extension direction of the channel region of the threshold compensation transistor, the dimension of the channel definition portion of the threshold compensation top trace is the first top dimension, and the dimension of the enlarged portion of the threshold compensation bottom trace is the first bottom dimension; the difference between the first bottom dimension and the first top dimension is 0.5 to 0.75 times the third dimension.

3. The display panel according to claim 1, wherein, Along the extension direction of the channel region of the threshold compensation transistor, the dimension of the channel definition portion of the threshold compensation top trace is the first top dimension, and the dimension of the enlarged portion of the threshold compensation bottom trace is the first bottom dimension; The first bottom dimension is 1.3 to 2 times the first top dimension.

4. The display panel according to claim 3, wherein, The first bottom dimension is 1.4 to 1.7 times the first top dimension.

5. The display panel according to claim 1, wherein, Along the extension direction of the channel region of the threshold compensation transistor, the dimension of the channel definition portion of the threshold compensation top trace is the first top dimension, and the dimension of the enlarged portion of the threshold compensation bottom trace is the first bottom dimension; The first bottom dimension is at least 1.5 micrometers larger than the first top dimension.

6. The display panel according to claim 5, wherein, The first bottom dimension is 2-3 micrometers larger than the first top dimension.

7. The display panel according to claim 1, wherein, Along the extension direction of the channel region of the threshold compensation transistor, the boundary of the orthographic projection of the bulge portion of the threshold compensation bottom trace on the substrate extends at least 0.2 micrometers beyond the boundary of the orthographic projection of the channel definition portion of the threshold compensation top trace on the substrate.

8. The display panel according to claim 1, wherein, There is an electrical connection between two adjacent second conductive structures.

9. The display panel according to claim 1, wherein, The driving circuit layer further includes a first buffer layer, a polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, a second buffer layer, a second gate layer, a second gate insulating layer, a metal oxide semiconductor layer, a third gate insulating layer, a third gate layer, and an interlayer dielectric layer, which are sequentially stacked between the substrate and the first source / drain metal layer. The channel region of the driving transistor and the channel region of the data writing transistor are disposed on the polysilicon semiconductor layer, and the first electrode plate of the storage capacitor is disposed on the first gate layer. The first gate layer covers the channel region of the driving transistor; The threshold compensation bottom trace and the second electrode plate of the storage capacitor are disposed on the second gate layer, and the threshold compensation top trace is disposed on the third gate layer; the channel region of the threshold compensation transistor is disposed on the metal oxide semiconductor layer.

10. A display device comprising the display panel as described in any one of claims 1 to 9.

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