Method and apparatus for testing memory synchronization switching noise
By setting high and low frequency data terminals in the memory and utilizing spectrum analysis, the problem of observing synchronous switching noise in the memory is solved, the accuracy of signal sampling is improved, and it is suitable for testing DDR memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-03-07
- Publication Date
- 2026-06-05
Smart Images
Figure CN116779013B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor memory technology, and in particular to a method and apparatus for testing synchronous switching noise in memory. Background Technology
[0002] Currently, circuit system designs are becoming increasingly complex, and as circuit systems operate at ever-increasing speeds, their operating frequencies are also rising. This increase in operating frequency inevitably affects the stability of system operation, and synchronous-switching noise (SSN) interference is one of the more prominent problems.
[0003] For Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), often simply referred to as DDR, this type of memory has multiple parallel I / O buses, making it particularly susceptible to the effects of synchronous switching noise. DDR4 can achieve data transfer rates of up to 3200 Mbps, and DDR5 can reach 6400 Mbps. Due to the steeper rising and falling edges of the signal and the shorter signal period, the synchronous switching noise (SSN) interference increases rapidly. If many chip pins simultaneously switch output signals, this can cause the synchronous switching noise to superimpose, leading to inaccurate signal sampling due to fluctuations in the chip's sampling reference level.
[0004] In related technologies, it is not yet possible to effectively observe the noise of synchronous switching. Summary of the Invention
[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0006] This disclosure provides a method and apparatus for testing memory synchronous switching noise.
[0007] According to a first aspect of the present disclosure, a method for testing memory synchronization switching noise is provided, the method comprising:
[0008] One data input / output terminal of the memory is designated as the first data terminal, and the remaining data input / output terminals are designated as the second data terminals. The transmission frequency of the first data terminal is designated as the first frequency, and the transmission frequency of the second data terminals is designated as the second frequency; wherein, the first frequency is higher than the second frequency.
[0009] Write first preset data to the first data terminal and write second preset data to the second data terminal. The first preset data corresponds to the first frequency and the second preset data corresponds to the second frequency.
[0010] Read the first preset data written from the first data terminal;
[0011] Based on the spectral information corresponding to the data read from the first data terminal, it is determined whether the memory has synchronous switching noise.
[0012] According to some embodiments of this disclosure, determining whether the memory has synchronous switching noise based on the spectrum information corresponding to the data read from the first data terminal includes:
[0013] Determine whether the spectrum information contains spectrum information of the second frequency;
[0014] If present, it is determined that the memory contains synchronous switching noise.
[0015] According to some embodiments of this disclosure, the second frequency is an N-division of the first frequency, where N is a positive integer greater than or equal to 2.
[0016] According to some embodiments of this disclosure, the test method further includes:
[0017] Set the mapping relationship between the first preset data and the first frequency, and between the second preset data and the second frequency.
[0018] According to some embodiments of this disclosure, writing the first preset data to the first data terminal includes:
[0019] The first preset data is written to a preset location in the memory through the first data terminal.
[0020] According to some embodiments of this disclosure, reading the first preset data written from the first data terminal includes:
[0021] The first preset data is read and written from a preset location in the memory through the first data terminal.
[0022] According to some embodiments of this disclosure, the test method further includes:
[0023] The data transceiver platform of the memory test device writes the first preset data to the first data terminal and the second preset data to the second data terminal;
[0024] The first preset data written by the data transceiver platform of the test device of the memory is read from the first data terminal.
[0025] According to some embodiments of this disclosure, both the first data terminal and the second data terminal are bidirectional data transmission ports.
[0026] According to some embodiments of this disclosure, the test method further includes:
[0027] The second frequency is adjusted according to preset rules.
[0028] According to some embodiments of this disclosure, the spectrum information corresponding to the data read from the first data terminal is obtained based on the spectrum function of an oscilloscope.
[0029] A second aspect of this disclosure provides a testing apparatus for memory synchronization switching noise, the testing apparatus comprising:
[0030] The processor is configured to determine one data terminal of the memory as a first data terminal and the remaining data terminals as second data terminals, and to determine the transmission frequency of the first data terminal as a first frequency and the transmission frequency of the second data terminals as a second frequency; wherein the first frequency is higher than the second frequency.
[0031] The controller is configured to write first preset data to the first data terminal, write second preset data to the second data terminal, wherein the first preset data corresponds to the first frequency and the second preset data corresponds to the second frequency; and read the written first preset data from the first data terminal.
[0032] An oscilloscope is configured to determine whether synchronous switching noise exists in the memory based on the spectral information corresponding to the data read from the first data terminal.
[0033] According to some embodiments of this disclosure, the oscilloscope is configured as follows:
[0034] Determine whether the spectrum information contains spectrum information of the second frequency;
[0035] If present, it is determined that the memory contains synchronous switching noise.
[0036] According to some embodiments of this disclosure, the second frequency is an N-division of the first frequency, where N is a positive integer greater than or equal to 2.
[0037] According to some embodiments of this disclosure, the processor is configured to set a mapping relationship between the first preset data and the first frequency, and between the second preset data and the second frequency.
[0038] According to some embodiments of this disclosure, the controller is configured to write the first preset data to a preset location in the memory via the first data terminal.
[0039] According to some embodiments of this disclosure, the controller is configured to read the first preset data written from a preset location in the memory via the first data terminal.
[0040] According to some embodiments of this disclosure, the controller is configured to write the first preset data to the first data terminal and the second preset data to the second data terminal via a data transceiver platform; and to read the written first preset data from the first data terminal via the data transceiver platform.
[0041] According to some embodiments of this disclosure, the processor is further configured to adjust the second frequency according to preset rules.
[0042] The memory synchronous switching noise testing method and apparatus provided in this disclosure define one data input / output terminal of the memory as the first data terminal and the remaining data input / output terminals as the second data terminals, and determine that the transmission frequency of the first data terminal is higher than that of the second data terminals. By distinguishing the transmission frequencies of the first and second data terminals, and based on the spectral information during data read / write, it is easy to determine whether synchronous switching noise exists in the memory, and the location of the synchronous switching noise can be accurately pinpointed. Furthermore, by adjusting the second frequency to cover the changes in transmission frequency from high to low, not only can the integrity of the spectral information be observed, but also the synchronous switching noise at different transmission frequencies can be observed, locating the position of the maximum synchronous switching noise, thereby providing an adaptive and effective solution to reduce the synchronous switching noise. The memory synchronous switching noise testing method provided in this disclosure is applicable to DDR systems to test the synchronous switching noise of DDR memory. In addition, the testing method provided in this disclosure is also well-suited for simulation and verification simulation.
[0043] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.
[0045] Figure 1 This is a schematic diagram of the structure of a memory testing apparatus according to an exemplary embodiment;
[0046] Figure 2This is a flowchart illustrating a method for testing memory synchronous switching noise according to an exemplary embodiment;
[0047] Figure 3 This is a timing diagram of a bidirectional data transfer port for a memory according to an exemplary embodiment;
[0048] Figure 4 This is a timing diagram of a bidirectional data transfer port for a memory according to another exemplary embodiment;
[0049] Figure 5 This is a schematic diagram illustrating the measured spectrum information according to an exemplary embodiment;
[0050] Figure 6 This is a flowchart illustrating one implementation of step S240 according to an exemplary embodiment. Detailed Implementation
[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0052] During circuit operation, when a large number of output pins switch from high to low or from low to high at the same time, noise is introduced onto adjacent pins. This is known as synchronous switching noise (SSN). When the interfering signal and the interfered signal switch from low to high simultaneously, a negative voltage noise will be observed on the interfered signal; when the interfering signal switches from high to low simultaneously, a positive voltage noise will be observed on the interfered signal.
[0053] For memory systems like DDR SDRAM, which have multiple parallel I / O buses, the impact of Synchronous Switching Noise (SSN) is particularly pronounced. Due to their high data transfer rates (DDR4 up to 3200 Mbps, DDR5 up to 6400 Mbps), the steeper rise and fall edges and shorter signal period cause a rapid increase in SSN interference. If many chip pins simultaneously switch output signals, this can lead to superposition of SSN noise, causing the chip's sampling reference level to fluctuate to the point of inaccurate signal sampling.
[0054] Studying SSN in the time domain typically involves capturing noise waveforms and comparing noise amplitude and timing delay as performance benchmarks between different devices and systems. However, measuring and observing SSN in actual testing is not easy.
[0055] This disclosure provides a method for testing synchronous switching noise in a memory, applied to a memory testing apparatus, to test whether synchronous switching noise exists in the memory. For example, it can be used to test whether synchronous switching noise exists in a DDR memory.
[0056] Figure 1 This is a schematic diagram of a memory testing apparatus according to an exemplary embodiment, with reference to... Figure 1 As shown, the test apparatus 100 includes a Central Processing Unit (CPU) 111, a controller 112, and an oscilloscope 120. The processor 111 is connected to the controller 112, and the controller 112 is connected to the DDR memory 130 under test via a DDR interface 113. The DDR memory 130 under test is connected to the oscilloscope 120. The signal transmission channels between the DDR interface 113 and the DDR memory 130 include a clock channel CLK, a command channel CMD, an address channel ADDR, and a data channel DATA. The data channel DATA is a bidirectional transmission channel connected to the data input / output terminals of the DDR memory 130. The clock channel CLK, command channel CMD, and address channel ADDR are all unidirectional transmission channels from the DDR interface 113 to the DDR memory 130.
[0057] In this embodiment, the processor 111, controller 112, and DDR interface 113 constitute a system-on-chip (SOC) 110 to implement data writing and reading operations on the DDR memory 130.
[0058] Using the test apparatus 100 for this memory, the DDR memory 130 under test is simultaneously connected to both the SOC 110 and the oscilloscope 120. The SOC 110 writes and reads data from the DDR memory 130, and the oscilloscope 120 displays the spectral information during the data writing and reading process. Based on this spectral information, the synchronous switching noise of the DDR memory 130 can be determined. Of course, in other embodiments of this disclosure, in addition to using a SOC system, synchronous switching noise can also be tested using a field-programmable gate array (FPGA). The SOC or FPGA performs the test by continuously sending test data to the memory under test.
[0059] Figure 2This is a flowchart illustrating a memory testing method according to an exemplary embodiment, with reference to... Figure 2 As shown, the testing method includes the following steps:
[0060] Step S210: Determine one data input / output terminal of the memory as the first data terminal, and the remaining data input / output terminals as the second data terminals, and determine the transmission frequency of the first data terminal as the first frequency and the transmission frequency of the second data terminal as the second frequency; wherein, the first frequency is higher than the second frequency.
[0061] Step S220: Write first preset data to the first data terminal and write second preset data to the second data terminal. The first preset data corresponds to the first frequency and the second preset data corresponds to the second frequency.
[0062] Step S230: Read the first preset data to be written from the first data terminal;
[0063] Step S240: Determine whether there is synchronous switching noise in the memory based on the spectrum information corresponding to the data read from the first data terminal.
[0064] The memory testing method provided in this disclosure identifies one data input / output terminal of the memory as a first data terminal and the remaining data input / output terminals as second data terminals, and determines that the transmission frequency of the first data terminal is higher than that of the second data terminals. Data is then written to both the first and second data terminals, and the written data is read from the first data terminal. Based on the spectral information during the data reading process, the presence of synchronous switching noise in the memory can be determined. In other words, by differentiating the transmission frequencies of the data input / output terminals, targeted testing of the data input / output terminals is performed. This allows for the verification of multiple data input / output terminals of the memory, verifying the synchronous switching noise phenomenon between any different data input / output terminals, accurately testing for the presence of synchronous switching noise in the memory, and precisely locating the location of the synchronous switching noise, thereby ensuring product yield.
[0065] The testing method provided in this disclosure can verify whether synchronous switching noise exists in the memory, thereby ensuring accurate data read and write operations. For example, this testing method can... Figure 1 The test setup shown is used to test the synchronous switching noise of the DDR memory 130.
[0066] DRAM, as a parallel bus memory system with multiple data input / output terminals, is prone to synchronous switching noise (SSN) problems. In this embodiment, in step S210, one of the multiple data input / output terminals is designated as the first data terminal, and the remaining data input / output terminals are designated as the second data terminals. It is determined that the transmission frequency of the first data terminal is higher than the data transmission frequency of the second data terminals. Therefore, by observing the spectrum of the higher-frequency first data terminal, it can be determined whether it contains spectral components of the lower-frequency second data terminal, thereby verifying whether synchronous switching noise (SSN) exists in the DRAM.
[0067] In some embodiments, both the first data port and the second data port are bidirectional data transmission ports. For example, as shown... Figure 1 The DATA transmission channel shown corresponds to the bidirectional data transmission port on the DDR memory 130.
[0068] For example, the DRAM includes n+1 bidirectional data transmission ports: DQ0, DQ1, ..., DQn, where n is an integer greater than or equal to 1. The DQx terminal is designated as the first data terminal, where x is an integer greater than or equal to 0 and less than or equal to n, and the remaining DQ terminals are designated as the second data terminals. The data transmission frequency of the DQx terminal is designated as the first frequency, and the data transmission frequency of the remaining DQ terminals is maintained at the same frequency, designated as the second frequency, wherein the first frequency is higher than the second frequency.
[0069] Figure 3 and Figure 4 Timing diagrams of a DRAM bidirectional data transmission port in an exemplary embodiment are shown, such as... Figure 3 and Figure 4 As shown, the DQx terminal serves as the first data terminal, and the remaining DQ terminals serve as the second data terminals. The timing period of the first data terminal is shorter than the timing period of the second data terminals, meaning the first frequency is higher than the second frequency. For example... Figure 3 The remaining DQ terminals shown are half the frequency of the DQx terminals, i.e., divided by 2. Figure 4 The remaining DQ terminals shown are 16 divisions of the DQx terminals.
[0070] In the test method provided in this embodiment, the first frequency is higher than the second frequency, which ensures that the first data terminal and the second data terminal generate different phases during data reading and writing, ensuring that the first data terminal and the second data terminal will not synchronously flip, thereby allowing accurate observation of synchronous switching noise. Simultaneously, it also ensures that between the target signal A of the interfered first data terminal and the noise signal B generated by the second data terminal relative to the first data terminal, the target signal A always has the maximum signal strength, thus allowing observation of the strength of the synchronous switching noise. (Refer to...) Figure 5The spectrum information diagram shown clearly shows the presence of synchronous switching noise signal B and its impact on the target signal A in the spectrum information of the test results.
[0071] In some exemplary embodiments, the spectral information in this testing method can be obtained based on the spectral capabilities of an oscilloscope. For example... Figure 1 As shown, the spectrum information corresponding to the data read from the first data terminal is obtained based on the spectrum function of the oscilloscope 120, and the spectrum information is analyzed to determine whether there is synchronous switching noise in the memory.
[0072] exist Figure 2 In step S220, first preset data is written to the first data terminal at a first frequency; and second preset data is written to the second data terminal at a second frequency.
[0073] Since DRAM, as a semiconductor memory, cannot send data itself, embodiments of this disclosure can use a System on Chip (SoC) to send first and second preset data to the DRAM, for example... Figure 1 In the test apparatus 100 shown, data is sent to the DDR memory 130 via the SOC 110; alternatively, a data transceiver platform such as an FPGA (Field Programmable Gate Array) can be used to send first preset data and second preset data to the DRAM. According to test requirements, the first preset data and second preset data are set in the SOC or FPGA, and a first frequency for sending the first preset data to the first data terminal DQx and a second frequency for sending the second preset data to the second data terminal are also set.
[0074] After writing data in step S220, step S230 is executed to read the first preset data written from the first data terminal. During the process of reading the written first preset data, the spectrum information of the reading process is acquired and recorded.
[0075] For example, while reading the first preset data written from the first data terminal, the second preset data written from the second data terminal can also be read, and the spectrum information during the reading process can be obtained and recorded as the basis for the judgment in step S240.
[0076] In step S240, by determining whether the spectral information in the reading process of step S230 contains other spectral information, such as the spectral information of the second frequency, it is determined whether other signals affect the reading process of the first data terminal, thereby determining whether there is synchronous switching noise in the memory.
[0077] For example, it can be utilized Figure 1The spectral analysis function of the oscilloscope 120 shown allows for intuitive and rapid observation of whether the spectrum information at the first data terminal contains a spectral component of the second frequency.
[0078] Figure 6 A flowchart of one implementation of step S240 is shown, with reference to Figure 6 As shown, in some embodiments, determining whether the memory has synchronous switching noise based on the spectrum information corresponding to the data read from the first data terminal includes:
[0079] Step S241: Determine whether the spectrum information contains spectrum information of the second frequency;
[0080] Step S242: If present, determine that the memory has synchronous switching noise.
[0081] If the spectrum information corresponding to the data read from the first data terminal contains the spectrum information of the second frequency, it indicates that the data was affected by the signal from the second data terminal during the process of reading the data from the first data terminal. Therefore, it can be determined that the memory has synchronous switching noise, for example, synchronous switching noise exists.
[0082] In this embodiment of the disclosure, a DQx terminal is set as a first data terminal in the DRAM system to output a higher frequency signal, and the remaining DQ terminals are set as second data terminals to output lower frequency signals. By observing the spectrum signal of the higher frequency first data terminal, it is determined whether it contains the spectrum component of the lower frequency second data terminal, thereby verifying whether there is switching noise in the memory.
[0083] In some embodiments, the second frequency is an N-division of the first frequency, where N is a positive integer greater than or equal to 2.
[0084] By using a frequency division method to distinguish between the first and second frequencies, it is easy to implement through reading and writing data, which is convenient to operate. Moreover, it can effectively distinguish between the first and second frequencies, which is beneficial for the analysis of spectrum information and facilitates the detection of synchronous switching noise in the memory.
[0085] For example, the DQx terminal is selected as the first data terminal, and its transmission frequency is determined to be A. The remaining DQ terminals are selected as the second data terminals, and their transmission frequencies are determined to be B. Frequency B is a division of frequency A by N, i.e., B = A / N. The frequency division operation can be implemented using consecutive data "1" and "0".
[0086] Return to reference Figure 4As shown, taking DDR4 as an example, the DRAM operating frequency is 3200Mbps. Writing consecutive data "1010..." to the first data terminal (DQx) results in a data transmission frequency of 3200Mbps. Writing 16 consecutive "1"s and 16 consecutive "0"s to the remaining DQ terminals (which act as the second data terminal) achieves a 16-fold frequency division, resulting in a second data transmission frequency of 200Mbps. Writing two consecutive "1"s and two consecutive "0"s to the remaining DQ terminals (which act as the second data terminal), i.e., "11001100...", achieves a 2-fold frequency division. The timing diagram can be found in [reference needed]. Figure 3 As shown, the second frequency is 1600Mbps.
[0087] In some embodiments, the testing method further includes:
[0088] Set the mapping relationship between the first preset data and the first frequency, and between the second preset data and the second frequency.
[0089] For example, the mapping relationship between the first preset data and the first frequency includes that the first frequency is used when reading or writing the first preset data to any data terminal; the mapping relationship between the second preset data and the second frequency includes that the second frequency is used when reading or writing the second preset data to any data terminal.
[0090] In this embodiment of the disclosure, by setting a mapping relationship between the first preset data and the first frequency, and a mapping relationship between the second preset data and the second frequency, the first frequency is directly used when writing or reading the first preset data, and the second frequency is directly used when writing or reading the second preset data, which facilitates the control and implementation of the testing process.
[0091] For example, as described above, the first frequency and the second frequency can be distinguished directly by the "1" and "0" in the first preset data and the second preset data, and at the same time, there is a mapping relationship between the first preset data and the first frequency, and a mapping relationship between the second preset data and the second frequency.
[0092] In some embodiments, writing first preset data to the first data terminal includes:
[0093] The first preset data is written to the preset location of the memory through the first data terminal.
[0094] Accordingly, in some embodiments, reading the first preset data written from the first data terminal includes:
[0095] First preset data is read from a preset location in the memory via the first data terminal.
[0096] In this embodiment of the disclosure, DRAM testing can be performed without pre-charging and activation operations. First preset data is continuously stored into the DRAM's row buffer via the first data terminal. When reading the first preset data via the first data terminal, it is read continuously directly from the row buffer. Correspondingly, second preset data can also be continuously stored into the DRAM's row buffer via the second data terminal, and the second preset data can be continuously read from the row buffer via the second data terminal.
[0097] Since DRAM itself does not have the ability to send data, the test method of this embodiment utilizes the data transceiver platform of the test device to realize the writing and reading operations of the first preset data and the second preset data into the DRAM.
[0098] In some embodiments, the testing method further includes:
[0099] The data transceiver platform of the memory test device writes first preset data to the first data terminal and second preset data to the second data terminal.
[0100] The first preset data is read and written from the first data terminal through the data transceiver platform of the test device of the memory.
[0101] The data transceiver platform of the memory testing device can be a SOC or an FPGA. Within this data transceiver platform, first preset data and second preset data can be customized according to testing requirements, and a first frequency of the first preset data and a second frequency of the second preset data can be preset.
[0102] In an exemplary embodiment, the operating frequency of the DRAM is set to 3200 Mbps. First preset data and second preset data are set in the SOC / FPGA, and the first frequency is determined to be 1.6 GHz and the second frequency to be 1.6 GHz / 2 (or 3, 4, 5...29, 30, etc.). Then, one DQ terminal of the DRAM is designated as the first data terminal, and the remaining DQ terminals are designated as the second data terminals. The first preset data and second preset data are continuously sent to the DRAM via the SOC / FPGA. The DRAM writes the first preset data through the first data terminal and the second preset data through the second preset data terminal. Using the spectrum analysis function of an oscilloscope, it is observed whether the spectrum of the first data terminal contains a second frequency component. If so, it is determined that the DRAM has synchronous switching noise (SSN).
[0103] In some exemplary embodiments, the method for testing memory synchronous switching noise provided in this disclosure further includes:
[0104] The second frequency is adjusted according to preset rules.
[0105] That is, when the DQx end is used as the first data end and the remaining DQ ends are used as the second data ends, the following is executed: Figure 2 After steps S210 to S240, the first frequency of the first data terminal remains unchanged, and the second frequency of the second data terminal is adjusted according to a preset rule. Then, the above steps are executed again to obtain the spectral information of the DQx terminal at different second frequencies. In practical applications, for the same first data terminal, the second frequency can be adjusted multiple times and tested sequentially to obtain a series of spectral information for the DQx terminal. By comparison, the second frequency corresponding to the synchronous switching noise that has the greatest impact on the DQx terminal can be determined.
[0106] In this embodiment, the preset rule for adjusting the second frequency can be a decreasing or increasing method. The adjustment range of the increasing or decreasing can be a fixed value or a variable value. For example, the second frequency can be adjusted by increasing or decreasing a preset difference, or the second frequency can be adjusted with the goal of satisfying a preset condition. For instance, it is necessary to ensure that the adjusted second frequency is 1 / m of the first frequency, where m is an integer greater than 1, and that the value of m increases or decreases with the number of adjustments during the adjustment process.
[0107] For example, if the second frequency before adjustment is half of the first frequency, then during the adjustment process, the value of m increases with the number of adjustments. For instance, in the first adjustment, m can be 3, meaning the adjusted second frequency is 3 times the first frequency; in the second adjustment, m can be 4, meaning the adjusted second frequency is 4 times the first frequency; and so on.
[0108] If the second frequency before adjustment is 30 times the first frequency, then during the adjustment process, the value of m decreases as the number of adjustments increases. For example, in the first adjustment, m can be 29, meaning the adjusted second frequency is 29 times the first frequency; in the second adjustment, m can be 28, meaning the adjusted second frequency is 28 times the first frequency; and so on.
[0109] It should be noted that, regardless of the adjustment method used for the preset rules, the second frequency after each adjustment must be lower than the first frequency; and in the adjusted test, DQx, as the first data terminal, uses the first frequency to write and read the first preset data, while the other DQ terminals use the same adjusted second frequency to write and read the second preset data.
[0110] In some exemplary embodiments, the memory synchronous switching noise testing method provided in this disclosure allows for the following steps: after the DQx terminal has been tested as the first data terminal, the current DQx terminal can be switched to the second data terminal, and another DQ terminal, such as DQx+1, can be switched to the first data terminal. Then, the above testing process is executed. This process is repeated until all DQ terminals of the memory have been tested, allowing for accurate observation of the synchronous switching noise of each DQ terminal of the memory.
[0111] The test results obtained using the test method provided in this embodiment are basically consistent with the simulation results, as verified by the simulation method, demonstrating the reliability of this solution.
[0112] Return to reference Figure 1 As shown in this embodiment, the processor 111 is configured to determine one data terminal of the memory as a first data terminal and the remaining data terminals as second data terminals, and to determine the transmission frequency of the first data terminal as a first frequency and the transmission frequency of the second data terminals as a second frequency; wherein the first frequency is higher than the second frequency.
[0113] The controller 112 is configured to write first preset data to a first data terminal, write second preset data to a second data terminal, wherein the first preset data corresponds to a first frequency and the second preset data corresponds to a second frequency; and read the written first preset data from the first data terminal.
[0114] The oscilloscope 120 is configured to determine whether there is synchronous switching noise in the memory based on the spectral information corresponding to the data read from the first data terminal.
[0115] In this embodiment, the processor 111 determines the first data terminal and the second data terminal, and distinguishes that the transmission frequency of the first data terminal is higher than that of the second data terminal. The controller 112 implements the data writing and data reading operations of the first data terminal and the second data terminal. The oscilloscope 120, based on the spectrum information of the controller 112 during the data writing and reading process, and taking advantage of the fact that the first frequency is higher than the second frequency, can easily distinguish the spectrum information of the first data terminal and accurately determine whether there is synchronous switching noise in the memory.
[0116] In some embodiments, the second frequency is an N-division of the first frequency, where N is a positive integer greater than or equal to 2.
[0117] This embodiment of the present disclosure can use the processor to use different data input / output terminals as the first data terminal, and verify each data input / output terminal of the DRAM in sequence to accurately test whether there is a preset sequential state in the DRAM and the location of the synchronous switching noise, thereby improving the product yield.
[0118] Both the first data port and the second data port are bidirectional data transmission ports.
[0119] DRAM, as a parallel bus memory system with multiple data input / output terminals, is prone to synchronous switching noise (SSN) problems. In this embodiment, the processor 111 designates one of the multiple data input / output terminals as a first data terminal and the remaining data input / output terminals as second data terminals. It also determines that the transmission frequency of the first data terminal is higher than the data transmission frequency of the second data terminals. Therefore, by observing the spectrum of the higher-frequency first data terminal, it can be determined whether it contains spectral components of the lower-frequency second data terminal, thereby verifying the presence of SSN in the DRAM.
[0120] In some embodiments, the oscilloscope 120 is configured to:
[0121] Determine whether the spectrum information contains spectrum information of the second frequency;
[0122] If present, it indicates that synchronous switching noise exists in the memory.
[0123] In this embodiment of the disclosure, a DQx terminal is set as a first data terminal in the DRAM system to output a higher frequency signal, and the remaining DQ terminals are set as second data terminals to output lower frequency signals. By observing the spectrum signal of the higher frequency first data terminal, it is determined whether it contains the spectrum component of the lower frequency second data terminal, thereby verifying whether there is switching noise in the memory.
[0124] For example, by using the spectrum analysis function of an oscilloscope, the spectrum information of the first data terminal and the second data terminal can be directly analyzed to determine whether the spectrum information of the first data terminal contains a spectrum component of the second frequency, thereby determining whether there is synchronous switching noise in the DRAM.
[0125] In some embodiments, the processor 111 is configured to set a mapping relationship between a first preset data and a first frequency, and between a second preset data and a second frequency.
[0126] In this embodiment of the present disclosure, the processor 111 sets a mapping relationship between the first preset data and the first frequency, and a mapping relationship between the second preset data and the second frequency, so that the controller 112 can directly write or read the first preset data through the first frequency and write or read the second preset data through the second frequency, which facilitates the control and implementation of the test process.
[0127] In some embodiments, the controller 112 is configured to write first preset data to a preset location in the memory via a first data terminal.
[0128] In this embodiment of the disclosure, DRAM testing can be performed without pre-charging and activation operations. The controller 112 continuously stores the first preset data into the row buffer of the DRAM through the first data terminal. Correspondingly, the controller 112 can also continuously store the second preset data into the row buffer of the DRAM through the second data terminal.
[0129] In some embodiments, the controller 112 is further configured to read first preset data written from a preset location in the memory via a first data terminal.
[0130] In this embodiment of the disclosure, DRAM testing can be performed without pre-charging and activation operations. When the controller 112 reads the first preset data through the first data terminal, it directly reads continuously from the row buffer. Correspondingly, the controller 112 can also continuously read the second preset data from the row buffer through the second data terminal.
[0131] Since DRAM itself does not have the ability to send data, the test apparatus 100 of this embodiment utilizes the data transceiver platform of the test apparatus to perform write and read operations on the first preset data and the second preset data in the DRAM.
[0132] In some embodiments, the controller 112 is configured to write or read first preset data to a first data terminal and write or read second preset data to a second data terminal via a data transceiver platform.
[0133] For example, the data transceiver platform of the memory testing apparatus can be a SOC110 or an FPGA. Within this data transceiver platform, first preset data and second preset data can be customized according to testing requirements, and a first frequency of the first preset data and a second frequency of the second preset data can be preset.
[0134] In some embodiments, the processor 111 is further configured to adjust the second frequency according to a preset rule.
[0135] The specific details of each module in the aforementioned memory testing apparatus 100 have been described in detail in the corresponding memory testing methods, and therefore will not be repeated here.
[0136] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.
[0137] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0138] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0139] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0140] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.
[0141] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0142] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.
Claims
1. A method for testing synchronous switching noise in a memory, characterized in that, The testing method includes: One data input / output terminal of the memory is designated as the first data terminal, and the remaining data input / output terminals are designated as the second data terminals. The transmission frequency of the first data terminal is designated as the first frequency, and the transmission frequency of the second data terminals is designated as the second frequency; wherein, the first frequency is higher than the second frequency. Write first preset data to the first data terminal and write second preset data to the second data terminal. The first preset data corresponds to the first frequency and the second preset data corresponds to the second frequency. Read the first preset data written from the first data terminal; Based on the spectral information corresponding to the data read from the first data terminal, it is determined whether the memory has synchronous switching noise.
2. The method for testing memory synchronous switching noise according to claim 1, characterized in that, The step of determining whether the memory has synchronous switching noise based on the spectrum information corresponding to the data read from the first data terminal includes: Determine whether the spectrum information contains spectrum information of the second frequency; If present, it is determined that the memory contains synchronous switching noise.
3. The method for testing memory synchronous switching noise according to claim 1 or 2, characterized in that, The second frequency is N times the first frequency, where N is a positive integer greater than or equal to 2.
4. The method for testing memory synchronous switching noise according to claim 3, characterized in that, The testing method also includes: Set the mapping relationship between the first preset data and the first frequency, and between the second preset data and the second frequency.
5. The method for testing memory synchronous switching noise according to claim 1 or 2, characterized in that, The step of writing the first preset data to the first data terminal includes: The first preset data is written to a preset location in the memory through the first data terminal.
6. The method for testing memory synchronous switching noise according to claim 1 or 2, characterized in that, The first preset data read and written from the first data terminal includes: The first preset data is read and written from a preset location in the memory through the first data terminal.
7. The method for testing memory synchronous switching noise according to claim 1, characterized in that, The testing method also includes: The first preset data is written to the first data terminal through the data transceiver platform, and the second preset data is written to the second data terminal. The first preset data is read and written from the first data terminal through the data transceiver platform.
8. The method for testing memory synchronous switching noise according to claim 1, characterized in that, Both the first data port and the second data port are bidirectional data transmission ports.
9. The method for testing memory synchronous switching noise according to claim 1 or 2, characterized in that, The testing method also includes: The second frequency is adjusted according to preset rules.
10. The method for testing memory synchronous switching noise according to claim 1, characterized in that, The spectrum information corresponding to the data read from the first data terminal is obtained based on the spectrum function of the oscilloscope.
11. A testing device for memory synchronous switching noise, characterized in that, The testing apparatus includes: The processor is configured to determine one data terminal of the memory as a first data terminal and the remaining data terminals as second data terminals, and to determine the transmission frequency of the first data terminal as a first frequency and the transmission frequency of the second data terminals as a second frequency; wherein the first frequency is higher than the second frequency. The controller is configured to write first preset data to the first data terminal, write second preset data to the second data terminal, wherein the first preset data corresponds to the first frequency and the second preset data corresponds to the second frequency; and read the written first preset data from the first data terminal. An oscilloscope is configured to determine whether synchronous switching noise exists in the memory based on the spectral information corresponding to the data read from the first data terminal.
12. The testing apparatus for memory synchronous switching noise according to claim 11, characterized in that, The oscilloscope is configured to: Determine whether the spectrum information contains spectrum information of the second frequency; If present, it is determined that the memory contains synchronous switching noise.
13. The testing apparatus for memory synchronous switching noise according to claim 11 or 12, characterized in that, The second frequency is N times the first frequency, where N is a positive integer greater than or equal to 2.
14. The testing apparatus for memory synchronous switching noise according to claim 13, characterized in that, The processor is configured to set a mapping relationship between the first preset data and the first frequency, and between the second preset data and the second frequency.
15. The testing apparatus for memory synchronous switching noise according to claim 11, characterized in that, The controller is configured to write the first preset data to the first data terminal and the second preset data to the second data terminal via a data transceiver platform; and to read the written first preset data from the first data terminal via the data transceiver platform.
16. The testing apparatus for memory synchronous switching noise according to claim 11, characterized in that, The processor is also configured to adjust the second frequency according to a preset rule.