Digital signal filters, chips, systems and electronic devices

Abstract

A digital signal filter, chip, system, and electronic device include: a filter chain module, a third edge trigger module, a fourth edge trigger module, and an output judgment module. The filter chain module performs preliminary filtering on the data signal. In response to the data signal, the third edge trigger module is reset or the fourth edge trigger module is set. Since a glitch signal crosses a valid clock edge, when a glitch signal is mixed into the data signal, the first trigger signal and the second trigger signal, which differ by one clock cycle, will necessarily have one high level and the other low level. This ensures that the signal at the output of the output judgment module remains unchanged, thus filtering out the glitch signal. By setting the third edge trigger module, the fourth edge trigger module, and the output judgment module, the digital signal filter can effectively filter out glitch signals that cross the valid clock edge while ensuring the real-time performance of the filtered signal.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more particularly to digital signal filters, chips, systems, and electronic devices. Background Technology

[0002] Signal processing mainly includes the processing of analog signals and the processing of digital signals. Digital signals, primarily represented by high and low voltage levels, exhibit strong noise immunity and interference resistance. However, due to the complexity of the everyday electromagnetic environment and signal fluctuations that may occur within the circuit itself, glitches can easily develop in digital signals, leading to inaccuracies or even errors in information transmission.

[0003] Especially for increasingly integrated chips, electronic products often rely on digital signal communication for judgment, control, or communication with other chips. However, the increasingly complex electromagnetic environment outside the chips frequently disrupts wired communication, causing glitches that lead to communication failures or signal errors. Therefore, digital signal filters are needed to filter digital signals to ensure normal communication, judgment, and control of the chips. For example, a digital signal filter filters the signals received by the chip's I / O ports, and then transmits the glitched signal to subsequent circuits.

[0004] In existing technologies, digital signal filters mainly perform filtering in two ways.

[0005] One approach is to use software filtering algorithms. This involves storing the digital signal data first, and then the software determines which filtering algorithm to use to process the data. However, due to differences in the algorithms used and the processor's performance, this method results in uncertain data signal delay times, poor real-time performance, and higher power consumption when processing high-speed signals.

[0006] Another approach is to use hardware filtering, typically a filter chain composed of multiple flip-flops, such as a filter chain consisting of multiple D flip-flops. Since D flip-flops only change data at the clock edge, they can mask some glitches. However, because D flip-flops transmit signals internally when the valid clock edge arrives, if a glitch is too close to the valid clock edge, it can easily be incorporated into the signal transmission within the D flip-flop, meaning the glitch is mistakenly sampled by the flip-flop. The likelihood of a glitch being mistakenly sampled is even greater when it crosses the valid clock edge. Therefore, a filter chain composed of edge-triggered flip-flops can directly filter out glitches that do not cross the valid clock edge; however, a filter chain cannot filter out glitches that cross the valid clock edge.

[0007] It is evident that existing digital signal filters either have poor real-time performance or insufficient filtering effect, failing to effectively filter out glitches that are close to the effective clock edge.

[0008] Therefore, how to ensure the real-time performance of the signal while enabling digital signal filters to filter out glitches that cross the effective clock edge has become an urgent technical problem to be solved. Summary of the Invention

[0009] Based on the above situation, the main objective of this invention is to provide a digital signal filter, chip, system, and electronic device to solve the technical problem of how to filter out glitches that cross the effective clock edge while ensuring the real-time performance of the signal.

[0010] Therefore, according to a first aspect, embodiments of the present invention disclose a digital signal filter, including: a filter chain module, a third edge triggering module, a fourth edge triggering module, and an output judgment module;

[0011] The data input terminal of the filter chain module receives data signals, the clock input terminal of the filter chain module receives clock signals, and the filter output terminal of the filter chain module outputs a second trigger signal; the first trigger terminal of the filter chain module outputs a first trigger signal; the inverting output terminal of the filter chain module outputs a first inverted trigger signal with a phase opposite to the first trigger signal; the second trigger signal is delayed by one clock cycle compared to the first trigger signal.

[0012] The reset terminal of the third edge trigger module and the set input terminal of the fourth edge trigger module receive data signals respectively;

[0013] When the data signal is low, the third edge trigger module is reset, and the third trigger signal output by the third edge trigger module is a low-level signal; when the data signal is high, in response to the rising edge of the first trigger signal, the third trigger signal is a high-level signal.

[0014] When the data signal is high, the fourth edge trigger module is set, and the fourth trigger signal output by the fourth edge trigger module is a high-level signal; when the data signal is low, in response to the rising edge of the first inverted trigger signal, the fourth trigger signal is a low-level signal.

[0015] The output judgment module receives a first trigger signal, a second trigger signal, a third trigger signal, and a fourth trigger signal: when the first trigger signal, the second trigger signal, and the third trigger signal are all high, the output judgment module outputs a high-level signal; when the first trigger signal, the second trigger signal, and the fourth trigger signal are all low, the output judgment module outputs a low-level signal; otherwise, the output signal of the output judgment module is the same as the output signal corresponding to the previous clock cycle; the output terminal of the output judgment module is the output terminal of the digital signal filter.

[0016] Preferably, the filter chain module includes a first edge-triggered submodule and a second edge-triggered submodule;

[0017] The data input terminal of the first edge-triggered submodule receives a data signal, the clock input terminal of the first edge-triggered submodule receives a clock signal, the data output terminal of the first edge-triggered submodule is the first trigger terminal of the filter chain module, and the inverted data output terminal of the first edge-triggered submodule is the inverted output terminal of the filter chain module.

[0018] The data input terminal of the second edge-triggered submodule receives the first trigger signal, the clock input terminal of the second edge-triggered submodule receives the clock signal, and the data output terminal of the second edge-triggered submodule outputs the second trigger signal.

[0019] Preferably, the fourth edge triggering module includes an inverting submodule and a fourth triggering submodule, wherein the set valid signal of the fourth triggering submodule and the reset valid signal of the third edge triggering module are both high-level signals or low-level signals.

[0020] The input terminal of the inverting submodule is the set input terminal of the fourth edge-triggered module, so as to output a data inverted signal with the opposite phase to the data signal;

[0021] The set terminal of the fourth trigger submodule receives the inverted data signal, and the output terminal of the fourth trigger submodule is the data output terminal of the fourth edge trigger module; when the inverted data signal is a set valid signal, the fourth trigger signal is a high-level signal.

[0022] Preferably, the fourth edge triggering module is a fourth triggering submodule, and the set terminal of the fourth triggering submodule is the set input terminal of the fourth edge triggering module;

[0023] In the fourth trigger submodule's set valid signal and the third edge trigger module's reset valid signal, one is a high-level signal and the other is a low-level signal, so that the third edge trigger module being reset and the fourth edge trigger module being set cannot occur simultaneously.

[0024] Preferably, the output judgment module includes a three-AND submodule, a three-NOR submodule, and a latch submodule;

[0025] The input terminal of the three AND gate submodule receives the first trigger signal, the second trigger signal, and the third trigger signal, and the output terminal of the three AND gate submodule outputs an AND gate signal; when the first trigger signal, the second trigger signal, and the third trigger signal are all high-level signals, the AND gate signal is a high-level signal.

[0026] The input terminal of the three NOR submodule receives the first trigger signal, the second trigger signal, and the fourth trigger signal, and the output terminal of the three NOR submodule outputs the NOR gate signal; when the first trigger signal, the second trigger signal, and the fourth trigger signal are all low-level signals, the NOR gate signal is a high-level signal;

[0027] The set terminal of the latch submodule receives an AND gate signal, the reset terminal of the latch submodule receives a NOR gate signal, and the output terminal of the latch submodule outputs a filtered signal.

[0028] When the AND gate signal is high, the filtered signal is high; when the NOR gate signal is high, the filtered signal is low.

[0029] Preferably, the digital signal filter further includes a frequency divider module, which outputs a clock signal to the filter chain module and is used to adjust the length of the clock period of the clock signal.

[0030] According to a second aspect, embodiments of the present invention disclose a chip for signal processing, including a digital signal filter as disclosed in the first aspect.

[0031] Preferably, the chip further includes an I / O pin module and a logic circuit module;

[0032] The IO pin module receives external digital signals and transmits them to the digital signal filter, so that the digital signal filter filters the external digital signals to obtain a filtered signal, and the logic circuit module receives the filtered signal;

[0033] And / or, the logic circuit module transmits internal digital signals to the digital signal filter so that the digital signal filter filters the internal digital signals to obtain a filtered signal, and the IO pin module receives the filtered signal and transmits it to the external circuit.

[0034] According to a third aspect, embodiments of the present invention disclose a filtering system comprising at least two chips, wherein at least one chip is a chip as disclosed in the second aspect.

[0035] According to a third aspect, embodiments of the present invention disclose an electronic device with signal processing function, the electronic device including a digital signal filter as disclosed in the first aspect.

[0036] [Beneficial Effects]

[0037] In the digital signal filter disclosed in this embodiment, the filter chain module performs preliminary filtering on the data signal to obtain and output a second trigger signal. When the data signal is low, the third edge trigger module is reset, and the third trigger signal is low. At this time, the fourth edge trigger module is not set, so the fourth trigger signal remains unchanged before the first inverted trigger signal rises; after the first inverted trigger signal rises, the fourth trigger signal is low. When the data signal is high, the fourth edge trigger module is set, and the fourth trigger signal is high. At this time, the third edge trigger module is not reset, so the third trigger signal remains unchanged before the first trigger signal rises; after the first trigger signal rises, the third trigger signal is high. When the first, second, and third trigger signals are all high, the output judgment module outputs a high-level signal; when the first, second, and fourth trigger signals are all low, the output judgment module outputs a low-level signal. Otherwise, when the first, second, third, and fourth trigger signals are any other combination, the output signal of the output judgment module remains unchanged. Furthermore, since the glitch signal crosses a valid clock edge, when a glitch signal is mixed into the data signal, the first and second trigger signals, which differ by one clock cycle, will necessarily have one high and the other low, thus keeping the output signal of the output judgment module unchanged. In other words, the glitch signal in the data signal will not cause a change in the output signal of the filter, effectively filtering out the glitch signal. Therefore, even if the glitch signal approaches or even crosses the effective clock edge, it will not cause a change in the output signal of the filter, thus ensuring that the glitch signal is completely filtered out. Furthermore, the digital signal filter disclosed in this embodiment abandons the filtering method of software filtering algorithm, thereby effectively improving the filtering precision and filtering effect of digital signal filter while ensuring the real-time performance of the filtered signal.

[0038] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0039] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a digital signal filter circuit disclosed in this embodiment.

[0041] Figure 2 This is a signal timing diagram for a digital signal filter that receives a high-level data signal as input to this embodiment.

[0042] Figure 3 This is a signal timing diagram for a digital signal filter that receives a low-level data signal as input to this embodiment. Detailed Implementation

[0043] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0046] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] To improve the filtering effect of digital signal filters by filtering out glitches that are close to the effective clock edge while ensuring real-time signal performance, this embodiment discloses a digital signal filter. Please refer to... Figure 1 , Figure 1This is a schematic diagram of a digital signal filter circuit disclosed in this embodiment. The digital signal filter disclosed in this embodiment receives data signals and clock signals to filter out glitches in the data signals. The applicant's research has found that in glitches that need to be addressed by filters, the duration of the glitches is often less than two clock cycles. When the duration of the glitches is greater than two clock cycles, it is usually caused by hardware circuit layout or other reasons, and cannot be solved by filters alone. This patent solves the problem of filtering glitches that only span one effective clock edge.

[0048] Please see Figure 1 The digital signal filter includes a filter chain module 100, a third edge triggering module 300, a fourth edge triggering module 400, and an output judgment module 500, wherein:

[0049] The data input terminal of the filter chain module 100 is the data input terminal of the digital signal filter, used to receive the data signal cin. The clock input terminal of the filter chain module 100 is the clock input terminal of the digital signal filter, used to receive the clock signal smp_clk. The filter output terminal A of the filter chain module 100 is used to output the second trigger signal. If the data signal cin contains glitches that are close to the edge of the effective clock, the second trigger signal may still contain glitches, and the filtering effect on the data signal cin is not refined enough. In this embodiment, the filter chain module 100 also includes a first trigger terminal B and an inverting output terminal C. The first trigger terminal B is used to output a first trigger signal; when the first trigger terminal B outputs the first trigger signal, the inverting output terminal C synchronously outputs a first inverted trigger signal with a phase opposite to the first trigger signal. The second trigger signal is delayed by at least one clock cycle from the first trigger signal. The reset terminal of the filter chain module 100 receives a reset signal rst. When the reset signal rst is low, the filter chain module 100 is reset, and both the first trigger signal and the second trigger signal are low. When the reset signal rst is low, the reset of the filter chain module 100 is invalid.

[0050] It should be noted that when a glitch signal does not cross any valid clock edge, since the filter chain module 100 is triggered by a valid clock edge, the glitch signal that does not cross a valid clock edge will not be synchronized by the filter chain module 100. That is, when a glitch signal does not cross a valid clock edge, the filter chain module 100 can directly filter out the glitch signal. However, when a glitch signal crosses a valid clock edge, the glitch signal will be synchronized by the filter chain module 100 to the subsequent circuit.

[0051] The reset terminal of the third edge trigger module 300 and the set input terminal D of the fourth edge trigger module 400 respectively receive the data signal cin.

[0052] When the data signal cin is low, the third edge trigger module 300 is reset, and the third trigger signal output by the third edge trigger module 300 is a low-level signal; when the data signal cin is high, in response to the rising edge of the first trigger signal, the third trigger signal is a high-level signal.

[0053] When the data signal cin is high, the fourth edge trigger module 400 is set, and the fourth trigger signal output by the fourth edge trigger module 400 is a high-level signal; when the data signal cin is low, in response to the rising edge of the first inverted trigger signal, the fourth trigger signal is a low-level signal.

[0054] The data input terminal of the third edge trigger module 300 is used to receive a high-level signal, the clock input terminal of the third edge trigger module 300 is used to receive a first trigger signal, the reset terminal of the third edge trigger module 300 is used to receive a data signal cin, and the data output terminal of the third edge trigger module 300 is used to output a third trigger signal.

[0055] It should be noted that the data input terminal of the third edge trigger module 300 can be connected to the power supply terminal VDD to ensure that the clock receives a high-level signal, or it can be connected to other high-level signal input terminals, as long as the data input terminal of the third edge trigger module 300 always receives a high-level signal.

[0056] In this embodiment, when the data signal cin is a valid reset signal for the third edge trigger module 300, the third edge trigger module 300 is reset and outputs a low level. Optionally, the valid reset signal for the third edge trigger module 300 can be either a low-level signal or a high-level signal. In a specific embodiment, the valid reset signal for the third edge trigger module 300 is a low-level signal. That is, whenever the data signal cin is low, the third edge trigger module 300 is reset, thereby making the third trigger signal low. When the data signal cin is high, the reset of the third edge trigger module 300 is invalid, and the third trigger signal is determined by the signals received from the data input terminal and the clock input terminal.

[0057] In this embodiment, the third edge triggering module 300 uses the first trigger signal as its clock signal smp_clk. That is, if the third edge triggering module 300 is not reset, when the first trigger signal is the effective clock edge of the third edge triggering module 300, the third trigger signal is a high-level signal. The effective clock edge of the third edge triggering module 300 can be either a rising edge or a falling edge. In a specific embodiment, the effective clock edge of the third edge triggering module 300 is a rising edge.

[0058] The data input terminal of the fourth edge trigger module 400 is used to receive a low-level signal, the clock input terminal of the fourth edge trigger module 400 is used to receive a first inverted trigger signal, the set input terminal D of the fourth edge trigger module 400 is used to receive a data signal cin, and the data output terminal of the fourth edge trigger module 400 is used to output a fourth trigger signal.

[0059] In this embodiment, when the data signal cin is the set valid signal of the fourth edge trigger module 400, the fourth edge trigger module 400 is set, thereby making the output fourth trigger signal high. Optionally, the set valid signal of the fourth edge trigger module 400 can be either a low-level signal or a high-level signal. In a specific embodiment, the set valid signal of the fourth edge trigger module 400 is a high-level signal, that is, as long as the data signal cin is high, the fourth edge trigger module 400 is set, thereby making the fourth trigger signal high; when the data signal cin is low, the setting of the fourth edge trigger module 400 is invalid, and the fourth trigger signal is determined by the signals received by the data input terminal and the clock input terminal.

[0060] In this embodiment, the fourth edge-triggered module 400 uses the first inverted trigger signal as the clock signal smp_clk. That is, if the fourth edge-triggered module 400 is not set, when the first inverted trigger signal is the effective clock edge of the fourth edge-triggered module 400, the fourth trigger signal is a low-level signal. The effective clock edge of the fourth edge-triggered module 400 can be either a rising edge or a falling edge. In this specific embodiment, the effective clock edge of the fourth edge-triggered module 400 is a rising edge.

[0061] Therefore, in response to the data signal cin, the third edge trigger module 300 is reset to make the third trigger signal low, or the fourth edge trigger module 400 is set to make the fourth trigger signal high. Since the data signal cin switches between high and low levels, the reset of the third edge trigger module 300 and the setting of the fourth edge trigger module 400 also switch with the level of the data signal cin. Specifically, when the data signal cin is low, the third edge trigger module 300 is reset to make the third trigger signal low, and the setting of the fourth edge trigger module 400 is invalid. Therefore, when the first inverted trigger signal is a rising edge, the fourth trigger signal is low. When the data signal cin is high, the fourth edge trigger module 400 is set to make the fourth trigger signal high, and the reset of the third edge trigger module 300 is invalid. Therefore, when the first trigger signal is a rising edge, the third trigger signal is high.

[0062] In a specific embodiment, the third edge triggering module 300 is a D flip-flop dff03, and the four edge triggering module 400 is a D flip-flop dff04.

[0063] In this embodiment, the output judgment module 500 receives a first trigger signal, a second trigger signal, a third trigger signal, and a fourth trigger signal. When all three trigger signals are high, the output terminal of the output judgment module 500 outputs a high-level signal. When all three trigger signals are low, the output terminal of the output judgment module 500 outputs a low-level signal. The output terminal of the output judgment module 500 is the output terminal of the digital signal filter. Otherwise, when the first, second, third, and fourth trigger signals are any other arbitrary level, the output signal of the output judgment module 500 is the same as the output signal corresponding to the previous clock cycle, that is, the output signal of the output judgment module 500 remains unchanged.

[0064] In the digital signal filter disclosed in this embodiment, the output judgment module outputs a high-level signal when the first, second, and third trigger signals are all high, and a low-level signal when they are all low. Since the third and fourth trigger signals are determined by the data signal cin, the output judgment module compares the signal levels of adjacent clock cycles of the data signal cin to determine if there are any glitches. If a low-level glitch is present, the output judgment module maintains a high level to remove it; if a high-level glitch is present, the output judgment module maintains a low level to remove it. Therefore, even if a glitch is close to the effective clock edge, it can be filtered out. Furthermore, the digital signal filter disclosed in this embodiment abandons the software filtering algorithm, thereby effectively improving the filtering precision and effect of the digital signal filter while ensuring the real-time performance of the filtered signal.

[0065] In this embodiment, the precision of the glitches that the digital signal filter can remove can be adjusted by changing the time the second trigger signal is delayed compared to the first trigger signal. For example, if the second trigger signal is delayed by one clock cycle compared to the first trigger signal, it is equivalent to comparing the level signals of three adjacent clock cycles in the data signal cin. In this case, the duration of the glitches that the digital filter can remove is less than one clock cycle. If the second trigger signal is delayed by two clock cycles compared to the first trigger signal, it is equivalent to comparing the level signals of the first, middle, and last three of four adjacent clock cycles in the data signal cin. In this case, the duration of the glitches that the digital filter can remove is less than two clock cycles.

[0066] In a specific embodiment, the second trigger signal is delayed by one clock cycle compared to the first trigger signal, and the glitch signal is a digital signal with a duration of less than one clock cycle. That is, regardless of whether the glitch signal is active or passive, as long as its duration is less than one clock cycle, the digital signal filter disclosed in this embodiment can filter it out. This ensures both the filtering effect and the real-time performance of the digital signal filter.

[0067] In a specific embodiment, the filter chain module 100 includes two-stage trigger submodules: a first edge-triggered submodule 110 and a second edge-triggered submodule 120. The data input terminal of the first edge-triggered submodule 110 receives the data signal cin, the clock input terminal receives the clock signal smp_clk, the data output terminal of the first edge-triggered submodule 110 is the first trigger terminal B of the filter chain module 100, and the inverted data output terminal of the first edge-triggered submodule 110 is the inverted output terminal C of the filter chain module 100. The data input terminal of the second edge-triggered submodule 120 receives the first trigger signal, the clock input terminal receives the clock signal smp_clk, and the data output terminal outputs the second trigger signal.

[0068] In a preferred embodiment, the first edge-triggered submodule 110 and the second edge-triggered submodule 120 are D flip-flops, and both have rising edges as their effective clock edges. Specifically, the first edge-triggered submodule 110 is a D flip-flop dff01, and the second edge-triggered submodule 120 is a D flip-flop dff02.

[0069] In one embodiment, the fourth edge triggering module 400 is a fourth trigger submodule 420, and the set terminal of the fourth trigger submodule 420 is the set input terminal D of the fourth edge triggering module 400. One of the set valid signal of the fourth trigger submodule 420 and the reset valid signal of the third edge triggering module 300 is a high-level signal, and the other is a low-level signal; this ensures that the reset of the third edge triggering module 300 and the set of the fourth edge triggering module 400 cannot occur simultaneously.

[0070] In a specific embodiment, the reset valid signal of the third edge trigger module 300 is low, and the set valid signal of the fourth trigger submodule 420 is high. Therefore, when the data signal cin is low, the third edge trigger module 300 is reset, and the set of the fourth trigger submodule 420 is invalid; conversely, when the data signal cin is high, the reset of the third edge trigger module 300 is invalid, and the fourth trigger submodule 420 is set.

[0071] In another embodiment, the fourth edge-triggered module 400 includes an inverting submodule 410 and a fourth triggering submodule 420. The set signal of the fourth triggering submodule 420 and the reset signal of the third edge-triggered module 300 are both high-level or low-level signals. The input terminal of the inverting submodule 410 is the set input terminal D of the fourth edge-triggered module 400, and the inverting submodule 410 is used to output a data inverted signal with the opposite phase to the data signal cin. The set terminal of the fourth triggering submodule 420 receives the data inverted signal, and the output terminal of the fourth triggering submodule 420 is the data output terminal of the fourth edge-triggered module 400. When the data inverted signal is the set signal of the fourth triggering submodule 420, the fourth triggering signal is a high-level signal. That is, when the data signal cin is high and the data inverted signal is low, the fourth triggering submodule 420 is set, and the fourth triggering signal is a high-level signal.

[0072] In a specific embodiment, both the reset valid signal of the third edge trigger module 300 and the set valid signal of the fourth trigger submodule 420 are low. Therefore, when the data signal cin is low, the third edge trigger module 300 is reset, the inverting submodule 410 outputs a high level to the set terminal of the fourth trigger submodule 420, and the fourth trigger submodule 420 is set invalidally; when the data signal cin is high, the reset of the third edge trigger module 300 is invalid, the inverting submodule 410 outputs a low level to the set terminal of the fourth trigger submodule 420, and the fourth trigger submodule 420 is set.

[0073] In this embodiment, the output judgment module 500 includes a three AND gate submodule 510, a three NOR gate submodule 520, and a latch submodule 530.

[0074] The input terminal of the three AND gate submodule 510 receives the first trigger signal, the second trigger signal, and the third trigger signal, and the output terminal of the three AND gate submodule 510 outputs an AND gate signal; when the first trigger signal, the second trigger signal, and the third trigger signal are all high-level signals, the AND gate signal is a high-level signal.

[0075] The input terminal of the three NOR submodule 520 receives the first trigger signal, the second trigger signal and the fourth trigger signal, and the output terminal of the three NOR submodule 520 outputs the NOR gate signal; when the first trigger signal, the second trigger signal and the fourth trigger signal are all low level signals, the NOR gate signal is a high level signal.

[0076] The set terminal S of the latch submodule 530 receives an AND gate signal, the reset terminal R of the latch submodule 530 receives a NOR gate signal, and the output terminal of the latch submodule 530 outputs a filtered signal. When the AND gate signal is high and the NOR gate signal is low, the filtered signal is high; when both the AND gate signal and the NOR gate signal are high, the filtered signal is low; when both the AND gate signal and the NOR gate signal are low, the filtered signal remains unchanged.

[0077] Please see Figure 2 , Figure 2 This is a timing diagram of a high-level data signal cin input to a digital signal filter disclosed in this embodiment. When a low-level glitch signal is mixed into the high-level data signal cin, the first trigger signal, the second trigger signal, and the third trigger signal are all high-level signals, thus the AND gate signal is high-level; at the same time, since the first trigger signal and the second trigger signal are both high-level signals, the NOR gate signal is low-level signal; thus, the set terminal S of the latch submodule 530 receives a high-level signal, and the reset terminal R of the latch submodule 530 receives a low-level signal, so the filtered signal output by the latch submodule 530 is a high-level signal, thereby filtering out the low-level glitch signal in the data signal cin.

[0078] Please see Figure 3 , Figure 3 This is a timing diagram of a low-level data signal cin input to a digital signal filter disclosed in this embodiment. When a high-level glitch signal is mixed into the low-level data signal cin, the first trigger signal, the second trigger signal, and the fourth trigger signal are all low-level signals, thus the NOR gate signal is high-level; at the same time, since the first trigger signal and the second trigger signal are both low-level signals, the AND gate signal is low-level signal; consequently, the set terminal S of the latch submodule 530 receives a low-level signal, and the reset terminal R of the latch submodule 530 receives a high-level signal, so the filtered signal output by the latch submodule 530 is a low-level signal, thus filtering out the high-level glitch signal in the data signal cin.

[0079] In a specific embodiment, the three AND gate submodule 510 is a three-input AND gate AND00, the three NOR gate submodule 520 is a three-input NOR gate NOR00, and the latch submodule 530 is an RS latch rs00.

[0080] In a preferred embodiment, the digital signal filter further includes a frequency divider module. The frequency divider module outputs a clock signal smp_clk to the filter chain module 100. The frequency divider module is used to adjust the length of the clock period of the clock signal smp_clk. By setting a frequency divider module with an adjustable clock period, the clock period of the clock signal smp_clk received by the filter chain module 100 can be adjusted according to the duration of the glitches. This allows the maximum duration of the glitches that the digital signal filter can filter to be adjusted, further improving the filtering effect of the digital signal filter.

[0081] In the digital signal filter disclosed in this embodiment, when a glitch signal that only crosses one valid clock edge is mixed into the data signal cin, the process of filtering out the glitch signal is described below. It should be noted that 1 is used to represent a high-level signal and 0 is used to represent a low-level signal. The reset signal rst is used to control the reset of D flip-flops dff01 and dff02. When the reset signal rst is 0, the reset is valid, and both the first and second trigger signals are 0. When the reset signal rst is 1, the reset is invalid, and the output signals of D flip-flops dff01 and dff02 are determined by the signals received from their respective clock input and data input terminals.

[0082] Please see Figure 2 , Figure 2 This is a timing diagram of the input high-level data signal cin of a digital signal filter disclosed in this embodiment. For ease of explanation, when the correct data signal cin is high and the mixed-in signal (glitch signal) is low, a low-level glitch signal spanning a rising edge of 1.2 is used as an example.

[0083] Period 1.1: When the rising edge of the clock is reached, the data signal cincin is a normal high-level signal 1. Therefore, at the rising edge of the clock, the first trigger signal output by the D flip-flop dff01 jumps to 1 and the first inverted trigger signal jumps to 0.

[0084] During cycle 1.1, the first trigger signal remains 1 and the first inverting trigger signal remains 0, while the second trigger signal output by D flip-flop dff02 remains 0. Furthermore, since D flip-flop dff03 is not reset and D flip-flop dff04 is set when the data signal cincin is 1, the third trigger signal is determined by the first trigger signal and the high level of the data input terminal of D flip-flop dff03; that is, the third trigger signal jumps from 0 to 1 at the rising edge of the clock 1.1; the fourth trigger signal remains 1.

[0085] Period 1.2: When the rising edge of the clock is reached at 1.2, the data signal cincin is still a normal high-level signal 1. Therefore, at the rising edge of the clock at 1.2, the first trigger signal and the first inverted trigger signal remain unchanged. Since the first trigger signal is 1, the second trigger signal jumps from 0 to 1.

[0086] When the falling edge of the glitch is reached, the D flip-flop dff03 is immediately reset while the D flip-flop dff04 is set to invalid. Therefore, the third trigger signal changes from 1 to 0 at this time, while the fourth trigger signal is determined by the low level input of the first inverted trigger signal and the data input terminal of the D flip-flop dff04. That is, the fourth trigger signal remains at 1 until the first inverted trigger signal changes from 0 to 1.

[0087] During cycle 1.2, since the first, second, and third trigger signals are all 1 from the rising edge of the clock 1.2 to the falling edge of the glitch, the AND gate signal output by the three-input AND gate AND00 changes from 0 to 1. At the same time, the NOR gate signal output by the three-input NOR gate NOR00 is 0. Therefore, the set input S of the RS latch rs00 is 1 and the reset input R is 0, so the signal output by the RS latch rs00 changes from 0 to 1.

[0088] From the falling edge of the glitch to the rising edge of the clock (1.3), the first trigger signal, the first inverted trigger signal, the second trigger signal, and the fourth trigger signal remain unchanged, while the third trigger signal is 0. Therefore, the AND gate signal changes from 1 to 0, and the NOR gate signal remains 0. Consequently, the set input S and the reset input R of the RS latch rs00 are both 0, and the output signal of the RS latch rs00 remains unchanged at 1.

[0089] Period 1.3: When the rising edge of the clock is reached at 1.3, the low-level glitch signal mixed in with the data signal cincin crosses the rising edge of the clock at 1.3. Therefore, at the rising edge of the clock at 1.3, the first trigger signal jumps to 0 and the first inverted trigger signal jumps to 1. The jump of the first inverted trigger signal to 1 causes the fourth trigger signal to jump from 1 to 0.

[0090] When the rising edge of the glitch is reached, the reset of D flip-flop dff03 is invalid, while D flip-flop dff04 is immediately set. Therefore, the third trigger signal is determined by the rising edge of the first trigger signal and the high level of the data input terminal of D flip-flop dff03. That is, the third trigger signal remains unchanged at 0 before the first trigger signal jumps to 1; the fourth trigger signal jumps from 0 to 1.

[0091] In cycle 1.3, since the first, third, and fourth trigger signals are all 0 from the rising edge of the clock 1.3 to the rising edge of the glitch, and the second trigger signal is 1, the AND gate signal or NOT gate signal remains unchanged at 0.

[0092] From the rising edge of the glitch to the rising edge of the clock 1.4, the first trigger signal, the first inverted trigger signal, and the third trigger signal all remain unchanged at 0, the second trigger signal remains unchanged at 1, and the fourth trigger signal is 1. Therefore, the AND gate signal and the NOT gate signal all remain unchanged at 0.

[0093] Therefore, throughout the entire cycle 1.3, both the set terminal S and the reset terminal R of the RS latch rs00 are input to 0, so the signal output by the RS latch rs00 remains unchanged at 1.

[0094] Therefore, it can be seen that during periods 1.1-1.3, the data signal cincin contains a low-level glitch signal that crosses the rising edge of the clock 1.3. However, the output signal of the RS latch rs00 is not affected by this low-level glitch signal. The output signal of the RS latch rs00 is the output signal of the digital signal filter. It can be seen that the output signal of the digital signal filter is not affected by this low-level glitch signal. Thus, the digital signal filter disclosed in this embodiment filters out the low-level glitch signal.

[0095] Please see Figure 3 , Figure 3 This is a timing diagram of the input low-level data signal cin of a digital signal filter disclosed in this embodiment. For ease of explanation, when the correct data signal cin is low and the injected glitches are high, a high-level glitches spanning the rising edge 2.3 are used as an example.

[0096] Period 2.1: When the rising edge of the clock 2.1 is reached, the data signal cincin is a normal low-level signal 0. Therefore, at the rising edge of the clock 2.1, the first trigger signal jumps to 0 and the first inverted trigger signal jumps to 1. At this time, the D flip-flop dff04 is set invalid, and the rising edge of the first inverted trigger signal causes the fourth trigger signal to jump from 1 to 0.

[0097] In cycle 2.1, the first trigger signal remains 0 and the first inverting trigger signal remains 1, while the second trigger signal output by D flip-flop dff02 remains 1. Furthermore, since D flip-flop dff03 is reset while D flip-flop dff04 is not set when the data signal cincin is 0, the third trigger signal remains 0, and the fourth trigger signal remains 1.

[0098] Period 2.2: When the rising edge of the clock is reached at 2.2, the data signal cincin is still a normal low-level signal 0. Therefore, at the rising edge of the clock at 2.2, the first trigger signal and the first inverted trigger signal remain unchanged. Since the first trigger signal is 0, the second trigger signal jumps from 1 to 0.

[0099] When the rising edge of the glitch is reached, the D flip-flop dff03 is not reset and the D flip-flop dff04 is immediately set. Before the first trigger signal changes from 0 to 1, the third trigger signal remains 0; while the fourth trigger signal changes from 0 to 1.

[0100] In cycle 2.2, since the first, second, third, and fourth trigger signals are all 0 from the rising edge of the clock 2.2 to the rising edge of the glitch, the AND gate signal output by the three-input AND gate AND00 remains unchanged at 0. At the same time, the NOR gate signal is 1. Therefore, the set input S of the RS latch rs00 is 0 and the reset input R is 1, so the signal output by the RS latch rs00 jumps from 1 to 0.

[0101] Between the rising edge of the glitch and the rising edge of the clock (2.3), the first trigger signal, the first inverted trigger signal, the second trigger signal, and the third trigger signal remain unchanged, while the fourth trigger signal is 1. Therefore, the AND gate signal remains 0, and the NOR gate signal jumps to 0. Consequently, the set input S and the reset input R of the RS latch rs00 are both 0, and the output signal of the RS latch rs00 remains unchanged at 0.

[0102] Period 2.3: When the clock rises to 2.3, the low-level glitch signal mixed in with the data signal cincin crosses the clock rises to 2.3. Therefore, at the clock rises to 2.3, the first trigger signal jumps to 1 and the first inverted trigger signal jumps to 0. The rising edge of the first trigger signal causes the third trigger signal to jump from 0 to 1.

[0103] When the falling edge of the glitch is reached, the D flip-flop dff03 is immediately reset and invalidated, while the D flip-flop dff04 is set and invalidated. Therefore, the third trigger signal changes from 1 to 0 at this time. The fourth trigger signal is determined by the rising edge of the first inverted trigger signal and the low level of the data input terminal of the D flip-flop dff04. That is, the fourth trigger signal remains unchanged at 1 until the first inverted trigger signal changes to 1.

[0104] In cycle 2.3, since the first, third, and fourth trigger signals are all 1 and the second trigger signal is 0 from the rising edge of the clock 2.3 to the falling edge of the glitch, the AND gate signal or the NOT gate signal remains unchanged at 0.

[0105] From the falling edge of the glitch to the rising edge of the clock 2.4, the first and fourth trigger signals remain unchanged at 1, the second trigger signal remains unchanged at 0, and the third trigger signal is 0. Therefore, the AND gate signal and the NOT gate signal remain unchanged at 0.

[0106] Therefore, throughout the entire cycle 2.3, both the set terminal S and the reset terminal R of the RS latch rs00 are input to 0, so the signal output by the RS latch rs00 remains unchanged at 0.

[0107] Therefore, it can be seen that during periods 2.1-2.3, the data signal cincin contains a low-level glitch signal that crosses the rising edge of the clock 2.3. However, the output signal of the RS latch rs00 is not affected by this low-level glitch signal. It is evident that the output signal of the digital signal filter is not affected by this low-level glitch signal. Thus, the digital signal filter disclosed in this embodiment filters out this low-level glitch signal.

[0108] In summary, the filter chain module performs preliminary filtering on the data signal cin to obtain and output the second trigger signal. When the data signal cin is low, the third edge trigger module is reset, and the third trigger signal is low. At this time, the fourth edge trigger module is not set, so the fourth trigger signal remains unchanged before the first inverted trigger signal rises; after the first inverted trigger signal rises, the fourth trigger signal is low. When the data signal cin is high, the fourth edge trigger module is set, and the fourth trigger signal is high. At this time, the third edge trigger module is not reset, so the third trigger signal remains unchanged before the first trigger signal rises; after the first trigger signal rises, the third trigger signal is high. When the first, second, and third trigger signals are all high, the output judgment module outputs a high-level signal; when the first, second, and fourth trigger signals are all low, the output judgment module outputs a low-level signal. Otherwise, when the first, second, third, and fourth trigger signals are any other combination, the output signal of the output judgment module remains unchanged. Furthermore, since the glitch signal crosses a valid clock edge, when a glitch signal is present in the data signal cin, the first and second trigger signals, which differ by one clock cycle, will necessarily have one high and the other low. This ensures that the output signal of the output judgment module remains unchanged; that is, the glitch signal in the data signal cin will not cause a change in the output signal of the filter, thus filtering out the glitch signal. Therefore, even if the glitch signal approaches or even crosses the effective clock edge, it will not cause a change in the output signal of the filter, thus ensuring that the glitch signal is completely filtered out. Furthermore, the digital signal filter disclosed in this embodiment abandons the filtering method of software filtering algorithm, thereby effectively improving the filtering precision and filtering effect of digital signal filter while ensuring the real-time performance of the filtered signal.

[0109] This embodiment also discloses a chip for signal processing, including a digital signal filter as disclosed in the above embodiments.

[0110] In a specific embodiment, the chip also includes an I / O pin module and a logic circuit module.

[0111] The I / O pin module receives external digital signals and transmits them to a digital signal filter, which then filters the external digital signals to obtain a filtered signal. The logic circuit module receives the filtered signal; and / or,

[0112] The logic circuit module transmits internal digital signals to the digital signal filter so that the digital signal filter can filter the internal digital signals to obtain a filtered signal. The IO pin module receives the filtered signal and then transmits it to the external circuit.

[0113] This embodiment also discloses a filtering system, including at least two chips, wherein at least one chip is the chip disclosed in the above embodiment.

[0114] This embodiment also discloses an electronic device with signal processing function, including a digital signal filter as disclosed in the above embodiments.

[0115] Those skilled in the art will understand that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0116] It should be understood that the above embodiments are merely exemplary and not restrictive. Various obvious or equivalent modifications or substitutions that can be made by those skilled in the art regarding the above details without departing from the basic principles of the present invention will be included within the scope of the claims of the present invention.

Claims

1. A digital signal filter, characterized in that, include: The filter chain module (100), the third edge triggering module (300), the fourth edge triggering module (400), and the output judgment module (500) are included. The data input terminal of the filter chain module (100) receives a data signal (cin), the clock input terminal of the filter chain module (100) receives a clock signal (smp_clk), the filter output terminal (A) of the filter chain module (100) outputs a second trigger signal; the first trigger terminal (B) of the filter chain module (100) outputs a first trigger signal; the inverting output terminal (C) of the filter chain module (100) outputs a first inverted trigger signal with a phase opposite to the first trigger signal; the second trigger signal is delayed by one clock cycle compared to the first trigger signal. The reset terminal of the third edge trigger module (300) and the set input terminal (D) of the fourth edge trigger module (400) respectively receive the data signal (cin); When the data signal (cin) is low, the third edge trigger module (300) is reset, and the third trigger signal output by the third edge trigger module (300) is a low-level signal; when the data signal (cin) is high, in response to the rising edge of the first trigger signal, the third trigger signal is a high-level signal. When the data signal (cin) is high, the fourth edge trigger module (400) is set, and the fourth trigger signal output by the fourth edge trigger module (400) is a high-level signal; when the data signal (cin) is low, in response to the rising edge of the first inverted trigger signal, the fourth trigger signal is a low-level signal. The output judgment module (500) receives the first trigger signal, the second trigger signal, the third trigger signal, and the fourth trigger signal: when the first trigger signal, the second trigger signal, and the third trigger signal are all high, the output judgment module (500) outputs a high-level signal; when the first trigger signal, the second trigger signal, and the fourth trigger signal are all low, the output judgment module (500) outputs a low-level signal; otherwise, the output signal of the output judgment module (500) is the same as the output signal corresponding to the previous clock cycle; the output terminal of the output judgment module (500) is the output terminal of the digital signal filter.

2. The digital signal filter as described in claim 1, characterized in that, The filter chain module (100) includes a first edge-triggered submodule (110) and a second edge-triggered submodule (120); The data input terminal of the first edge-triggered submodule (110) receives the data signal (cin), the clock input terminal of the first edge-triggered submodule (110) receives the clock signal, the data output terminal of the first edge-triggered submodule (110) is the first trigger terminal (B) of the filter chain module (100), and the inverted data output terminal of the first edge-triggered submodule (110) is the inverted output terminal (C) of the filter chain module (100); The data input terminal of the second edge-triggered submodule (120) receives the first trigger signal, the clock input terminal of the second edge-triggered submodule (120) receives the clock signal, and the data output terminal of the second edge-triggered submodule (120) outputs the second trigger signal.

3. The digital signal filter as described in claim 1, characterized in that, The fourth edge trigger module (400) includes an inverting submodule (410) and a fourth trigger submodule (420). The set valid signal of the fourth trigger submodule (420) and the reset valid signal of the third edge trigger module (300) are both high-level signals or low-level signals. The input terminal of the inverting submodule (410) is the set input terminal (D) of the fourth edge triggering module (400) to output a data inverting signal that is opposite in phase to the data signal (cin); The set terminal of the fourth trigger submodule (420) receives the data inversion signal, and the output terminal of the fourth trigger submodule (420) is the data output terminal of the fourth edge trigger module (400); when the data inversion signal is a set valid signal, the fourth trigger signal is a high-level signal.

4. The digital signal filter as described in claim 1, characterized in that, The fourth edge trigger module (400) is a fourth trigger submodule (420), and the set terminal of the fourth trigger submodule (420) is the set input terminal (D) of the fourth edge trigger module (400); In the fourth trigger submodule (420), one of the set valid signal and the third edge trigger module (300) reset valid signal is a high-level signal and the other is a low-level signal, so that the reset of the third edge trigger module (300) and the set of the fourth edge trigger module (400) cannot be performed simultaneously.

5. The digital signal filter as described in claim 1, characterized in that, The output judgment module (500) includes a three AND gate submodule (510), a three NOR gate submodule (520), and a latch submodule (530); The input terminal of the three AND gate submodule (510) receives the first trigger signal, the second trigger signal, and the third trigger signal, and the output terminal of the three AND gate submodule (510) outputs an AND gate signal; when the first trigger signal, the second trigger signal, and the third trigger signal are all high-level signals, the AND gate signal is a high-level signal; The input terminal of the three NOR submodule (520) receives the first trigger signal, the second trigger signal and the fourth trigger signal, and the output terminal of the three NOR submodule (520) outputs a NOR gate signal; when the first trigger signal, the second trigger signal and the fourth trigger signal are all low level signals, the NOR gate signal is a high level signal; The set terminal of the latch submodule (530) receives the AND gate signal, the reset terminal of the latch submodule (530) receives the NOR gate signal, and the output terminal of the latch submodule (530) outputs the filtered signal. When the AND gate signal is high, the filtered signal is high; when the NOR gate signal is high, the filtered signal is low.

6. The digital signal filter as described in claim 1, characterized in that, The digital signal filter also includes a frequency divider module, which outputs the clock signal to the filter chain module (100) and is used to adjust the length of the clock period of the clock signal.

7. A chip for signal processing, characterized in that, Includes a digital signal filter as described in any one of claims 1-6.

8. The chip as described in claim 7, characterized in that, The chip also includes an I / O pin module and a logic circuit module; The IO pin module receives external digital signals and transmits them to the digital signal filter, so that the digital signal filter filters the external digital signals to obtain a filtered signal, and the logic circuit module receives the filtered signal; And / or, the logic circuit module transmits an internal digital signal to the digital signal filter so that the digital signal filter filters the internal digital signal to obtain a filtered signal, and the IO pin module receives the filtered signal and transmits it to an external circuit.

9. A filtering system, characterized in that, It includes at least two chips, wherein at least one chip is the chip as described in claim 7 or 8.

10. An electronic device with signal processing function, characterized in that, The electronic device includes a digital signal filter as claimed in any one of claims 1-6.

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