System for context-aware distributed processing and memory optimization in multi-core computer architectures

Abstract

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality.

Description

Invention filed The present invention relates generally to the field of computer technology and high-performance computing systems, in particular multi-core computer architectures with parallel and distributed processing. The invention specifically relates to a system that is implemented as a component in a computer architecture and enables context-sensitive distributed processing as well as adaptive memory optimization across multiple processor cores. The disclosed subject matter lies at the interface of processor architecture design, runtime planning, memory hierarchy management, and hardware-based performance optimization. Background of the invention Modern multi-core computer architectures are designed to handle increasingly complex workloads by distributing tasks across multiple processor units. However, conventional task scheduling and memory management methods often fail to adequately consider the execution context. This leads to inefficient use of computing resources, increased latency, cache conflicts, and excessive memory access overhead. Existing systems are typically based on static or semi-dynamic scheduling policies that do not sufficiently account for runtime variations such as workload characteristics, inter-process communication patterns, data locality, and memory hierarchy behavior. Furthermore, conventional memory optimization approaches cannot dynamically adapt to changing computational contexts, resulting in suboptimal cache utilization, frequent memory bottlenecks, and increased power consumption.These limitations necessitate the development of a system that can dynamically adjust processing distribution and memory allocation strategies in multi-core environments based on real-time context information. The development of multi-core computer architectures was driven by the need for sustained performance gains beyond the frequency scaling limits of single-core processors, particularly given the constraints of power density and the diminishing returns of instruction parallelism. Modern processors integrate multiple processor cores onto a single chip, interconnected via high-speed communication networks and supported by hierarchical memory subsystems with multi-level caches and shared main memory. While such architectures theoretically offer significant performance improvements through parallel execution, their realization depends heavily on efficient task allocation and memory management mechanisms.Existing solutions in distributed processing and storage optimization have attempted to address these challenges; however, they exhibit several technical limitations stemming from insufficient context awareness, rigid scheduling strategies, and inadequate coordination between processing and storage subsystems. Conventional operating system schedulers, such as those based on time-sharing or priority-based scheduling, primarily use coarse-grained metrics like CPU utilization, process priority, and fairness conditions to distribute tasks across cores. These schedulers typically operate at an abstraction level that doesn't fully capture detailed runtime characteristics like cache behavior, memory access patterns, or thread communication dependencies. Therefore, tasks may be assigned to processor cores without considering data locality, leading to frequent cache errors, increased memory access latency, and inefficient use of the cache hierarchy. Furthermore, such schedulers often lack the ability to dynamically adapt to rapidly changing workload conditions, especially in heterogeneous computing environments where cores may differ in their performance characteristics and power profiles.To improve task distribution across cores, advanced scheduling techniques, including load balancing and work stealing, have been proposed. Work stealing schedulers dynamically redistribute tasks by allowing unused cores to take over tasks from busy cores. This improves load balancing and reduces idle time. While these techniques increase overall system throughput, they introduce additional overhead due to task migration, synchronization, and competition for shared resources. Furthermore, these methods typically operate without detailed knowledge of memory hierarchy behavior, leading to suboptimal data placement and increased cache coherence traffic.Migrating tasks between cores often results in the invalidation of cache lines and requires data reloading, which can significantly impact the performance of memory-intensive applications. Attempts have been made to integrate more sophisticated scheduling mechanisms in parallel computing frameworks such as thread-level parallelism models and task-based runtime systems. These frameworks often use dependency graphs and task queues to control execution order and parallelization. However, many of these systems rely on a static or semi-static analysis of the program structure, limiting their ability to respond to dynamic runtime conditions. Furthermore, the separation of scheduling logic and memory management in such frameworks leads to a lack of coordinated optimization, as decisions about task placement are not closely tied to decisions about data placement.This discrepancy can lead to tasks being scheduled on cores that are geographically far from the storage locations of the required data, thereby increasing communication latency and reducing overall efficiency. Memory management in multi-core architectures has evolved similarly to address challenges related to data locality, bandwidth limitations, and cache coherence. Techniques such as Non-Uniform Memory Access (NUMA) optimization aim to improve performance by allocating memory closer to the processor cores that access it most frequently. NUMA-enabled schedulers attempt to align task placement with memory locality by binding threads to specific cores and memory areas. While such approaches can yield performance improvements in certain scenarios, they are often limited by their reliance on static allocation policies and manual optimization.For dynamic workloads with fluctuating access patterns, static NUMA policies may not ensure optimal data placement, leading to increased access to remote storage areas and reduced performance. Cache optimization techniques, including prefetching, cache partitioning, and optimized replacement policies, are also employed to improve the efficiency of the storage subsystem. Hardware prefetchers attempt to predict future memory accesses and preload data into the cache to reduce access latency. However, inaccurate predictions can lead to cache pollution, where useful data is displaced in favor of incorrectly preloaded data. Cache partitioning techniques, such as way partitioning and page coloring, aim to reduce conflicts between competing processes by allocating separate cache areas. While these techniques effectively isolate workloads, they often require prior knowledge of application behavior and may not be well-suited for dynamic execution contexts.Furthermore, such approaches typically operate independently of task scheduling mechanisms, which limits their ability to optimize the system holistically. Cache coherence protocols, including snooping-based and directory-based approaches, are essential for ensuring the consistency of shared data across multiple cores. However, these protocols introduce significant overhead in the form of coherence traffic, especially in systems with high data exchange. Frequent invalidation and update messages can overload connections and increase latency, particularly when tasks are not optimally positioned with respect to the shared data. Existing coherence mechanisms generally operate at the hardware level without incorporating contextual information about application behavior. This limits optimization opportunities based on workload characteristics. Recent developments in machine learning for scheduling and adaptive resource management aim to equip multi-core systems with predictive capabilities. These approaches leverage historical execution data to model workload behavior and make informed decisions about task allocation and resource utilization. While promising, such solutions often require significant computational overhead for model training and inference, which can negate the performance gains achieved. Furthermore, many machine learning techniques are implemented at the software level, leading to delays between context observation and decision execution. The lack of tight integration with hardware components also limits the granularity and responsiveness of such systems. Energy efficiency plays an increasingly important role in multi-core architectures and has led to the development of dynamic voltage and frequency scaling (DVFS) and energy-aware scheduling methods. These methods adapt the operating frequency and voltage of the processor cores to the workload, thereby reducing power consumption. However, existing power management systems often operate independently of memory optimization strategies and may not consider the interplay between computing power and data movement. Consequently, the energy savings achieved through reduced computing power can be offset by increased memory access costs, especially in data-intensive applications. Another limitation of existing solutions lies in their inability to effectively capture and utilize the broader execution context. While some systems monitor basic performance metrics such as instructions per clock cycle or cache error rates, they fail to synthesize this information into a unified view that enables coordinated decision-making across processing and storage subsystems. The lack of a holistic context model prevents these systems from achieving optimal trade-offs between competing goals such as performance, energy efficiency, and resource utilization. Furthermore, scalability remains a key challenge as the number of cores in modern processors continues to increase. Many existing scheduling and memory management methods exhibit diminishing returns or increased overhead with large core counts. Centralized control mechanisms can lead to bottlenecks, while decentralized approaches may suffer from a lack of coordination and consistency. The increasing complexity of interconnect architectures and memory hierarchies further exacerbates these challenges and necessitates more sophisticated and adaptive solutions. Despite significant advances in multi-core processors and memory optimization, existing solutions still suffer from limitations: limited context awareness, a lack of integration between scheduling and memory management, and an inability to dynamically adapt to changing workload conditions. These shortcomings underscore the need for a system that can continuously monitor the detailed execution context, integrate this information into unified decision-making processes, and coordinate and efficiently optimize both task allocation and memory usage. Summary of the invention The present invention relates to a system for context-sensitive distributed processing and memory optimization in multi-core computer architectures. A device structure monitors the execution context parameters and dynamically regulates task distribution and memory utilization. The system comprises multiple processor cores interconnected via a high-speed network, a context detection circuit for capturing runtime attributes, a scheduling circuit for distributing computational tasks based on context-aware intelligence, and a memory management circuit for optimizing data placement across hierarchical memory layers. The system further includes a predictive computation circuit for analyzing temporal and spatial execution patterns, enabling proactive reassignment of computational tasks and memory segments.By integrating context-controlled decision mechanisms directly into the hardware-software interaction layer, the invention achieves improved processing efficiency, reduced latency, increased cache coherence, and optimized memory bandwidth utilization. The present invention aims to provide a system for context-sensitive distributed processing and memory optimization in multi-core computer architectures. This system is intended to dynamically adapt task allocation and data placement strategies to the execution conditions in real time, thereby improving the overall efficiency of the computing power and the responsiveness of the system. The invention overcomes the limitations of conventional scheduling and memory management methods through a unified mechanism that continuously monitors the execution context and uses this information for coordinated decision-making in the processing and memory subsystems. A further objective of the invention is to improve data locality and reduce memory access latency by intelligently aligning task execution with the physical storage location of the associated data within a hierarchical memory structure. By ensuring that computational tasks are assigned to processor cores located near frequently accessed data, the system aims to minimize cache errors, reduce communication overhead between cores, and improve effective memory utilization. A further objective of the invention is to provide an adaptive scheduling mechanism that dynamically distributes computational loads across multiple processor cores. This is based on context parameters such as load intensity, execution priority, dependencies between tasks, and runtime performance metrics. The invention is designed to avoid resource conflicts and load imbalances by continuously adapting task assignments to changing execution conditions. A further objective of the invention is to optimize the use of multi-level cache and main memory through context-dependent data placement and migration strategies. The system is designed to ensure that frequently accessed and latency-sensitive data are placed in cache layers with lower latency, while less critical data is stored in memory areas with higher capacity. This achieves an optimal balance between speed and storage efficiency. A further objective of the invention is the integration of predictive functions that analyze historical execution patterns and anticipate future workload behavior in order to enable proactive task distribution and memory reallocation. This predictive function is intended to reduce performance losses due to sudden workload fluctuations and to ensure system stability under varying computing demands. A further objective of the invention is to improve synchronization and data consistency across multiple processor cores by dynamically controlling coherence operations based on the execution context. The system aims to reduce unnecessary coherence data traffic and synchronization overhead, thereby increasing throughput and reducing latency in shared memory environments. A further objective of the invention is to provide an energy-efficient solution for processing and memory management through the integration of context-sensitive power control techniques. The invention aims to optimize energy consumption by selectively adjusting the activity of the processor cores, the operating frequencies, and the memory access patterns according to the workload requirements, without compromising performance. A further objective of the invention is to ensure the scalability of processing and memory optimization strategies across architectures with a large number of processor cores. The system is designed to maintain efficient operation and low overhead even with increasing complexity of the computing environment, thus supporting next-generation high-performance and parallel computing systems. Another objective of the invention is to provide a device implementation that integrates context acquisition, task planning, memory management, predictive analysis and synchronization control in a coherent structure, thus enabling seamless interaction between hardware and software components and facilitating real-time optimization of computing resources. Another objective of the invention is to improve the overall system reliability and robustness by enabling continuous monitoring and adaptive response to execution anomalies, thereby reducing the probability of performance degradation and ensuring consistent operation under different workload conditions. BRIEF DESCRIPTION OF THE IMAGE These and other features, aspects and advantages of the present invention will be better understood if the following detailed description is read with reference to the accompanying drawing, in which the same symbols represent the same parts: Fig. 1 shows a block diagram of a system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture. Furthermore, those skilled in the art will recognize that the elements in the drawing are simplified and not necessarily drawn to scale. For example, the flowcharts illustrate the process by highlighting the main steps to facilitate understanding of the present disclosure. With regard to the construction of the device, one or more components may be represented in the drawing by conventional symbols. The drawing may show only those specific details relevant to understanding the embodiments of the present disclosure, so as not to clutter the drawing with details that are already apparent to those skilled in the art from the description contained herein. Detailed description of the invention To facilitate understanding of the principles of the invention, reference is made below to the embodiment shown in the drawing, which is described using specific terms. It is understood, however, that this does not limit the scope of protection of the invention. Rather, modifications and further developments of the depicted system, as well as further applications of the inventive principles shown therein, are conceivable, insofar as they would normally occur to a person skilled in the art in the field of the invention. It will be clear to those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not to be understood as a limitation thereof. References to “an aspect”, “another aspect”, or similar phrases in this description mean that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, phrases such as “in one embodiment”, “in another embodiment”, and similar expressions in this description may, but do not necessarily, all refer to the same embodiment. The terms "includes," "comprehensive," or similar expressions denote non-exclusive inclusion. Thus, a procedure or method containing a list of steps does not only include those steps but may also include further steps not explicitly listed or inherent in the procedure or method. Likewise, the statement "includes..." for one or more devices, subsystems, elements, structures, or components, without further limitations, does not preclude the existence of other devices, subsystems, elements, structures, or components. Unless otherwise defined, all technical and scientific terms used herein have the same meanings generally known to those skilled in the art in the field to which this invention belongs. The systems, methods, and examples described herein serve only for illustration and are not to be understood as limiting. Embodiments of the present disclosure are described in detail below with reference to the attached drawing. Fig. 1 shows a block diagram of a system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture. The system 100 comprises: multiple processor cores (102) arranged in a processor structure and configured for the parallel execution of computational tasks; a link network (104) connecting the processor cores for data communication; a context capture unit (106) connected to each processor core and monitoring execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, with the context capture unit generating context descriptors representing the runtime conditions; and a scheduling processor (108) connected to the context capture unit, which distributes computational tasks among the processor cores based on the generated context descriptors.and a memory management unit (110) operationally connected to a hierarchical storage arrangement comprising multiple cache levels and main memory, wherein the memory management unit is configured to dynamically allocate and migrate data segments across the hierarchical storage arrangement according to the context descriptors, thus achieving alignment between task execution and data locality. In one embodiment, the context acquisition unit (!06) comprises a plurality of hardware counters and sensor circuits configured to acquire detailed execution metrics at predetermined time intervals, and further comprises a context aggregation processor configured to convert the acquired metrics into structured descriptors containing temporal execution patterns and spatial data access properties. In one embodiment, the scheduling processor (!08) is configured to evaluate task assignment based on dependency relationships between tasks, execution priority levels, and predicted execution duration, and is further configured to assign tasks to the processing cores that have the minimum communication latency with respect to the associated data storage locations. In one embodiment, the scheduling processor (108) includes a redistribution mechanism configured to dynamically migrate tasks between the processing cores when an imbalance in the processing load or a change in the execution context is detected. This migration is performed while maintaining the consistency of the execution state. In one embodiment, the memory management unit (110) comprises a data classification processor configured to categorize data segments based on access frequency, reuse interval, and common properties, and a placement controller configured to allocate frequently accessed data segments to lower-latency cache levels and less frequently accessed data segments to higher-capacity memory areas. In one embodiment, the storage management unit (110) further comprises a migration controller configured to move data segments between storage levels in response to changes in access patterns, the move being performed using a predictive evaluation of future access requests derived from context descriptors. In an embodiment further comprising a predictive processing unit operationally linked to the context acquisition unit, configured to analyze historical execution data to generate predictive models that indicate future workload distribution and memory access behavior, wherein the scheduling processor and the memory management unit utilize the predictive models for proactive task assignment and data placement. In one embodiment, the predictive processing unit comprises a timing analysis processor configured to identify recurring execution patterns and a correlation processor configured to determine relationships between task execution sequences and memory access properties. In an embodiment further comprising a synchronization control unit configured to maintain data coherence across the plurality of processing cores, wherein the synchronization control unit dynamically adjusts the coherence operations based on context descriptors indicating the intensity of data exchange and the update frequency. In one embodiment, the synchronization control unit includes a coherence control processor configured to selectively enable or suppress cache invalidation and update operations to minimize communication overhead and maintain the consistency of the shared data. The present invention describes a system implemented as a device in a multi-core computing architecture. The system performs context-sensitive distributed processing and adaptive memory optimization through a tightly coordinated sequence of acquisition, analysis, prediction, allocation, and control operations. The underlying technology operates continuously in iterative cycles, each cycle comprising context acquisition, descriptor generation, decision computation, execution enforcement, and feedback adjustment. The system is configured such that all processor cores, memory units, and control units work together synchronously to ensure a real-time response to dynamic execution conditions. In the initial phase, the context acquisition unit continuously monitors the execution parameters of each processor core and its associated memory interfaces. This monitoring is performed using hardware-based sensor circuits and counters that capture instruction execution rates, execution latency, cache hits and misses, memory access frequency, core communication events, and synchronization delays. The captured raw data is time-stamped and forwarded to a context aggregation processor, which normalizes, filters, and aligns the data in time. The aggregation process transforms heterogeneous raw metrics into structured, multidimensional context descriptors. Each descriptor represents a state vector associated with a specific processor core and a specific time interval.The descriptor includes temporal gradients of execution load, spatial indicators of data locality, and correlation measures that represent the intensity of communication between tasks. After descriptor creation, the scheduling processor executes a context evaluation method to determine the optimal task distribution across the processor cores. This method first creates a dependency-based task graph, where nodes represent executable tasks and edges represent data or control dependencies. Each node is equipped with context-based attributes such as expected execution time, memory requirements, and communication needs. The scheduling processor then calculates a cost function for assigning each task to a potential processor core. This cost function considers weighted parameters such as processing load, proximity to required data, communication latency between cores, and predicted cache utilization.The scheduling processor then applies an optimization procedure to determine the allocation of tasks to cores by minimizing the cumulative cost of all tasks while adhering to dependency constraints. This optimization is performed iteratively using a restricted allocation method, which ensures that tasks with strong dependencies are placed on processor cores with minimal communication distance within the interconnect network. In parallel with task allocation, the memory management unit executes a data placement process that adapts memory allocation to the planned task distribution. The data classification processor categorizes data segments into different classes based on context descriptors, including frequently accessed data, shared data, transient data, and low-priority data. For each category, the placement controller determines the optimal memory level within the hierarchical memory structure. Frequently accessed and latency-sensitive data segments are allocated to lower-level cache memory, while less frequently accessed data is assigned to higher-level cache or main memory.The placement procedure uses a locality assessment function that evaluates temporal reuse intervals and the spatial proximity of data accesses, thus ensuring that data is positioned in storage locations that minimize access latency for the corresponding processor core. The system also includes a predictive processing unit that applies a forecasting technique based on historical context descriptors. This unit manages a time-series repository of context descriptors and uses pattern recognition to identify recurring workload patterns. The forecasting technique calculates indicators for future execution load, memory access requirements, and communication patterns between cores. Based on these indicators, both scheduling and memory allocation are adjusted in advance of actual workload changes. For example, if the forecasting technique detects an impending increase in memory access for a specific data segment, the memory management unit proactively migrates this segment to a lower-latency cache. Similarly, an anticipated increase in processing load for certain tasks leads to the pre-allocation of processor cores to meet the expected demand. Task and data migration are coordinated by the scheduling processor and the memory management unit. If a change in the execution context is detected, such as an uneven load distribution or increased communication overhead, the scheduling processor initiates a reassignment. Based on updated context descriptors and predictive indicators, the reassignment technique evaluates suitable processor cores for task migration. Before the migration, the memory management unit ensures that the relevant data segments are either already present in the target core's cache or have been pre-transferred to minimize interruptions. The migration process maintains the execution state by capturing intermediate results of calculations and restoring them to the target processor core, thus ensuring continuity of execution. The synchronization control unit operates in parallel to maintain data consistency across processor cores. It dynamically adjusts coherence strategies based on context descriptors that indicate data exchange intensity and update frequency. At high data exchange rates, the synchronization control unit enables selective update forwarding mechanisms to ensure consistency. At low data exchange rates, it suppresses unnecessary coherence operations to reduce communication overhead. The system also prioritizes synchronization events based on task criticality, ensuring that latency-sensitive tasks receive accelerated coherence updates. The power management unit uses an adaptive power management method that employs context descriptors to control energy consumption. For each processor core, the power management unit calculates a utilization index and determines optimal operating parameters such as clock frequency and power state. Processor cores with low utilization are put into a power-saving mode, while cores with high power demands operate at increased performance. The power management unit also coordinates with the memory management unit to reduce unnecessary memory accesses and thus minimize energy consumption during data transfer. The system also includes a feedback adjustment mechanism that continuously compares the results of scheduling and memory allocation decisions with actual execution performance. The context capture unit collects post-decision performance metrics, which are compared to predicted values ​​to calculate error measures. These error measures are used to refine the weighting parameters within scheduling and memory optimization, thereby improving decision accuracy across multiple cycles. The feedback mechanism ensures the dynamic evolution of the system and the maintenance of optimal performance under varying workload conditions. In large-scale multi-core architectures, the system is extended through hierarchical coordination. Groups of processor cores are managed by local scheduling processors, while a higher-level coordinating processor integrates global context information. This hierarchical structure reduces the computational overhead of central control while ensuring system consistency. Local scheduling decisions are optimized within core clusters, and global adjustments are made to balance the workload distribution across clusters. By integrating context analysis, predictive analytics, task scheduling, memory optimization, synchronization control, and power regulation into a unified technical framework, the system achieves efficient distributed processing and memory utilization. The continuous and adaptive nature of the system ensures that it responds effectively to dynamic execution conditions, minimizes latency, increases throughput, and optimizes resource utilization in multi-core computer architectures. The present invention describes a system implemented as a device integrated into a multi-core computer architecture. The system is configured to enable context-sensitive distributed processing and adaptive memory optimization. The device comprises several processor cores arranged in a parallel computer configuration, interconnected via an inter-core communication network for low-latency data exchange. Each processor core has a local cache memory and is also connected to a common memory hierarchy comprising multiple levels of cache and main memory units. The system includes a context capture circuit that is physically connected to the processor cores and configured to continuously monitor execution-specific parameters. These parameters include instruction execution rates, cache hit and failure rates, memory access latency, thread dependency properties, data exchange frequency, and communication patterns between cores. The context capture circuit transforms the monitored parameters into structured context descriptors that represent the current computational state of each processor core and its associated workloads. A scheduling circuit is connected to the context detection circuit and configured to dynamically distribute computational tasks across the various processor cores. The scheduling circuit uses context-sensitive assignment logic, where task distribution is based on generated context descriptors. The scheduling circuit evaluates factors such as workload intensity, data locality, execution priority, and dependencies between tasks to assign them to specific processor cores in a way that minimizes execution delays and reduces resource conflicts. The system also includes a memory management circuit configured to optimize data placement and access within the hierarchical storage architecture. This circuit dynamically assigns data segments to appropriate storage levels based on context descriptors that specify access frequency, temporal reuse patterns, and spatial location. Frequently accessed data segments are proactively moved to lower-latency cache layers, while less critical data is stored in higher-capacity storage units. The memory management circuit also coordinates with the scheduling circuit to ensure alignment between task distribution and data placement, thereby reducing storage access overhead. A predictive computing circuit is integrated into the device and analyzes historical execution patterns to generate predictive models for future workload behavior. This circuit uses temporal correlation analysis and pattern recognition techniques to predict changes in workload distribution and memory access patterns. Based on these predictions, the system performs preventive task migrations and memory reallocations to prevent performance degradation. The system also includes a synchronization controller that ensures data consistency and coherence across multiple processor cores. This controller ensures the efficient propagation of shared data updates with minimal synchronization overhead. The circuit dynamically adapts the coherence protocols based on context descriptors, thereby reducing unnecessary data invalidation and improving system throughput. Furthermore, the device features an energy-efficient control circuit that adapts processing and storage operations to power consumption limits. This control circuit uses contextual information to selectively activate or deactivate processor cores, regulate clock frequencies, and control memory access intensity. This achieves optimized energy efficiency without compromising performance. During operation, the system continuously gathers information about the execution context, processes it to generate context descriptors, and uses these to control task scheduling and memory allocation. The integration of context-sensitive mechanisms into the processing and memory subsystems enables the system to dynamically adapt to changing computing conditions. This results in improved scalability, reduced latency, optimized resource utilization, and lower energy consumption. The presented system thus offers a comprehensive device-level solution for intelligent distributed processing and memory optimization in multi-core computer architectures, overcoming the limitations of conventional static and context-independent approaches. The present invention relates generally to computer architecture and high-performance computing systems, in particular multi-core processing environments with parallel execution and memory hierarchy management. The invention specifically relates to a system implemented as a component in a computer architecture that enables context-sensitive distributed processing and adaptive memory optimization across multiple processor cores. The disclosed subject matter includes techniques related to runtime planning, improved data locality, cache and memory management, core communication, and energy-efficient processing. The invention is applicable to general-purpose processors, embedded computer systems, and large-scale parallel computing infrastructures where efficient coordination between processing units and memory resources is essential for improved computing performance, scalability, and energy efficiency. The drawing and the preceding description illustrate embodiments. Those skilled in the art will recognize that one or more of the described elements can be combined to form a single functional element. Alternatively, certain elements can be divided into several functional elements. Elements of one embodiment can be added to another. For example, the process flows described here can be modified and are not limited to the manner described herein. Furthermore, the actions of a flowchart need not be performed in the sequence shown; nor do all actions necessarily need to be carried out. Actions that do not depend on other actions can be performed in parallel with the other actions. The scope of protection of the embodiments is in no way limited by these specific examples. Numerous variations, whether explicitly stated in the description or not, such as...Differences in structure, dimensions, and materials are possible. The scope of protection of the embodiments is at least as comprehensive as described by the following claims. The advantages, other benefits, and problem solutions have been described above with reference to specific embodiments. However, the advantages, benefits, problem solutions, and any components that can effect or enhance an advantage, benefit, or solution are not to be construed as critical, necessary, or essential features or components of the claims. REFERENCES 100 A system for context-aware distributed processing and memory optimization in a multi-core computer architecture. 102 Multiple processing cores 104 Interconnect structure 106 Context acquisition unit 108 Scheduling processor 110 Memory management unit

Claims

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality. System according to claim 1, wherein the context acquisition unit comprises a plurality of hardware counters and sensor circuits configured to acquire detailed execution metrics at predetermined time intervals, and further comprises a context aggregation processor configured to convert the acquired metrics into structured descriptors containing temporal execution patterns and spatial data access properties. System according to claim 1, wherein the scheduling processor is configured to evaluate task assignment based on dependency relationships between tasks, execution priority levels and predicted execution duration, and is further configured to assign tasks to processing cores that have minimal communication latency relative to the associated data storage locations. System according to claim 1, wherein the scheduling processor comprises a redistribution mechanism configured to dynamically migrate tasks between processing cores when an imbalance in the processing load or a change in the execution context is detected, wherein this migration is performed while maintaining the consistency of the execution state. System according to claim 1, wherein the memory management unit comprises a data classification processor configured to categorize data segments based on access frequency, reuse interval and common properties, and a placement controller configured to allocate frequently accessed data segments to lower latency cache levels and less frequently accessed data segments to higher capacity memory areas. System according to claim 1, wherein the storage management unit further comprises a migration controller configured to move data segments between storage levels in response to changes in access patterns, wherein the move is performed using a predictive evaluation of future access requests derived from context descriptors. The system according to claim 1 further comprises a predictive processing unit that is operationally connected to the context acquisition unit and is configured to analyze historical execution data to generate predictive models that indicate future workload distribution and memory access behavior, wherein the scheduling processor and the memory management unit use the predictive models for proactive task assignment and data placement. System according to claim 7, wherein the predictive processing unit comprises a time analysis processor configured to identify recurring execution patterns and a correlation processor configured to determine relationships between task execution sequences and memory access properties. System according to claim 1, further comprising a synchronization control unit configured to maintain data coherence across the plurality of processing cores, wherein the synchronization control unit dynamically adjusts the coherence operations based on context descriptors indicating the intensity of data exchange and the update frequency. System according to claim 9, wherein the synchronization control unit comprises a coherence control processor configured to selectively enable or suppress cache invalidation and update operations to minimize communication overhead and maintain consistency of the shared data.

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