Display device and method of manufacturing the same

Abstract

A display device of one embodiment includes a first display element including a first lower electrode, a first upper electrode, and a first organic layer that emits light in response to a voltage between the first lower electrode and the first upper electrode; a second display element including a second lower electrode, a second upper electrode, and a second organic layer that emits light in response to a voltage between the second lower electrode and the second upper electrode; and a partition wall provided between the first display element and the second display element. The partition wall includes a lower portion including a first side surface on the first display element side and a second side surface on the second display element side, and an upper portion including a first end portion protruding from the first side surface and a second end portion protruding from the second side surface. The first end portion has light-blocking properties, and the second end portion has light-transmitting properties.

Description

[0001] Cross-referencing of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2022-047128, filed on March 23, 2022, and incorporates all the contents of that Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Technology

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. These display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0005] When manufacturing the aforementioned display device, techniques are needed to suppress reliability degradation. Summary of the Invention

[0006] In general, according to the embodiments, the display device includes: a first display element comprising a first lower electrode, a first upper electrode, and a first organic layer that emits light corresponding to a voltage between the first lower electrode and the first upper electrode; a second display element comprising a second lower electrode, a second upper electrode, and a second organic layer that emits light corresponding to a voltage between the second lower electrode and the second upper electrode; and a partition wall disposed between the first display element and the second display element. The partition wall includes: a lower portion having a first side surface on the side of the first display element and a second side surface on the side of the second display element; and an upper portion having a first end portion protruding from the first side surface and a second end portion protruding from the second side surface. The first end portion is light-shielding, and the second end portion is light-transmitting.

[0007] Furthermore, according to an embodiment, the manufacturing method of the display device includes the following processes: forming a first lower electrode and a second lower electrode; forming a partition wall having a lower portion and an upper portion, wherein the lower portion has a first side surface on the side of the first lower electrode and a second side surface on the side of the second lower electrode, and the upper portion has a light-shielding first end protruding from the first side surface and a light-transmitting second end protruding from the second side surface; and sequentially forming a first organic layer including a light-emitting layer, a first upper electrode covering the first organic layer, and a layer of material on the first lower electrode, the second lower electrode, and the partition wall. A first sealing layer formed of inorganic material and a first photoresist covering the first sealing layer; exposing the portion of the first photoresist overlapping the second lower electrode and the second end, removing the exposed portion of the first photoresist by exposing the first photoresist to a developer; and removing the portion of the first organic layer, the first upper electrode, and the first sealing layer exposed from the first photoresist by a first etching, thereby forming a first display element comprising the first lower electrode, the first organic layer, and the first upper electrode.

[0008] The reliability of the display device can be improved by adjusting the configuration of the implementation method. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating an example configuration of a display device according to one embodiment.

[0010] Figure 2 This is a diagram showing an example of the layout of subpixels.

[0011] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device along line III-III.

[0012] Figure 4 It is a magnified schematic cross-sectional view of the partition between the first and second sub-pixels and its vicinity.

[0013] Figure 5 This is a schematic cross-sectional view showing another example of a construction that can be applied to a partition.

[0014] Figure 6 This is a rough top view of the building next door.

[0015] Figure 7 This is a flowchart illustrating an example of a method for manufacturing a display device.

[0016] Figure 8 This is a schematic cross-sectional view showing a part of the manufacturing process of the display device.

[0017] Figure 9 It shows the next step. Figure 8 A simplified cross-sectional view of the manufacturing process.

[0018] Figure 10 It shows the next step. Figure 9 A simplified cross-sectional view of the manufacturing process.

[0019] Figure 11 It shows the next step. Figure 10 A simplified cross-sectional view of the manufacturing process.

[0020] Figure 12 It shows the next step. Figure 11 A simplified cross-sectional view of the manufacturing process.

[0021] Figure 13 It shows the next step. Figure 12 A simplified cross-sectional view of the manufacturing process.

[0022] Figure 14 It shows the next step. Figure 13 A simplified cross-sectional view of the manufacturing process.

[0023] Figure 15 It shows the next step. Figure 14 A simplified cross-sectional view of the manufacturing process.

[0024] Figure 16 It shows the next step. Figure 15 A simplified cross-sectional view of the manufacturing process.

[0025] Figure 17 It shows the next step. Figure 16 A simplified cross-sectional view of the manufacturing process.

[0026] Figure 18 It shows the next step. Figure 17 A simplified cross-sectional view of the manufacturing process.

[0027] Figure 19 It shows the next step. Figure 18 A simplified cross-sectional view of the manufacturing process.

[0028] Figure 20 It shows the next step. Figure 19 A simplified cross-sectional view of the manufacturing process.

[0029] Figure 21 It shows the next step. Figure 20 A simplified cross-sectional view of the manufacturing process.

[0030] Figure 22 It shows the next step. Figure 21 A simplified cross-sectional view of the manufacturing process.

[0031] Figure 23 It shows the next step. Figure 22 A simplified cross-sectional view of the manufacturing process.

[0032] Figure 24 It shows the next step. Figure 23 A simplified cross-sectional view of the manufacturing process.

[0033] Figure 25 It shows the next step. Figure 24 A simplified cross-sectional view of the manufacturing process.

[0034] Figure 26 It shows the next step. Figure 25 A simplified cross-sectional view of the manufacturing process. Detailed Implementation

[0035] One embodiment is described with reference to the accompanying drawings.

[0036] The disclosure is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art without departing from the spirit of the invention are naturally included within the scope of this invention. Furthermore, regarding the accompanying drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form, but this is merely an example and not a limitation on the interpretation of the invention. Additionally, in this specification and the various figures, for constituent elements that perform the same or similar functions as those described with respect to the already presented figures, there are instances where the same reference numerals are used and repeated detailed descriptions are appropriately omitted.

[0037] It should be noted that, for ease of understanding, mutually orthogonal X-axis, Y-axis, and Z-axis are shown in the accompanying drawings. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis as the second direction, and the direction along the Z-axis as the third direction. The observation of various elements parallel to the third direction Z is called a top-down view.

[0038] The display device of this embodiment is an organic electroluminescent display device that includes an organic light-emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet computers, smartphones, mobile phones, etc.

[0039] Figure 1 This diagram illustrates a configuration example of the display device DSP according to this embodiment. The display device DSP has a display area DA for displaying images and a peripheral area SA surrounding the display area DA on an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0040] In this embodiment, the substrate 10 viewed from above has a rectangular shape. However, the shape of the substrate 10 viewed from above is not limited to a rectangle; it can also be other shapes such as a square, a circle, or an ellipse.

[0041] The display area DA has multiple pixels PX arranged in a matrix along the first direction X and the second direction Y. Each pixel PX contains multiple sub-pixels SP. In one example, pixel PX contains a blue first sub-pixel SP1, a green second sub-pixel SP2, and a red third sub-pixel SP3. It should be noted that pixel PX may also contain sub-pixels SP of other colors, such as white, along with or in place of any of the sub-pixels SP1, SP2, and SP3.

[0042] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements, for example, made of thin-film transistors.

[0043] The gate electrode of pixel switch 2 is connected to scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE. Display element DE is an organic light-emitting diode (OLED) that serves as the light-emitting element.

[0044] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0045] Figure 2 This diagram illustrates an example of the layout of subpixels SP1, SP2, and SP3. Figure 2 In the example, the second sub-pixel SP2 and the first sub-pixel SP1 are arranged in the first direction X. The third sub-pixel SP3 and the first sub-pixel SP1 are also arranged in the first direction X. In addition, the third sub-pixel SP3 and the second sub-pixel SP2 are arranged in the second direction Y.

[0046] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains multiple columns in which the first sub-pixel SP1 is repeatedly arranged in the second direction Y, and columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y. These columns are alternately arranged in the first direction X.

[0047] It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to... Figure 2 For example, the sub-pixels SP1, SP2, and SP3 in each pixel PX can also be arranged sequentially in the first direction X.

[0048] The display area DA is provided with ribs 5 and partitions 6. Rib 5 has a first pixel opening AP1 at the first sub-pixel SP1, a second pixel opening AP2 at the second sub-pixel SP2, and a third pixel opening AP3 at the third sub-pixel SP3. Figure 2 In the example, the second pixel opening AP2 is larger than the third pixel opening AP3, and the first pixel opening AP1 is larger than the second pixel opening AP2.

[0049] The partition 6 is disposed on the boundary of adjacent sub-pixels SP and overlaps with the rib 5 when viewed from above. The partition 6 has a plurality of first partitions 6x extending along a first direction X and a plurality of second partitions 6y extending along a second direction Y. The plurality of first partitions 6x are respectively disposed between two adjacent first pixel openings AP1 in the second direction Y, and between adjacent pixel openings AP2 and AP3 in the second direction Y. The second partitions 6y are respectively disposed between adjacent pixel openings AP1 and AP2 in the first direction X, and between adjacent pixel openings AP1 and AP3 in the first direction X.

[0050] exist Figure 2 In the example, the first partition 6x and the second partition 6y are interconnected. Thus, partition 6 as a whole forms a lattice shape surrounding the pixel openings AP1, AP2, and AP3. Partition 6 can also have openings in the sub-pixels SP1, SP2, and SP3, similar to rib 5.

[0051] The first sub-pixel SP1 has a first lower electrode LE1, a first upper electrode UE1, and a first organic layer OR1 that overlap with the first pixel opening AP1, respectively. The second sub-pixel SP2 has a second lower electrode LE2, a second upper electrode UE2, and a second organic layer OR2 that overlap with the second pixel opening AP2, respectively. The third sub-pixel SP3 has a third lower electrode LE3, a third upper electrode UE3, and a third organic layer OR3 that overlap with the third pixel opening AP3, respectively. Figure 2 In the example, the first upper electrode UE1 has the same shape as the first organic layer OR1, the second upper electrode UE2 has the same shape as the second organic layer OR2, and the third upper electrode UE3 has the same shape as the third organic layer OR3.

[0052] The first lower electrode LE1, the first upper electrode UE1, and the first organic layer OR1 constitute the first display element DE1 of the first sub-pixel SP1. The second lower electrode LE2, the second upper electrode UE2, and the second organic layer OR2 constitute the second display element DE2 of the second sub-pixel SP2. The third lower electrode LE3, the third upper electrode UE3, and the third organic layer OR3 constitute the third display element DE3 of the third sub-pixel SP3.

[0053] For example, the first display element DE1 emits light in the blue wavelength region, the second display element DE2 emits light in the green wavelength region, and the third display element DE3 emits light in the red wavelength region.

[0054] The first lower electrode LE1 is connected to the pixel circuit 1 of the first sub-pixel SP1 through the first contact hole CH1 (see...). Figure 1 The second lower electrode LE2 is connected to the pixel circuit 1 of the second sub-pixel SP2 through the second contact hole CH2. The third lower electrode LE3 is connected to the pixel circuit 1 of the third sub-pixel SP3 through the third contact hole CH3.

[0055] exist Figure 2 In the example, the first contact hole CH1 completely overlaps with the first partition 6x between two adjacent first pixel openings AP1 in the second direction Y. Contact holes CH2 and CH3 completely overlap with the first partition 6x between adjacent pixel openings AP2 and AP3 in the second direction Y. Alternatively, at least a portion of the contact holes CH1, CH2, and CH3 may not overlap with the first partition 6x.

[0056] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness created by circuit layer 11. Although in Figure 3 The cross-section is not shown, but the contact holes CH1, CH2, and CH3 mentioned above are disposed on the organic insulating layer 12.

[0057] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Ribs 5 are disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0058] The partition 6 includes a lower conductive portion 61 disposed above the rib 5 and an upper portion 62 disposed above the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. Therefore, in Figure 3 In the middle, the two ends of the upper part 62 protrude beyond the sides of the lower part 61. Such a shape of the partition 6 can also be called cantilevered.

[0059] The upper part 62 includes a transparent layer TP that is translucent and a light-blocking layer LS that is opaque. Figure 3 In the example, the transparent layer TP is positioned above the lower part 61, and the light-shielding layer LS is positioned above the transparent layer TP.

[0060] In the partition 6 between sub-pixels SP1 and SP2, the light-shielding layer LS covers a portion of the transparent layer TP near the first sub-pixel SP1. In the partition 6 between sub-pixels SP1 and SP3, the light-shielding layer LS covers a portion of the transparent layer TP near the first sub-pixel SP1.

[0061] Organic layer OR1 (1st layer) covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 (1st layer) covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 (2nd layer) covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 (2nd layer) covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 (3rd layer) covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 (3rd layer) covers organic layer OR3 and is opposite to lower electrode LE3.

[0062] exist Figure 3 In the example, a first capping layer CP1 is disposed on the first upper electrode UE1, a second capping layer CP2 is disposed on the second upper electrode UE2, and a third capping layer CP3 is disposed on the third upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively adjust the optical properties of the light emitted by the organic layers OR1, OR2, and OR3.

[0063] A portion of the first organic layer OR1, the first upper electrode UE1, and the first capping layer CP1 is located on the upper portion 62. This portion is separate from the other portions of the first organic layer OR1, the first upper electrode UE1, and the first capping layer CP1. Similarly, a portion of the second organic layer OR2, the second upper electrode UE2, and the second capping layer CP2 is located on the upper portion 62, and this portion is separate from the other portions of the second organic layer OR2, the second upper electrode UE2, and the second capping layer CP2. Furthermore, a portion of the third organic layer OR3, the third upper electrode UE3, and the third capping layer CP3 is located on the upper portion 62, and this portion is separate from the other portions of the third organic layer OR3, the third upper electrode UE3, and the third capping layer CP3.

[0064] The first sub-pixel SP1 is provided with a first sealing layer SE1, the second sub-pixel SP2 is provided with a second sealing layer SE2, and the third sub-pixel SP3 is provided with a third sealing layer SE3. The first sealing layer SE1 continuously covers the first capping layer CP1 and the partition 6. The second sealing layer SE2 continuously covers the second capping layer CP2 and the partition 6. The third sealing layer SE3 continuously covers the third capping layer CP3 and the partition 6.

[0065] Sealing layers SE1, SE2, and SE3 are covered by resin layer 13. Resin layer 13 is covered by sealing layer 14. Furthermore, sealing layer 14 is covered by resin layer 15.

[0066] The organic insulating layer 12 and resin layers 13 and 15 are formed of organic materials. The ribs 5 and sealing layers 14, SE1, SE2, and SE3 are formed of inorganic materials such as silicon nitride (SiNx). The ribs 5 and sealing layers 14, SE1, SE2, and SE3 can also be formed as any one of the following monolayers: silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, the ribs 5 and sealing layers 14, SE1, SE2, and SE3 can also be formed as a laminate consisting of at least two of the following layers: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, and aluminum oxide layer.

[0067] The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0068] Organic layers OR1, OR2, and OR3 comprise a pair of functional layers and a light-emitting layer disposed between the functional layers. As an example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially.

[0069] The capping layers CP1, CP2, and CP3 are formed, for example, from a multilayer of transparent thin films. The multilayer may also comprise thin films formed of inorganic and organic materials. Furthermore, these multiple thin films have different refractive indices. The materials constituting the multilayer are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. It should be noted that the capping layers CP1, CP2, and CP3 can also be omitted.

[0070] A common voltage is supplied to the partition 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages via the pixel circuits 1 of each of the sub-pixels SP1, SP2, and SP3.

[0071] If a potential difference is formed between the first lower electrode LE1 and the first upper electrode UE1, the light-emitting layer of the first organic layer OR1 emits light in the blue wavelength region. If a potential difference is formed between the second lower electrode LE2 and the second upper electrode UE2, the light-emitting layer of the second organic layer OR2 emits light in the green wavelength region. If a potential difference is formed between the third lower electrode LE3 and the third upper electrode UE3, the light-emitting layer of the third organic layer OR3 emits light in the red wavelength region.

[0072] Figure 4This is a schematic cross-sectional view of the partition 6 and its vicinity located between sub-pixels SP1 and SP2, enlarged. In this figure, the substrate 10, circuit layer 11, resin layer 13, sealing layer 14, and resin layer 15 are omitted.

[0073] The lower portion 61 of the partition 6 has a first side surface F1 on the side of the first sub-pixel SP1 (the side of the first display element DE1) and a second side surface F2 on the side of the second sub-pixel SP2 (the side of the second display element DE2). The upper portion 62 of the partition 6 has a first end portion E1 protruding from the first side surface F1 and a second end portion E2 protruding from the second side surface F2. The first upper electrode UE1 is in contact with the first side surface F1, and the second upper electrode UE2 is in contact with the second side surface F2.

[0074] exist Figure 4 In this example, the lower part 61 has a first metal layer 611 disposed on the rib 5 and a second metal layer 612 disposed on the first metal layer 611. The second metal layer 612 is formed to be thicker than the first metal layer 611.

[0075] The transparent layer TP of the upper part 62 is formed within the range from the first end E1 to the second end E2. Figure 4 In the example, the transparent layer TP has a first transparent layer 621 disposed on the first metal layer 611 and a second transparent layer 622 disposed on the first transparent layer 621.

[0076] The light-shielding layer LS of the upper portion 62 is disposed above the second transparent layer 622 at least at the first end E1, but not at the second end E2. That is, the first end E1 includes the transparent layer TP and the light-shielding layer LS. On the other hand, the second end E2 includes the transparent layer TP but not the light-shielding layer LS. Figure 4 In the example, the light-shielding layer LS also reaches the area between the first end E1 and the second end E2.

[0077] The light-shielding layer LS may not necessarily be disposed above the transparent layer TP. As another example, the light-shielding layer LS may also be disposed below the transparent layer TP. In addition, the light-shielding layer LS may also be disposed between the first transparent layer 621 and the second transparent layer 622.

[0078] The first metal layer 611 is formed of, for example, molybdenum (Mo). The second metal layer 612 is formed of, for example, aluminum (Al). The second metal layer 612 can be formed of an aluminum alloy or have a laminated structure of aluminum and aluminum alloy.

[0079] The first transparent layer 621 is formed of, for example, silicon oxide. The second transparent layer 622 is formed of, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and IGZO (Indium Gallium Zinc Oxide).

[0080] The light-shielding layer LS is formed of, for example, titanium (Ti). Preferably, the light-shielding layer LS has a transmittance of less than 10% for at least one of light with a wavelength of 436 nm (g line) and light with a wavelength of 405 nm (h line).

[0081] exist Figure 3 and Figure 4 In the example, the first organic layer OR1, the first upper electrode UE1 and the first capping layer CP1 above the upper part 62 are separated from the second organic layer OR2, the second upper electrode UE2 and the second capping layer CP2 above the upper part 62.

[0082] The first sealing layer SE1 continuously covers the first display element DE1, the first side F1, and the first end E1. The second sealing layer SE2 continuously covers the second display element DE2, the second side F2, and the second end E2. The ends of the first sealing layer SE1 and the second sealing layer SE2 are located above the upper part 62 and are separated from each other.

[0083] A void V, not filled by the first sealing layer SE1, is formed below the first end E1. A void V, not filled by the second sealing layer SE2, is also formed below the second end E2.

[0084] A portion of the first organic layer OR1, the first upper electrode UE1, the first capping layer CP1, and the first sealing layer SE1 lies above the light-shielding layer LS. Figure 4 In one example, the aforementioned portion does not contact the second transparent layer 622. In another example, the aforementioned portion may also contact the second transparent layer 622.

[0085] Figure 5 This is a schematic cross-sectional view showing another example of a construction that can be applied to partition 6. In this example, the lower part 61 has a single-layer construction. Additionally, the transparent layer TP also has a single-layer construction.

[0086] The lower part 61 of the single-layer structure can be formed of, for example, aluminum or an aluminum alloy. The transparent layer TP of the single-layer structure can be formed of, for example, silicon oxide.

[0087] It should be noted that the structure of neighboring 6 is not limited to Figure 4 and Figure 5For example, the lower part 61 may have a layered structure, while the transparent layer TP may have a single-layer structure. Alternatively, the lower part 61 may have a single-layer structure, while the transparent layer TP may have a layered structure.

[0088] The structure of the partition 6 between sub-pixels SP1 and SP3 and its vicinity Figure 4 or Figure 5 The partition 6 between sub-pixels SP1 and SP2 and its vicinity have the same structure.

[0089] Figure 6 This is a rough top view of layer 6 next door. The area with the dotted pattern corresponds to the transparent layer TP, and the area with the diagonal pattern corresponds to the light-blocking layer LS. The light-blocking layer LS overlaps entirely with the transparent layer TP.

[0090] The transparent layer TP is a grid-like structure surrounding sub-pixels SP1, SP2, and SP3 (display elements DE1, DE2, and DE3). The light-shielding layer LS surrounds the first sub-pixel SP1 (the first display element DE1).

[0091] Specifically, the light-shielding layer LS is disposed entirely in the first partition 6x between adjacent first sub-pixels SP1 in the second direction Y. Furthermore, the light-shielding layer LS is disposed in a portion of the second partition 6y between sub-pixels SP1 and SP2 near the first sub-pixel SP1, and in a portion of the second partition 6y between sub-pixels SP1 and SP3 near the first sub-pixel SP1.

[0092] The shape of the light-shielding layer LS is not limited to Figure 6 For example, the light-shielding layer LS is a frame surrounding each first sub-pixel SP1, and the light-shielding layers LS surrounding adjacent first sub-pixels SP1 can also be separated from each other.

[0093] Next, the manufacturing method of the display device DSP will be explained.

[0094] Figure 7 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figures 8 to 26 This is a schematic cross-sectional view showing a part of the manufacturing process of a display device DSP.

[0095] In the manufacturing of the display device DSP, a circuit layer 11 and an organic insulating layer 12 are first formed on the substrate 10. Figure 7 Process P1).

[0096] After process P1, such as Figure 8 As shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Figure 7 Process P2).

[0097] After process P2, such as Figure 9 As shown, an insulating layer 5a is formed as the base of the rib 5. Figure 7 (Process P3). The insulating layer 5a is formed of an inorganic material such as silicon nitride and covers the lower electrodes LE1, LE2, and LE3.

[0098] Partition 6 is formed after process P3. Figure 7 Process P4). Specifically, firstly, as Figure 10 As shown, a metal layer 61a, serving as the base of the lower portion 61, is formed on the insulating layer 5a. A transparent layer TPa, serving as the base of the transparent layer TP, is formed on the metal layer 61a. A light-shielding layer LSa, serving as the base of the light-shielding layer LS, is formed on the transparent layer TPa. A photoresist R11 is formed on the light-shielding layer LSa. The photoresist R11 is patterned as follows: Figure 6 The shape of the light-shielding layer LS is shown.

[0099] In the lower part 61, as shown Figure 4 In the case shown, which includes a first metal layer 611 and a second metal layer 612, metal layer 61a comprises two layers formed from the material of metal layers 611 and 612. In the transparent layer TP, as... Figure 4 In the case shown, which includes a first transparent layer 621 and a second transparent layer 622, the transparent layer TPa comprises two layers formed of the material of the transparent layers 621 and 622.

[0100] Next, as Figure 11 As shown, through etching with resist R11 as a mask, the portion of the light-shielding layer LSa exposed from resist R11 is removed. Thus, as... Figure 11 The light-shielding layer LS is formed as shown. After the light-shielding layer LS is formed, the resist R11 is removed.

[0101] Next, as Figure 12 As shown, a photoresist R12, corresponding to the shape of the partition 6, is formed on the transparent layer TPa and the light-shielding layer LS. Furthermore, through etching using the photoresist R12 as a mask, the portions of the transparent layer TPa and the metal layer 61a exposed from the photoresist R12 are removed. Thus, as... Figure 13 As shown, an upper portion 62 is formed, comprising a transparent layer TP and a light-shielding layer LS. Figure 13 In the example, a portion of the metal layer 61a exposed from the resist R12 remains. As an example, the etching of the transparent layer TPa is a wet etching, while the etching of the metal layer 61a is anisotropic dry etching.

[0102] Next, an isotropic wet etching is performed on the metal layer 61a. For example, this wet etching uses an etching solution containing phosphoric acid, nitric acid, and acetic acid. Through this wet etching, the portion of the metal layer 61a exposed from the resist R12 is removed, such as... Figure 14 The lower portion 61 is formed as shown. During this wet etching, the sides of the lower portion 61 are also etched. Therefore, the width of the lower portion 61 is smaller than the width of the upper portion 62, resulting in a cantilevered partition 6. After wet etching, the resist R12 is removed.

[0103] After the formation of septum 6, as Figure 15 As shown, the insulating layer 5a is patterned to form pixel openings AP1, AP2, and AP3. Figure 7 (Process P5). By forming pixel openings AP1, AP2, and AP3 after forming the partition 6, the lower electrodes LE1, LE2, and LE3 can be protected from etching during the formation of the partition 6.

[0104] After process P5, such as Figure 16 As shown, a first organic layer OR1 that contacts the first lower electrode LE1 through the first pixel opening AP1 is sequentially formed by vapor deposition; a first upper electrode UE1 covering the first organic layer OR1; a first capping layer CP1 covering the first upper electrode UE1; and a first sealing layer SE1 covering the first capping layer CP1. Figure 7 (Process P6). The first organic layer OR1, the first upper electrode UE1, the first capping layer CP1 and the first sealing layer SE1 are formed at least for the entire display area DA, and are disposed not only in the first sub-pixel SP1, but also in the second sub-pixel SP2 and the third sub-pixel SP3.

[0105] After process P6, the first display element DE1 is formed by patterning the first organic layer OR1, the first upper electrode UE1, the first capping layer CP1, and the first sealing layer SE1. Figure 7 Process P7).

[0106] Specifically, firstly, as Figure 17 As shown, a positive first resist R21 is formed (coated) to cover the first sealing layer SE1. The first resist R21 fills the voids V formed below the first end E1 and the second end E2 of each partition 6.

[0107] Next, the portion of the first resist R21 that overlaps with the lower electrodes LE2 and LE3 in the third direction Z, and the portion that overlaps with the second end E2 of each partition 6 in the third direction Z, excluding the first sub-pixel SP1 and the first end E1 of the surrounding partition 6, are exposed. The light EX1 used for this exposure includes at least one of, for example, light with a wavelength of 436 nm (g line) and light with a wavelength of 405 nm (h line).

[0108] The transparent layer TP has good light transmittance to the aforementioned g-line and h-line. Therefore, the first resist R21, which enters the gap V below the second end E2, is also irradiated by light EX1.

[0109] After exposure of the first photoresist R21, the first photoresist R21 is developed. That is, by exposing the first photoresist R21 to the developer, it is developed as shown in the image. Figure 18 As shown, the portion of the first resist R21 irradiated by light EX1 is removed. The first resist R21 that enters the gap V below the second end E2 is also removed in this process.

[0110] After development of the first resist R21, a first etching is performed using the first resist R21 as a mask, thereby achieving... Figure 19 As shown, portions of the first organic layer OR1, the first upper electrode UE1, the first capping layer CP1, and the first sealing layer SE1 exposed from the first resist R21 are removed. For example, the first etching includes dry etching of the first sealing layer SE1, wet etching or ashing of the first capping layer CP1, wet etching of the first upper electrode UE1, and ashing of the first organic layer OR1. In the dry etching of the first sealing layer SE1, the first capping layer CP1 and the first organic layer OR1 function as etching barriers.

[0111] Then, as Figure 20 As shown, by removing the first resist R21, a first display element DE1 comprising a first organic layer OR1, a first upper electrode UE1, a first capping layer CP1, and a first sealing layer SE1 is completed.

[0112] After process P7, such as Figure 21 As shown, a second organic layer OR2, which contacts the second lower electrode LE2 through the second pixel opening AP2, is sequentially formed by vapor deposition; a second upper electrode UE2 covering the second organic layer OR2; a second capping layer CP2 covering the second upper electrode UE2; and a second sealing layer SE2 covering the second capping layer CP2. Figure 7 (Process P8). The second organic layer OR2, the second upper electrode UE2, the second capping layer CP2 and the second sealing layer SE2 are formed at least in the entire display area DA, and are disposed not only in the second sub-pixel SP2, but also in the first sub-pixel SP1 and the third sub-pixel SP3.

[0113] exist Figure 21 In the example, gaps V that are not filled by sealing layers SE1, SE2, etc. are formed below the first end E1 and the second end E2 of each partition 6.

[0114] After process P8, the second display element DE2 is formed by patterning the second organic layer OR2, the second upper electrode UE2, the second capping layer CP2, and the second sealing layer SE2. Figure 7 Process P9).

[0115] Specifically, firstly, as Figure 22 As shown, a positive second resist R22 is formed (coated) to cover the second sealing layer SE2, etc. The second resist R22 fills the gap V below the first end E1 and the second end E2 of each partition 6.

[0116] Next, the portion of the second resist R22 that overlaps with the first display element DE1 in the third direction Z, the portion that overlaps with the third lower electrode LE3 in the third direction Z, the portion that overlaps with the partition 6 between sub-pixels SP1 and SP3 in the third direction Z, and the portion that overlaps with the first end E1 of the partition 6 between sub-pixels SP1 and SP2 in the third direction Z, excluding the second sub-pixel SP2 and the second end E2 of the surrounding partition 6, is exposed. The light EX2 used for this exposure, like the light EX1 described above, includes at least one of, for example, g lines and h lines.

[0117] The second resist R22, which enters the gap V located below the second end E2 of the partition 6 surrounding the third sub-pixel SP3, is also illuminated by light EX2. On the other hand, light EX2 is blocked by the light-shielding layer LS. Therefore, the second resist R22, which enters the gap V located below the first end E1 of the light-shielding layer LS, is almost not illuminated by light EX2.

[0118] After the second resist R22 is exposed, the second resist R22 is developed. That is, by exposing the second resist R22 to the developer, it is developed as shown in the image. Figure 23 As shown, the portion of the second resist R22 irradiated by light EX2 is removed. The second resist R22 that enters the gap V located below the second end E2 of the partition 6 surrounding the third sub-pixel SP3 is also removed in this process. On the other hand, the second resist R22 that enters the gap V located below the first end E1 of each partition 6 remains unremoved by the developer. Hereinafter, the second resist R22 remaining in the gap V will be referred to as residual portion R22a.

[0119] After development with the second resist R22, a second etching is performed using the second resist R22 as a mask, as follows: Figure 24 As shown, portions of the second organic layer OR2, the second upper electrode UE2, the second capping layer CP2, and the second sealing layer SE2 exposed from the second resist R22 are removed. Residual portions 22a also remain during the second etching. For example, the second etching includes dry etching of the second sealing layer SE2, wet etching or ashing of the second capping layer CP2, wet etching of the second upper electrode UE2, and ashing of the second organic layer OR2. In the dry etching of the second sealing layer SE2, the second capping layer CP2 and the second organic layer OR2 function as etching barriers.

[0120] Then, as Figure 25As shown, by removing the second resist R22 and the residual portion R22a, a second display element DE2 comprising a second organic layer OR2, a second upper electrode UE2, a second capping layer CP2 and a second sealing layer SE2 is completed.

[0121] The third display element DE is also formed using the same steps as the first display element DE1 and the second display element DE2. That is, by vapor deposition, a third organic layer OR3 that contacts the third lower electrode LE3 through the third pixel opening AP3, a third upper electrode UE3 covering the third organic layer OR3, a third capping layer CP3 covering the third upper electrode UE3, and a third sealing layer SE3 covering the third capping layer CP3 are sequentially formed. Figure 7 Process P10).

[0122] Furthermore, through the same patterning as processes P7 and P9, thus achieving... Figure 26 As shown, a third display element DE3 is formed in the third sub-pixel SP3, comprising a third organic layer OR3, a third upper electrode UE3, a third capping layer CP3, and a third sealing layer SE3. Figure 7 The patterning process includes forming a positive third resist that integrally covers the third sealing layer SE3, exposing and developing the third resist, and a third etching that uses the third resist as a mask. For example, the exposure of the third resist uses light that includes g-lines and h-lines, similar to light EX1 and EX2. After the development of the third resist, similar to the aforementioned residual portion R22a, a residual portion of the third resist may be generated below the first end E1.

[0123] After forming display elements DE1, DE2, and DE3, they are formed sequentially. Figure 3 The resin layer 13, sealing layer 14, and resin layer 15 shown complete the display device DSP (DSP). Figure 7 Process P12).

[0124] In the above embodiment, the upper portion 62 of the partition 6 adjacent to the first sub-pixel SP1 has a light-shielding first end E1 and a light-transmitting second end E2. With this configuration, when using... Figures 7 to 26 The manufacturing method illustrated herein can improve the reliability of the display device DSP during the manufacturing process.

[0125] That is, in Figure 17When the first resist R21 is exposed, assuming that the first resist R21 entering the gap V below the second end E2 is not sufficiently irradiated by light EX1, even after development of the first resist R21, residual portions of the first resist R21 will be generated in the gap V. If such residual portions are generated, in the subsequent first etching, the portions covered by these residual portions in the first sealing layer SE1, the first organic layer OR1, the first upper electrode UE1, and the first capping layer CP1 will not be removed and may hinder the formation of display elements DE2 and DE3. For example, if the residual first sealing layer SE1, etc., creates areas where the upper electrodes UE2 and UE3 do not contact the lower part 61 of the partition 6, good conductivity between the upper electrodes UE2 and UE3 and the lower part 61 cannot be ensured.

[0126] In contrast, if the second end E2 has good light transmittance to light EX1, as in this embodiment, the first resist R21 entering the gap V below the second end E2 is also irradiated by light EX1. Therefore, the formation of residual portions of the first resist R21 in the gap V can be suppressed. As a result, a highly reliable display device DSP with a well-shaped second display element DE2 and a third display element DE3 can be manufactured.

[0127] On the other hand, assuming that the upper part 62 is entirely translucent, then in such a case... Figure 22 When the second resist R22 shown is exposed, the second resist R22 that enters the gap V below the first end E1 is also irradiated by light EX2. In this case, no... Figure 23 The residual portion R22a is shown. Near the gap V below the first end E1, the first sealing layer SE1 and the second sealing layer SE2 are thin, and the second capping layer CP2 and the second organic layer OR2, which function as etch barriers for dry etching of the second sealing layer SE2, are not sufficiently formed. Therefore, during the second and third etching processes, the first sealing layer SE1 and the first display element DE1 below the first end E1 may be damaged.

[0128] In contrast, when the first end E1 is light-shielding as in this embodiment, a residual portion R22a is generated in the gap V below the first end E1. This residual portion 22a protects the first sealing layer SE1 and the first display element DE1 below the first end E1 from the effects of the second and third etching processes. As a result, a highly reliable display device DSP with a well-shaped first display element DE1 can be manufactured.

[0129] All display devices and manufacturing methods that can be appropriately designed, modified, and implemented by those skilled in the art based on the display devices and manufacturing methods described above as embodiments of the present invention, as long as they contain the essence of the present invention, are also within the scope of the present invention.

[0130] Within the scope of the present invention, various modifications that can be conceived by those skilled in the art should also be considered within the scope of the present invention. For example, any additions, deletions, design changes, or additions, omissions, or changes in steps or conditions made by those skilled in the art to the above embodiments, provided that the essence of the present invention is present, are also not included within the scope of the present invention.

[0131] Furthermore, other effects resulting from the methods described in the above embodiments, effects that are explicit according to the description in this specification, or effects that can be reasonably conceived by those skilled in the art should naturally be considered as benefits of this invention.

Claims

1. A display device, comprising: The first display element includes a first lower electrode, a first upper electrode, and a first organic layer that emits light in response to a voltage between the first lower electrode and the first upper electrode; A second display element includes a second lower electrode, a second upper electrode, and a second organic layer that emits light corresponding to the voltage between the second lower electrode and the second upper electrode; and A partition is disposed between the first display element and the second display element. The partition wall has: The lower part has a first side surface on the side of the first display element and a second side surface on the side of the second display element; and The upper part has a first end protruding from the first side and a second end protruding from the second side. The first end is light-shielding, and the second end is light-transmitting.

2. The display device according to claim 1, wherein, The upper part has: A transparent layer extending from the first end to the second end; and A light-shielding layer is disposed at the first end.

3. The display device according to claim 2, wherein, The light-shielding layer is disposed on top of the transparent layer.

4. The display device according to claim 2, wherein, The light-shielding layer is made of titanium.

5. The display device according to claim 2, wherein, The light-shielding layer has a transmittance of less than 10% for light with a wavelength of 436 nm or light with a wavelength of 405 nm.

6. The display device according to claim 2, wherein, The partition wall surrounds the first display element and the second display element. The light-shielding layer surrounds the first display element.

7. The display device according to claim 2, wherein, The transparent layer comprises: The first transparent layer is formed of silicon oxide; and The second transparent layer is formed of conductive oxide.

8. The display device according to claim 2, wherein, The transparent layer has a single-layer structure of silicon oxide.

9. The display device according to claim 1, wherein, The lower part is conductive. The first upper electrode is in contact with the first side surface. The second upper electrode is in contact with the second side surface.

10. The display device according to claim 1, further comprising: a first sealing layer formed of an inorganic material, covering the first display element, the first side surface, and the first end; and A second sealing layer, formed of inorganic material, covers the second display element, the second side surface, and the second end. The ends of the first sealing layer and the second sealing layer are located above the upper part and are separated from each other.

11. A method for manufacturing a display device, comprising: Forming the first lower electrode and the second lower electrode; A partition wall is formed having a lower part and an upper part, wherein the lower part has a first side surface on the side of the first lower electrode and a second side surface on the side of the second lower electrode, and the upper part has a light-shielding first end protruding from the first side surface and a light-transmitting second end protruding from the second side surface; On the first lower electrode, the second lower electrode, and the partition wall, a first organic layer including a light-emitting layer, a first upper electrode covering the first organic layer, a first sealing layer made of inorganic material, and a first resist covering the first sealing layer are sequentially formed. The portion of the first photoresist that overlaps with the second lower electrode and the second end is exposed. The exposed portion of the first photoresist is removed by exposing it to the developer. A first display element comprising the first lower electrode, the first organic layer, and the first upper electrode is formed by removing the portions of the first organic layer, the first upper electrode, and the first sealing layer exposed from the first photoresist using a first etching process.

12. The method of manufacturing a display device according to claim 11, further comprising: After the first display element is formed, a second organic layer including a light-emitting layer, a second upper electrode covering the second organic layer, a second sealing layer made of inorganic material, and a second resist covering the second sealing layer are sequentially formed on the first display element, the second lower electrode, and the partition wall. The portion of the second photoresist that overlaps with the first display element and the first end is exposed. The exposed portion of the second photoresist is removed by exposing it to the developer. A second display element comprising the second lower electrode, the second organic layer, and the second upper electrode is formed by removing the portions of the second organic layer, the second upper electrode, and the second sealing layer that are exposed from the second photoresist using a second etching process.

13. The method of manufacturing a display device according to claim 12, wherein, A portion of the second resist is located below the first end. The light exposing the second photoresist to the light is blocked by the first end. After the second resist is exposed to the developer, a portion of the second resist located below the first end remains during the second etching.

14. The method of manufacturing a display device according to claim 12, wherein, The upper part has: A transparent layer extending from the first end to the second end; and A light-shielding layer is disposed at the first end.

15. The method of manufacturing a display device according to claim 14, wherein, The light-shielding layer has a transmittance of less than 10% to the light used in the exposure of the second photoresist.

16. The method of manufacturing a display device according to claim 15, wherein, The exposure of the second photoresist uses light with a wavelength of 436 nm or light with a wavelength of 405 nm.

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