A processing method and device of a resource waiting queue and related equipment
By modifying the bit value of the atomic lock when it is acquired in the resource waiting queue to wake up other tasks, the problem of low system resource utilization caused by the resource waiting queue is solved, and more efficient resource utilization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA MOBILE M2M
- Filing Date
- 2022-03-21
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, once a resource waiting queue is locked, resources that have not yet accessed the resource waiting queue need to wait for the lock to be released, resulting in low resource utilization of the system.
When the first resource in a task context or interrupt context is released, acquire the atomic lock of the resource waiting queue, and wake up tasks in other resource waiting queues by modifying the bit value of the atomic lock, thereby reducing busy waiting and improving resource utilization.
By modifying the bit values of the atomic lock, busy waiting for resources was reduced, the system's resource utilization was improved, and the execution efficiency of tasks was optimized.
Smart Images
Figure CN116820696B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of operating system technology, and more specifically to a method, apparatus, and related equipment for processing resource waiting queues. Background Technology
[0002] In operating systems, there are situations where multiple tasks or interrupts need to access a resource waiting queue simultaneously. Locking the resource waiting queue is necessary to prevent concurrent access by multiple tasks or interrupts. However, in related technologies, after the resource waiting queue is locked, resources not yet accessed must wait for the lock to be released, resulting in busy waiting and low system resource utilization.
[0003] It is evident that existing technologies suffer from low system resource utilization. Summary of the Invention
[0004] This invention provides a method, apparatus, and related equipment for processing resource waiting queues to solve the problem of low resource utilization in existing systems.
[0005] To solve the above problems, the present invention is implemented as follows:
[0006] In a first aspect, embodiments of the present invention provide a method for processing a resource waiting queue, the method comprising:
[0007] When the first resource in a task context or interrupt context is released, the atomic lock of the first resource waiting queue is acquired for the first time, and the first resource corresponds to the first resource waiting queue.
[0008] If the atomic lock has been acquired by the second resource, a first set value is written to the first bit of the atomic lock. The value of the first bit is used to indicate that the task to be executed by the first resource needs to be performed using the second resource. The second resource is a resource other than the first resource.
[0009] After the setting value is written, the first resource is used to wake up the task in another resource waiting queue, which is a resource waiting queue other than the first resource waiting queue.
[0010] If the atomic lock is not acquired by the second resource, a second setting value is written to the second bit of the atomic lock, where the second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource.
[0011] Pop the task at the head of the first resource waiting queue and execute the task;
[0012] Acquire the atomic lock from the first resource waiting queue for the second time;
[0013] Based on the value of the first bit, pop the task at the head of the first resource waiting queue and execute the task;
[0014] Release the atomic lock from the first resource waiting queue.
[0015] Secondly, embodiments of the present invention also provide a processing apparatus for a resource waiting queue, comprising:
[0016] The first acquisition module is used to acquire the atomic lock of the first resource waiting queue for the first time when the first resource in the task context or interrupt context is released, wherein the first resource corresponds to the first resource waiting queue.
[0017] The first processing module is configured to write a first set value to the first bit of the atomic lock when the atomic lock has been acquired by the second resource. The value of the first bit is used to indicate that the second resource needs to execute the task to be executed by the first resource. The second resource is a resource other than the first resource.
[0018] The second processing module is used to wake up tasks in other resource waiting queues using the first resource after the written setting value is achieved, wherein the other resource waiting queue is a resource waiting queue other than the first resource waiting queue.
[0019] The third processing module is used to write a second setting value to the second bit of the atomic lock when the atomic lock is not acquired by the second resource. The second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource.
[0020] The fourth processing module is used to pop the task at the head of the first resource waiting queue and execute the task;
[0021] The second acquisition module is used to acquire the atomic lock of the first resource waiting queue for the second time;
[0022] The fifth processing module is used to pop the task located at the head of the first resource waiting queue based on the value of the first bit, and execute the task;
[0023] The first release module is used to release the atomic lock of the first resource waiting queue.
[0024] Thirdly, embodiments of the present invention also provide a processing apparatus for a resource waiting queue, including a transceiver and a processor.
[0025] The processor is configured to acquire an atomic lock of a first resource waiting queue for the first time when the first resource in a task context or interrupt context is released, wherein the first resource corresponds to the first resource waiting queue.
[0026] The processor is further configured to, when the atomic lock has been acquired by the second resource, write a first set value to the first bit of the atomic lock, wherein the value of the first bit is used to indicate that the second resource needs to execute the task to be executed by the first resource, and the second resource is a resource other than the first resource;
[0027] The processor is further configured to, after writing the set value, use the first resource to wake up tasks in other resource waiting queues, wherein the other resource waiting queue is a resource waiting queue other than the first resource waiting queue;
[0028] The processor is further configured to write a second preset value to a second bit of the atomic lock when the atomic lock is not acquired by the second resource, wherein the second bit is the second preset value used to indicate that the atomic lock is acquired by the first resource;
[0029] The processor is further configured to pop the task at the head of the first resource waiting queue from the first resource waiting queue and execute the task;
[0030] The processor is also configured to acquire the atomic lock of the first resource waiting queue for the second time;
[0031] The processor is further configured to pop the task at the head of the first resource waiting queue based on the value of the first bit, and execute the task;
[0032] The processor is also configured to release the atomic lock of the first resource waiting queue.
[0033] Fourthly, embodiments of the present invention also provide a communication device, including: a transceiver, a memory, a processor, and a program stored in the memory and executable on the processor; the processor is used to read the program in the memory to implement the steps in the resource waiting queue processing method as described in the first aspect above.
[0034] Fifthly, embodiments of the present invention also provide a readable storage medium for storing a program, characterized in that, when the program is executed by a processor, it implements the steps of the resource waiting queue processing method described in the first aspect above.
[0035] In this embodiment of the invention, when the atomic lock of the first resource waiting queue is acquired by the second resource, the first bit of the atomic lock is modified, the first resource does not busy wait, and the corresponding operation on the first resource waiting queue is implemented by the second resource, thereby improving the resource utilization of the system. Attached Figure Description
[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a flowchart of a resource waiting queue processing method provided by an embodiment of the present invention;
[0038] Figure 2 This is a schematic diagram of the head task of the pop-up resource waiting queue provided in an embodiment of the present invention;
[0039] Figure 3 This is a schematic diagram of inserting a task into a resource waiting queue according to an embodiment of the present invention;
[0040] Figure 4 This is a schematic diagram illustrating the removal of a task from the resource waiting queue according to an embodiment of the present invention;
[0041] Figure 5 This is a schematic diagram of releasing the atomic lock provided in an embodiment of the present invention;
[0042] Figure 6 This is a schematic diagram of the structure of a resource waiting queue processing device provided in an embodiment of the present invention;
[0043] Figure 7 This is a schematic diagram of the structure of a communication device provided in an embodiment of the present invention. Detailed Implementation
[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, many other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of the present invention.
[0045] Please see Figure 1 , Figure 1 This is a flowchart of a resource waiting queue processing method provided by an embodiment of the present invention, as shown below. Figure 1 As shown, the methods for handling resource waiting queues include:
[0046] Step 101: If the first resource in the task context or interrupt context is released, acquire the atomic lock of the first resource waiting queue for the first time. The first resource corresponds to the first resource waiting queue.
[0047] A task context is essential data for a task; it consists of programs, functions, or code. This data allows the task to be interrupted, and execution can resume after the interruption ends. An interrupted task is a task that executes when a task is interrupted, typically triggered by an external device or a system-defined time point. It interrupts the task context, enters the interrupted task routine, and resumes the task context after the interrupted task routine completes.
[0048] In an operating system, multiple tasks or interrupts may access processor resources in parallel. When resources are insufficient, tasks needing to access resources are blocked and suspended in a resource waiting queue. When the resource is released by another task or terminal, the task in the resource waiting queue is woken up and continues execution. In this embodiment, one resource waiting queue corresponds to one atomic lock. If the atomic lock is acquired, the processor can use the resource to perform corresponding operations on the resource waiting queue; if the atomic lock is not acquired, the processor cannot operate on the resource waiting queue.
[0049] The operations performed on the resource waiting queue include three categories: adding tasks to the resource waiting queue, removing tasks from the resource waiting queue, and popping the head task from the resource waiting queue and executing it. In this implementation, the first resource consists of a task context and an interrupt task. The processor can utilize the first resource to pop the head task from the resource waiting queue and execute it.
[0050] Step 102: If the atomic lock has been acquired by the second resource, write the first setting value to the first bit of the atomic lock. The value of the first bit is used to indicate that the task to be executed by the first resource needs to be executed using the second resource. The second resource is a resource other than the first resource.
[0051] When the atomic lock is acquired by the second resource, it can only be used to process the first resource queue, not the first resource. At this point, a first preset value is written to the first bit of the atomic lock, redirecting the task that would otherwise require the first resource to be executed using the second resource. This eliminates the need for the first resource to wait for the atomic lock to be released by the second resource before acquiring it again.
[0052] For example, suppose the first setting is 1, and the initial value of the first bit is 0. If the atomic lock is acquired by the second resource, write 1 to the value of the first bit. If the atomic lock is attempted to be acquired by N resources, but all of them are acquired by the second resource, repeat the writing to the first bit until the value of the first bit is N.
[0053] Step 103: After writing the set value, use the first resource to wake up the tasks in other resource waiting queues. Other resource waiting queues are resource waiting queues other than the first resource waiting queue.
[0054] After the first resource is written with the set value up to the first bit, it no longer needs to be used to execute tasks in the original first resource waiting queue. Instead, it can be used to execute tasks in other resource waiting queues, effectively reducing busy waiting for resources.
[0055] Step 104: If the atomic lock is not acquired by the second resource, write the second setting value to the second bit of the atomic lock. The second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource.
[0056] When an atomic lock can be acquired, the first resource can be used to execute tasks in the first resource waiting queue. Specifically, writing a second setting value to the second bit of the atomic lock allows the second resource to determine, through the second bit of the atomic lock, that the atomic lock has already been acquired by another resource, i.e., the first resource, when the second resource needs to acquire the atomic lock of the first resource waiting queue. At this point, the first setting value is written to the first bit of the atomic lock. After the writing is completed, the second resource can be used to wake up tasks in other resource queues.
[0057] For example, suppose the value of the second bit is 0 when the atomic lock is not acquired by a resource, and the value of the second bit is 1 after the atomic lock is acquired. After acquiring the atomic lock, if the second bit is 0, the atomic lock is not acquired by a resource, and the value of the second bit is written to 1. At this time, the atomic lock is acquired, and operations can be performed on tasks in the waiting queue of the first resource. If the second bit is 1, the atomic lock is acquired by the second resource, and a first set value is written to the first bit. The second resource that acquired the atomic lock then performs the corresponding wake-up operation based on the first bit.
[0058] Step 105: Pop the task at the head of the first resource waiting queue and execute the task;
[0059] Since the first resource is released by the task context or interrupt context, it can be used to wake up tasks in the first resource waiting queue, allowing those tasks to continue execution. Tasks in the first resource waiting queue are arranged by priority; when waking up a task using the first resource, the task at the head of the queue is woken up according to its priority.
[0060] Step 106: Acquire the atomic lock of the first resource waiting queue for the second time;
[0061] After waking up and executing the task using the first resource, it is necessary to determine whether other resources attempted to acquire the atomic lock during the task execution. If other resources attempted to acquire the atomic lock but failed, a first preset value will be written to the first bit of the atomic lock. At this point, by acquiring the atomic lock, the number of times other resources attempted to acquire the atomic lock can be effectively determined.
[0062] Step 107: Based on the value of the first bit, pop the task at the head of the first resource waiting queue and execute the task;
[0063] The value of the first bit represents the number of times other resources attempt to access the first resource waiting queue. Based on the value of the first bit, the task at the head of the first resource waiting queue is popped from the queue using the first resource instead of using other resources to pop the task at the head of the queue, thus reducing the busy waiting of other resources.
[0064] For example, when acquiring an atomic lock, the first bit is initially set to 0. If other resources fail to acquire the atomic lock during the time when the first resource acquires it, a first set value M is written to the first bit. At this time, the value of the first bit when acquiring the atomic lock is M, and the task at the head of the queue is popped from the waiting queue of the first resource based on M.
[0065] Step 108: Release the atomic lock of the first resource waiting queue.
[0066] After completing the tasks that need to be processed in the first resource waiting queue using the first resource, release the atomic lock. The first resource can then be used to wake up tasks in other resource waiting queues.
[0067] In this embodiment, when the atomic lock of the first resource waiting queue is acquired by the second resource, the first bit of the atomic lock is modified, the first resource does not busy wait, and the corresponding operation on the first resource waiting queue is implemented by the second resource, thereby improving the resource utilization of the system.
[0068] In one embodiment, popping the task at the head of the first resource waiting queue based on the value of the first bit includes:
[0069] Record the first bit of the atomic lock acquired for the first time as the first variable;
[0070] Record the first bit of the atomic lock acquired the second time as the second variable;
[0071] The task at the head of the first resource waiting queue is popped out, and the number of times it is popped out is the ratio of the difference between the second variable and the first variable to the first set value.
[0072] In this embodiment, during the process of the first resource acquiring the atomic lock, if other resources attempt to acquire the atomic lock, a first preset value will be written into the first bit of the atomic lock, making the first bit acquired in the first acquisition different from the first bit acquired in the second acquisition. For example, if the first variable is 0, the second variable is 3, and the first preset value is 1, then the difference between the second variable and the first variable is 3. It can be considered that during the time the first resource acquires the atomic lock, other resources attempted to acquire the atomic lock three times, requiring the task at the head of the queue to be popped three times from the waiting queue of the first resource. Alternatively, if the first variable is 0 and the second variable is 0, then the difference between the second variable and the first variable is 0. It can be considered that during the time the first resource acquires the atomic lock, no other resources acquired the atomic lock, and the first resource does not need to pop the task at the head of the queue again, and can directly release the atomic lock.
[0073] In one embodiment, if releasing the atomic lock of the first resource waiting queue fails, the method includes:
[0074] If there are tasks in the first resource waiting queue, acquire the atomic lock for the third time;
[0075] Record the first bit of the atomic lock acquired for the third time as the third variable;
[0076] The task at the head of the first resource waiting queue is popped out, and the number of times it is popped out is the ratio of the difference between the third variable and the second variable to the first set value.
[0077] Release the atomic lock from the first resource waiting queue;
[0078] If there are no tasks in the resource waiting queue, forcibly release the atomic lock of the first resource waiting queue.
[0079] In this embodiment, obtaining the value of the atomic lock and writing a value to the first or second bit of the atomic lock both require processor-specific load / store instructions with bus monitoring capabilities. These instructions can distinguish between interrupt service routines and non-interrupt service routines; by searching for specific instructions in the interrupt server, the address of the atomic lock can be analyzed. Furthermore, if other instructions of this type exist during the writing process to the first or second bit of the atomic lock, the write operation will fail, requiring a resend of the instruction.
[0080] In this embodiment, the release of the atomic lock of the first resource waiting queue fails, that is, the writing of the first bit of the atomic lock of the first resource waiting queue fails. At this time, other instructions of this type have been executed, that is, the first bit of the source resource has changed again, and it is necessary to operate on the changed first bit again.
[0081] For example, if the value of the second variable is 5 and the value of the third variable is 8, then the task at the head of the first resource waiting queue is popped from the queue. The number of pops is the ratio of the difference between the third and second variables to the first set value, meaning the task at the head of the queue needs to be popped 3 times. After the task is completed, the atomic lock of the first resource waiting queue is released again. If releasing the atomic lock of the first resource waiting queue fails again, the above steps are repeated.
[0082] Additionally, if releasing the atomic lock of the first resource waiting queue fails, but there are no tasks in the first resource waiting queue, then tasks cannot be popped. However, load / store instructions with bus listening functionality cannot modify the first bit of the atomic lock. It is necessary to modify the first bit to its initial value using ordinary instructions to forcibly release the atomic lock of the first resource waiting queue.
[0083] In one embodiment, before acquiring the atomic lock of the first resource waiting queue for the first time, the method further includes:
[0084] When the processor corresponding to the first resource is multi-core, multiple interrupt tasks are disabled;
[0085] If the processor corresponding to the first resource is a single core, disable the timing interrupt task. The timing interrupt task is one of multiple interrupt tasks.
[0086] After releasing the atomic lock on the first resource waiting queue, the method also includes:
[0087] Open multiple interrupt tasks.
[0088] In this embodiment, when the processor is a single core, only the timing interrupt task needs to be disabled. The timing interrupt task is the lowest priority interrupt task. During the process of popping the first task from the first resource waiting queue using the first resource, the high-priority interrupt tasks can still be responded to, avoiding the abnormal problem caused by the high-priority interrupt tasks not being responded to.
[0089] In one embodiment, the method further includes:
[0090] If the first resource cannot be acquired in the task context, repeatedly acquire the atomic lock of the first resource waiting queue until the atomic lock is acquired;
[0091] Insert tasks into the first resource waiting queue according to their priority;
[0092] Release the atomic lock on the first resource waiting queue.
[0093] In this embodiment, when inserting a task into the first resource waiting queue, it is also necessary to acquire the atomic lock of the first resource waiting queue before performing operations on it. In this embodiment, because it is necessary to insert a task into the first resource waiting queue, it is difficult for other resources to achieve the effect of inserting a task into the first resource waiting queue if they have acquired the atomic lock; therefore, the first resource still needs to acquire the atomic lock of the first resource waiting queue. After the first resource acquires the atomic lock, it then inserts the task into the first resource waiting queue according to the task's priority.
[0094] Additionally, if a task has a timeout parameter, the task will also be inserted into the timer queue.
[0095] In one embodiment, the method further includes repeatedly acquiring the atomic lock of the first resource waiting queue until the atomic lock is acquired:
[0096] When the processor corresponding to the first resource is multi-core, multiple interrupt tasks are disabled;
[0097] If the processor corresponding to the first resource is a single core, disable the timing interrupt task. The timing interrupt task is one of multiple interrupt tasks.
[0098] After releasing the atomic lock on the first resource waiting queue, the method also includes:
[0099] Open multiple interrupt tasks.
[0100] In this embodiment, when the processor is single-core, only the timing interrupt task needs to be disabled, allowing high-priority interrupts to be responded to. In contrast, existing technologies, even with a single-core processor, require disabling multiple interrupt tasks, preventing high-priority interrupts from being responded to during task insertion into the first resource waiting queue, resulting in significant processing delays. This embodiment effectively reduces interrupt task latency and improves system real-time performance.
[0101] In one embodiment, the method further includes:
[0102] In the context of a timed-out task in the first resource queue within the timed interrupt context, repeatedly acquire the atomic lock of the first resource waiting queue until the atomic lock is acquired.
[0103] Remove timed-out tasks from the first resource waiting queue;
[0104] Release the atomic lock on the first resource waiting queue.
[0105] In this embodiment, some tasks have timeout parameters. While inserting a task into the resource waiting queue, it is also simultaneously inserted into a timing queue to monitor whether the task has timed out. If a timed-out task exists in the first resource queue, it needs to be removed from the resource waiting queue to prevent the timed-out task from being executed later.
[0106] In one embodiment, the method further includes repeatedly acquiring the atomic lock of the first resource waiting queue until the atomic lock is acquired:
[0107] If the processor corresponding to the first resource queue is multi-core, disable multiple interrupt tasks;
[0108] If the processor corresponding to the first resource queue is a single core, interrupt tasks should not be disabled;
[0109] After releasing the atomic lock on the first resource waiting queue, the method also includes:
[0110] Open multiple interrupt tasks.
[0111] In this embodiment, when the processor is a single core, interrupt tasks are not disabled, interrupts can be responded to, latency can be reduced, and the real-time performance of the system can be improved.
[0112] In this embodiment, popping a task from the head of the first resource waiting queue, inserting a task into the first resource waiting queue, and removing a task from the first resource waiting queue all require steps such as acquiring an atomic lock, performing the corresponding operation, and releasing the atomic lock. The following design can be made for different types of operations.
[0113] For example, popping a task from the head of the first resource waiting queue can be designed as follows: Figure 2 As shown. In Figure 2 The first bit is initially set to 0, and the first set value is 1 each time it is written; the second bit is 0 when the atomic lock is not acquired, and 1 when it is acquired. Since there is an operation that does not require re-execution of the pop queue head task, step 107 is designed into the atomic lock unlocking process.
[0114] In addition, the design for inserting tasks into the first resource waiting queue is as follows: Figure 3 As shown, the task removal from the first resource waiting queue is designed as follows: Figure 4 As shown, the release atomic lock is designed as follows: Figure 5 As shown. Operations on the first bit are only required when a task is popped from the head of the first resource waiting queue. Operations on the first bit are not required when inserting or removing a task from the first resource waiting queue. Therefore, in... Figure 5During the process of releasing the atomic lock, a task popped from the head of the first resource waiting queue may be executed multiple times, while inserting a task into the first resource waiting queue and removing a task from the first resource waiting queue will directly release the atomic lock.
[0115] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a resource waiting queue processing device provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the resource waiting queue processing device 600 includes:
[0116] The first acquisition module 601 is used to acquire the atomic lock of the first resource waiting queue for the first time when the first resource in the task context or interrupt context is released, wherein the first resource corresponds to the first resource waiting queue.
[0117] The first processing module 602 is used to write a first set value to the first bit of the atomic lock when the atomic lock has been acquired by the second resource. The value of the first bit is used to indicate that the second resource needs to execute the task to be executed by the first resource. The second resource is a resource other than the first resource.
[0118] The second processing module 603 is used to wake up tasks in other resource waiting queues using the first resource after the setting value is written, wherein the other resource waiting queue is a resource waiting queue other than the first resource waiting queue.
[0119] The third processing module 604 is used to write a second setting value to the second bit of the atomic lock when the atomic lock is not acquired by the second resource. The second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource.
[0120] The fourth processing module 605 is used to pop the task located at the head of the first resource waiting queue and execute the task;
[0121] The second acquisition module 606 is used to acquire the atomic lock of the first resource waiting queue for the second time;
[0122] The fifth processing module 607 is used to pop the task located at the head of the first resource waiting queue based on the value of the first bit, and execute the task;
[0123] The first release module 608 is used to release the atomic lock of the first resource waiting queue.
[0124] In one embodiment, the fifth processing module includes:
[0125] The first recording unit is used to record the first bit of the atomic lock acquired for the first time as the first variable;
[0126] The second recording unit is used to record the first bit of the atomic lock acquired the second time as the second variable;
[0127] The first processing unit is configured to pop the task at the head of the first resource waiting queue, wherein the number of times the task is popped is the ratio of the difference between the second variable and the first variable to the first set value.
[0128] In one embodiment, in the event that the first release module fails to execute, the apparatus includes:
[0129] The third acquisition module is used to acquire the atomic lock for the third time if there is a task in the first resource waiting queue;
[0130] The first recording module is used to record the first bit of the atomic lock obtained for the third time as the third variable;
[0131] The sixth processing module is used to pop the task at the head of the first resource waiting queue, wherein the number of times the task is popped is the ratio of the difference between the third variable and the second variable to the first set value.
[0132] The second release module is used to release the atomic lock of the first resource waiting queue;
[0133] The third release module is used to forcibly release the atomic lock of the first resource waiting queue when there are no tasks in the resource waiting queue.
[0134] In one embodiment, prior to the first acquisition module, the apparatus further includes:
[0135] The first shutdown module is used to disable multiple interrupt tasks when the processor corresponding to the first resource is multi-core.
[0136] The second shutdown module is used to shut down the timing interrupt task when the processor corresponding to the first resource is a single core, wherein the timing interrupt task is one of the plurality of interrupt tasks;
[0137] Following the first release module, the device further includes:
[0138] The first opening module is used to open the multiple interrupt tasks.
[0139] In one embodiment, the apparatus further includes:
[0140] The fourth acquisition module is used to repeatedly acquire the atomic lock of the first resource waiting queue until the atomic lock is acquired if the first resource cannot be acquired in the task context.
[0141] The seventh processing module is used to insert the task into the first resource waiting queue according to the task priority;
[0142] The fourth release module is used to release the atomic lock of the first resource waiting queue.
[0143] In one embodiment, prior to the fourth acquisition module, the apparatus further includes:
[0144] The third shutdown module is used to disable multiple interrupt tasks when the processor corresponding to the first resource is multi-core.
[0145] The fourth shutdown module is used to shut down the timing interrupt task when the processor corresponding to the first resource is a single core, wherein the timing interrupt task is one of the plurality of interrupt tasks;
[0146] Following the fourth release module, the device further includes:
[0147] The second opening module is used to open the multiple interrupt tasks.
[0148] In one embodiment, the apparatus further includes:
[0149] The fifth acquisition module is used to repeatedly acquire the atomic lock of the first resource waiting queue until the atomic lock is acquired when there is a timed-out task in the first resource queue in the timed interrupt context.
[0150] The eighth processing module is used to remove the timed-out task from the first resource waiting queue;
[0151] The fifth release module is used to release the atomic lock of the first resource waiting queue.
[0152] In one embodiment, prior to the fifth acquisition module, the apparatus further includes:
[0153] The fifth shutdown module is used to disable multiple interrupt tasks when the processor corresponding to the first resource queue is multi-core.
[0154] The sixth shutdown module is used to ensure that interrupt tasks are not disabled when the processor corresponding to the first resource queue is a single core.
[0155] Following the fifth release module, the device further includes:
[0156] The third opening module is used to open the multiple interrupt tasks.
[0157] The processing device for the resource waiting queue is capable of implementing each process of the above-described processing method applied to the resource waiting queue. The technical features are one-to-one and can achieve the same technical effect. To avoid repetition, it will not be described again here.
[0158] This invention also provides a resource waiting queue processing apparatus, including: a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the steps of the resource waiting queue processing method described above.
[0159] For details, see Figure 7 The present invention also provides a schematic diagram of the structure of a communication device, including a bus 701, a transceiver 702, an antenna 703, a bus interface 704, a processor 705, and a memory 706.
[0160] The processor 705 is configured to acquire an atomic lock of a first resource waiting queue for the first time when the first resource in a task context or interrupt context is released, wherein the first resource corresponds to the first resource waiting queue.
[0161] The processor 705 is further configured to write a first set value to a first bit of the atomic lock when the atomic lock has been acquired by a second resource, wherein the value of the first bit is used to indicate that the second resource needs to execute the task to be executed by the first resource, and the second resource is a resource other than the first resource;
[0162] The processor 705 is further configured to, after writing the set value, use the first resource to wake up a task in another resource waiting queue, wherein the other resource waiting queue is a resource waiting queue other than the first resource waiting queue;
[0163] The processor 705 is further configured to write a second setting value to a second bit of the atomic lock when the atomic lock is not acquired by the second resource, wherein the second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource;
[0164] The processor 705 is further configured to pop the task at the head of the first resource waiting queue from the first resource waiting queue and execute the task;
[0165] The processor 705 is also configured to acquire the atomic lock of the first resource waiting queue for the second time;
[0166] The processor 705 is further configured to pop the task located at the head of the first resource waiting queue based on the value of the first bit, and execute the task;
[0167] The processor 705 is also configured to release the atomic lock of the first resource waiting queue.
[0168] In one embodiment, popping the task at the head of the first resource waiting queue based on the value of the first bit includes:
[0169] The first bit of the atomic lock acquired for the first time is recorded as the first variable;
[0170] The first bit of the atomic lock obtained the second time is recorded as the second variable;
[0171] The task at the head of the first resource waiting queue is popped out, and the number of times it is popped out is the ratio of the difference between the second variable and the first variable to the first set value.
[0172] In one embodiment, if the atomic lock for releasing the first resource waiting queue fails, the method includes:
[0173] If a task exists in the first resource waiting queue, acquire the atomic lock for the third time;
[0174] The first bit of the atomic lock obtained for the third time is recorded as the third variable;
[0175] The task at the head of the first resource waiting queue is popped out, and the number of times it is popped out is the ratio of the difference between the third variable and the second variable to the first set value;
[0176] Release the atomic lock from the first resource waiting queue;
[0177] If there are no tasks in the resource waiting queue, the atomic lock of the first resource waiting queue is forcibly released.
[0178] In one embodiment, prior to the first acquisition of the atomic lock of the first resource waiting queue, the method further includes:
[0179] If the processor corresponding to the first resource is multi-core, multiple interrupt tasks are disabled;
[0180] When the processor corresponding to the first resource is a single core, the timing interrupt task is disabled, and the timing interrupt task is one of the plurality of interrupt tasks;
[0181] After releasing the atomic lock of the first resource waiting queue, the method further includes:
[0182] Open the multiple interrupt tasks.
[0183] In one embodiment, if the first resource cannot be obtained in the task context, the atomic lock of the first resource waiting queue is repeatedly acquired until the atomic lock is acquired.
[0184] The task is inserted into the first resource waiting queue according to its priority;
[0185] Release the atomic lock from the first resource waiting queue.
[0186] In one embodiment, before repeatedly acquiring the atomic lock of the first resource waiting queue until the atomic lock is acquired, the method further includes:
[0187] If the processor corresponding to the first resource is multi-core, multiple interrupt tasks are disabled;
[0188] When the processor corresponding to the first resource is a single core, the timing interrupt task is disabled, and the timing interrupt task is one of the plurality of interrupt tasks;
[0189] After releasing the atomic lock of the first resource waiting queue, the method further includes:
[0190] Open the multiple interrupt tasks.
[0191] In one embodiment, if there is a timed-out task in the first resource queue in the timed interrupt context, the atomic lock of the first resource waiting queue is repeatedly acquired until the atomic lock is acquired.
[0192] Remove the timed-out task from the first resource waiting queue;
[0193] Release the atomic lock from the first resource waiting queue.
[0194] In one embodiment, before repeatedly acquiring the atomic lock of the first resource waiting queue until the atomic lock is acquired, the method further includes:
[0195] If the processor corresponding to the first resource queue is multi-core, disable multiple interrupt tasks;
[0196] If the processor corresponding to the first resource queue is a single core, the interrupt task is not disabled;
[0197] After releasing the atomic lock of the first resource waiting queue, the method further includes:
[0198] Open the multiple interrupt tasks.
[0199] exist Figure 7In this document, a bus architecture (represented by bus 701) is used. Bus 701 can include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 705 and memory represented by memory 706. Bus 701 can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 704 provides an interface between bus 701 and transceiver 702. Transceiver 702 can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 705 is transmitted over a wireless medium via antenna 703, which further receives data and transmits data to processor 705.
[0200] Processor 705 manages bus 701 and general processing, and also provides various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. Memory 706 can be used to store data used by processor 705 during operation.
[0201] Optionally, the processor 705 can be a CPU, ASIC, FPGA, or CPLD.
[0202] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, this computer program implements the various processes of the resource waiting queue processing method embodiments described above, achieving the same technical effects. To avoid repetition, it will not be described again here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.
[0203] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0204] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of the various embodiments of the present invention.
[0205] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.
Claims
1. A method for processing a resource waiting queue, characterized in that, The method includes: When the first resource in a task context or interrupt context is released, the atomic lock of the first resource waiting queue is acquired for the first time, and the first resource corresponds to the first resource waiting queue. If the atomic lock has been acquired by the second resource, a first set value is written to the first bit of the atomic lock. The value of the first bit is used to indicate that the task to be executed by the first resource needs to be performed using the second resource. The second resource is a resource other than the first resource. After the setting value is written, the first resource is used to wake up the task in another resource waiting queue, which is a resource waiting queue other than the first resource waiting queue. If the atomic lock is not acquired by the second resource, a second setting value is written to the second bit of the atomic lock, where the second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource. Pop the task at the head of the first resource waiting queue and execute the task; Acquire the atomic lock from the first resource waiting queue for the second time; Based on the value of the first bit, pop the task at the head of the first resource waiting queue and execute the task; Release the atomic lock from the first resource waiting queue.
2. The method according to claim 1, characterized in that, The step of popping the task at the head of the first resource waiting queue based on the value of the first bit includes: The first bit of the atomic lock acquired for the first time is recorded as the first variable; The first bit of the atomic lock obtained the second time is recorded as the second variable; The task at the head of the first resource waiting queue is popped out, and the number of times it is popped out is the ratio of the difference between the second variable and the first variable to the first set value.
3. The method according to claim 2, characterized in that, In the event that the atomic lock for releasing the first resource waiting queue fails, the method includes: If a task exists in the first resource waiting queue, acquire the atomic lock for the third time; The first bit of the atomic lock obtained for the third time is recorded as the third variable; The task at the head of the first resource waiting queue is popped out, and the number of times it is popped out is the ratio of the difference between the third variable and the second variable to the first set value; Release the atomic lock from the first resource waiting queue; If there are no tasks in the resource waiting queue, the atomic lock of the first resource waiting queue is forcibly released.
4. The method according to claim 1, characterized in that, Before acquiring the atomic lock of the first resource waiting queue for the first time, the method further includes: If the processor corresponding to the first resource is multi-core, multiple interrupt tasks are disabled; When the processor corresponding to the first resource is a single core, the timing interrupt task is disabled, and the timing interrupt task is one of the plurality of interrupt tasks; After releasing the atomic lock of the first resource waiting queue, the method further includes: Open the multiple interrupt tasks.
5. The method according to claim 1, characterized in that, The method further includes: If the first resource cannot be obtained in the task context, the atomic lock of the first resource waiting queue is repeatedly acquired until the atomic lock is acquired. The task is inserted into the first resource waiting queue according to its priority; Release the atomic lock from the first resource waiting queue.
6. The method according to claim 5, characterized in that, Before repeatedly acquiring the atomic lock of the first resource waiting queue until the atomic lock is acquired, the method further includes: If the processor corresponding to the first resource is multi-core, multiple interrupt tasks are disabled; When the processor corresponding to the first resource is a single core, the timing interrupt task is disabled, and the timing interrupt task is one of the plurality of interrupt tasks; After releasing the atomic lock of the first resource waiting queue, the method further includes: Open the multiple interrupt tasks.
7. The method according to claim 1, characterized in that, The method further includes: If a timed-out task exists in the first resource queue within the timed interrupt context, the atomic lock of the first resource waiting queue is repeatedly acquired until the atomic lock is acquired. Remove the timed-out task from the first resource waiting queue; Release the atomic lock from the first resource waiting queue.
8. The method according to claim 7, characterized in that, Before repeatedly acquiring the atomic lock of the first resource waiting queue until the atomic lock is acquired, the method further includes: If the processor corresponding to the first resource queue is multi-core, disable multiple interrupt tasks; If the processor corresponding to the first resource queue is a single core, the interrupt task is not disabled; After releasing the atomic lock of the first resource waiting queue, the method further includes: Open the multiple interrupt tasks.
9. A processing apparatus for a resource waiting queue, characterized in that, include: The first acquisition module is used to acquire the atomic lock of the first resource waiting queue for the first time when the first resource in the task context or interrupt context is released, wherein the first resource corresponds to the first resource waiting queue. The first processing module is configured to write a first set value to the first bit of the atomic lock when the atomic lock has been acquired by the second resource. The value of the first bit is used to indicate that the second resource needs to execute the task to be executed by the first resource. The second resource is a resource other than the first resource. The second processing module is used to wake up tasks in other resource waiting queues using the first resource after the written setting value is achieved, wherein the other resource waiting queue is a resource waiting queue other than the first resource waiting queue. The third processing module is used to write a second setting value to the second bit of the atomic lock when the atomic lock is not acquired by the second resource. The second bit is the second setting value used to indicate that the atomic lock is acquired by the first resource. The fourth processing module is used to pop the task at the head of the first resource waiting queue and execute the task; The second acquisition module is used to acquire the atomic lock of the first resource waiting queue for the second time; The fifth processing module is used to pop the task located at the head of the first resource waiting queue based on the value of the first bit, and execute the task; The first release module is used to release the atomic lock of the first resource waiting queue.
10. The apparatus according to claim 9, characterized in that, The fifth processing module includes: The first recording unit is used to record the first bit of the atomic lock acquired for the first time as the first variable; The second recording unit is used to record the first bit of the atomic lock acquired the second time as the second variable; The first processing unit is configured to pop the task at the head of the first resource waiting queue, wherein the number of times the task is popped is the ratio of the difference between the second variable and the first variable to the first set value.
11. The apparatus according to claim 10, characterized in that, In the event that the first release module fails to execute, the device includes: The third acquisition module is used to acquire the atomic lock for the third time if there is a task in the first resource waiting queue; The first recording module is used to record the first bit of the atomic lock obtained for the third time as the third variable; The sixth processing module is used to pop the task at the head of the first resource waiting queue, wherein the number of times the task is popped is the ratio of the difference between the third variable and the second variable to the first set value. The second release module is used to release the atomic lock of the first resource waiting queue; The third release module is used to forcibly release the atomic lock of the first resource waiting queue when there are no tasks in the resource waiting queue.
12. The apparatus according to claim 9, characterized in that, Prior to the first acquisition module, the device further includes: The first shutdown module is used to disable multiple interrupt tasks when the processor corresponding to the first resource is multi-core. The second shutdown module is used to shut down the timing interrupt task when the processor corresponding to the first resource is a single core, wherein the timing interrupt task is one of the plurality of interrupt tasks; Following the first release module, the device further includes: The first opening module is used to open the multiple interrupt tasks.
13. The apparatus according to claim 9, characterized in that, The device further includes: The fourth acquisition module is used to repeatedly acquire the atomic lock of the first resource waiting queue until the atomic lock is acquired if the first resource cannot be acquired in the task context. The seventh processing module is used to insert the task into the first resource waiting queue according to the task priority; The fourth release module is used to release the atomic lock of the first resource waiting queue.
14. The apparatus according to claim 13, characterized in that, Prior to the fourth acquisition module, the device further includes: The third shutdown module is used to disable multiple interrupt tasks when the processor corresponding to the first resource is multi-core. The fourth shutdown module is used to shut down the timing interrupt task when the processor corresponding to the first resource is a single core, wherein the timing interrupt task is one of the plurality of interrupt tasks; Following the fourth release module, the device further includes: The second opening module is used to open the multiple interrupt tasks.
15. The apparatus according to claim 9, characterized in that, The device further includes: The fifth acquisition module is used to repeatedly acquire the atomic lock of the first resource waiting queue until the atomic lock is acquired when there is a timed-out task in the first resource queue in the timed interrupt context. The eighth processing module is used to remove the timed-out task from the first resource waiting queue; The fifth release module is used to release the atomic lock of the first resource waiting queue.
16. The apparatus according to claim 15, characterized in that, Prior to the fifth acquisition module, the device further includes: The fifth shutdown module is used to disable multiple interrupt tasks when the processor corresponding to the first resource queue is multi-core. The sixth shutdown module is used to ensure that interrupt tasks are not disabled when the processor corresponding to the first resource queue is a single core. Following the fifth release module, the device further includes: The third opening module is used to open the multiple interrupt tasks.
17. A processing apparatus for a resource waiting queue, characterized in that, Including transceivers and processors, The processor is configured to acquire an atomic lock of a first resource waiting queue for the first time when the first resource in a task context or interrupt context is released, wherein the first resource corresponds to the first resource waiting queue. The processor is further configured to, when the atomic lock has been acquired by the second resource, write a first set value to the first bit of the atomic lock, wherein the value of the first bit is used to indicate that the second resource needs to execute the task to be executed by the first resource, and the second resource is a resource other than the first resource; The processor is further configured to, after writing the set value, use the first resource to wake up tasks in other resource waiting queues, wherein the other resource waiting queue is a resource waiting queue other than the first resource waiting queue; The processor is further configured to write a second preset value to a second bit of the atomic lock when the atomic lock is not acquired by the second resource, wherein the second bit is the second preset value used to indicate that the atomic lock is acquired by the first resource; The processor is further configured to pop the task at the head of the first resource waiting queue from the first resource waiting queue and execute the task; The processor is also configured to acquire the atomic lock of the first resource waiting queue for the second time; The processor is further configured to pop the task at the head of the first resource waiting queue based on the value of the first bit, and execute the task; The processor is also configured to release the atomic lock of the first resource waiting queue.
18. A communication device, comprising: A transceiver, a memory, a processor, and a program stored in the memory and executable on the processor; characterized in that the processor is configured to read the program in the memory to implement the steps of the method for processing a resource waiting queue as described in any one of claims 1 to 8.
19. A readable storage medium for storing a program, characterized in that, When the program is executed by the processor, it implements the steps of the resource waiting queue processing method as described in any one of claims 1 to 8.