System-on-chip exception processing method, system-on-chip and apparatus thereof

Abstract

A system-on-chip exception processing method, a system-on-chip and an apparatus thereof. In the present application, a first data processing request from a master device is received; the first data processing request is sent to a target slave device, and it is monitored whether a processing operation of the first data processing request meets a timeout condition; when it is monitored that the processing operation of the first data processing request meets the timeout condition, the first data processing request is sent to a virtual slave device to trigger the virtual slave device to return a processing response of the first data processing request.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method for handling exceptions in a system-on-a-chip, a system-on-a-chip, and an apparatus thereof. Background Technology

[0002] With the continuous development of semiconductor technology, more and more processing units are integrated into system-on-chip (SoC), and these processing units are interconnected using a network-on-chip (NoC) architecture. However, as the integration density of SoC increases, the failure rate of processing units and interconnect paths leads to a decrease in the overall stability and reliability of NoC, resulting in reduced performance.

[0003] In a NoC interconnect architecture, if an anomaly occurs, the request of the master device may not be processed normally. The request will remain in a waiting state, causing the system to hang. The request of the master device or other master devices will not be able to work normally, affecting the overall stability and reliability of NoC. Summary of the Invention

[0004] This application provides an on-chip system exception handling method, on-chip system, and apparatus to solve on-chip system exceptions caused by data processing request timeouts, thereby improving the stability and reliability of the on-chip system.

[0005] Firstly, an on-chip system exception handling method is provided, including:

[0006] Receive the first data processing request from the master device;

[0007] Send the first data processing request to the target slave device and monitor whether the processing operation of the first data processing request meets the timeout condition;

[0008] When it is detected that the processing operation of the first data processing request meets the timeout condition, the first data processing request is sent to the virtual slave device to trigger the virtual slave device to return the processing response of the first data processing request.

[0009] In the above implementation, when the operation of the first data processing request times out, it is sent to the virtual slave device for processing. The virtual slave device returns a processing response, thereby promptly ending the first data processing request that has timed out. This avoids the first data processing request that has timed out occupying system resources for a long time, which could cause the system to hang, thus ensuring the stability and reliability of the on-chip system.

[0010] In one possible implementation, the method further includes: if a processing response from the target slave device is received before receiving the processing response of the first data processing request returned by the virtual slave device, then the processing response from the target slave device is discarded.

[0011] In the above implementation, after the first data processing request is sent to the virtual slave device for processing, if a processing response from the target slave device is received before the processing response returned by the virtual slave device is received, the processing response returned by the target slave device is discarded to avoid conflict with the processing of the virtual slave device.

[0012] In one possible implementation, after receiving the first data processing request from the master device, the process further includes:

[0013] Generate first cache information, which includes information from the first data processing request;

[0014] Before detecting that the processing operation of the first data processing request has met the timeout condition, the process also includes:

[0015] Receive a second data processing request, the second data processing request and the first data processing request originating from the same thread of the master device;

[0016] Generate second cache information, which includes information about the second data processing request;

[0017] When it is detected that the processing operation of the first data processing request meets the timeout condition, the method further includes:

[0018] The first cached information is retained, and the cache resources occupied by the second cached information are released; or, the second cached information is retained, and the cache resources occupied by the first cached information are released.

[0019] In the above implementation, if the first data processing request and the second data processing request come from the same thread of the same master device, when the first data processing request is detected to meet the timeout condition, the cache resources occupied by the cache information corresponding to the first data processing request or the second data processing request are released. This ensures that if the processing operation of one of the data processing requests from the same master device and the same thread meets the timeout condition, only the cache resources occupied by one of the data processing requests are retained. Thus, when the data processing request from the same thread of the same master device times out, the cache resources occupied by the data processing requests from the same source are reduced.

[0020] Furthermore, it also includes sending the second data processing request to the virtual slave device.

[0021] Furthermore, if a processing response from the target slave device of the second data processing request is received before the processing response of the second data processing request returned by the virtual slave device is received, then the processing response from the target slave device of the second data processing request is discarded.

[0022] In the above implementation, if one of the multiple data processing requests from the same source (such as the same thread of the same master device) times out, all of these data processing requests from the same source are sent to the virtual slave device. Considering that these data processing requests from the same source may correspond to the same target slave device, if the data processing request times out due to a failure of the target slave device, the above method can promptly terminate the processing of these data processing requests, release the system resources occupied by these data processing operations, avoid unnecessary waiting for the target slave device to return a processing response, and thus ensure the stability and reliability of the on-chip system.

[0023] In one possible implementation, after retaining the first cached information and releasing the cache resources occupied by the second cached information, the method further includes:

[0024] Receive a third data processing request, wherein the third data processing request and the first data processing request originate from the same thread of the master device;

[0025] When the cache resources occupied by the first cache information are released based on the processing response returned by the virtual slave device, the third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the first cache information.

[0026] In one possible implementation, after retaining the second cached information and releasing the cache resources occupied by the first cached information, the method further includes:

[0027] Receive a third data processing request, wherein the third data processing request and the first data processing request originate from the same thread of the master device;

[0028] When the cache resources occupied by the second cache information are released based on the processing response returned by the virtual slave device, third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the second cache information.

[0029] In the above implementation, when one of the multiple data processing requests from the same source (e.g., from the same thread of the same master device) meets the timeout condition and only the cache resources occupied by one of the data processing requests are retained, if a third data processing request from the same source is received again, no new cache resources will be allocated for the newly received third data processing request. Instead, after the cache resources occupied by the retained data processing request are released, the cache resources will be used to cache the information of the third data processing request. Thus, when the data processing request from that source times out and has not yet been processed (i.e., the cache resources occupied by the corresponding cache information have not yet been released), no new cache resources will be allocated for the new data processing request from that source, thereby reducing the overhead of cache resources in the on-chip system and ensuring the reliability and stability of the on-chip system.

[0030] In one possible implementation, after receiving the first data processing request from the master device, the process further includes:

[0031] The count value of the common counter is increased or decreased, wherein the count value of the common counter is increased or decreased whenever a data processing request is received, and the common counter is reset when the count value overflows;

[0032] A private counter is set for the first data processing request. When the count value of the public counter overflows, the count value of the private counter for the first data processing request is increased or decreased. When the count value of the private counter for the first data processing request overflows, the processing operation of the first data processing request meets the timeout condition.

[0033] Furthermore, it also includes resetting the common counter after all received data processing requests have been processed. Resetting the common counter after all received data processing requests have been processed and there is no cached information ensures that subsequent data processing requests can be correctly counted.

[0034] In one possible implementation, the method further includes: when it is detected that the processing operation of the first data processing request meets the timeout condition, performing at least one of the following processing operations: reporting a timeout interruption event, wherein the timeout interruption event carries information of the first data processing request; and saving the information of the first data processing request to the system exception event log.

[0035] In the above implementation, the reported timeout interruption event may contain relevant information (such as context) of the data processing request that timed out, thereby indicating the abnormal data processing request and enabling targeted processing.

[0036] In a second aspect, a system-on-a-chip is provided, comprising: an entry processing unit, a bus, and an exit processing unit, wherein the entry processing unit includes a virtual slave device;

[0037] The ingress processing unit is configured to receive a first data processing request from the master device; monitor whether the processing operation of the first data processing request meets the timeout condition; and when the processing operation of the first data processing request meets the timeout condition, send the first data processing request to the virtual slave device to trigger the virtual slave device to return a processing response to the first data processing request.

[0038] The bus is used to route the first data processing request received by the ingress processing unit to the egress processing unit;

[0039] The export processing unit is used to send the first data processing request to the target slave device.

[0040] In one possible implementation, the ingress processing unit is further configured to: if a processing response from the target slave device is received before receiving a processing response from the first data processing request returned by the virtual slave device, then the processing response from the target slave device is discarded.

[0041] In one possible implementation, the ingress processing unit is further configured to:

[0042] After receiving the first data processing request from the master device, first cache information is generated, which includes the information of the first data processing request.

[0043] The inlet processing unit is also used for:

[0044] Before the processing operation of the first data processing request is detected to meet the timeout condition, a second data processing request is received, wherein the second data processing request and the first data processing request originate from the same thread of the master device.

[0045] Generate second cache information, which includes information about the second data processing request;

[0046] The inlet processing unit is also used for:

[0047] When it is detected that the processing operation of the first data processing request meets the timeout condition, the method further includes:

[0048] The first cached information is retained, and the cache resources occupied by the second cached information are released; or, the second cached information is retained, and the cache resources occupied by the first cached information are released.

[0049] Furthermore, the ingress processing unit is also configured to: send the second data processing request to the virtual slave device.

[0050] In one possible implementation, the ingress processing unit is further configured to:

[0051] After retaining the first cached information and releasing the cache resources occupied by the second cached information, a third data processing request is received. The third data processing request and the first data processing request come from the same thread of the master device.

[0052] When the cache resources occupied by the first cache information are released based on the processing response returned by the virtual slave device, the third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the first cache information.

[0053] In one possible implementation, the ingress processing unit is further configured to:

[0054] After retaining the second cache information and releasing the cache resources occupied by the first cache information, a third data processing request is received. The third data processing request and the first data processing request come from the same thread of the master device.

[0055] When the cache resources occupied by the second cache information are released based on the processing response returned by the virtual slave device, third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the second cache information.

[0056] In one possible implementation, the ingress processing unit is further configured to:

[0057] After receiving the first data processing request from the master device, the count value of the common counter is increased or decreased. Whenever a data processing request is received, the count value of the common counter is increased or decreased. When the count value of the common counter overflows, the common counter is reset.

[0058] A private counter is set for the first data processing request. When the count value of the public counter overflows, the count value of the private counter for the first data processing request is increased or decreased. When the count value of the private counter for the first data processing request overflows, the processing operation of the first data processing request meets the timeout condition.

[0059] Furthermore, the entry processing unit is also used to: reset the common counter after all received data processing requests have been processed.

[0060] In one possible implementation, the ingress processing unit is further configured to:

[0061] When it is detected that the processing operation of the first data processing request meets the timeout condition, at least one of the following processing operations is performed:

[0062] Report a timeout interruption event, wherein the timeout interruption event carries information about the first data processing request;

[0063] Save the information of the first data processing request to the system exception event log.

[0064] Thirdly, a chip is provided, the chip being coupled to a memory for reading and executing program instructions stored in the memory to implement the method as described in any one of the first aspects.

[0065] Fourthly, a communication device is provided, comprising at least one processor connected to a memory, the at least one processor being configured to read and execute a program stored in the memory, such that the communication device performs the method as described in any one of the first aspects.

[0066] Fifthly, a computer storage medium is provided, the computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform any of the methods described in the first aspect.

[0067] In a sixth aspect, a computer product is provided, wherein when invoked by a computer, the computer program product causes the computer to perform any of the methods described in the first aspect. Attached Figure Description

[0068] Figure 1 This is a schematic diagram of the on-chip system architecture in the embodiments of this application;

[0069] Figure 2a , Figure 2b These are connection diagrams of the entry processing unit, bus, and exit processing unit in the on-chip system of this application embodiment;

[0070] Figure 3 This is a schematic diagram of the structure of the entry processing unit in the on-chip system of this application embodiment;

[0071] Figure 4 This is a schematic diagram illustrating the principle of timeout monitoring and anomaly handling implemented by the entry processing unit in this embodiment of the application.

[0072] Figure 5 A flowchart illustrating the on-chip system exception handling method provided in this application embodiment;

[0073] Figure 6 A schematic flowchart of on-chip system exception handling provided in another embodiment of this application;

[0074] Figure 7 This is a schematic diagram of the structure of the communication device provided in the embodiments of this application. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0076] The following explanations of some terms used in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0077] In this application's embodiments, the terms "system" and "network" are used interchangeably. "Multiple" refers to two or more; therefore, in this application's embodiments, "multiple" can also be understood as "at least two." "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C could mean including A, B, C, A and B, A and C, B and C, or A and B and C. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0078] Unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, sequence, priority or importance of multiple objects.

[0079] The specific operating methods in the method embodiment can also be applied to the device embodiment or system embodiment.

[0080] See Figure 1 This is a schematic diagram of the architecture of the system-on-a-chip in the embodiments of this application.

[0081] As shown in the figure, the system-on-chip 100 is connected to one or more master devices, such as master device 1, master device 2, up to master device N; the system-on-chip 100 is also connected to one or more slave devices, such as slave device 1, slave device 2, up to slave device M.

[0082] The master device may include a processor, such as a CPU, graphics processing unit (GPU), or image signal processor (ISP). The slave device may include memory, storage controllers, or similar devices. The master device initiates a data processing request, such as a read data request, a write data request, or other types of data processing requests. This data processing request is transmitted via the on-chip system to the target slave device for processing.

[0083] Taking a processor as the master device and a memory controller as the slave device as an example, the processor sends a read data request. The system-on-a-chip (SoC) transmits this read data request (including the address) to the memory controller and then waits for the memory controller's response. After a period of time, the memory controller sends the data read from the memory chip to the SoC based on the address. The SoC then transmits this data to the processor. If the processor receives the data and verifies that it is correct (e.g., ECC or parity check is successful), the read operation is complete. If the processor sends a write data request, the SoC transmits the write data request (including the address) and data to the memory controller. The memory controller writes the data to the memory chip based on the address and sends an acknowledgment message after completing the write operation. This acknowledgment message is then returned to the processor via the SoC, completing the write operation.

[0084] The system-on-chip 100 may include an input processing unit 200, a bus 300, and an output processing unit 400. The input processing unit may also be referred to as an initial bridge (IB), and the output processing unit may also be referred to as an output bridge (TB). The input processing unit 200, the bus 300, and the output processing unit 400 may be implemented using a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0085] The entry processing unit 200 is used to receive data processing requests from the master device, and further perform protocol conversion to convert the received data processing requests into a format that conforms to the internal processing requirements of the on-chip system. It can also perform security policy (i.e., authentication) and other processing. Furthermore, in this embodiment, the entry processing unit 200 can implement one or more functions such as timeout monitoring, interrupt reporting, exception logging, and exception handling; specific implementation methods can be found in the following description.

[0086] The export processing unit 400 is used to send data processing requests to the slave device. It can further perform protocol conversion on the data processing requests that need to be sent to the slave device, thereby converting the data processing requests into a format that meets the requirements of the slave device.

[0087] Bus 300 is used to route data processing requests from the master device to the target slave device. Bus 300 can also be referred to as a switching network.

[0088] See Figure 2a and Figure 2b The figures show the connection diagrams of the ingress processing unit 200, bus 300, and egress processing unit 400 in the system-on-a-chip according to embodiments of this application. As shown, bus 300 may include multiple routing units (routers) to form an interconnection structure of multiple routing units. The figures only exemplify a few routing units; in actual scenarios, bus 300 may contain fewer or more routing units, and this embodiment of the application does not impose any limitations on this.

[0089] It should be noted that in some embodiments, the master device and the slave device may also be components of the system-on-a-chip, and this application does not limit this.

[0090] In the on-chip system provided by the embodiments of this application, the timeout monitoring processing operation performed by the entry processing unit may include:

[0091] Upon receiving a data processing request from the master device, the system monitors whether the processing operation of the data processing request meets the timeout condition. The data processing request can be any data processing request from the master device, such as the first, second, or third data processing request involved in the embodiments of this application.

[0092] Optionally, the inlet processing unit can use a two-stage counter to implement timeout monitoring; for details, please refer to [link to implementation details]. Figure 4 And related descriptions. Of course, the embodiments of this application may also use other methods to monitor whether the processing operation of the data processing request has timed out, such as using a timer to time the processing operation of the data processing request. When the timer reaches a set threshold, it can be determined that the processing operation of the corresponding data processing request has met the timeout condition.

[0093] In the on-chip system provided by the embodiments of this application, taking the first data processing request as an example, the exception handling operation performed by the entry processing unit may include:

[0094] When the processing operation of the first data processing request is detected to meet the timeout condition, the first data processing request is sent to the virtual slave device to trigger the virtual slave device to return a processing response for the first data processing request. Furthermore, the processing response returned by the virtual slave device for the first data processing request can be sent to the sending master device of the first data processing request to complete the processing operation of the first data processing request.

[0095] Optionally, when it is detected that the processing operation of the first data processing request meets the timeout condition, the first data processing request can be marked as timeout to indicate that the first data processing request is a data processing request whose processing operation has timed out, and the marked first data processing request is sent to the virtual slave device for response.

[0096] Optionally, the virtual slave device may generate a processing failure response for a first data processing request that has timed out, and this processing failure response may be sent to the sending master device of the data processing request. In other embodiments, the virtual slave device may perform the processing and generate a processing response, which may be sent to the sending master device of the data processing request.

[0097] For example, if the first data processing request is a write data request, the virtual slave device, upon receiving the write data request, can return a write data failure response. As another example, if the first data processing request is a read data request, the virtual slave device, upon receiving the read data request, can return a read data failure response. Yet another example, if the first data processing request is a read data request, the virtual slave device, upon receiving the read data request, can include a default read operation return value in its processing response and return that response. This default read operation return value differs from the read operation return values ​​that any slave device connected to the system-on-chip's bus can return. This allows the master device, upon receiving the processing response, to determine that the read operation return value carried in the processing response is not returned by the actual target slave device, but by the virtual slave device, thus confirming a read operation failure.

[0098] Optionally, the virtual slave device can be set in the ingress processing unit so that when the ingress processing unit detects that the processing operation of the data processing request meets the timeout condition, it can send the data processing request to the virtual slave device for response as soon as possible.

[0099] Through the above-mentioned exception handling operations, the virtual slave device can respond to the first data processing request that meets the timeout condition and return a processing response, thereby promptly ending the first data processing request that has timed out. This is to prevent the first data processing request that has timed out from occupying system resources for a long time and causing the system to hang. For data processing requests that have not timed out, they can still be processed in the normal way, thereby ensuring the reliability and stability of the on-chip system.

[0100] Optionally, if the ingress processing unit receives a processing response from the target slave device for the first data processing request before receiving the processing response from the virtual slave device, the processing response from the target slave device is discarded to avoid a conflict between the processing response from the virtual slave device and the processing response from the target slave device.

[0101] Optionally, after receiving the first data processing request from the master device, the entry processing unit can generate first cache information. The first cache information includes information about the first data processing request, such as the context of the first data processing request. The context of the first data processing request may include: information about the master device that sent the first data processing request, its thread ID, the address corresponding to the first data processing request (e.g., the memory address of data in a read or write data request), and the type of the first data processing request (e.g., whether it is a read or write data request). When the entry processing unit performs the above-mentioned exception handling, it can send the first data processing request to the virtual slave device. After receiving the processing response from the virtual slave device, it deletes the first cache information, releases the cache resources occupied by the first cache information, and can further return the processing response to the master device that sent the first data processing request, thereby completing the processing operation of the first data processing request and preventing data processing requests that time out from occupying system resources for a long time, which could cause the system to hang.

[0102] Optionally, before the ingress processing unit detects that the processing operation of the first data processing request has met the timeout condition, it may receive a second data processing request. The second data processing request and the first data processing request originate from the same thread on the same master device. Upon receiving the second data processing request, the ingress processing unit generates second cache information. This second cache information includes information about the second data processing request, such as the context of the second data processing request. When the ingress processing unit detects that the processing operation of the first data processing request has met the timeout condition, it may either retain the first cache information and release the cache resources occupied by the second cache information, or retain the second cache information and release the cache resources occupied by the first cache information.

[0103] Furthermore, since the second data processing request and the first data processing request originate from the same source (the same thread on the same master device), when the processing operation of the first data processing request meets the timeout condition, in addition to sending the first data processing request to the virtual slave device, the second data processing request, which also originates from the same source, can also be sent to the virtual slave device. Furthermore, if a processing response from the target slave device of the second data processing request is received before receiving the processing response from the virtual slave device, the processing response from the target slave device of the second data processing request is discarded.

[0104] Since the second data processing request and the first data processing request come from the same thread on the same master device, when the processing operation of the first data processing request meets the timeout condition, the cache resources occupied by the second cache information corresponding to the second data processing request are released after exception handling of the first data processing request. This ensures that among multiple data processing requests from the same master device and the same thread, if the processing operation of one of the data processing requests meets the timeout condition, only the cache resources occupied by one of the data processing requests are retained, thereby reducing the cache resources occupied by data processing requests from the same source.

[0105] Furthermore, after retaining the first cached information corresponding to the first data processing request and releasing the cache resources occupied by the second cached information corresponding to the second data processing request, the entry processing unit may receive a third data processing request. This third data processing request originates from the same thread on the same master device as the first data processing request. Upon receiving the third data processing request, since the first data processing request from the same thread on the same master device has already timed out, the entry processing unit does not need to allocate new cache resources to cache the information (such as context) of the third data processing request. Instead, after the cache resources occupied by the retained first cached information are released based on the processing response returned by the virtual slave device, the third cached information is generated to cache the information (such as context) of the third data processing request. Furthermore, the cache resources occupied by the third cached information are the same as those occupied by the first cached information; that is, no new cache resources need to be allocated. Instead, after the cache resources occupied by the first cached information are released, the released cache resources are used to store the third cached information.

[0106] The cache resources occupied by the retained first cache information can be released after the virtual slave device returns at least one of the processing responses corresponding to the first data processing request and the second data processing request.

[0107] Based on the same principle, after retaining the second cached information corresponding to the second data processing request and releasing the cache resources occupied by the first cached information corresponding to the first data processing request, the entry processing unit does not allocate new cache resources to cache the information (such as context) of the third data processing request. Instead, when the cache resources occupied by the retained second cached information are released based on the processing response returned by the virtual slave device, the third cached information is generated to cache the information (such as context) of the third data processing request. Furthermore, the cache resources occupied by the third cached information are the same as those occupied by the second cached information.

[0108] In this way, when one of the multiple data processing requests from the same thread on the same master device times out, and only the cache resources corresponding to that one data processing request are retained, if a third data processing request from the same master device and the same thread is received again, no new cache resources will be allocated for the newly received third data processing request. Instead, after the cache resources occupied by the retained cache information are released, the cache resources will be used to cache the context of the third data processing request. This reduces the system resources occupied by subsequent data processing requests from the same source (i.e., the same thread on the same master device) when a data processing request from a certain source times out. The processing operations of data processing requests from other sources will not be affected, thus ensuring the overall reliability and stability of the on-chip system.

[0109] Optionally, after detecting that the processing operation of the first data processing request meets the timeout condition, the entry processing unit may also report a timeout interrupt event. Optionally, the timeout interrupt event may carry information about the first data processing request, such as the context of the first data processing request, so as to further determine the cause of the timeout based on the information contained in the timeout interrupt event.

[0110] Optionally, after detecting that the processing operation of the first data processing request meets the timeout condition, the entry processing unit may also save the information of the first data processing request to the system exception event log. Optionally, the context of the first data processing request may be recorded in the system exception event log so that the timeout cause can be analyzed later based on the log.

[0111] See Figure 3 This is a schematic diagram of the structure of the entry processing unit in the on-chip system provided in the embodiments of this application.

[0112] As shown in the figure, the entry processing unit 200 may include a timeout monitoring module 301, an exception handling module 302, and a virtual slave device 303. Furthermore, it may also include at least one of an interrupt reporting module 304 and an interrupt recording module 305.

[0113] The following description uses the example of the ingress processing unit 200 receiving a first data processing request from the master device to illustrate the functions of each module in the ingress processing unit. It should be noted that although the description uses the first data processing request as an example, it should be understood that any data processing request from the master device (such as a second data processing request, a third data processing request, etc.) can be processed in the following manner.

[0114] The timeout monitoring module 301 monitors whether the processing operation of the first data processing request from the master device meets the timeout condition. When the timeout condition is met, the exception handling module 302 is triggered to handle the exception. Furthermore, the interrupt reporting module 304 can be triggered to report the timeout interrupt event. Furthermore, the interrupt recording module 306 can be triggered to record system exception events in the log.

[0115] The exception handling module 302 is used to perform exception handling operations. Specifically, the exception handling module 302 sends a first data processing request to the virtual slave device 303, so that the virtual slave device 303 returns a processing response to the first data processing request. Further, the processing response can be returned to the master device that sent the first data processing request to complete the processing of the first data processing request.

[0116] Virtual slave device 303 is used to respond to a first data processing request that has timed out. For example, the virtual slave device can generate a processing failure response for the first data processing request that has timed out, and the processing failure response can be sent to the master device that sent the data processing request.

[0117] Interrupt reporting module 304 is used to report timeout interrupt events. Optionally, the timeout interrupt event may carry information about a first data processing request that meets the timeout conditions, such as the context of the first data processing request.

[0118] The interrupt recording module 305 is used to save the information of the first data processing request to the system exception event log. Optionally, the context of the first data processing request can also be recorded in the system exception event log.

[0119] For details on the specific implementation of the functions of the above modules, please refer to the relevant content of the foregoing embodiments.

[0120] It should be noted that, Figure 3 The structure of the entry processing unit shown is only an example. This application does not limit the way the entry processing unit is divided. For example, in some other embodiments, the virtual slave device may be included in the exception handling module; in other embodiments, the function of the virtual slave device may be implemented by the exception handling module, without the need to set up a separate virtual slave device.

[0121] Optionally, in some embodiments, a two-stage counter can be used to monitor whether the processing operation of the data processing request has timed out.

[0122] See Figure 4 This is a schematic diagram illustrating the principle of timeout monitoring and exception handling implemented by the entry processing unit in this embodiment.

[0123] As shown in the figure, the ingress processing unit can cache the information of each data processing request from the master device, so as to wait for the target to return the processing response from the device.

[0124] Specifically, after receiving a first data processing request from the master device, the ingress processing unit generates a first cache (entry1), which includes information about the first data processing request. Optionally, the information about the first data processing request can be the context of the first data processing request. After receiving a second data processing request from the master device, the ingress processing unit generates a second cache (entry2), which includes the context of the second data processing request. After receiving a third data processing request from the master device, the ingress processing unit generates a third cache (entry3), which includes the context of the third data processing request, and so on. The cache information corresponding to these data processing requests forms a cache queue 410.

[0125] The entry processing unit can transmit the data processing requests corresponding to each cached item in the cache queue 410 to the on-chip system bus in a first-in-first-out (FIFO) order, so that the data processing requests can be transmitted to the target slave device via the bus. Upon receiving the processing response from the target slave device, the processing response can be returned to the corresponding master device, and the cached information for that data processing request can be removed from the cache queue 410 (i.e., the cache resources occupied by the corresponding cached information) to complete the processing operation of the data processing request. Of course, the entry processing unit can also transmit the data processing requests corresponding to each cached item in the cache queue 410 to the on-chip system bus in other ways or in other orders; this embodiment does not limit this.

[0126] The entry processing unit can be configured with a public counter 420 and a private counter 421. The public counter 420 is a globally shared counter. The number of private counters 421 is related to the number of cached information in the cache queue 410; one cached entry for one data processing request corresponds to one private counter.

[0127] Optionally, if the common counter uses an incrementing count method, the count value is incremented (e.g., by 1) each time a data processing request is received from the master device. When the common counter overflows, i.e., when it needs to be incremented by 1 even after reaching its maximum value, the common counter is reset (cleared to zero) to restart counting. When the buffer queue 410 is empty, the common counter is reset (cleared to zero). The common counter remains in a reset state while the buffer queue 410 is empty.

[0128] Optionally, if the common counter counts by decrementing its value, then each time a data processing request is received from the master device, the count value of the common counter is decremented (e.g., by 1). When the count value of the common counter overflows, that is, when the count value is zero and still needs to be decremented by 1, the common counter is reset (set to its maximum value) so that counting can start again. When the buffer queue 410 is empty, the common counter is reset.

[0129] Optionally, the private counter can be created and deleted at the following times: when a data processing request is received from the master device and the corresponding cache information is generated, the private counter corresponding to the cache information can be created; when the cache information corresponding to a data processing request in the cache queue 410 is deleted (i.e. the cache resources occupied by the corresponding cache information are released), the private counter corresponding to the cache information can be deleted.

[0130] When the public counter overflows, it triggers a change in the count value of each private counter. Optionally, if the private counters use an incrementing count method, then when the public counter overflows, the count value of each private counter increments (e.g., by 1). Optionally, if the private counters use a decrementing count method, then when the public counter overflows, the count value of each private counter decrements (e.g., by 1).

[0131] When the private counter reaches a set threshold or overflows, it indicates that the processing operation of the data processing request corresponding to the cached information has timed out. Furthermore, the private counter's count value can remain unchanged at this time. For example, if the private counter increments its count, then when the count reaches or exceeds the maximum value, or reaches the specified threshold, it indicates that the processing operation of the corresponding data processing request has timed out. If the private counter decrements its count, then when the count overflows (e.g., the count value decreases to 0), it indicates that the processing operation of the corresponding data processing request has timed out.

[0132] The maximum value of the public counter and the maximum value of the private counter can be set according to factors such as the performance requirements of the on-chip system, and this application embodiment does not impose any restrictions on this.

[0133] When a data processing request is determined to have met the timeout conditions, the exception handling process can be initiated. For example, the data processing request that has met the timeout conditions can be sent to the virtual slave device for a response.

[0134] Optionally, when a data processing request is detected to have met the timeout condition, the data processing request can be marked as timed out. For example, for the first data processing request, when the private counter corresponding to its first cache (entry1) overflows, it indicates that the operation of the first data processing request has met the timeout condition, so the first cache corresponding to the first data processing request is marked as timed out.

[0135] Optionally, when the processing operation of a data processing request times out, all cached information corresponding to data processing requests in the cache queue that have the same source as the timed-out data processing request (e.g., from the same thread on the same main device) can be marked as timed out. For example, the cache queue includes a first cache corresponding to a first data processing request and a second cache corresponding to a second data processing request. The first and second data processing requests originate from the same thread on the same main device. When the processing operation of the first data processing request is detected to meet the timeout condition, both the first and second caches can be marked as timed out. The above description uses the example of two data processing requests originating from the same thread on the same main device. It should be understood that the number of data processing requests with the same source in the cache queue can be larger. In this case, when the processing operation of one of the data processing requests meets the timeout condition, all cached information corresponding to these data processing requests with the same source can be marked as timed out.

[0136] Optionally, when the processing operation of the first data processing request meets the timeout condition, and all cached information corresponding to data processing requests from the same source as the first data processing request is marked as timeout, only the cached information corresponding to one of these data processing requests from the same source that has been marked as timeout can be retained. For example, the first cached information corresponding to the first data processing request can be retained, and the cached resources occupied by the cached information corresponding to other data processing requests from the same source can be released.

[0137] Furthermore, if a third data processing request from the same source is subsequently received (i.e., the third data processing request and the first data processing request originate from the same thread on the same master device), then it is no longer necessary to request new resources to cache the context of the third data processing request. Instead, once the cache resources occupied by the retained cache information are released, the cache information is used to store the context of the third data processing request.

[0138] For example, assuming the first and second data processing requests originate from the same thread on the same master device, when the processing operation of the first data processing request meets the timeout condition, the cache resources occupied by the second cache information corresponding to the second data processing request can be released, only the first cache information corresponding to the first data processing request is retained, and the first cache information can be marked as locked. When a third data processing request is received, the master device and thread from which the third data processing request originates are determined, and they match the master device information and thread ID in the first cache information marked as locked. Therefore, no new cache resources are requested for the third data processing request. Instead, after the cache resources occupied by the first cache information are released, the cache resources are used to store the context of the third data processing request.

[0139] See Figure 5 The figure shows a flowchart illustrating the on-chip system exception handling method provided in this application embodiment. The flowchart may include:

[0140] S501: Receive the first data processing request from the master device.

[0141] Optionally, the first data processing request can be a read data request or a write data request.

[0142] S502: Send the first data processing request to the target slave device.

[0143] Optionally, in this step, based on Figure 1 The system architecture shown allows the on-chip system's entry processing unit to perform protocol conversion after receiving the first data processing request, and then send the converted first data processing request to the bus for transmission to the target slave device.

[0144] S503: Monitor whether the processing operation of the first data processing request meets the timeout condition. If the processing operation of the first data processing request meets the timeout condition, proceed to S504; otherwise, proceed to S505.

[0145] The first data processing request may time out due to several reasons. First, during bus routing, a fault in the interconnect path could prevent the request from being sent to the target slave device, thus preventing the system-on-chip from receiving the processing response and causing a timeout. Second, a fault in the target slave device could prevent it from returning a processing response, leading to the system-on-chip's inability to receive the response and resulting in a timeout.

[0146] In this embodiment, the processing operation of the first data processing request can be monitored to see if it meets the timeout condition. The method for timeout monitoring is as described above and will not be repeated here. When the processing operation of the first data processing request is detected to have timed out, the process can proceed to step 504 to enter the exception handling process.

[0147] S504: Execute exception handling procedure.

[0148] The exception handling process may include the following steps: sending a first data processing request to the virtual slave device to trigger the virtual slave device to return a processing response for the first data processing request.

[0149] In this step, after receiving the first data processing response, the virtual slave device can return a processing response, such as a processing failure response. Furthermore, this processing response can be sent to the master device that sent the first data processing request.

[0150] Optionally, when the processing operation of the first data processing request is detected to meet the timeout condition, a timeout interruption event can also be reported. Optionally, the timeout interruption event carries information about the first data processing request, such as the context of the first data processing request.

[0151] Optionally, when it is detected that the processing operation of the first data processing request meets the timeout condition, the information of the first data processing request can also be saved to the system abnormal event log.

[0152] S505: Use standard processing procedures. For example, wait for the target to return a processing response from the device.

[0153] In the above process, when the processing operation of the first data processing request times out, it is sent to the virtual slave device for processing. The virtual slave device returns a processing response, thereby ending the first data processing request that has timed out in a timely manner. This is to prevent the first data processing request that has timed out from occupying system resources for a long time and causing the system to hang, thus ensuring the stability and reliability of the on-chip system.

[0154] Optionally, if a processing response from the target slave device is received before the processing response of the first data processing request returned by the virtual slave device is received, the processing response from the target slave device is discarded.

[0155] Optionally, after receiving the first data processing request from the master device, the method further includes: generating first cache information, which includes information about the first data processing request, such as the context of the first data processing request; before detecting that the processing operation of the first data processing request meets the timeout condition, the method further includes: receiving a second data processing request, which, like the first data processing request, originates from the same thread of the same master device; and generating second cache information, which includes information about the second data processing request. When detecting that the processing operation of the first data processing request meets the timeout condition, the method further includes: retaining the first cache information and releasing the cache resources occupied by the second cache information, or retaining the second cache information and releasing the cache resources occupied by the first cache information.

[0156] Furthermore, when it is detected that the processing operation of the first data processing request meets the timeout condition, a second data processing request from the same source as the first data processing request is sent to the virtual slave device.

[0157] Optionally, after retaining the first cache information and releasing the cache resources occupied by the second cache information, the method further includes: receiving a third data processing request, wherein the third data processing request and the first data processing request originate from the same thread of the same master device; and generating third cache information after releasing the cache resources occupied by the first cache information based on the processing response returned by the virtual slave device, wherein the third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the first cache information.

[0158] Optionally, after retaining the second cache information and releasing the cache resources occupied by the first cache information, the method further includes: receiving a third data processing request, wherein the third data processing request and the first data processing request originate from the same thread of the same master device; and generating third cache information after releasing the cache resources occupied by the second cache information based on the processing response returned by the virtual slave device, wherein the third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the second cache information.

[0159] For details on the specific implementation of each step in the above process, please refer to the aforementioned embodiments.

[0160] based on Figure 5 The process shown, combined with Figure 4 The principle shown Figure 6An exemplary flowchart of an on-chip system exception handling method in a specific application scenario is shown in the figure. The flowchart may include:

[0161] S601: Receives a data processing request from the master device.

[0162] S602: Cache the context of the data processing request and obtain the cache information corresponding to the data processing request.

[0163] S603: The count value of the public counter is incremented by 1. The count value of the private counter corresponding to the data processing request is incremented by 1 when the count value of the public counter overflows.

[0164] S604: Has the count value of the private counter corresponding to the data processing request reached the threshold or overflowed? If so, it indicates that the processing operation of the data processing request has timed out, and then proceed to S605; otherwise, proceed to S612.

[0165] S605: Reports a timeout interruption event and records the context of the data processing request in the exception event log.

[0166] S606: Mark the cached information of the data processing request in the cache queue, as well as the cached information of the data processing request originating from the same master device and the same thread, as timed out.

[0167] S607: Send the data processing request corresponding to the cached information marked as timed out to the virtual slave device for response.

[0168] S608: For cached information marked as timed out in S606, only one cached information is retained (a cached information refers to the cached information corresponding to a data processing request, such as an entry), the cache resources occupied by the other cached information are released, and the retained cached information is marked as locked.

[0169] S609: If a new data processing request is received from the same source (i.e., the same thread on the same master device), no new cache resources will be requested for that new data processing request. After the cache resources occupied by the aforementioned reserved and locked cache information are released, the context of the new data processing request is stored using those cache resources (i.e., the cache resources occupied by the locked cache information) to obtain the corresponding cache information.

[0170] S610: If a processing response is received from the target slave device corresponding to the data processing request marked as timed out in S606, it is discarded directly.

[0171] S611: After receiving the processing response returned by the virtual slave device, release the cache resources occupied by the corresponding cache information, and may further return to the master device to complete the timeout exception handling operation.

[0172] Optionally, if in S606 there are multiple data processing requests marked as timed out, in S607 all multiple data processing requests are sent to the virtual slave device for response, and in S608 the cached information that is retained and marked as locked is the first cached information, then in S611, after receiving the processing responses returned by the virtual slave device for the multiple data processing requests, the cache resources occupied by the first cached information are released.

[0173] S612: Process according to the standard procedure.

[0174] It should be noted that this description only uses the example of a counter counting by incrementing the count value. If the counter counts by decrementing the count value, the principle of the process is the same as described above.

[0175] The specific implementation methods of each step in the above process can be found in the description of the foregoing embodiments, and will not be repeated here.

[0176] Based on the same technical concept, embodiments of this application also provide a communication device, which can have the following functions: Figure 7 As shown in the diagram, the communication device can be a system-on-a-chip that implements the above method, or it can be a chip or chip system that implements the above method.

[0177] like Figure 7 The communication device 700 shown may include at least one processor 702, which is coupled to a memory to read and execute instructions in the memory to implement the steps involved in the method provided in the embodiments of this application. Optionally, the communication device 700 may further include at least one interface 703 for providing program instructions or data to the at least one processor. The communication device 700 can perform actions such as... Figure 5 or Figure 6The steps in the method shown are illustrated. Furthermore, interface 703 can be used to support communication by communication device 700. Optionally, communication device 700 may also include memory 704, which stores computer programs and instructions. Memory 704 may be coupled to processor 702 and / or interface 703 to support processor 702 in calling the computer programs and instructions in memory 704 to implement the steps involved in the method provided in this application embodiment. Additionally, memory 704 may also be used to store data involved in the method embodiments of this application, for example, to store data and instructions necessary for interface 703 to implement interaction, and / or to store configuration information necessary for communication device 700 to execute the method described in this application embodiment.

[0178] Based on the same concept as the above-described method embodiments, this application also provides a computer-readable storage medium storing some instructions. When these instructions are invoked and executed by a computer, the computer can perform the methods involved in any possible design of the above-described method embodiments. In this application, the computer-readable storage medium is not limited; for example, it can be RAM (random-access memory), ROM (read-only memory), etc.

[0179] Based on the same concept as the above method embodiments, this application also provides a computer program product that, when executed by a computer, can perform the methods involved in the method embodiments and any possible designs of the above method embodiments.

[0180] Based on the same concept as the above method embodiments, this application also provides a chip, which may include a processor and an interface circuit, for performing the methods involved in any possible implementation of the above method embodiments, wherein "coupling" means that two components are directly or indirectly combined with each other, and such combination may be fixed or movable, and such combination may allow fluid, electricity, electrical signals or other types of signals to communicate between the two components.

[0181] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0182] The various illustrative logic units and circuits described in the embodiments of this application can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0183] The steps of the methods or algorithms described in the embodiments of this application can be directly embedded in hardware, software units executed by a processor, or a combination of both. The software units can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC, which can be housed in a terminal device. Optionally, the processor and storage medium can also be housed in different components within the terminal device.

[0184] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0185] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A method for handling exceptions in an on-chip system, characterized in that, include: Receive a first data processing request from the master device and generate first cache information, wherein the first cache information includes information from the first data processing request; Send the first data processing request to the target slave device and monitor whether the processing operation of the first data processing request meets the timeout condition; A second data processing request is received, and second cache information is generated, the second cache information including information of the second data processing request; wherein, the second data processing request and the first data processing request originate from the same thread of the master device; When it is detected that the processing operation of the first data processing request meets the timeout condition, the first data processing request and the second data processing request are sent to the virtual slave device to trigger the virtual slave device to return the processing response of the first data processing request and the second data processing request, retain one of the cached information of the first cached information and the second cached information, and release the cache resources occupied by the other cached information.

2. The method as described in claim 1, characterized in that, Also includes: If a processing response from the target slave device is received before the processing response of the first data processing request returned by the virtual slave device is received, then the processing response from the target slave device is discarded.

3. The method as described in claim 1, characterized in that: After retaining the first cached information and releasing the cache resources occupied by the second cached information, the process further includes: Receive a third data processing request, wherein the third data processing request and the first data processing request originate from the same thread of the master device; When the cache resources occupied by the first cache information are released based on the processing response returned by the virtual slave device, the third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the first cache information. Alternatively, after retaining the second cache information and releasing the cache resources occupied by the first cache information, the method further includes: Receive a third data processing request, wherein the third data processing request and the first data processing request originate from the same thread of the master device; When the cache resources occupied by the second cache information are released based on the processing response returned by the virtual slave device, the third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the second cache information.

4. The method according to any one of claims 1-3, characterized in that: After receiving the first data processing request from the master device, it also includes: The count value of the common counter is increased or decreased, wherein the count value of the common counter is increased or decreased whenever a data processing request is received, and the common counter is reset when the count value overflows; A private counter is set for the first data processing request. When the count value of the public counter overflows, the count value of the private counter for the first data processing request is increased or decreased. When the count value of the private counter for the first data processing request overflows, the processing operation of the first data processing request meets the timeout condition.

5. The method as described in claim 4, characterized in that, Also includes: Once all received data processing requests have been processed, the common counter is reset.

6. The method according to any one of claims 1-3, characterized in that, Also includes: When it is detected that the processing operation of the first data processing request meets the timeout condition, at least one of the following processing operations is performed: Report a timeout interruption event, wherein the timeout interruption event carries information about the first data processing request; Save the information of the first data processing request to the system exception event log.

7. A system-on-a-chip, characterized in that, include: The system includes an ingress processing unit, a bus, and an egress processing unit, wherein the ingress processing unit includes a virtual slave device. The entry processing unit is configured to receive a first data processing request from the master device, generate first cache information, the first cache information including information of the first data processing request; monitor whether the processing operation of the first data processing request meets the timeout condition; receive a second data processing request, generate second cache information, the second cache information including information of the second data processing request; wherein the second data processing request and the first data processing request originate from the same thread of the master device; when it is detected that the processing operation of the first data processing request meets the timeout condition, send the first data processing request and the second data processing request to the virtual slave device to trigger the virtual slave device to return the processing response of the first data processing request and the second data processing request, retain one of the first cache information and the second cache information, and release the cache resources occupied by the other cache information; The bus is used to route the first data processing request received by the ingress processing unit to the egress processing unit; The export processing unit is used to send the first data processing request to the target slave device.

8. The system-on-a-chip as described in claim 7, characterized in that, The inlet processing unit is also used for: If a processing response from the target slave device is received before the processing response of the first data processing request returned by the virtual slave device is received, then the processing response from the target slave device is discarded.

9. The system-on-a-chip as claimed in claim 7, characterized in that: The inlet processing unit is further configured to: After retaining the first cached information and releasing the cache resources occupied by the second cached information, a third data processing request is received. The third data processing request and the first data processing request come from the same thread of the master device. When the cache resources occupied by the first cache information are released based on the processing response returned by the virtual slave device, the third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the first cache information. Alternatively, the inlet processing unit is further configured to: After retaining the second cache information and releasing the cache resources occupied by the first cache information, a third data processing request is received. The third data processing request and the first data processing request come from the same thread of the master device. When the cache resources occupied by the second cache information are released based on the processing response returned by the virtual slave device, third cache information is generated. The third cache information includes the information of the third data processing request, and the cache resources occupied by the third cache information are the same as those occupied by the second cache information.

10. The system-on-a-chip as claimed in any one of claims 7-9, characterized in that, The inlet processing unit is also used for: After receiving the first data processing request from the master device, the count value of the common counter is increased or decreased. Whenever a data processing request is received, the count value of the common counter is increased or decreased. When the count value of the common counter overflows, the common counter is reset. A private counter is set for the first data processing request. When the count value of the public counter overflows, the count value of the private counter for the first data processing request is increased or decreased. When the count value of the private counter for the first data processing request overflows, the processing operation of the first data processing request meets the timeout condition.

11. The system-on-a-chip as claimed in claim 10, characterized in that, The inlet processing unit is also used for: Once all received data processing requests have been processed, the common counter is reset.

12. The system-on-a-chip as claimed in any one of claims 7-9, characterized in that, The inlet processing unit is also used for: When it is detected that the processing operation of the first data processing request meets the timeout condition, at least one of the following processing operations is performed: Report a timeout interruption event, wherein the timeout interruption event carries information about the first data processing request; Save the information of the first data processing request to the system exception event log.

13. A chip, characterized in that, The chip is coupled to a memory for reading and executing program instructions stored in the memory to implement the method as described in any one of claims 1-6.

14. A communication device, characterized in that, The device includes at least one processor connected to a memory, the at least one processor being configured to read and execute a program stored in the memory, such that the communication device performs the method as described in any one of claims 1-6.

15. A computer storage medium, characterized in that, The computer storage medium stores computer instructions that, when executed on the computer, cause the computer to perform the method as described in any one of claims 1-6.

16. A computer program product, characterized in that, When the computer program product is invoked by a computer, it causes the computer to perform the method as described in any one of claims 1-6.

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