Voltage supply circuit, voltage supply method, voltage supply module, and display device

Abstract

The present disclosure provides a voltage supply circuit, a voltage supply method, a voltage supply module and a display device. The voltage supply circuit comprises a first node control circuit, a first control node control circuit, a second node control circuit and a driving voltage output circuit. The first node control circuit controls the potential of the first node; the first control node control circuit controls the potential of the first control node; the second node control circuit controls the potential of the second node; and the driving voltage output circuit is electrically connected with the second node, a driving voltage output end and an initial voltage end, respectively, and is configured to control the driving voltage output end to output a driving voltage according to an initial voltage provided by the initial voltage end under the control of the potential of the second node. The voltage supply circuit provided by the embodiments of the present disclosure can provide a driving voltage for a pixel circuit capable of realizing an internal compensation function.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a voltage supply circuit, a voltage supply method, a voltage supply module, and a display device. Background Technology

[0002] In related technologies, a simple pixel circuit capable of implementing internal compensation cannot be provided, nor can a voltage supply circuit be proposed to conveniently provide driving voltage to the pixel circuit. Consequently, related display devices are not conducive to achieving simplified pixel structures or high PPI (pixel density). Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a voltage supply circuit, including a first node control circuit, a first control node control circuit, a second node control circuit, and a drive voltage output circuit, wherein...

[0004] The first node control circuit is electrically connected to the first node, the input terminal, the first clock signal terminal, the first control node, the first voltage terminal, and the second voltage terminal, respectively. It is used to control the potential of the first node according to the first voltage signal provided by the first voltage terminal and the second voltage signal provided by the second voltage terminal, under the control of the input signal provided by the input terminal, the first clock signal provided by the first clock signal terminal, and the potential of the first control node.

[0005] The first control node control circuit is electrically connected to the first control node, the input terminal, and the second clock signal terminal, respectively, and is used to control the potential of the first control node under the control of the second clock signal provided by the second clock signal terminal and the input signal.

[0006] The second node control circuit is electrically connected to the second node, the first control node, the first clock signal terminal, the first node, and the second voltage terminal, respectively, and is used to control the potential of the second node according to the first clock signal and the second voltage signal under the control of the potential of the first node, the potential of the first control node, and the first clock signal.

[0007] The driving voltage output circuit is electrically connected to the second node, the driving voltage output terminal, and the initial voltage terminal, respectively, and is used to control the driving voltage output terminal to output a driving voltage according to the initial voltage provided by the initial voltage terminal under the control of the potential of the second node.

[0008] Optionally, the driving voltage output circuit is also electrically connected to the first node and the third voltage terminal respectively, for controlling the driving voltage output terminal to be electrically connected to the third voltage terminal under the control of the potential of the first node.

[0009] Optionally, the voltage supply circuit described in at least one embodiment of this disclosure further includes a carry signal output circuit;

[0010] The carry signal output circuit is electrically connected to the carry signal output terminal, the first node, the second node, the first voltage terminal, and the second voltage terminal, respectively, and is used to control the carry signal output terminal to output a carry signal according to the first voltage signal and the second voltage signal under the control of the potential of the first node and the potential of the second node.

[0011] Optionally, the first node control circuit includes a second control node control sub-circuit, a first node control sub-circuit, and a first energy storage circuit.

[0012] The second control node control sub-circuit is electrically connected to the second control node, the input terminal, and the first clock signal output terminal, respectively, and is used to control the connection between the second control node and the input terminal under the control of the first clock signal;

[0013] The first terminal of the first energy storage circuit is electrically connected to the second control node, and the second terminal of the first energy storage circuit is electrically connected to the first node. The first energy storage circuit is used to store electrical energy.

[0014] The first node control sub-circuit is electrically connected to the second control node, the first node, the first voltage terminal, the first clock signal terminal, the first control node, and the second voltage terminal, respectively. It is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second control node, and to control the connection between the first node and the second voltage terminal under the control of the first clock signal and the potential of the first control node.

[0015] Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0016] The control electrode of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0017] The control electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0018] The control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor.

[0019] The control electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal.

[0020] Optionally, the first node control circuit may further include a fifth transistor;

[0021] The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor;

[0022] The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

[0023] Optionally, the second control node control sub-circuit includes a first transistor;

[0024] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the second control node.

[0025] The first energy storage circuit includes a first capacitor;

[0026] The first terminal of the first capacitor is electrically connected to the second control node, and the second terminal of the first capacitor is electrically connected to the first node;

[0027] The first node control sub-circuit includes a second transistor, a third transistor, and a fourth transistor;

[0028] The control electrode of the second transistor is electrically connected to the second control node, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0029] The control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor.

[0030] The control electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal.

[0031] Optionally, the first node control sub-circuit may further include a fifth transistor;

[0032] The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor;

[0033] The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

[0034] Optionally, the control circuit of the first control node includes a sixth transistor and a seventh transistor;

[0035] The control electrode of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage terminal or the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first control node.

[0036] The control electrode of the seventh transistor is electrically connected to the input terminal, the first electrode of the seventh transistor is electrically connected to the first control node, and the second electrode of the seventh transistor is electrically connected to the second clock signal terminal.

[0037] Optionally, the second node control circuit includes an eighth transistor, a ninth transistor, a second capacitor, and a tenth transistor;

[0038] The control electrode of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the ninth transistor.

[0039] The first terminal of the second capacitor is electrically connected to the first control node, and the second terminal of the second capacitor is electrically connected to the first electrode of the ninth transistor.

[0040] The control electrode of the ninth transistor is electrically connected to the first clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second node;

[0041] The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second node, and the second electrode of the tenth transistor is electrically connected to the second voltage terminal.

[0042] Optionally, the second node control circuit may further include a third capacitor;

[0043] The first terminal of the third capacitor is electrically connected to the second node, and the second terminal of the third capacitor is electrically connected to the second voltage terminal.

[0044] Optionally, the carry signal output circuit includes an eleventh transistor and a twelfth transistor;

[0045] The control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the carry signal output terminal.

[0046] The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal.

[0047] Optionally, the drive voltage output circuit includes a thirteenth transistor;

[0048] The control electrode of the thirteenth transistor is electrically connected to the second node, the first electrode of the thirteenth transistor is electrically connected to the drive voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

[0049] Optionally, the drive voltage output circuit includes a thirteenth transistor, a fourteenth transistor, and a fourth capacitor;

[0050] The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the drive voltage output terminal.

[0051] The control electrode of the thirteenth transistor is electrically connected to the second node, the first electrode of the thirteenth transistor is electrically connected to the driving voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

[0052] The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the driving voltage output terminal.

[0053] In a second aspect, embodiments of this disclosure provide a voltage supply method applied to the aforementioned voltage supply circuit, wherein the voltage supply cycle includes a first stage, a second stage, a third stage, a fourth stage, and a fifth stage set sequentially; the voltage supply method includes:

[0054] In the first stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node to the first level, and the second node control circuit controls the potential of the second node to the second level.

[0055] In the second stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node.

[0056] In the third stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node.

[0057] In the fourth stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the second level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node.

[0058] In the fifth stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node, and the second node control circuit controls the potential of the second node to the second level.

[0059] Optionally, the driving voltage output circuit is also electrically connected to the first node and the third voltage terminal respectively, and the voltage supply method further includes:

[0060] In the first stage and the fifth stage, the driving voltage output circuit controls the connection between the driving voltage output terminal and the third voltage terminal under the control of the potential of the first node.

[0061] Optionally, the voltage providing circuit further includes a carry signal output circuit; the voltage providing method further includes:

[0062] In the first stage and the fifth stage, the carry signal output circuit controls the connection between the carry signal output terminal and the first voltage terminal under the control of the potential of the first node;

[0063] In the second, third, and fourth stages, the carry signal output circuit controls the connection between the carry signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0064] In a third aspect, embodiments of this disclosure provide a voltage supply module, including multiple stages of the voltage supply circuit described above;

[0065] The voltage supply circuit includes a carry signal output terminal;

[0066] The carry signal output terminal of the voltage supply circuit is electrically connected to the input terminal of the adjacent next-stage voltage supply circuit, and is used to provide an input signal to the input terminal of the adjacent next-stage voltage supply circuit.

[0067] In a fourth aspect, embodiments of this disclosure provide a display device including the voltage supply module described above.

[0068] Optionally, the display device described in at least one embodiment of this disclosure further includes a multi-row, multi-column pixel circuit; the pixel circuit includes a light-emitting element and a driving circuit, a data writing circuit, an initialization circuit, and a second energy storage circuit;

[0069] The first terminal of the driving circuit is electrically connected to the driving voltage output terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element. The driving circuit is used to generate a current to drive the light-emitting element to emit light under the control of the potential at its control terminal.

[0070] The voltage supply module includes a voltage supply circuit that is electrically connected to the drive voltage output terminal, and is used to provide drive voltage to the drive voltage output terminal;

[0071] The data writing circuit is electrically connected to the scan line, the data line and the control terminal of the driving circuit, respectively, and is used to control the writing of the data voltage on the data line to the control terminal of the driving circuit under the control of the scan signal provided by the scan line.

[0072] The initialization circuit is electrically connected to the initialization control line, the reference voltage terminal, and the control terminal of the drive circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the control terminal of the drive circuit under the control of the initialization control signal provided by the initialization control line.

[0073] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy.

[0074] Optionally, the pixel circuit further includes a driving control circuit; the driving control circuit is electrically connected to the light emission control line, the first terminal and the fourth voltage terminal of the driving circuit respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal into the first terminal of the driving circuit under the control of the light emission control signal provided by the light emission control line.

[0075] Optionally, the nth-level voltage supply circuit in the voltage supply module includes at least two thirteenth transistors and at least two nth-level drive voltage output terminals, wherein the at least two thirteenth transistors and the pixel circuit are both disposed in the display area; the components of the nth-level voltage supply circuit, excluding the thirteenth transistors, are disposed in the peripheral area; n is a positive integer;

[0076] The control electrode of the thirteenth transistor is electrically connected to the corresponding second node, the first electrode of the thirteenth transistor is electrically connected to the corresponding nth stage drive voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

[0077] Each of the nth-level driving voltage output terminals is electrically connected to the first terminal of the driving circuit included in at least one pixel circuit located in the nth row, for providing a corresponding nth-level driving voltage to the first terminal of the driving circuit included in at least one pixel circuit located in the nth row.

[0078] Optionally, the driving circuit includes a driving transistor, the data writing circuit includes a data writing transistor, the initialization circuit includes an initialization transistor, the second energy storage circuit includes a storage capacitor, and the driving control circuit includes a driving control transistor.

[0079] The control electrode of the data writing transistor is electrically connected to the scan line, the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the control electrode of the driving transistor.

[0080] The control electrode of the initialization transistor is electrically connected to the initialization control line, the first electrode of the initialization transistor is electrically connected to the reference voltage terminal, and the second electrode of the initialization transistor is electrically connected to the control electrode of the driving transistor.

[0081] The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the storage capacitor is electrically connected to the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the fourth voltage terminal.

[0082] The first terminal of the driving transistor is electrically connected to the driving voltage output terminal, and the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element;

[0083] The control electrode of the driving control transistor is electrically connected to the light-emitting control line, the first electrode of the driving control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving control transistor is electrically connected to the fourth voltage terminal. Attached Figure Description

[0084] Figure 1This is a structural diagram of the voltage supply circuit described in the embodiments of this disclosure;

[0085] Figure 2 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0086] Figure 3 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0087] Figure 4 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0088] Figure 5 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0089] Figure 6 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0090] Figure 7 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0091] Figure 8 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0092] Figure 9 This is a structural diagram of the voltage supply circuit according to at least one embodiment of the present disclosure;

[0093] Figure 10 This is a circuit diagram of a voltage supply circuit according to at least one embodiment of the present disclosure;

[0094] Figure 11 This is a public announcement. Figure 10 The timing diagram of the voltage supply circuit shown is as follows;

[0095] Figure 12 This is a circuit diagram of a voltage supply circuit according to at least one embodiment of the present disclosure;

[0096] Figure 13 This is a circuit diagram of a voltage supply circuit according to at least one embodiment of the present disclosure;

[0097] Figure 14 This is a public announcement. Figure 13 The timing diagram of the voltage supply circuit shown is as follows;

[0098] Figure 15 This is a circuit diagram of a voltage supply circuit according to at least one embodiment of the present disclosure;

[0099] Figure 16 This is a circuit diagram of a voltage supply circuit according to at least one embodiment of the present disclosure;

[0100] Figure 17 This is a structural diagram of a voltage supply module according to at least one embodiment of the present disclosure;

[0101] Figure 18 This is a structural diagram of a voltage supply module according to at least one embodiment of the present disclosure;

[0102] Figure 19 This is a structural diagram of at least one embodiment of the pixel circuit in the display device described in this disclosure;

[0103] Figure 20 This is a circuit diagram of at least one embodiment of the pixel circuit;

[0104] Figure 21 yes Figure 20 The timing diagram of at least one embodiment of the pixel circuit shown;

[0105] Figure 22 This is a schematic diagram showing the connection relationship between the nth row pixel circuit and the voltage supply circuit A1, the scan signal generation circuit A2, and the initialization control signal generation circuit A3.

[0106] Figure 23 This is a circuit diagram of at least one embodiment of the pixel circuit;

[0107] Figure 24 This is a circuit diagram of at least one embodiment of the pixel circuit;

[0108] Figure 25 yes Figure 24 The timing diagram of at least one embodiment of the pixel circuit shown;

[0109] Figure 26 This is a schematic diagram of at least one embodiment of the display panel included in the display device described in the embodiments of this disclosure. Detailed Implementation

[0110] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0111] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0112] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0113] like Figure 1 As shown, the voltage supply circuit described in this embodiment includes a first node control circuit 11, a first control node control circuit 12, a second node control circuit 13, and a drive voltage output circuit 14, wherein,

[0114] The first node control circuit 11 is electrically connected to the first node Q, the input terminal STU, the first clock signal terminal KA, the first control node P, the first voltage terminal V1, and the second voltage terminal V2, respectively. It is used to control the potential of the first node Q under the control of the input signal provided by the input terminal STU, the first clock signal provided by the first clock signal terminal KA, and the potential of the first control node P, according to the first voltage signal provided by the first voltage terminal V1 and the second voltage signal provided by the second voltage terminal V2.

[0115] The first control node control circuit 12 is electrically connected to the first control node P, the input terminal STU, and the second clock signal terminal KB, respectively, and is used to control the potential of the first control node P under the control of the second clock signal provided by the second clock signal terminal KB and the input signal.

[0116] The second node control circuit 13 is electrically connected to the second node QB, the first control node P, the first clock signal terminal KA, the first node Q, and the second voltage terminal V2, respectively, and is used to control the potential of the second node QB according to the first clock signal and the second voltage signal under the control of the potential of the first node Q, the potential of the first control node P, and the first clock signal.

[0117] The driving voltage output circuit 14 is electrically connected to the second node QB, the driving voltage output terminal I(n), and the initial voltage terminal V01, respectively, and is used to control the driving voltage output terminal I(n) to output the driving voltage according to the initial voltage provided by the initial voltage terminal V01 under the control of the potential of the second node.

[0118] The voltage supply circuit described in this embodiment can provide a driving voltage for a pixel circuit that can achieve internal compensation function, and the pixel circuit has a simple structure and can achieve extremely high PPI.

[0119] In at least one embodiment of this disclosure, the first voltage terminal V1 may be a first high voltage terminal for providing a first high voltage signal, and the second voltage terminal V2 may be a first low voltage terminal for providing a first low voltage signal; however, this is not a limitation.

[0120] When the voltage supply circuit described in this embodiment is working, the voltage supply cycle may include a first stage, a second stage, a third stage, a fourth stage, and a fifth stage set sequentially.

[0121] In the first stage, the first node control circuit 11 controls the potential of the first node Q to the first level, the first control node control circuit 12 controls the potential of the first control node P, and the second node control circuit 13 controls the potential of the second node QB to the second level.

[0122] In the second stage, the first node control circuit 11 controls the potential of the first node Q to the first level, the first control node control circuit 12 controls the potential of the first control node P to the first level, and the second node control circuit 13 controls the potential of the second node QB to the second level.

[0123] In the third stage, the first node control circuit 11 controls the potential of the first node Q to the second level, the first control node control circuit 12 controls the potential of the first control node P to the first level, the second node control circuit 13 controls the potential of the second node QB to the first level, and the drive voltage output circuit 14 controls the drive voltage output terminal I(n) to output the initial voltage under the control of the potential of the second node QB.

[0124] In the fourth stage, the first node control circuit 11 controls the potential of the first node Q to the second level, the first control node control circuit 12 controls the potential of the first control node P, the second node control circuit 13 controls the potential of the second node QB to the first level, and the drive voltage output circuit 14 controls the drive voltage output terminal I(n) to output the initial voltage under the control of the potential of the second node QB.

[0125] In the fifth stage, the first node control circuit 11 controls the potential of the first node Q to the first level, the first control node control circuit 12 controls the potential of the first control node P, and the second node control circuit 13 controls the potential of the second node QB to the second level.

[0126] In at least one embodiment of this disclosure, such as Figure 2 As shown, in Figure 1 Based on the embodiment of the voltage supply circuit shown, the driving voltage output circuit 14 is also electrically connected to the first node Q and the third voltage terminal V3 respectively, for controlling the driving voltage output terminal I(n) to be electrically connected to the third voltage terminal V3 under the control of the potential of the first node Q.

[0127] Optionally, the third voltage terminal V3 can be a second high voltage terminal, but is not limited thereto.

[0128] This disclosure is as follows Figure 2 At least one embodiment of the voltage supply circuit shown, when in operation,

[0129] In the first stage, the second stage, and the fifth stage, the driving voltage output circuit 14 controls the connection between the driving voltage output terminal I(n) and the third voltage terminal V3 under the control of the potential of the first node Q.

[0130] like Figure 3 As shown, in Figure 1 Based on the embodiment of the voltage supply circuit shown, the voltage supply circuit described in at least one embodiment of this disclosure may further include a carry signal output circuit 30;

[0131] The carry signal output circuit 30 is electrically connected to the carry signal output terminal CR(n), the first node Q, the second node QB, the first voltage terminal V1, and the second voltage terminal V2, respectively. It is used to control the carry signal output terminal CR(n) to output a carry signal under the control of the potential of the first node Q and the potential of the second node QB, according to the first voltage signal provided by the first voltage terminal V1 and the second voltage signal provided by the second voltage terminal V2.

[0132] When the voltage providing circuit described in at least one embodiment of this disclosure is in operation, it can provide an input signal to the input terminal of the adjacent next row voltage providing circuit through the carry signal output by the row voltage providing circuit, but it is not limited thereto.

[0133] This disclosure is as follows Figure 3 At least one embodiment of the voltage supply circuit shown, when in operation,

[0134] In the first stage, the second stage and the fifth stage, the carry signal output circuit 30 controls the carry signal output terminal CR(n) to be connected to the first voltage terminal V1 under the control of the potential of the first node Q;

[0135] In the third and fourth stages, the carry signal output circuit 30 controls the carry signal output terminal CR(n) to connect with the second voltage terminal V2 under the control of the potential of the second node QB.

[0136] In at least one embodiment of this disclosure, the first node control circuit may include a second control node control sub-circuit, a first node control sub-circuit, and a first energy storage circuit;

[0137] The second control node control sub-circuit is electrically connected to the second control node, the input terminal, and the first clock signal output terminal, respectively, and is used to control the connection between the second control node and the input terminal under the control of the first clock signal;

[0138] The first terminal of the first energy storage circuit is electrically connected to the second control node, and the second terminal of the first energy storage circuit is electrically connected to the first node. The first energy storage circuit is used to store electrical energy.

[0139] The first node control sub-circuit is electrically connected to the second control node, the first node, the first voltage terminal, the first clock signal terminal, the first control node, and the second voltage terminal, respectively. It is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second control node, and to control the connection between the first node and the second voltage terminal under the control of the first clock signal and the potential of the first control node.

[0140] In a specific implementation, the first node control circuit may include a second control node control sub-circuit, a first node control sub-circuit, and a first energy storage circuit; the second control node control sub-circuit is used to control the potential of the second control node, the first energy storage circuit can be used to control the potential of the first node according to the potential of the second control node, and the first node control sub-circuit is used to control the potential of the first node.

[0141] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the voltage supply circuit shown, the first node control circuit may include a second control node control sub-circuit 41, a first node control sub-circuit 42, and a first energy storage circuit 43.

[0142] The second control node control sub-circuit 41 is electrically connected to the second control node Q1, the input terminal STU, and the first clock signal output terminal KA, respectively, and is used to control the connection between the second control node Q1 and the input terminal STU under the control of the first clock signal.

[0143] The first terminal of the first energy storage circuit 43 is electrically connected to the second control node Q1, and the second terminal of the first energy storage circuit 43 is electrically connected to the first node Q. The first energy storage circuit 43 is used to store electrical energy.

[0144] The first node control sub-circuit 42 is electrically connected to the second control node Q1, the first node Q, the first voltage terminal V1, the first clock signal terminal KA, the first control node P, and the second voltage terminal V2, respectively. It is used to control the connection between the first node Q and the first voltage terminal V1 under the control of the potential of the second control node Q1, and to control the connection between the first node Q and the second voltage terminal V2 under the control of the potential of the first clock signal and the first control node P.

[0145] Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0146] The control electrode of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0147] The control electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0148] The control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor.

[0149] The control electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal.

[0150] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the voltage supply circuit shown, the first node control circuit 11 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4;

[0151] The gate of the first transistor T1 is electrically connected to the input terminal STU, the drain of the first transistor T1 is electrically connected to the first high voltage terminal VGH, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2; the first high voltage terminal VGH is used to provide the first high voltage Vgh.

[0152] The gate of the second transistor T2 is electrically connected to the first clock signal terminal KA, and the source of the second transistor T2 is electrically connected to the first node Q.

[0153] The gate of the third transistor T3 is electrically connected to the first clock signal terminal KA, the drain of the third transistor T3 is electrically connected to the first node Q, and the source of the third transistor T3 is electrically connected to the drain of the fourth transistor T4.

[0154] The gate of the fourth transistor T4 is electrically connected to the first control node P, and the source of the fourth transistor T4 is electrically connected to the first low-voltage terminal VGL.

[0155] exist Figure 5 In at least one embodiment of the voltage supply circuit shown, T1, T2, T3 and T4 may all be NMOS (N-type metal-oxide-semiconductor) transistors, but are not limited thereto.

[0156] exist Figure 5 In at least one embodiment of the voltage supply circuit shown, the aspect ratio of T2 is greater than that of T1, so that the current passing through T1 can be amplified by T2, thereby shortening the time it takes for the potential of the first node Q to reach Vgh. For example, when the aspect ratio of T1 is 10:10, the aspect ratio of T2 can be 20:10 or 40:10, but is not limited thereto.

[0157] Optionally, the first node control circuit may further include a fifth transistor;

[0158] The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor;

[0159] The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

[0160] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the voltage supply circuit shown, the first node control circuit 11 further includes a fifth transistor T5;

[0161] The source of the second transistor T2 and the drain of the third transistor T3 are electrically connected to the first node Q through the fifth transistor T5;

[0162] The gate of the fifth transistor T5 is electrically connected to the first high-voltage terminal VGH, the drain of the fifth transistor T5 is electrically connected to the source of the second transistor T2 and the drain of the third transistor T3, and the source of the fifth transistor T5 is electrically connected to the first node Q.

[0163] The second node control circuit 13 is electrically connected to the first node Q through the fifth transistor T5.

[0164] In at least one embodiment of this disclosure, the first node control circuit 11 may further include a fifth transistor T5, the gate of which is electrically connected to a first high-voltage terminal VGH. When the first transistor T1 and the second transistor T2 included in the first node control circuit are turned off, the fifth transistor T5 can be completely turned off (when the gate-source voltage of the fifth transistor T5 is 0, the fifth transistor T5 is completely turned off) to prevent leakage current from affecting the potential of the first node Q.

[0165] Optionally, the second control node control sub-circuit includes a first transistor;

[0166] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the second control node.

[0167] The first energy storage circuit includes a first capacitor;

[0168] The first terminal of the first capacitor is electrically connected to the second control node, and the second terminal of the first capacitor is electrically connected to the first node;

[0169] The first node control sub-circuit includes a second transistor, a third transistor, and a fourth transistor;

[0170] The control electrode of the second transistor is electrically connected to the second control node, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0171] The control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor.

[0172] The control electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal.

[0173] The first node control sub-circuit also includes a fifth transistor;

[0174] The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor;

[0175] The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

[0176] Optionally, the first node control sub-circuit may further include a fifth transistor;

[0177] The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor;

[0178] The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

[0179] Optionally, the control circuit of the first control node includes a sixth transistor and a seventh transistor;

[0180] The control electrode of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage terminal or the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first control node.

[0181] The control electrode of the seventh transistor is electrically connected to the input terminal, the first electrode of the seventh transistor is electrically connected to the first control node, and the second electrode of the seventh transistor is electrically connected to the second clock signal terminal.

[0182] like Figure 7 As shown, in Figure 4 Based on at least one embodiment of the voltage supply circuit shown, the second control node control sub-circuit 41 includes a first transistor T1;

[0183] The gate of the first transistor T1 is electrically connected to the first clock signal terminal KA, the drain of the first transistor T1 is electrically connected to the input terminal STU, and the source of the first transistor T1 is electrically connected to the second control node Q1.

[0184] The first energy storage circuit 43 includes a first capacitor C1;

[0185] The first terminal of the first capacitor C1 is electrically connected to the second control node Q1, and the second terminal of the first capacitor C1 is electrically connected to the first node Q.

[0186] The first node control sub-circuit 42 includes a second transistor T2, a third transistor T3, and a fourth transistor T4;

[0187] The gate of the second transistor T2 is electrically connected to the second control node Q1, the drain of the second transistor T2 is electrically connected to the first high voltage terminal VGH, and the source of the second transistor T2 is electrically connected to the first node Q.

[0188] The gate of the third transistor T3 is electrically connected to the first clock signal terminal KA, the drain of the third transistor T3 is electrically connected to the first node Q, and the source of the third transistor T3 is electrically connected to the drain of the fourth transistor T4.

[0189] The gate of the fourth transistor T4 is electrically connected to the first control node P, and the source of the fourth transistor T4 is electrically connected to the first low-voltage terminal VGL.

[0190] exist Figure 7 In at least one embodiment of the voltage supply circuit shown, T1, T2, T3 and T4 may all be NMOS transistors, but are not limited thereto.

[0191] exist Figure 7 In at least one embodiment of the voltage supply circuit shown, the aspect ratio of T2 is greater than that of T1, so that the current passing through T1 can be amplified by T2, thereby shortening the time it takes for the potential of the first node Q to reach Vgh. For example, when the aspect ratio of T1 is 10:10, the aspect ratio of T2 can be 20:10 or 40:10, but is not limited thereto.

[0192] Optionally, the second node control circuit includes an eighth transistor, a ninth transistor, a second capacitor, and a tenth transistor;

[0193] The control electrode of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the ninth transistor.

[0194] The first terminal of the second capacitor is electrically connected to the first control node, and the second terminal of the second capacitor is electrically connected to the first electrode of the ninth transistor.

[0195] The control electrode of the ninth transistor is electrically connected to the first clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second node;

[0196] The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second node, and the second electrode of the tenth transistor is electrically connected to the second voltage terminal.

[0197] In at least one embodiment of this disclosure, the second node control circuit further includes a third capacitor;

[0198] The first terminal of the third capacitor is electrically connected to the second node, and the second terminal of the third capacitor is electrically connected to the second voltage terminal.

[0199] Optionally, the carry signal output circuit includes an eleventh transistor and a twelfth transistor;

[0200] The control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the carry signal output terminal.

[0201] The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal.

[0202] Optionally, the drive voltage output circuit includes a thirteenth transistor;

[0203] The control electrode of the thirteenth transistor is electrically connected to the second node, the first electrode of the thirteenth transistor is electrically connected to the drive voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

[0204] like Figure 8 As shown, in Figure 5 Based on at least one embodiment of the voltage supply circuit shown, the drive voltage output circuit 14 may include a thirteenth transistor T13;

[0205] The gate of the thirteenth transistor T13 is electrically connected to the second node QB, the drain of the thirteenth transistor T13 is electrically connected to the driving voltage output terminal I(n), and the source of the thirteenth transistor T13 is electrically connected to the initial voltage terminal V01.

[0206] Optionally, the drive voltage output circuit includes a thirteenth transistor, a fourteenth transistor, and a fourth capacitor;

[0207] The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the drive voltage output terminal.

[0208] The control electrode of the thirteenth transistor is electrically connected to the second node, the first electrode of the thirteenth transistor is electrically connected to the driving voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

[0209] The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the driving voltage output terminal.

[0210] like Figure 9 As shown, in Figure 7 Based on at least one embodiment of the voltage supply circuit shown, the second control node control sub-circuit 41 further includes a fifth transistor T5;

[0211] The source of the second transistor T2 and the drain of the third transistor T3 are electrically connected to the first node Q through the fifth transistor T5;

[0212] The gate of the fifth transistor T5 is electrically connected to the first high-voltage terminal VGH, the drain of the fifth transistor T5 is electrically connected to the source of the second transistor T2 and the drain of the third transistor T3, and the source of the fifth transistor T5 is electrically connected to the first node Q.

[0213] The driving voltage output circuit 14 is also electrically connected to the first node Q and the second high voltage terminal VDD, respectively, and is used to control the driving voltage output terminal I(n) to be electrically connected to the second high voltage terminal VDD under the control of the potential of the first node Q.

[0214] The drive voltage output circuit 14 may include a thirteenth transistor T13, a fourteenth transistor T14, and a fourth capacitor C4;

[0215] The gate of the fourteenth transistor T14 is electrically connected to the first node Q, the drain of the fourteenth transistor T4 is electrically connected to the second high voltage terminal VDD, and the source of the fourteenth transistor T14 is electrically connected to the driving voltage output terminal I(n).

[0216] The gate of the thirteenth transistor T13 is electrically connected to the second node Q1, the drain of the thirteenth transistor T13 is electrically connected to the driving voltage output terminal I(n), and the source of the thirteenth transistor T13 is electrically connected to the initial voltage terminal V01.

[0217] The first terminal of the fourth capacitor C4 is electrically connected to the first node Q, and the second terminal of the fourth capacitor C4 is electrically connected to the driving voltage output terminal I(n).

[0218] exist Figure 9 In at least one embodiment of the voltage supply circuit shown, the fourth capacitor C4 is used, which is connected between the first node Q and the drive voltage output terminal I(n) to improve the driving capability of I(n).

[0219] exist Figure 9In at least one embodiment of the voltage supply circuit shown, the aspect ratio of T2 is greater than that of T1, so that the current passing through T1 can be amplified by T2, thereby shortening the time for the potential of the first node Q to reach Vgh; the aspect ratio of T14 is greater than that of T2, so as to enable high current drive.

[0220] In this disclosure Figure 9 In at least one embodiment of the voltage supply circuit shown, the first node control circuit 11 may further include a fifth transistor T5, the gate of which is electrically connected to the first high voltage terminal VGH to prevent erroneous output caused by leakage of T2.

[0221] exist Figure 9 In at least one embodiment of the voltage supply circuit shown, if the fifth transistor T5 is not provided, due to the coupling effect of C4, when the driving voltage output by I(n) is high, the potential of the first node Q is also pulled high, and due to the coupling effect of C1, the potential of the second node Q1 is also pulled high. That is, both the gate potential and the source potential of T2 are high, and T2 will have the risk of leakage. Based on this, at least one embodiment of this disclosure provides a fifth transistor T5 between the first node Q and the second node Q to prevent erroneous output caused by leakage of T2.

[0222] like Figure 10 As shown, in Figure 9 Based on at least one embodiment of the voltage supply circuit shown, the first control node control circuit 12 includes a sixth transistor T6 and a seventh transistor T7;

[0223] The gate of the sixth transistor T6 is electrically connected to the second clock signal terminal KB, the drain of the sixth transistor T6 is electrically connected to the first high voltage terminal VGH, and the source of the sixth transistor T6 is electrically connected to the first control node P.

[0224] The gate of the seventh transistor T7 is electrically connected to the input terminal STU, the drain of the seventh transistor T7 is electrically connected to the first control node P, and the source of the seventh transistor T7 is electrically connected to the second clock signal terminal KB.

[0225] The second node control circuit 13 includes an eighth transistor T8, a ninth transistor T9, a second capacitor C2, and a tenth transistor T10;

[0226] The gate of the eighth transistor T8 is electrically connected to the first control node P, the drain of the eighth transistor T8 is electrically connected to the first clock signal terminal KA, and the source of the eighth transistor T8 is electrically connected to the drain of the ninth transistor T9.

[0227] The first terminal of the second capacitor C2 is electrically connected to the first control node P, and the second terminal of the second capacitor C2 is electrically connected to the drain of the ninth transistor T9.

[0228] The gate of the ninth transistor T9 is electrically connected to the first clock signal terminal KA, and the source of the ninth transistor T9 is electrically connected to the second node QB.

[0229] The gate of the tenth transistor T10 is electrically connected to the first node Q, the drain of the tenth transistor T10 is electrically connected to the second node QB, and the source of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL.

[0230] The second node control circuit 13 also includes a third capacitor C3;

[0231] The first terminal of the third capacitor C3 is electrically connected to the second node QB, and the second terminal of the third capacitor is electrically connected to the first low voltage terminal VGL.

[0232] The carry signal output circuit 30 includes an eleventh transistor T11 and a twelfth transistor T12;

[0233] The gate of the eleventh transistor T11 is electrically connected to the first node Q, the drain of the eleventh transistor T11 is electrically connected to the first high voltage terminal VGH, and the source of the eleventh transistor T11 is electrically connected to the carry signal output terminal CR(n).

[0234] The gate of the twelfth transistor T12 is electrically connected to the second node QB, the drain of the twelfth transistor T12 is electrically connected to the carry signal output terminal CR(n), and the source of the twelfth transistor T12 is electrically connected to the first low voltage terminal VGL.

[0235] exist Figure 10 In at least one embodiment of the voltage supply circuit shown, all transistors are NMOS transistors, but this is not a limitation.

[0236] At least one embodiment of the voltage supply circuit described in this disclosure is capable of providing high and low voltages in I(n) time division, reducing the number of transistors used, thereby enabling narrow bezels.

[0237] exist Figure 10 In at least one embodiment of the voltage supply circuit shown, when the potential of the second control node Q1 is high, T4 is turned on, the potential of the first terminal of C1 rises from low voltage to high voltage, and the potential of the second terminal of C1 also rises accordingly, ensuring that the potential of the first node Q is high, so that T14 can be fully turned on, thereby improving the driving capability of I(n).

[0238] exist Figure 10 In at least one embodiment of the voltage supply circuit shown, the second control node Q1 is a first-stage pull-up node, and the first node Q is a second-stage pull-up node;

[0239] Because n-type transistors experience threshold voltage loss when transmitting high voltages, if only one pull-up node is used, the potential of the pull-up node will be low, preventing the corresponding drive voltage output transistor from fully turning on, thus weakening the driving capability of I(n). Based on this, this disclosure... Figure 10 At least one embodiment of the voltage supply circuit shown employs two-stage pull-up nodes to enhance the driving capability of I(n).

[0240] In at least one embodiment of this disclosure, the voltage value of the first high voltage signal provided by the first high voltage terminal VGH may be greater than or equal to 15V and less than or equal to 20V, and the voltage value of the second high voltage signal provided by the second high voltage terminal VDD may be greater than or equal to 12V and less than or equal to 16V, but is not limited thereto.

[0241] like Figure 11 As shown, this disclosure is as follows Figure 10 When at least one embodiment of the voltage supply circuit shown is in operation, the voltage supply cycle includes a first stage S1, a second stage S2, a third stage S3, a fourth stage S4, and a fifth stage S5 arranged sequentially.

[0242] In the first stage S1, STU inputs a low voltage signal, KB provides a high voltage signal, KA provides a low voltage signal, T6 is turned on, the potential of the first control node P is high voltage, T7 is turned off, T8 is turned on, T9 is turned off, the potential of the second control node Q1 is maintained at high voltage, T2 is turned on, the potential of the first node Q is high voltage, T11 and T14 are turned on, CR(n) outputs a high voltage signal, and I(n) outputs a high voltage signal.

[0243] In the second stage S2, STU inputs a low voltage signal, KB provides a low voltage signal, KA provides a high voltage signal, T6 and T7 are turned off, the potential of the first control node P is maintained at a high voltage, T1 is turned on, the potential of the second control node Q1 is low voltage, T2 is turned off, T3 and T4 are turned on, the potential of the first node Q is low voltage, T11 and T14 are turned off, T10 is turned off, T9 is turned on to pull up the potential of the second node QB, T12 and T13 are turned on, CR(n) outputs a low voltage signal, I(n) is connected to the initial voltage terminal V01, the initial voltage terminal V01 provides a low voltage signal, and I(n) outputs a low voltage signal;

[0244] In the third stage S3, STU outputs a high voltage signal, KB provides a high voltage signal, KA provides a low voltage signal, T6 and T7 are turned on, the potential of the first control node P is high voltage, T8 is turned on, T3 and T4 are turned on to control the potential of the first node Q to be maintained at low voltage, T9 is turned on, the potential of the second node QB is high voltage, T12 and T13 are turned on, CR(n) outputs a low voltage signal, I(n) is connected to the initial voltage terminal V01, the initial voltage terminal V01 provides a low voltage signal, and I(n) outputs a low voltage signal;

[0245] In the fourth stage S4, STU outputs a high voltage signal, KB provides a low voltage signal, KA provides a low voltage signal, T7 is turned on, the first control node P is connected to KB, the potential of the first control node P is a low voltage signal, T3 and T4 are turned off, T1 is turned off, the potential of the second control node Q1 is maintained at a low voltage, T2 is turned off, the potential of the first node Q is maintained at a low voltage, T9 is turned off, the potential of the second node QB is maintained at a high voltage, T12 and T13 are turned on, CR(n) outputs a low voltage signal, I(n) is connected to the initial voltage terminal V01, the initial voltage terminal V01 provides a low voltage signal, and I(n) outputs a low voltage signal.

[0246] In the fifth stage S5, STU outputs a high voltage signal, KB provides a low voltage signal, KA provides a high voltage signal, T1 is turned on, the potential of the second control node Q1 is high voltage, T2 is turned on, the potential of the first node Q is high voltage, T11 and T14 are turned on, CR(n) outputs a high voltage signal, I(n) outputs a high voltage signal; T10 is turned on, the potential of the second node QB is low voltage, T12 and T13 are turned off; T7 is turned on, the first control node P is connected to KB, and the potential of the first control node P is low voltage.

[0247] This disclosure is as follows Figure 12 At least one embodiment of the voltage supply circuit shown is consistent with this disclosure. Figure 10 The difference in at least one embodiment of the voltage supply circuit shown is that:

[0248] The drain of T6 is electrically connected to the second clock signal terminal KB, and since the gate-source parasitic capacitance Cgs of T13 is large, the third capacitor C3 is not required.

[0249] like Figure 13 As shown, in Figure 8 Based on at least one embodiment of the voltage supply circuit shown,

[0250] The first control node control circuit 42 includes a sixth transistor T6 and a seventh transistor T7;

[0251] The gate of the sixth transistor T6 is electrically connected to the second clock signal terminal KB, the drain of the sixth transistor T6 is electrically connected to the first high voltage terminal VGH, and the source of the sixth transistor T6 is electrically connected to the first control node P.

[0252] The gate of the seventh transistor T7 is electrically connected to the input terminal STU, the drain of the seventh transistor T7 is electrically connected to the first control node P, and the source of the seventh transistor T7 is electrically connected to the second clock signal terminal KB.

[0253] The second node control circuit 13 includes an eighth transistor T8, a ninth transistor T9, a second capacitor C2, and a tenth transistor T10;

[0254] The gate of the eighth transistor T8 is electrically connected to the first control node P, the drain of the eighth transistor T8 is electrically connected to the first clock signal terminal KA, and the source of the eighth transistor T8 is electrically connected to the drain of the ninth transistor T9.

[0255] The first terminal of the second capacitor C2 is electrically connected to the first control node P, and the second terminal of the second capacitor C2 is electrically connected to the drain of the ninth transistor T9.

[0256] The gate of the ninth transistor T9 is electrically connected to the first clock signal terminal KA, and the source of the ninth transistor T9 is electrically connected to the second node QB.

[0257] The gate of the tenth transistor T10 is electrically connected to the first node Q, the drain of the tenth transistor T10 is electrically connected to the second node QB, and the source of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL.

[0258] The carry signal output circuit 30 includes an eleventh transistor T11, a twelfth transistor T12, and a fourth capacitor C4.

[0259] The gate of the eleventh transistor T11 is electrically connected to the first node Q, the drain of the eleventh transistor T11 is electrically connected to the first high voltage terminal VGH, and the source of the eleventh transistor T11 is electrically connected to the carry signal output terminal CR(n).

[0260] The gate of the twelfth transistor T12 is electrically connected to the second node QB, the drain of the twelfth transistor T12 is electrically connected to the carry signal output terminal CR(n), and the source of the twelfth transistor T12 is electrically connected to the first low voltage terminal VGL.

[0261] The first end of the fourth capacitor C4 is electrically connected to the first node Q, and the second end of the fourth capacitor C4 is electrically connected to the carry signal output terminal CR(n).

[0262] exist Figure 13 In at least one embodiment of the voltage supply circuit shown, all transistors are NMOS transistors, but this is not a limitation.

[0263] exist Figure 13 In the figure, Cgs is the gate-source parasitic capacitance of T13.

[0264] exist Figure 13 In at least one embodiment of the voltage supply circuit shown, the structure of the drive voltage output circuit 14 is simplified. The drive circuit output circuit 14 includes only a thirteenth transistor controlled by the second node QB. The drive circuit output circuit 14 is not controlled by the first node Q, which simplifies the structure of the first node control circuit 11, so that the first node control circuit 11 uses only one pull-up node.

[0265] This disclosure is as follows Figure 13 At least one embodiment of the voltage supply circuit shown can be applied to a display panel with multiplexed data lines. At least two rows of pixel circuits in the display panel share a single data line. When the data write transistor in a pixel circuit is turned on, the data line electrically connected to the data write transistor is in a floating state for a period of time. If a low voltage signal is provided at the drive voltage output terminal during this time, it will affect the potential of the second electrode of the drive transistor in the pixel circuit. Therefore, it is necessary to control the drive voltage output terminal to be in a floating state. If it is necessary to control the drive voltage output terminal to be in a floating state during a specific period, too many transistors cannot be connected to the drive voltage output terminal to reduce the parasitic capacitance connected to the same drive voltage output terminal. In this case, a thirteenth transistor can be placed in the display area, with at least two pixel circuits sharing one thirteenth transistor and one drive voltage output terminal. Alternatively, each pixel circuit can be electrically connected to one thirteenth transistor and one drive voltage output terminal to reduce the parasitic capacitance of the drive voltage output terminal.

[0266] like Figure 14 As shown, this disclosure is as follows Figure 13 When at least one embodiment of the voltage supply circuit shown is in operation, the voltage supply cycle includes a first stage S1, a second stage S2, a third stage S3, a fourth stage S4, and a fifth stage S5 arranged sequentially.

[0267] In the first stage S1, STU provides a low voltage signal, KB provides a high voltage signal, KA provides a low voltage signal, T1 is turned off, T2 is turned off, T3 is turned off, T6 is turned on, T7 is turned off, the potential of the first control node P is high voltage, T3 is turned on, T4 is turned off, the potential of the first node Q is maintained at high voltage, T10 is turned on, the potential of QB is low voltage, T11 is turned on, T12 and T13 are turned off, and CR(n) outputs a high voltage signal.

[0268] In the second stage S2, STU provides a low voltage signal, KB provides a low voltage signal, KA provides a high voltage signal, T1 is turned off, T2 is turned on, T6 and T7 are turned off, the potential of the first control node P is maintained at a high voltage, T8 and T9 are turned on, the potential of the second node QB is a high voltage, T3 is turned on, T4 is turned on, the potential of the first node Q is a low voltage; T11 is turned off, T12 and T13 are turned on, CR(n) outputs a low voltage signal, I(n) is connected to the initial voltage terminal V01, V01 provides a low voltage signal, and I(n) outputs a low voltage signal;

[0269] In the third stage S3, STU provides a high voltage signal, KB provides a high voltage signal, KA provides a low voltage signal, T1 is turned on, T2 is turned off, T6 is turned on, T7 is turned on, the potential of the first control node P is high voltage, T8 is turned on, T9 is turned off, the potential of the first node Q is maintained at low voltage, the potential of the second node QB is maintained at high voltage, T11 is turned off, T12 and T13 are turned on, CR(n) outputs a low voltage signal, I(n) is connected to the initial voltage terminal V01, V01 provides a low voltage signal, and I(n) outputs a low voltage signal.

[0270] In the fourth stage S4, STU provides a high voltage signal, KB provides a low voltage signal, KA provides a low voltage signal, T1 is on, T2 is off, T3 is off, the potential of the first node Q is maintained at a low voltage, T6 is off, T7 is on, the potential of the first control node P is low voltage, T8 is off, T9 is off, T4 is off, the potential of the first node Q is maintained at a low voltage, the potential of the second node QB is maintained at a high voltage, T11 is off, T12 and T13 are on, CR(n) outputs a low voltage signal, I(n) is connected to the initial voltage terminal V01, V01 provides a low voltage signal, and I(n) outputs a low voltage signal.

[0271] In the fifth stage S5, STU provides a high voltage signal, KB provides a low voltage signal, KA provides a high voltage signal, T1 is turned on, T2 is turned on, the potential of the first node Q is high voltage, T7 is turned on, the first control node P is connected to KB, the potential of the first control node P is low voltage, T8 is turned off, T9 is turned on, T10 is turned on, the potential of the second node QB is low voltage, T11 is turned on, T12 and T13 are turned off, and CR(n) outputs a high voltage signal.

[0272] This disclosure is as follows Figure 13 At least one embodiment of the voltage supply circuit shown requires connection with Figure 24 At least one embodiment of the pixel circuit shown is used in conjunction with it. Figure 24 At least one embodiment of the pixel circuit shown includes a driving control circuit, which includes a driving control transistor T04; the gate of the driving control transistor T04 is electrically connected to the light emission control line E1, the source of the driving control transistor T04 is electrically connected to the second high voltage terminal VDD, and the source of the driving control transistor T04 is electrically connected to the driving voltage output terminal I(n); when the light emission control line E1 controls T04 to conduct, the second high voltage terminal VDD and I(n) are connected.

[0273] This disclosure is as follows Figure 15 At least one embodiment of the voltage supply circuit shown is consistent with this disclosure. Figure 13 The difference in at least one embodiment of the voltage supply circuit shown is that:

[0274] The first node control circuit 11 also includes a fifth transistor T5;

[0275] The source of the second transistor T2 and the drain of the third transistor T3 are electrically connected to the first node Q through the fifth transistor T5;

[0276] The gate of the fifth transistor T5 is electrically connected to the first high-voltage terminal VGH, the drain of the fifth transistor T5 is electrically connected to the source of the second transistor T2 and the drain of the third transistor T3, and the source of the fifth transistor T5 is electrically connected to the first node Q. In this disclosure as... Figure 15 In at least one embodiment of the voltage supply circuit shown, the first node control circuit 11 may further include a fifth transistor T5, the gate of which is electrically connected to the first high voltage terminal VGH. When the first transistor T1 and the second transistor T2 included in the first node control circuit 11 are turned off, the fifth transistor T5 can be completely turned off (when the gate-source voltage of the fifth transistor T5 is 0, the fifth transistor T5 is completely turned off) to prevent leakage current from affecting the potential of the first node Q.

[0277] This disclosure is as follows Figure 16 At least one embodiment of the voltage supply circuit shown is consistent with this disclosure. Figure 10 The difference between at least one embodiment of the voltage supply circuit shown is that: this disclosure is as follows Figure 16 At least one embodiment of the voltage supply circuit shown also includes a fifteenth transistor T15;

[0278] The gate of the fifteenth transistor T15 is connected to the set control terminal S01, the drain of the fifteenth transistor T15 is electrically connected to the first high voltage terminal VGH, and the source of the fifteenth transistor T15 is electrically connected to the first node Q.

[0279] exist Figure 16 In at least one embodiment of the voltage supply circuit shown, T15 is an NMOS transistor, but is not limited thereto.

[0280] This disclosure is as follows Figure 16 In at least one embodiment of the voltage supply circuit shown, when the display panel is first turned on, the set control terminal S01 can provide a high voltage signal to control T15 to conduct, so as to set the voltage of the first node Q to a high voltage, and control the potential of the second node QB to a low voltage through T10, thereby ensuring the normal use of the voltage supply circuit.

[0281] In at least one embodiment of this disclosure, in Figure 12 , Figure 13 , Figure 15 Based on at least one embodiment of the voltage supply circuit shown, the fifteenth transistor T15 can be added to set the potential of the first node Q and the potential of the second node QB when the display panel is first turned on.

[0282] The voltage supply method described in this embodiment is applied to the voltage supply circuit described above. The voltage supply cycle includes a first stage, a second stage, a third stage, a fourth stage, and a fifth stage set sequentially. The voltage supply method includes:

[0283] In the first stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node to the first level, and the second node control circuit controls the potential of the second node to the second level.

[0284] In the second stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node.

[0285] In the third stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node.

[0286] In the fourth stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the second level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node.

[0287] In the fifth stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node, and the second node control circuit controls the potential of the second node to the second level.

[0288] In at least one embodiment of this disclosure, the first level can be a high level and the second level can be a low level, but is not limited thereto.

[0289] Optionally, the driving voltage output circuit is also electrically connected to the first node and the third voltage terminal respectively, and the voltage supply method further includes:

[0290] In the first stage and the fifth stage, the driving voltage output circuit controls the connection between the driving voltage output terminal and the third voltage terminal under the control of the potential of the first node.

[0291] In at least one embodiment of this disclosure, the voltage providing circuit further includes a carry signal output circuit; the voltage providing method may further include:

[0292] In the first stage and the fifth stage, the carry signal output circuit controls the connection between the carry signal output terminal and the first voltage terminal under the control of the potential of the first node;

[0293] In the second, third, and fourth stages, the carry signal output circuit controls the connection between the carry signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0294] The voltage supply module described in this embodiment includes multiple stages of the voltage supply circuit described above;

[0295] The voltage supply circuit includes a carry signal output terminal;

[0296] The carry signal output terminal of the voltage supply circuit is electrically connected to the input terminal of the adjacent next-stage voltage supply circuit, and is used to provide an input signal to the input terminal of the adjacent next-stage voltage supply circuit.

[0297] like Figure 17 As shown, the voltage supply module described in this embodiment includes a multi-stage voltage supply circuit;

[0298] exist Figure 17In the diagram, P1 represents the first-stage voltage supply circuit, P2 represents the second-stage voltage supply circuit, PN-1 represents the (N-1)th-stage voltage supply circuit, and PN represents the Nth-stage voltage supply circuit, where N is an integer greater than 2.

[0299] The terminal labeled KA is the first clock signal terminal, and the terminal labeled KB is the second clock signal terminal;

[0300] The terminal labeled STU is the input terminal, and the input terminal of the first-stage voltage supply circuit P1 is connected to the start signal STV;

[0301] The terminal labeled CR(1) is the first-level carry signal output terminal, the terminal labeled CR(2) is the second-level carry signal output terminal, and the terminal labeled CR(N-1) is the N-1th-level carry signal output terminal.

[0302] The terminal labeled IN(1) is the first drive voltage output terminal, the terminal labeled IN(2) is the second drive voltage output terminal, the terminal labeled IN(N-1) is the (N-1)th drive voltage output terminal, and the terminal labeled IN(N) is the Nth drive voltage output terminal.

[0303] The input terminal of the second-stage voltage supply circuit P2 is electrically connected to CR(1), and the input terminal of the Nth-stage voltage supply circuit PN is electrically connected to CR(N-1).

[0304] like Figure 18 As shown, in Figure 17 Based on at least one embodiment of the voltage supply module shown, a set control terminal S01 is added; each voltage supply circuit is electrically connected to the set control terminal S01.

[0305] The display device described in this disclosure includes the voltage supply module described above.

[0306] The display device described in at least one embodiment of this disclosure may further include a multi-row, multi-column pixel circuit; the pixel circuit includes a light-emitting element and a driving circuit, a data writing circuit, an initialization circuit, and a second energy storage circuit.

[0307] The first terminal of the driving circuit is electrically connected to the driving voltage output terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element. The driving circuit is used to generate a current to drive the light-emitting element to emit light under the control of the potential at its control terminal.

[0308] The voltage supply module includes a voltage supply circuit that is electrically connected to the drive voltage output terminal, and is used to provide drive voltage to the drive voltage output terminal;

[0309] The data writing circuit is electrically connected to the scan line, the data line and the control terminal of the driving circuit, respectively, and is used to control the writing of the data voltage on the data line to the control terminal of the driving circuit under the control of the scan signal provided by the scan line.

[0310] The initialization circuit is electrically connected to the initialization control line, the reference voltage terminal, and the control terminal of the drive circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the control terminal of the drive circuit under the control of the initialization control signal provided by the initialization control line.

[0311] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy.

[0312] In at least one embodiment of this disclosure, the pixel circuit may include a light-emitting element and a driving circuit, a data writing circuit, an initialization circuit, and a second energy storage circuit; the data writing circuit performs data voltage writing, the initialization circuit is used to initialize the potential of the control terminal of the driving circuit, and the driving circuit is used to generate a current to drive the light-emitting element to emit light.

[0313] like Figure 19 As shown, at least one embodiment of the pixel circuit may include a light-emitting element 190, a driving circuit 191, a data writing circuit 192, an initialization circuit 193, and a second energy storage circuit 194.

[0314] The first terminal of the driving circuit 191 is electrically connected to the driving voltage output terminal I(n), and the second terminal of the driving circuit 191 is electrically connected to the light-emitting element 190. The driving circuit 191 is used to generate a current to drive the light-emitting element 190 to emit light under the control of the potential of its control terminal.

[0315] The voltage supply module includes a voltage supply circuit that is electrically connected to the drive voltage output terminal I(n) and is used to provide drive voltage to the drive voltage output terminal I(n);

[0316] The data writing circuit 192 is electrically connected to the scan line G1, the data line D1 and the control terminal of the driving circuit 191, respectively, and is used to control the data voltage on the data line D1 to be written to the control terminal of the driving circuit 191 under the control of the scan signal provided by the scan line G1.

[0317] The initialization circuit 193 is electrically connected to the initialization control line G2, the reference voltage terminal R1, and the control terminal of the driving circuit 191, respectively, and is used to write the reference voltage Vr provided by the reference voltage terminal R1 into the control terminal of the driving circuit 191 under the control of the initialization control signal provided by the initialization control line G2.

[0318] The second energy storage circuit 194 is electrically connected to the control terminal of the drive circuit 191 and is used to store electrical energy.

[0319] In at least one embodiment of this disclosure, the light-emitting element may be an organic light-emitting diode, but is not limited thereto.

[0320] This disclosure provides a pixel circuit suitable for extremely high PPI (pixel density) and capable of internal compensation, particularly suitable for medium and large-sized OLED (organic light-emitting diode) displays.

[0321] The transistors in the pixel circuit of the display device described in this embodiment can all be NMOS (N-type metal-oxide-semiconductor) transistors, and the NMOS process can be used, which is simple.

[0322] like Figure 19 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase, a compensation phase, a data writing phase, and a light emission phase that are set sequentially.

[0323] During the initialization phase, I(n) provides a low voltage signal, and the initialization circuit 193, under the control of the initialization control signal, writes the reference voltage Vr into the control terminal of the drive circuit 191.

[0324] During the compensation phase, I(n) provides a high voltage signal. Under the control of the initialization control signal, the initialization circuit 193 writes the reference voltage Vr into the control terminal of the driving circuit 191, so that the driving transistor included in the driving circuit 191 can be turned on. VDD charges the second energy storage circuit 193 through the turned-on driving transistor until the potential of the second terminal of the driving circuit 191 becomes Vr-Vth, where Vth is the threshold voltage of the driving transistor.

[0325] During the data writing phase, under the control of the scanning signal, the data writing circuit 192 writes the data voltage Vdata on the data line D1 to the control terminal of the driving circuit 191, and the potential of the second terminal of the driving circuit 191 is maintained at Vr-Vth.

[0326] During the light-emitting stage, the data writing circuit 191 stops writing data voltage values ​​to the control terminal of the driving circuit 191, and the driving circuit 191 drives the light-emitting element 190 to emit light.

[0327] like Figure 20 As shown, in Figure 19Based on at least one embodiment of the pixel circuit shown, the light-emitting element is an organic light-emitting diode O1; the driving circuit 191 includes a driving transistor T03, the data writing circuit 192 includes a data writing transistor T01, the initialization circuit 193 includes an initialization transistor T02, and the second energy storage circuit 194 includes a storage capacitor C0.

[0328] The gate of T01 is electrically connected to the scan line G1, the drain of T01 is electrically connected to the data line D1, and the source of T01 is electrically connected to the gate of T03.

[0329] The gate of T02 is electrically connected to the initialization control line G2, the drain of T02 is electrically connected to the reference voltage terminal R1, and the source of T02 is electrically connected to the gate of T03.

[0330] The drain of T03 is electrically connected to the drive voltage output terminal I(n), and the source of T03 is electrically connected to the anode of O1.

[0331] The cathode of O1 is grounded.

[0332] exist Figure 20 In at least one embodiment of the pixel circuit shown, T01, T02 and T03 can be n-type transistors, but are not limited thereto.

[0333] like Figure 20 At least one embodiment of the pixel circuit shown can be the nth row pixel circuit of the display panel, where n is a positive integer.

[0334] like Figure 21 As shown, Figure 20 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase t1, a compensation phase t2, a data writing phase t3, and a light emission phase t4 that are set sequentially.

[0335] During the initialization phase t1, G1 provides a low voltage signal, G2 provides a high voltage signal, I(n) provides a low voltage signal, T01 is turned off, and T02 is turned on, so that the reference voltage Vr provided by R1 is written into the gate of T03.

[0336] During the compensation phase t2, G1 provides a low voltage signal, G2 provides a high voltage signal, I(n) provides a high voltage signal, T01 is turned off, and T02 is turned on, so that the reference voltage Vr provided by R1 is written into the gate of T03. T03 is turned on, and VDD charges C0 through T03 to raise the potential of the gate of T03 until the potential of the gate of T03 becomes Vr-Vth, where Vth is the threshold voltage of T03.

[0337] During the data writing phase t3, I(n) provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, T01 is turned on, and the data line D1 provides the data voltage Vdata to write the data voltage Vdata to the gate of T03. The potential of the source of T03 is maintained at Vr-Vth (due to the large intrinsic capacitance of O1, the coupling effect of C0 is negligible during data voltage writing).

[0338] During the light-emitting stage t4, I(n) provides a high voltage signal, G1 provides a low voltage signal, G2 provides a low voltage signal, and T03 drives O1 to emit light. At this time, the gate-source voltage of T03 is Vgs = Vdata - Vr + Vth, so the driving current of T03 is independent of Vth.

[0339] exist Figure 21 In the diagram, G1(n+1) corresponds to the scan signal provided by the (n+1)th scan line, and G2(n+1) corresponds to the initialization control signal provided by the (n+1)th initialization control line.

[0340] exist Figure 22 The leftmost pixel circuit included in the nth row of pixel circuits is shown, as well as the rightmost pixel circuit included in the nth row of pixel circuits.

[0341] exist Figure 22 In the diagram, the data line labeled D01 is the first column of data lines, the data line labeled D0M is the Mth column of data lines, where M is an integer greater than 1; the data line labeled Vr is the reference voltage.

[0342] exist Figure 22 In the diagram, A1 is the voltage supply circuit, A2 is the scan signal generation circuit, and A3 is the initialization control signal generation circuit. The voltage supply circuit A1 is used to provide the driving voltage to I(n). The scan signal generation circuit A2 is electrically connected to G1 and is used to provide the scan signal. The initialization control signal generation circuit A3 is electrically connected to G2 and is used to provide the initialization control signal.

[0343] Optionally, the pixel circuit further includes a driving control circuit; the driving control circuit is electrically connected to the light emission control line, the first terminal and the fourth voltage terminal of the driving circuit respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal into the first terminal of the driving circuit under the control of the light emission control signal provided by the light emission control line.

[0344] In at least one embodiment of this disclosure, the fourth voltage terminal may be a second high voltage terminal, but is not limited thereto.

[0345] like Figure 23 As shown, in Figure 20Based on at least one embodiment of the pixel circuit shown, the at least one embodiment of the pixel circuit further includes a drive control circuit 230;

[0346] The drive control circuit 230 is electrically connected to the light-emitting control line E1, the first terminal and the second high-voltage terminal VDD of the drive circuit 191, respectively, and is used to write the second high-voltage signal provided by the second high-voltage terminal VDD into the first terminal of the drive circuit 191 under the control of the light-emitting control signal provided by the light-emitting control line E1.

[0347] In a specific implementation, the drive control circuit may include a drive control transistor;

[0348] The control electrode of the driving control transistor is electrically connected to the light-emitting control line, the first electrode of the driving control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving control transistor is electrically connected to the fourth voltage terminal.

[0349] like Figure 24 As shown, in Figure 23 Based on at least one embodiment of the pixel circuit shown, the drive control circuit 230 includes a drive control transistor T04;

[0350] The gate of T04 is electrically connected to the light-emitting control line E1, the drain of T04 is electrically connected to the drain of T03, and the source of T04 is electrically connected to the second high-voltage terminal VDD.

[0351] exist Figure 24 In at least one embodiment of the pixel circuit shown, T01, T02, T03 and T04 are all n-type transistors, but are not limited thereto.

[0352] like Figure 24 At least one embodiment of the pixel circuit shown can be the nth row pixel circuit of the display panel, where n is a positive integer.

[0353] When including such Figure 24 When the display panel of at least one embodiment of the pixel circuit shown is in operation, the display panel includes at least two columns of pixel circuits that can share a data line. When the data writing transistor in the pixel circuit is turned on, the data line electrically connected to the data writing transistor is in a floating state for a period of time. If the driving voltage output terminal provides a low voltage signal at this time, it will affect the potential of the second pole of the driving transistor in the pixel circuit. Therefore, it is necessary to control the driving voltage output terminal to be in a floating state.

[0354] like Figure 25 As shown, this disclosure is as follows Figure 24When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase t1, a compensation phase t2, a data writing phase t3, and a light emission phase t4 that are set sequentially.

[0355] During the initialization phase t1, G1 provides a low voltage signal, G2 provides a high voltage signal, I(n) provides a low voltage signal, T01 is turned off, and T02 is turned on, so that the reference voltage Vr provided by R1 is written into the gate of T03; E1 provides a low voltage signal, and T04 is turned off.

[0356] During the compensation phase t2, G1 provides a low voltage signal, G2 provides a high voltage signal, E1 provides a high voltage signal, T04 is turned on, the drain of T03 is connected to VDD, I(n) provides a high voltage signal, T01 is turned off, T02 is turned on, so that the reference voltage Vr provided by R1 is written into the gate of T03, T03 is turned on, VDD charges C0 through T03 to raise the potential of the gate of T03 until the potential of the gate of T03 becomes Vr-Vth, where Vth is the threshold voltage of T03;

[0357] During the data writing phase t3, G1 provides a high voltage signal, G2 provides a low voltage signal, E1 provides a low voltage signal, I(n) is in a floating state, T01 is turned on, and the data line D1 provides the data voltage Vdata to write the data voltage Vdata to the gate of T03. The potential of the source of T03 is maintained at Vr-Vth (due to the large intrinsic capacitance of O1, the coupling effect of C0 is negligible during data voltage writing).

[0358] During the light-emitting stage t4, E1 provides a high voltage signal, T04 is turned on, the drain of T03 is connected to VDD, I(n) provides a high voltage signal, G1 provides a low voltage signal, G2 provides a low voltage signal, and T03 drives O1 to emit light. At this time, the gate-source voltage of T03 is Vgs = Vdata - Vr + Vth, so the driving current of T03 is independent of Vth.

[0359] exist Figure 25 During the time period corresponding to the middle slash, I(n) and I(n+1) can be in a floating state, but this is not a limitation.

[0360] exist Figure 25 In the diagram, G1(n+1) corresponds to the scan signal provided by the (n+1)th scan line, G2(n+1) corresponds to the initialization control signal provided by the (n+1)th initialization control line, E1(n+1) is the (n+1)th light emission control line, and I(n+1) is the (n+1)th drive voltage output terminal.

[0361] In at least one embodiment of this disclosure, the nth-level voltage supply circuit in the voltage supply module may include at least two thirteenth transistors and at least two nth-level drive voltage output terminals, wherein the at least two thirteenth transistors and the pixel circuit are both disposed in the display area; the devices in the nth-level voltage supply circuit, except for the thirteenth transistors, are disposed in the peripheral area; n is a positive integer;

[0362] The control electrode of the thirteenth transistor is electrically connected to the corresponding second node, the first electrode of the thirteenth transistor is electrically connected to the corresponding nth stage drive voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

[0363] Each of the nth-level driving voltage output terminals is electrically connected to the first terminal of the driving circuit included in at least one pixel circuit located in the nth row, for providing a corresponding nth-level driving voltage to the first terminal of the driving circuit included in at least one pixel circuit located in the nth row.

[0364] In a specific implementation, the voltage supply circuit, including the thirteenth transistor and the driving voltage output terminal, can be located in the display area. At least two pixel circuits share a thirteenth transistor and a driving voltage output terminal. Alternatively, each pixel circuit can be electrically connected to a thirteenth transistor and a driving voltage output terminal to reduce the parasitic capacitance of the driving voltage output terminal. This allows the display panel to function normally when the driving voltage output terminal is in a floating state.

[0365] Optionally, the driving circuit includes a driving transistor, the data writing circuit includes a data writing transistor, the initialization circuit includes an initialization transistor, the second energy storage circuit includes a storage capacitor, and the driving control circuit includes a driving control transistor.

[0366] The control electrode of the data writing transistor is electrically connected to the scan line, the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the control electrode of the driving transistor.

[0367] The control electrode of the initialization transistor is electrically connected to the initialization control line, the first electrode of the initialization transistor is electrically connected to the reference voltage terminal, and the second electrode of the initialization transistor is electrically connected to the control electrode of the driving transistor.

[0368] The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the storage capacitor is electrically connected to the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the fourth voltage terminal.

[0369] The first terminal of the driving transistor is electrically connected to the driving voltage output terminal, and the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element;

[0370] The control electrode of the driving control transistor is electrically connected to the light-emitting control line, the first electrode of the driving control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving control transistor is electrically connected to the fourth voltage terminal.

[0371] The driving transistor, the data writing transistor, the initialization transistor, and the driving control transistor are all n-type transistors.

[0372] like Figure 26 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P12 is the first row and second column, and the pixel circuit labeled P1M is the first row and Mth column, where M is an integer greater than 1.

[0373] The pixel circuit labeled P21 is the first pixel circuit in the second row, the second pixel circuit in the second row, the second pixel circuit in the second row, and the pixel circuit labeled P2M is the Mth pixel circuit in the second row.

[0374] The pixel circuit labeled PN1 is the first pixel circuit in the Nth row, the second pixel circuit in the Nth row, and the pixel circuit labeled PNM is the first pixel circuit in the Nth row; N is an integer greater than 2.

[0375] exist Figure 26 In the diagram, A11 is the first GOA (Gate On Array, a gate drive circuit disposed on the array substrate), A12 is the second GOA circuit, and 260 is the display panel.

[0376] The terminal labeled I(1) is the first row drive voltage output terminal, the terminal labeled I(2) is the second drive voltage output terminal, and the terminal labeled I(N) is the Nth row drive voltage output terminal.

[0377] The first scan line is labeled G1(1), the second scan line is labeled G1(2), and the Nth scan line is labeled G1(N).

[0378] The first row of initialization control lines is labeled G2(1), the second row of initialization control lines is labeled G2(2), and the Nth row of initialization control lines is labeled G2(N).

[0379] The first GOA circuit A11 and the second GOA circuit A12 provide the first row driving voltage for I(1), the second row driving voltage for I(2), the Nth row driving voltage for I(N), the first row scanning signal for G1(1), the second row scanning signal for G1(2), the Nth row scanning signal for G1(N), the first row initialization control signal for G2(1), the second row initialization control signal for G2(2), and the Nth row initialization control signal for G2(N).

[0380] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0381] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A voltage supply circuit, characterized in that, It includes a first node control circuit, a first control node control circuit, a second node control circuit, and a drive voltage output circuit, wherein, The first node control circuit is electrically connected to the first node, the input terminal, the first clock signal terminal, the first control node, the first voltage terminal, and the second voltage terminal, respectively. It is used to control the potential of the first node according to the first voltage signal provided by the first voltage terminal and the second voltage signal provided by the second voltage terminal, under the control of the input signal provided by the input terminal, the first clock signal provided by the first clock signal terminal, and the potential of the first control node. The first control node control circuit is electrically connected to the first control node, the input terminal, and the second clock signal terminal, respectively, and is used to control the potential of the first control node under the control of the second clock signal provided by the second clock signal terminal and the input signal. The second node control circuit is electrically connected to the second node, the first control node, the first clock signal terminal, the first node, and the second voltage terminal, respectively, and is used to control the potential of the second node according to the first clock signal and the second voltage signal under the control of the potential of the first node, the potential of the first control node, and the first clock signal. The driving voltage output circuit is electrically connected to the second node, the driving voltage output terminal, and the initial voltage terminal, respectively, and is used to control the driving voltage output terminal to output a driving voltage according to the initial voltage provided by the initial voltage terminal under the control of the potential of the second node; The voltage supply cycle includes a first stage, a second stage, a third stage, a fourth stage, and a fifth stage, set sequentially. In the first stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node to the first level, and the second node control circuit controls the potential of the second node to the second level. In the second stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node. In the third stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node. In the fourth stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the second level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node. In the fifth stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node, and the second node control circuit controls the potential of the second node to the second level.

2. The voltage supply circuit as described in claim 1, characterized in that, The driving voltage output circuit is also electrically connected to the first node and the third voltage terminal respectively, and is used to control the driving voltage output terminal to be electrically connected to the third voltage terminal under the control of the potential of the first node.

3. The voltage supply circuit as described in claim 1 or 2, characterized in that, It also includes a carry signal output circuit; The carry signal output circuit is electrically connected to the carry signal output terminal, the first node, the second node, the first voltage terminal, and the second voltage terminal, respectively, and is used to control the carry signal output terminal to output a carry signal according to the first voltage signal and the second voltage signal under the control of the potential of the first node and the potential of the second node.

4. The voltage supply circuit as described in claim 1 or 2, characterized in that, The first node control circuit includes a second control node control sub-circuit, a first node control sub-circuit, and a first energy storage circuit; The second control node control sub-circuit is electrically connected to the second control node, the input terminal, and the first clock signal output terminal, respectively, and is used to control the connection between the second control node and the input terminal under the control of the first clock signal; The first terminal of the first energy storage circuit is electrically connected to the second control node, and the second terminal of the first energy storage circuit is electrically connected to the first node. The first energy storage circuit is used to store electrical energy. The first node control sub-circuit is electrically connected to the second control node, the first node, the first voltage terminal, the first clock signal terminal, the first control node, and the second voltage terminal, respectively. It is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second control node, and to control the connection between the first node and the second voltage terminal under the control of the first clock signal and the potential of the first control node.

5. The voltage supply circuit as described in claim 1 or 2, characterized in that, The first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal.

6. The voltage supply circuit as described in claim 5, characterized in that, The first node control circuit also includes a fifth transistor; The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor; The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

7. The voltage supply circuit as described in claim 4, characterized in that, The second control node control sub-circuit includes a first transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the second control node. The first energy storage circuit includes a first capacitor; The first terminal of the first capacitor is electrically connected to the second control node, and the second terminal of the first capacitor is electrically connected to the first node; The first node control sub-circuit includes a second transistor, a third transistor, and a fourth transistor; The control electrode of the second transistor is electrically connected to the second control node, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal.

8. The voltage supply circuit as described in claim 7, characterized in that, The first node control sub-circuit also includes a fifth transistor; The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first node through the fifth transistor; The control electrode of the fifth transistor is electrically connected to the first voltage terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the fifth transistor is electrically connected to the first node.

9. The voltage supply circuit as described in claim 1 or 2, characterized in that, The control circuit of the first control node includes a sixth transistor and a seventh transistor; The control electrode of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage terminal or the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first control node. The control electrode of the seventh transistor is electrically connected to the input terminal, the first electrode of the seventh transistor is electrically connected to the first control node, and the second electrode of the seventh transistor is electrically connected to the second clock signal terminal.

10. The voltage supply circuit as described in claim 1 or 2, characterized in that, The second node control circuit includes an eighth transistor, a ninth transistor, a second capacitor, and a tenth transistor; The control electrode of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the ninth transistor. The first terminal of the second capacitor is electrically connected to the first control node, and the second terminal of the second capacitor is electrically connected to the first electrode of the ninth transistor. The control electrode of the ninth transistor is electrically connected to the first clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second node; The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second node, and the second electrode of the tenth transistor is electrically connected to the second voltage terminal.

11. The voltage supply circuit as claimed in claim 10, characterized in that, The second node control circuit also includes a third capacitor; The first terminal of the third capacitor is electrically connected to the second node, and the second terminal of the third capacitor is electrically connected to the second voltage terminal.

12. The voltage supply circuit as described in claim 3, characterized in that, The carry signal output circuit includes an eleventh transistor, a twelfth transistor, and a fourth capacitor; The control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the carry signal output terminal. The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal.

13. The voltage supply circuit as claimed in claim 1, characterized in that, The drive voltage output circuit includes a thirteenth transistor; The control electrode of the thirteenth transistor is electrically connected to the second node, the first electrode of the thirteenth transistor is electrically connected to the drive voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal.

14. The voltage supply circuit as described in claim 2, characterized in that, The drive voltage output circuit includes a thirteenth transistor, a fourteenth transistor, and a fourth capacitor; The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the drive voltage output terminal. The control electrode of the thirteenth transistor is electrically connected to the second node, the first electrode of the thirteenth transistor is electrically connected to the driving voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal. The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the driving voltage output terminal.

15. A voltage supply method, applied to a voltage supply circuit as described in any one of claims 1 to 14, characterized in that, The voltage supply cycle includes a first stage, a second stage, a third stage, a fourth stage, and a fifth stage set sequentially; the voltage supply method includes: In the first stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node to the first level, and the second node control circuit controls the potential of the second node to the second level. In the second stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node. In the third stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the first level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node. In the fourth stage, the first node control circuit controls the potential of the first node to the second level, the first control node control circuit controls the potential of the first control node to the second level, the second node control circuit controls the potential of the second node to the first level, and the drive voltage output circuit controls the drive voltage output terminal to output the initial voltage under the control of the potential of the second node. In the fifth stage, the first node control circuit controls the potential of the first node to the first level, the first control node control circuit controls the potential of the first control node, and the second node control circuit controls the potential of the second node to the second level.

16. The voltage supply method as described in claim 15, characterized in that, The driving voltage output circuit is also electrically connected to the first node and the third voltage terminal respectively, and the voltage supply method further includes: In the first stage and the fifth stage, the driving voltage output circuit controls the connection between the driving voltage output terminal and the third voltage terminal under the control of the potential of the first node.

17. The voltage supply method as described in claim 15, characterized in that, The voltage providing circuit further includes a carry signal output circuit; the voltage providing method further includes: In the first stage and the fifth stage, the carry signal output circuit controls the connection between the carry signal output terminal and the first voltage terminal under the control of the potential of the first node; In the second, third, and fourth stages, the carry signal output circuit controls the connection between the carry signal output terminal and the second voltage terminal under the control of the potential of the second node.

18. A voltage supply module, characterized in that, Includes multiple stages of voltage supply circuitry as described in any one of claims 1 to 14; The voltage supply circuit includes a carry signal output terminal; The carry signal output terminal of the voltage supply circuit is electrically connected to the input terminal of the adjacent next-stage voltage supply circuit, and is used to provide an input signal to the input terminal of the adjacent next-stage voltage supply circuit.

19. A display device, characterized in that, Includes the voltage supply module as described in claim 18.

20. The display device as claimed in claim 19, characterized in that, It also includes a multi-row, multi-column pixel circuit; the pixel circuit includes a light-emitting element and driving circuit, a data writing circuit, an initialization circuit, and a second energy storage circuit. The first terminal of the driving circuit is electrically connected to the driving voltage output terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element. The driving circuit is used to generate a current to drive the light-emitting element to emit light under the control of the potential at its control terminal. The voltage supply module includes a voltage supply circuit that is electrically connected to the drive voltage output terminal, and is used to provide drive voltage to the drive voltage output terminal; The data writing circuit is electrically connected to the scan line, the data line and the control terminal of the driving circuit, respectively, and is used to control the writing of the data voltage on the data line to the control terminal of the driving circuit under the control of the scan signal provided by the scan line. The initialization circuit is electrically connected to the initialization control line, the reference voltage terminal, and the control terminal of the drive circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the control terminal of the drive circuit under the control of the initialization control signal provided by the initialization control line. The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy.

21. The display device as described in claim 20, characterized in that, The pixel circuit further includes a driving control circuit; the driving control circuit is electrically connected to the light emission control line, the first terminal and the fourth voltage terminal of the driving circuit respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal into the first terminal of the driving circuit under the control of the light emission control signal provided by the light emission control line.

22. The display device as claimed in claim 20 or 21, characterized in that, The nth-level voltage supply circuit in the voltage supply module includes at least two thirteenth transistors and at least two nth-level drive voltage output terminals. The at least two thirteenth transistors and the pixel circuit are both located in the display area. The components in the nth-level voltage supply circuit, excluding the thirteenth transistors, are all located in the peripheral area. n is a positive integer. The control electrode of the thirteenth transistor is electrically connected to the corresponding second node, the first electrode of the thirteenth transistor is electrically connected to the corresponding nth stage drive voltage output terminal, and the second electrode of the thirteenth transistor is electrically connected to the initial voltage terminal. Each of the nth-level driving voltage output terminals is electrically connected to the first terminal of the driving circuit included in at least one pixel circuit located in the nth row, for providing a corresponding nth-level driving voltage to the first terminal of the driving circuit included in at least one pixel circuit located in the nth row.

23. The display device as claimed in claim 21, characterized in that, The driving circuit includes a driving transistor, the data writing circuit includes a data writing transistor, the initialization circuit includes an initialization transistor, the second energy storage circuit includes a storage capacitor, and the driving control circuit includes a driving control transistor. The control electrode of the data writing transistor is electrically connected to the scan line, the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the control electrode of the driving transistor. The control electrode of the initialization transistor is electrically connected to the initialization control line, the first electrode of the initialization transistor is electrically connected to the reference voltage terminal, and the second electrode of the initialization transistor is electrically connected to the control electrode of the driving transistor. The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the storage capacitor is electrically connected to the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the fourth voltage terminal. The first terminal of the driving transistor is electrically connected to the driving voltage output terminal, and the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element; The control electrode of the driving control transistor is electrically connected to the light-emitting control line, the first electrode of the driving control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving control transistor is electrically connected to the fourth voltage terminal.

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