A driving circuit and its driving method, and a display device.

Abstract

This application provides a driving circuit and driving method thereof, as well as a display device, relating to the field of display technology. The driving circuit includes multiple shift registers arranged in cascade. Each shift register includes an input module, an output module, a pull-up module, a pull-down module, a reset module, and an adjustment module. Under the control of the voltage of the fourth node, the reset module can reset the output terminal of the shift register. The adjustment module can pull down the voltage of the fourth node, thereby improving the reset speed of the reset module at the output terminal and improving the driving capability of the shift register.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and driving method thereof, and a display device. Background Technology

[0002] Gate Driver On Array (GOA) is a technology that integrates gate driving circuitry onto an array substrate. The gate driving circuitry includes multiple shift registers, each corresponding to a row of gate lines, and these shift registers sequentially output scan signals. With the rapid development of display technology, gate driving circuitry technology has matured, and the industry's requirements for the driving performance of the shift registers within the gate driving circuitry are becoming increasingly stringent. Summary of the Invention

[0003] The embodiments of this application adopt the following technical solutions:

[0004] In a first aspect, embodiments of this application provide a driving circuit, including: a plurality of shift registers cascaded together, the shift registers including:

[0005] The pull-down module is electrically connected to the trigger signal input terminal, the first clock signal line, the second clock signal line, the first level signal line, the first node, and the second node, respectively. The pull-down module is configured to pull down the voltage of the first node under the control of the voltage of the second node.

[0006] The input module is electrically connected to the first clock signal line, the trigger signal input terminal, and the third node, respectively, and is configured to transmit the signal input from the trigger signal input terminal to the third node under the control of the signal input from the first clock signal line.

[0007] A pull-up module is electrically connected to the first node, the first level signal line, and the control terminal, respectively. The pull-up module is configured to pull up the voltage of the first node under the control of the control terminal.

[0008] The output module is electrically connected to the first node, the first level signal line, and the output terminal of the shift register, respectively. Under the control of the voltage of the first node, the output module transmits the signal input from the first level signal line to the output terminal.

[0009] A reset module is electrically connected to the third node, the second level signal line, and the fourth node, respectively. The reset module is configured to transmit the signal input from the second level signal line to the output terminal under the control of the voltage of the fourth node, so as to reset the output terminal.

[0010] The adjustment module is electrically connected to the first node, the fourth node, the fifth node, the first level signal line, and the control clock signal line, respectively. The adjustment module is configured to assist the reset module in resetting the output terminal under the control of the voltage of the fifth node.

[0011] In at least one embodiment of this application, both the first level signal line and the second level signal line transmit signals with constant voltage, and the voltage of the signal transmitted by the first level signal line is greater than the voltage of the signal transmitted by the second level signal line.

[0012] In at least one embodiment of this application, the control terminal includes the trigger signal input terminal;

[0013] Alternatively, the control terminal may include the third node, and the pull-up module may be electrically connected to the input module through the third node.

[0014] In at least one embodiment of this application, the pull-down module includes a first transistor, a second transistor, a third transistor, and a first capacitor;

[0015] The gate of the first transistor is electrically connected to the second node, the source of the first transistor is electrically connected to the first clock signal line, and the drain of the first transistor is electrically connected to the first node; the source of the second transistor and the source of the third transistor are respectively electrically connected to the first level signal line, the drain of the second transistor and the drain of the third transistor are respectively electrically connected to the second node, the gate of the second transistor is electrically connected to the trigger signal input terminal, and the gate of the third transistor is electrically connected to the second clock signal line; the first electrode of the first capacitor is electrically connected to the source of the first transistor, and the second electrode of the first capacitor is electrically connected to the second node.

[0016] In at least one embodiment of this application, the input module includes a fourth transistor, the gate of the fourth transistor being electrically connected to the first clock signal line, the source of the fourth transistor being electrically connected to the trigger signal input terminal, and the drain of the fourth transistor being electrically connected to the third node.

[0017] In at least one embodiment of this application, the pull-up module includes a fifth transistor, the source of which is electrically connected to the first node, and the drain of which is electrically connected to the first level signal line.

[0018] The gate of the fifth transistor is electrically connected to the third node; or the gate of the fifth transistor is electrically connected to the trigger signal input terminal.

[0019] In at least one embodiment of this application, the reset module includes a sixth transistor, a seventh transistor, and a second capacitor. The gate of the sixth transistor is electrically connected to the second level signal line, the source of the sixth transistor is electrically connected to the third node, and the drain of the sixth transistor is electrically connected to the fourth node. The gate of the seventh transistor is electrically connected to the fourth node, the source of the seventh transistor is electrically connected to the output terminal, and the drain of the seventh transistor is electrically connected to the second level signal line. The first electrode of the second capacitor is electrically connected to the fourth node, and the second electrode of the second capacitor is electrically connected to the output terminal.

[0020] In at least one embodiment of this application, the output module includes an eighth transistor and a third capacitor. The gate of the eighth transistor is electrically connected to the first node, the source of the eighth transistor is electrically connected to the first level signal line, and the drain of the eighth transistor is electrically connected to the output terminal. The first electrode of the third capacitor is electrically connected to the first node, and the second electrode of the third capacitor is electrically connected to the first level signal line.

[0021] In at least one embodiment of this application, the adjustment module includes a ninth transistor, a tenth transistor, and a fourth capacitor. The gate of the ninth transistor is electrically connected to the first node, the source of the ninth transistor is electrically connected to the first level signal line, and the drain of the ninth transistor is electrically connected to the fifth node. The gate of the tenth transistor is electrically connected to the fourth node, the source of the tenth transistor is electrically connected to the fifth node, and the drain of the tenth transistor is electrically connected to the control clock signal line.

[0022] In at least one embodiment of this application, the control clock signal line includes a third clock signal line and a fourth clock signal line, the third clock signal line being electrically connected to the drain of the tenth transistor in the odd-numbered shift register, and the fourth clock signal line being electrically connected to the drain of the tenth transistor in the even-numbered shift register.

[0023] The first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge of the fourth clock signal transmitted by the fourth clock signal line is delayed by the first preset time period relative to the first signal edge of the second clock signal transmitted by the second clock signal line. The first signal edge includes a rising edge or a falling edge.

[0024] In at least one embodiment of this application, the control clock signal line includes a third clock signal line, and the third clock signal line is electrically connected to the drain of the tenth transistor in each stage of the shift register;

[0025] The period and pulse width of the first clock signal transmitted by the first clock signal line are 2N times that of the third clock signal transmitted by the third clock signal line, where N is a positive integer; the first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge includes a rising edge or a falling edge.

[0026] In at least one embodiment of this application, the control clock signal line includes the first clock signal line.

[0027] In at least one embodiment of this application, the first preset time period includes 0 to 2 μs.

[0028] In at least one embodiment of this application, all of the transistors are P-type transistors.

[0029] Secondly, embodiments of this application provide a display device including a driving circuit as described in any one of the first aspects, and further including a plurality of sub-pixels arranged in an array, wherein each sub-pixel includes a pixel driving circuit, and a shift register is electrically connected to each of the pixel driving circuits in the same row of sub-pixels.

[0030] Thirdly, implementation of this application provides a driving method applied to a driving circuit as described in any one of the first aspects; the method includes:

[0031] During the input phase, a high-level trigger signal is input to the trigger signal input terminal electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line, a low-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a high-level control clock signal is input to the control clock signal line.

[0032] During the output phase, a high-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line.

[0033] During the reset phase, a low-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line.

[0034] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0037] Figures 2-4 Schematic diagrams of the circuit structures of three shift registers provided for embodiments of this application;

[0038] Figures 5-7 A schematic diagram showing the electrical connection relationship of multiple shift registers in three driving circuits provided for embodiments of this application;

[0039] Figure 8 for Figure 2 The corresponding timing diagram;

[0040] Figure 9 A comparison diagram of the reset time curves of a shift register and related shift registers provided for embodiments of this application;

[0041] Figure 10 for Figure 3 The corresponding timing diagram;

[0042] Figure 11A for Figure 2 The circuit structure shown and Figure 3 A comparison of the current variation curves of the seventh transistor T7 in the circuit structure shown.

[0043] Figure 11B for Figure 2 The circuit structure shown and Figure 3 A comparison of the current variation curves of the eighth transistor T8 in the circuit structure shown.

[0044] Figures 12-17 for Figure 2 The circuit structure shown is in Figure 8 The diagram shown illustrates the component states during the timing-driven process. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0047] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0048] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate a particular feature, structure, material, or characteristic associated with that embodiment or example, including at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0049] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0051] In embodiments of this application, the term "electrical connection" may refer to a direct electrical connection between two components, or an electrical connection between two components via one or more other components.

[0052] In the embodiments of this application, since the source and drain of the transistor are symmetrical, their source and drain can be interchanged.

[0053] To ensure high-frequency charging of each sub-pixel in the display product and to compensate for the uneven brightness caused by insufficient threshold voltage (Vth) of the driving transistor, related technologies employ methods such as... Figure 1 The pixel driving circuit (9T2C) shown is used to improve this, wherein, as Figure 1 The pixel driving circuit shown requires an AZn signal to drive the second transistor M2, the sixth transistor M6, and the seventh transistor M7. The main function of the second transistor M2 is to control the compensation time of the threshold voltage (Vth) of the driving transistor (M8). The AZn signal is provided by the shift register (GOA) circuit. At this time, the driving capability of the GOA that provides the AZn signal is particularly important.

[0054] However, the GOA used to provide the AZn signal in the related technology has a slow reset speed during reset, which affects the control of the compensation time of the threshold voltage (Vth) of the driving transistor (M8) by the second transistor M2 in the pixel driving circuit. This may cause differences in the compensation time of the threshold voltage (Vth) in each pixel. When applied to display products, this may result in uneven display brightness and reduce the display effect.

[0055] Therefore, embodiments of this application urgently need to provide a shift register (GOA) circuit that can be quickly reset in order to improve the display problem caused by the slow reset speed of the GOA.

[0056] Embodiments of this application provide a driving circuit, such as Figure 5 , Figure 6 or Figure 7 As shown, it includes: multiple shift registers (GOA) arranged in cascade; wherein, for the first-stage shift register (GOA1), a first scan signal G[1] can be output according to a trigger signal (e.g., STV signal) and a clock signal (at least including CK and CB signals). The first scan signal G[1] output by the first-stage shift register serves as the input signal of the second-stage shift register. Similarly, for the second-stage and subsequent shift registers, the scan signal output by the previous-stage shift register serves as the input signal of the subsequent-stage shift register (i.e., this signal serves as the trigger signal). The second-stage and subsequent shift registers (GOA2, GOA3...GOAN) output the scan signal of their respective shift registers according to the scan signal output by the previous-stage shift register and the received clock signal, wherein the output terminal of a shift register is electrically connected to at least one gate line to input the corresponding scan signal into the gate line.

[0057] In practical applications, only the trigger signal of the first-stage shift register (GOA1) is the STV signal. At this time, the first-stage shift register (GOA1) and the STV signal line are electrically connected. The trigger signals of each subsequent shift register are the scan signals output by the previous stage shift register.

[0058] In some embodiments of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the shift register includes:

[0059] Pull-down module 1 is electrically connected to the trigger signal input terminal (e.g., STV signal input terminal), the first clock signal line CK line, the second clock signal line CB line, the first level signal line VGH line, the first node PU, and the second node PU-c, respectively. Pull-down module 1 is configured to pull down the voltage of the first node PU under the control of the voltage of the second node PU-c.

[0060] Input module 2 is electrically connected to the first clock signal line CK, the trigger signal input terminal and the third node PD-in respectively, and is configured to transmit the signal input from the trigger signal input terminal to the third node PD-in under the control of the signal input from the first clock signal line CK.

[0061] Pull-up module 3 is electrically connected to the first node PU, the first level signal line VGH, and the control terminal, respectively. Pull-up module 3 is configured to pull up the voltage of the first node PU under the control of the control terminal.

[0062] Output module 5 is electrically connected to the first node PU, the first level signal line VGH, and the output terminal Gout of the shift register, respectively. Under the control of the voltage of the first node PU, output module 5 transmits the signal input from the first level signal line VGH to the output terminal Gout.

[0063] The reset module 4 is electrically connected to the third node PD-in, the second level signal line VGL, and the fourth node PD-out respectively. The reset module 4 is configured to transmit the signal input from the second level signal line VGL to the output terminal Gout under the control of the voltage of the fourth node PD-out, so as to reset the output terminal Gout.

[0064] The adjustment module 6 is electrically connected to the first node PU, the fourth node PD-out, the fifth node PD-c, the first level signal line VGH, and the control clock signal line, respectively. The adjustment module 6 is configured to assist the reset module 4 in resetting the output terminal Gout under the control of the voltage of the fifth node PD-c.

[0065] The specific circuit structures included in the pull-down module 1, input module 2, pull-up module 3, output module 5, reset module 4, and adjustment module 6 are not limited here. As long as they meet the corresponding functions, they are all within the scope of the drive circuit protection provided in the embodiments of this application.

[0066] The first node PU, the second node PU-c, the third node PD-in, the fourth node PD-out, and the fifth node PD-c mentioned above are defined only for the convenience of describing the circuit structure. The first node PU, the second node PU-c, the third node PD-in, the fourth node PD-out, and the fifth node PD-c are not the actual circuit structure.

[0067] In at least one embodiment of this application, the control terminal includes a trigger signal input terminal (e.g., an STV terminal).

[0068] In an exemplary embodiment, such as Figure 3 and Figure 4 As shown, the pull-up module 3 is electrically connected to the first node PU, the first level signal line VGH, and the trigger signal input terminal (e.g., STV terminal), respectively. The pull-up module 3 is configured to pull up the voltage of the first node PU under the control of the voltage of the third node PD-in.

[0069] In other embodiments, the control terminal includes a third node PD-in, and the pull-up module 3 is electrically connected to the input module 2 through the third node PD-in.

[0070] In an exemplary embodiment, such as Figure 2 As shown, the pull-up module 3 is electrically connected to the first node PU, the first level signal line VGH, and the third node PD-in, respectively. The pull-up module 3 is configured to pull up the voltage of the first node PU under the control of the voltage of the third node PD-in.

[0071] In an exemplary embodiment, such as Figure 4 As shown, the adjustment module 6 is electrically connected to the first node PU, the fourth node PD-out, the fifth node PD-c, the first level signal line VGH, and the first clock signal line CK, respectively. The adjustment module 6 is configured to pull down the voltage of the fourth node PD-out under the control of the voltage of the fifth node PD-c.

[0072] In an exemplary embodiment, such as Figure 2 and Figure 3As shown, the adjustment module 6 is electrically connected to the first node PU, the fourth node PD-out, the fifth node PD-c, the first level signal line VGH, and the third clock signal line CK2. The adjustment module 6 is configured to pull down the voltage of the fourth node PD-out under the control of the voltage of the fifth node PD-c. At this time, an additional third clock signal line CK2 needs to be set in the display device; wherein, the period and pulse width of the clock signal transmitted by the third clock signal line CK2 can be the same as the period and pulse width of the clock signal transmitted by the first clock signal line CK.

[0073] In the driving circuit provided in the embodiments of this application, by setting up a pull-down module 1, an input module 2, a pull-up module 3, an output module 5, a reset module 4, and an adjustment module 6 to cooperate with each other, on the one hand, scanning signals can be output sequentially to control the pixel scanning line by line in the array substrate; on the other hand, during the driving process of the driving circuit, when the reset module 4 resets the output terminal Gout of the shift register, the adjustment module 6 can quickly pull down the voltage of the fourth node PD-out, so that the reset module 4 can quickly transmit the signal input from the second level signal line VGL line to the output terminal Gout under the control of the voltage of the fourth node PD-out, so as to reset the output terminal Gout, thereby improving the reset speed of the output terminal Gout of the shift register, thereby improving the driving capability of the shift register. When this driving circuit is combined with such Figure 1 When the pixel driving circuit shown is used in conjunction with the array substrate, it can greatly reduce the difference in compensation time of the pixel driving circuit in each sub-pixel, thereby making the charging rate of each sub-pixel tend to be the same, improving the uniformity of display brightness and improving the display effect.

[0074] In at least one embodiment of this application, both the first level signal line VGH and the second level signal line VGL transmit signals with constant voltage, and the voltage of the signal transmitted by the first level signal line VGH is greater than the voltage of the signal transmitted by the second level signal line VGL.

[0075] The voltage of the signals transmitted by the first level signal line VGH and the second level signal line VGL is not limited here; it can be designed according to the product type.

[0076] In at least one embodiment of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the pull-down module 1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1;

[0077] The gate of the first transistor T1 is electrically connected to the second node PU-c, the source of the first transistor T1 is electrically connected to the first clock signal line CK, and the drain of the first transistor T1 is electrically connected to the first node PU. The sources of the second transistor T2 and the third transistor T3 are electrically connected to the first level signal line VGH, respectively. The drains of the second transistor T2 and the third transistor T3 are electrically connected to the second node PU-c, respectively. The gate of the second transistor T2 is electrically connected to the trigger signal input terminal (e.g., the STV terminal), and the gate of the third transistor T3 is electrically connected to the second clock signal line CB. The first electrode of the first capacitor C1 is electrically connected to the source of the first transistor T1, and the second electrode of the first capacitor C1 is electrically connected to the second node PU-c.

[0078] It should be noted that for the second transistor T2 in the first-stage shift register, its gate and trigger signal input terminal (e.g., STV terminal) are electrically connected; for shift registers after the first stage, its gate and trigger signal input terminal (e.g., the output terminal Gout of the previous stage shift register) are electrically connected.

[0079] In at least one embodiment of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the input module 2 includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the first clock signal line CK, the source of the fourth transistor T4 is electrically connected to the trigger signal input terminal (e.g., STV terminal), and the drain of the fourth transistor T4 is electrically connected to the third node PD-in.

[0080] It should be noted that for the fourth transistor T4 in the first-stage shift register, its source is electrically connected to the trigger signal input terminal (e.g., the STV terminal); for shift registers after the first stage, its source is electrically connected to the trigger signal input terminal (e.g., the output terminal Gout of the previous stage shift register).

[0081] In at least one embodiment of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the pull-up module 3 includes a fifth transistor T5, the source of the fifth transistor T5 is electrically connected to the first node PU, and the drain of the fifth transistor T5 is electrically connected to the first level signal line VGH.

[0082] Among them, such as Figure 2 As shown, the gate of the fifth transistor T5 is electrically connected to the third node PD-in; or, the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal (e.g., the STV terminal).

[0083] In an exemplary embodiment, when the gate of the fifth transistor T5 is electrically connected to the third node PD-in, the fifth transistor T5 is turned on or off under the control of the voltage of the third node PD-in; when the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal (e.g., the STV terminal), the fifth transistor T5 is turned on or off under the control of the signal transmitted from the trigger signal input terminal (e.g., the STV terminal).

[0084] Specifically, when the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal, for the fifth transistor T5 in the first-stage shift register, the trigger signal input terminal is the STV terminal; for shift registers after the first stage, the trigger signal input terminal is the output terminal Gout of the previous stage shift register.

[0085] In the embodiments of this application, when the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal (e.g., the STV terminal), the voltage of the first node PU can be pulled up in advance through the STV signal, the eighth transistor T8 is turned off first, and then the seventh transistor T7 is turned on. This avoids the possibility that the first level signal line VGH and the second level signal line VGL may be turned on simultaneously through the seventh transistor T7 and the eighth transistor T8, which can greatly reduce the power consumption of the shift register.

[0086] In at least one embodiment of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the reset module 4 includes a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The gate of the sixth transistor T6 is electrically connected to the second-level signal line VGL, the source of the sixth transistor T6 is electrically connected to the third node PD-in, and the drain of the sixth transistor T6 is electrically connected to the fourth node PD-out. The gate of the seventh transistor T7 is electrically connected to the fourth node PD-out, the source of the seventh transistor T7 is electrically connected to the output terminal Gout, and the drain of the seventh transistor T7 is electrically connected to the second-level signal line VGL. The first electrode of the second capacitor C2 is electrically connected to the fourth node PD-out, and the second electrode of the second capacitor C2 is electrically connected to the output terminal Gout.

[0087] In at least one embodiment of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the output module 5 includes an eighth transistor T8 and a third capacitor C3. The gate of the eighth transistor T8 is electrically connected to the first node PU, the source of the eighth transistor T8 is electrically connected to the first level signal line VGH, and the drain of the eighth transistor T8 is electrically connected to the output terminal Gout. The first electrode of the third capacitor C3 is electrically connected to the first node PU, and the second electrode of the third capacitor C3 is electrically connected to the first level signal line VGH.

[0088] In at least one embodiment of this application, such as Figure 2 , Figure 3 and Figure 4 As shown, the adjustment module 6 includes a ninth transistor T9, a tenth transistor T10, and a fourth capacitor C4. The gate of the ninth transistor T9 is electrically connected to the first node PU, the source of the ninth transistor T9 is electrically connected to the first level signal line VGH, and the drain of the ninth transistor T9 is electrically connected to the fifth node PD-c. The gate of the tenth transistor T10 is electrically connected to the fourth node PD-out, the source of the tenth transistor T10 is electrically connected to the fifth node PD-c, and the drain of the tenth transistor T10 is electrically connected to the control clock signal line.

[0089] In at least one embodiment of this application, such as Figure 5 As shown, the control clock signal lines include the third clock signal line CK2 and the fourth clock signal line CB2, combined with... Figure 2 or Figure 3 As shown, the third clock signal line CK2 is electrically connected to the drain of the tenth transistor T10 in the odd-level shift register, and the fourth clock signal line CB2 is electrically connected to the drain of the tenth transistor T10 in the even-level shift register.

[0090] The first signal edge of the third clock signal transmitted on the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted on the first clock signal line. The first signal edge of the fourth clock signal transmitted on the fourth clock signal line is delayed by a first preset time period relative to the first signal edge of the second clock signal transmitted on the second clock signal line. The first signal edge includes a rising edge or a falling edge.

[0091] In some embodiments, the rising edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to the rising edge of the first clock signal CK transmitted by the first clock signal line CK, and the rising edge of the fourth clock signal CB2 transmitted by the fourth clock signal line CB2 is delayed by a first preset time period relative to the rising edge of the second clock signal CB transmitted by the second clock signal line CB.

[0092] In other embodiments, reference is made to Figure 10 The markings at the bold dashed lines indicate that the falling edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to the falling edge of the first clock signal CK transmitted by the first clock signal line CK; and the falling edge of the fourth clock signal CB2 transmitted by the fourth clock signal line CB2 is delayed by a first preset time period relative to the falling edge of the second clock signal CB transmitted by the second clock signal line CB.

[0093] It should be noted that in a PMOS circuit, the falling edge determines the reset start time, while in an NMOS circuit, the rising edge determines the reset start time.

[0094] For example, such as Figure 8 and Figure 10 In the timing diagram shown, the third clock signal CK2 transmitted on the third clock signal line CK2 has the same period and pulse width as the first clock signal CK transmitted on the first clock signal line CK. Similarly, the fourth clock signal CB2 transmitted on the fourth clock signal line CB2 has the same period and pulse width as the second clock signal CB transmitted on the second clock signal line CB. Alternatively, the third clock signal CK2 transmitted on the third clock signal line CK2 has a different period and pulse width than the first clock signal CK transmitted on the first clock signal line CK. Likewise, the fourth clock signal CB2 transmitted on the fourth clock signal line CB2 has a different period and pulse width than the second clock signal CB transmitted on the second clock signal line CB.

[0095] In an exemplary embodiment, taking an odd-level shift register as an example, the third clock signal line CK2 is electrically connected to the drain of the tenth transistor T10 in the odd-level shift register; as shown... Figure 2 As shown, during the reset process of the shift register, the fourth transistor T4 is turned on by the control of the first clock signal CK, the signal input to the second level signal line VGL controls the sixth transistor T6 to turn on, and the trigger signal input to the trigger signal input terminal (e.g., the STV signal input terminal) can pull down the voltage of the fourth node PD-out, thereby controlling the seventh transistor T7 to turn on, and resetting (pulling down) the output terminal Gout through the seventh transistor T7. However, during the pull-down process, the seventh transistor T7 may have a threshold voltage Vth decay, and cannot quickly pull down the voltage of the output terminal Gout to the level of the VGL line. In the embodiment of this application, by setting a third clock signal CK2 that is slightly delayed relative to the first clock signal CK, the voltage of the fourth node PD-out is further pulled down through the coupling effect of the tenth transistor T10 and the fourth capacitor C4, extending the time for pulling down the voltage of the fourth node PD-out, thereby enabling the output terminal Gout to be quickly reset through the turn-on of the seventh transistor T7, and improving the driving capability of the shift register.

[0096] In an exemplary embodiment, taking an even-level shift register as an example, the fourth clock signal line CB2 is electrically connected to the drain of the tenth transistor T10 in the even-level shift register. During the reset process of the shift register, the fourth transistor T4 is turned on by the control of the second clock signal CB, the signal input to the second level signal line VGL controls the sixth transistor T6 to turn on, and the trigger signal input to the trigger signal input terminal (e.g., the STV signal input terminal) can pull down the voltage of the fourth node PD-out, thereby controlling the seventh transistor T7 to turn on, and resetting (pulling down) the output terminal Gout through the seventh transistor T7; however, During the pull-down process, the seventh transistor T7 may experience threshold voltage Vth decay, which may prevent it from quickly pulling the output voltage Gout down to the level of the VGL line. In the embodiments of this application, by setting a fourth clock signal CB2 that is slightly delayed relative to the second clock signal CB, the voltage of the fourth node PD-out is further pulled down through the coupling effect of the tenth transistor T10 and the fourth capacitor C4, thus extending the time for pulling down the voltage of the fourth node PD-out. This allows for a rapid reset of the output Gout through the conduction of the seventh transistor T7, improving the driving capability of the shift register.

[0097] like Figure 9 As shown, this application provides the following: Figure 2 The diagram shows a comparison of the reset curves of shift registers in the present invention and those in related technologies. The curve marked "Ref" represents the reset process curve of a shift register in related technologies, while the curve marked "A" represents that of this application. Figure 2 As shown in the reset time curve of the shift register, it can be clearly seen that the reset time of the output terminal Gout of the shift register provided in the embodiment of this application is significantly improved. Through simulation calculation, it can be found that the reset time of the output terminal Gout of the shift register can be reduced from 1.13 microseconds to about 0.58 microseconds, and the reset time is shortened by nearly half.

[0098] It should be noted that, as Figure 5 As shown, in even-numbered GOAs, the corresponding CK and CB signal lines are swapped relative to those in odd-numbered GOAs, thus making the driving process identical for each GOA level. For a detailed explanation, please refer to the relevant technical documentation on shift register cascading settings; it will not be repeated here.

[0099] In at least one embodiment of this application, such as Figure 6 As shown, the control clock signal line includes the third clock signal line CK2, and the drain of the tenth transistor T10 in each level of shift register (odd level GOA and even level GOA) is electrically connected.

[0100] The period and pulse width of the first clock signal CK transmitted by the first clock signal line CK are 2N times that of the third clock signal CK2 transmitted by the third clock signal line CK2, where N is a positive integer, typically 1.

[0101] The first signal edge of the third clock signal CK2 transmitted on the third clock signal line CK2 is delayed by a first preset time period relative to the first signal edge of the first clock signal CK transmitted on the first clock signal line CK.

[0102] For example, the first signal edge can be either a rising edge or a falling edge.

[0103] In some embodiments, the rising edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to the rising edge of the first clock signal CK transmitted by the first clock signal line CK.

[0104] In other embodiments, the falling edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to the falling edge of the first clock signal CK transmitted by the first clock signal line CK.

[0105] For example Figure 2 Or such as Figure 3 The specific circuit structure of the shift register shown is such that the drain of the tenth transistor T10 in each level of the shift register (odd level GOA and even level GOA) is electrically connected; and the rising edge of the third clock signal CK2 transmitted by the third clock signal CK2 is delayed by a first preset time period relative to the rising edge of the first clock signal CK transmitted by the first clock signal CK.

[0106] Thus, during the reset process of the shift register, the fourth transistor T4 is turned on by the control of the first clock signal CK, the signal input to the second level signal line VGL controls the sixth transistor T6 to turn on, and the trigger signal input to the trigger signal input terminal (e.g., the STV signal input terminal) can pull down the voltage of the fourth node PD-out, thereby controlling the seventh transistor T7 to turn on, and resetting (pulling down) the output terminal Gout through the seventh transistor T7; however, during the pull-down process, the seventh transistor T7 may have a threshold voltage Vth decay, and cannot quickly pull down the voltage of the output terminal Gout to the level of the VGL line; in the embodiment of this application, by setting a third clock signal CK2 that is slightly delayed relative to the first clock signal CK, the voltage of the fourth node PD-out is further pulled down through the coupling effect of the tenth transistor T10 and the fourth capacitor C4, prolonging the time to pull down the voltage of the fourth node PD-out, thereby enabling the output terminal Gout to be quickly reset through the turn-on of the seventh transistor T7, improving the driving capability of the shift register. In addition, compared to setting 4 clock signal lines, this embodiment only requires 3 clock signal lines, which can free up the design space of the peripheral area of ​​the array substrate, thus facilitating the fabrication of narrow bezel display products.

[0107] In at least one embodiment of this application, combined with Figure 4 and Figure 7 As shown, the control clock signal line includes a first clock signal line CK. That is, the drain of the tenth transistor T10 is electrically connected to the first clock signal line CK. In this way, while ensuring that the reset time of the shift register is shortened compared to the shift registers in related technologies, the design space of the peripheral area of ​​the array substrate can be greatly freed up, which is beneficial to the fabrication of narrow bezel display products.

[0108] In at least one embodiment of this application, the first preset time period includes 0 to 2 μs.

[0109] For example, the first preset time period can be 0μs, 0.5μs, 0.8μs, 1μs, 1.3μs, 1.5μs, or 1.8μs. The specific time of the first preset time period is determined by the load of the gate line and the capacitance of the capacitor inside the shift register, and can be set according to the actual situation.

[0110] In at least one embodiment of this application, all transistors are P-type transistors.

[0111] For example, all transistors can be MOS transistors, where MOS is an abbreviation for MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0112] Embodiments of this application provide a display device including the driving circuit as described above, and further including a plurality of sub-pixels arranged in an array. Each sub-pixel includes a pixel driving circuit, and a shift register is electrically connected to each pixel driving circuit in the same row of sub-pixels through a gate line.

[0113] The display device provided in the embodiments of this application, by setting up a pull-down module 1, an input module 2, a pull-up module 3, an output module 5, a reset module 4, and an adjustment module 6 to cooperate with each other, can, on the one hand, sequentially output scanning signals to control the pixel in the array substrate to scan line by line; on the other hand, during the driving process of the driving circuit, when the reset module 4 resets the output terminal Gout of the shift register, the adjustment module 6 can quickly pull down the voltage of the fourth node PD-out, so that the reset module 4 can, under the control of the voltage of the fourth node PD-out, quickly transmit the signal input of the second level signal line VGL line to the output terminal Gout to reset the output terminal Gout, thereby improving the reset speed of the output terminal Gout of the shift register, thereby improving the driving capability of the shift register, and can greatly reduce the difference in the compensation time of the pixel driving circuit in each sub-pixel, so that the charging rate of each sub-pixel tends to be the same, improving the uniformity of the display brightness of the display device and improving the display effect.

[0114] This application provides a driving method applied to the driving circuit described above, the driving method comprising:

[0115] S801. During the input phase, a high-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK, a low-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a high-level control clock signal is input to the control clock signal line.

[0116] S802. In the output stage, a high-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK, a high-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a low-level control clock signal is input to the control clock signal line.

[0117] S803. During the reset phase, a low-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK, a high-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a low-level control clock signal is input to the control clock signal line.

[0118] The driving method of the driving circuit provided in the embodiments of this application, during the driving process of the driving circuit, when the reset module 4 resets the output terminal Gout of the shift register, the adjustment module 6 can quickly pull down the voltage of the fourth node PD-out, so that the reset module 4 can quickly transmit the signal input of the second level signal line VGL line to the output terminal Gout under the control of the voltage of the fourth node PD-out, so as to reset the output terminal Gout, thereby improving the reset speed of the output terminal Gout of the shift register, thereby improving the driving capability of the shift register, and can greatly reduce the difference in the compensation time of the pixel driving circuit in each sub-pixel, so that the charging rate of each sub-pixel tends to be the same, improving the uniformity of the display brightness of the display device and improving the display effect.

[0119] The following is based on Figure 2 Taking the circuit diagram shown as an example, and assuming that all transistors are P-type transistors, the driving principle and driving process of this driving circuit will be explained in detail.

[0120] Figure 8 Provided Figure 2 The timing sequence corresponding to the circuit diagram in the middle. Figures 12-17 They provided Figure 2 The circuit diagram in Figure 8 The circuit states at different stages of the timing sequence are shown. It should be noted that... Figures 12-17 The symbol “H” indicates that the input signal is a high-level signal, and the symbol “L” indicates that the input signal is a low-level signal. The transistor is turned off by “×” and turned on by “√”.

[0121] In the first stage t1 (input stage), combined Figure 2 and Figure 8As shown, a high-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK, a low-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a high-level control clock signal is input to the control clock signal line (third clock signal line CK2).

[0122] At this time, as Figure 12 As shown, the second node PU-c is pulled high by the first capacitor C1, the first transistor T1 is cut off, the second transistor T2 is cut off, the third transistor T3 is turned on, the fourth transistor T4 is cut off, the fifth transistor T5 is turned on, the voltage of the first node PU is pulled high, the eighth transistor T8 is cut off, the ninth transistor T9 is cut off, the seventh transistor T7 is turned on, the tenth transistor T10 is turned on, and the output terminal Gout maintains a low level signal. This process is a lead shift process.

[0123] In the second stage t2 (output stage), combined with Figure 2 and Figure 8 As shown, a high-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK, a high-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a low-level control clock signal is input to the control clock signal line (third clock signal line CK2).

[0124] At this time, as Figure 13 As shown, the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. The voltage of the first node PU is pulled low, the eighth transistor T8 and the ninth transistor T9 are turned on, and the voltages of the third node PD-in and the fourth node PD-out are both pulled high. At this time, the first level signal line VGH transmits a high-level signal to the output terminal Gout through the eighth transistor T8.

[0125] In the third stage t3, combined with Figure 2 and Figure 8As shown, a high-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK, a low-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a high-level control clock signal is input to the control clock signal line (third clock signal line CK2).

[0126] At this time, as Figure 14 As shown, the first transistor T1 is off, the second transistor T2 is off, the third transistor T3 is on, the fourth transistor T4 is off, the fifth transistor T5 is on, the sixth transistor T6 is on, and the seventh transistor T7 is off. The voltage of the first node PU remains low, the eighth transistor T8 and the ninth transistor T9 are on, and the tenth transistor T10 is off. The output terminal Gout maintains a high-level output signal.

[0127] In stage t4, combined with Figure 2 and Figure 8 As shown, a high-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal) electrically connected to the shift register, a low-level first clock signal is input to the first clock signal line CK, a high-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a low-level control clock signal is input to the control clock signal line (third clock signal line CK2).

[0128] At this time, as Figure 15 As shown, the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. The voltage of the first node PU remains low. The eighth transistor T8 and the ninth transistor T9 are turned on. The voltages of the third node PD-in and the fourth node PD-out both remain high. At this time, the output terminal Gout maintains a high-level output signal.

[0129] In stage 5 (t5), combined with Figure 2 and Figure 8As shown, a low-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK, a low-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a high-level control clock signal is input to the control clock signal line (third clock signal line CK2).

[0130] At this time, as Figure 16 As shown, the first transistor T1 is off, the second transistor T2 is on, the third transistor T3 is on, the fourth transistor T4 is off, the fifth transistor T5 is off, the sixth transistor T6 is on, and the seventh transistor T7 is off. The voltage of the first node PU remains low, the eighth transistor T8 and the ninth transistor T9 are on, and the tenth transistor T10 is off. The output terminal Gout maintains a high-level output signal.

[0131] In the sixth stage t6 (reset stage), a low-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK, a high-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a low-level control clock signal is input to the control clock signal line (e.g., the third clock signal line CK2).

[0132] At this time, as Figure 17 As shown, the first transistor T1 is off, the second transistor T2 is on, the third transistor T3 is off, the fourth transistor T4 is on, and the fifth transistor T5 is on. The voltage of the first node PU is pulled high. The eighth transistor T8 and the ninth transistor T9 are off, the sixth transistor T6 is on, and the seventh transistor T7 is on. The voltages of the third node PD-in and the fourth node PD-out are both pulled low. The tenth transistor is on. Under the coupling effect of the fourth capacitor C4, the voltage of the fourth node PD-out is further pulled low. When the rising edge of the signal input to the control clock signal line (e.g., the third clock signal line CK2) is delayed by a first preset time relative to the rising edge of the signal input to the first clock signal line CK, the time for pulling down the voltage of the fourth node PD-out is extended, causing the voltage of the fourth node PD-out to drop rapidly. This helps to quickly reset the signal at the output terminal Gout through the seventh transistor T7, thereby quickly pulling down the voltage of the output terminal Gout.

[0133] The following is based on Figure 3Taking the circuit diagram shown as an example, and assuming that all transistors are P-type transistors, the driving principle and driving process of this driving circuit will be explained in detail. Figure 10 Provided Figure 3 Timing sequence corresponding to the circuit diagram;

[0134] Figure 3 The circuit structure shown in the diagram illustrates the driving process from the first stage t1 to the fourth stage t4. Figure 2 The driving process for the circuit structure shown is the same; please refer to the previous explanation for details.

[0135] In the fifth stage t5, a low-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK, a low-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a high-level control clock signal is input to the control clock signal line (third clock signal line CK2).

[0136] At this time, the first transistor T1 is off, the second transistor T2 is on, the third transistor T3 is on, the fourth transistor T4 is off, the fifth transistor T5 is on, the voltage of the first node PU is pulled high, the eighth transistor T8 and the ninth transistor T9 are off, the sixth transistor T6 is on, the voltages of the third node PD-in and the fourth node PD-out are both high, the seventh transistor T7 is off, and the tenth transistor T10 is off; the output terminal Gout maintains a high-level output signal.

[0137] In the sixth stage t6 (reset stage), a low-level trigger signal is input to the trigger signal input terminal (e.g., STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK, a high-level second clock signal is input to the second clock signal line CB, a first-level signal is input to the first-level signal line VGH, a second-level signal is input to the second-level signal line VGL, and a low-level control clock signal is input to the control clock signal line (e.g., the third clock signal line CK2).

[0138] At this time, the first transistor T1 is off, the second transistor T2 is on, the third transistor T3 is off, the fourth transistor T4 is on, and the fifth transistor T5 is on. The voltage of the first node PU is pulled high. The eighth transistor T8 and the ninth transistor T9 are off, the sixth transistor T6 is on, and the seventh transistor T7 is on (when the seventh transistor T7 starts to conduct, the eighth transistor T8 is completely off). The voltages of the third node PD-in and the fourth node PD-out are both pulled low. The tenth transistor T10 is on. Under the coupling effect of the fourth capacitor C4, the voltage of the fourth node PD-out is further pulled low. When the rising edge of the signal input to the control clock signal line (e.g., the third clock signal line CK2) is delayed by a first preset time relative to the rising edge of the signal input to the first clock signal line CK, the time for pulling down the voltage of the fourth node PD-out is extended, causing the voltage of the fourth node PD-out to drop rapidly. This helps to quickly reset the signal at the output terminal Gout through the seventh transistor T7, thereby quickly pulling down the voltage of the output terminal Gout. Furthermore, since the voltage of the first node PU has been pulled high before the reset begins, the eighth transistor T8 is completely turned off when the seventh transistor T7 starts to conduct. This avoids the possibility that the first level signal line VGH and the second level signal line VGL may be connected through the seventh transistor T7 and the eighth transistor T8, thereby reducing the power consumption of the drive circuit and extending its service life.

[0139] Figure 4 The driving process of the circuit structure shown and Figure 3 The circuit structures shown have the same driving process, the difference being that... Figure 4 The control clock signal terminal mentioned above is the first clock signal line. At this time, during the reset process, the circuit pulls down the fourth node PD-out voltage for a shorter period of time than... Figure 3 The circuit structure shown has a short time to pull down the voltage of the fourth node PD-out.

[0140] Additionally, it should be noted that Figure 11A Provided Figure 2 The circuit structure shown and Figure 3 The circuit structure shown in the diagram, during the reset process, displays a curve comparing the decrease in current of the seventh transistor T7 near the falling edge of the signal output at the Gout terminal. The comparison reveals that, compared to... Figure 2 The current change process of the seventh transistor T7 in the circuit structure shown (e.g.) Figure 11A (Curve marked A in the middle), when the gate of the fifth transistor T5 is electrically connected to the STV signal input terminal ( Figure 3(Circuit structure), because the voltage of the first node PU is pulled up in advance, the eighth transistor T8 is turned off completely in advance, and the current of the seventh transistor T7 is not affected by the first level signal line VGH. The current of the seventh transistor T7 decreases significantly and the rate of decrease is faster (e.g. Figure 11A (The curve marked B in the middle).

[0141] Figure 11B Provided Figure 2 The circuit structure shown and Figure 3 The circuit structure shown in the diagram, during the reset process, displays a curve comparing the current change of the eighth transistor T8 near the falling edge of the signal output at the Gout terminal. The comparison reveals that, compared to... Figure 2 The current change process of the eighth transistor T8 in the circuit structure shown (e.g.) Figure 11B (Curve marked A in the middle), when the gate of the fifth transistor T5 is electrically connected to the STV signal input terminal ( Figure 3 (Circuit structure) Because the voltage of the first node PU is pulled up in advance, the eighth transistor T8 is turned off completely in advance, and the current of the eighth transistor T8 almost disappears during this stage.

[0142] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driving circuit, wherein, include: Multiple shift registers cascaded together, the shift registers including: The pull-down module is electrically connected to the trigger signal input terminal, the first clock signal line, the second clock signal line, the first level signal line, the first node, and the second node, respectively. The pull-down module is configured to pull down the voltage of the first node under the control of the voltage of the second node. The input module is electrically connected to the first clock signal line, the trigger signal input terminal and the third node respectively, and is configured to transmit the signal input from the trigger signal input terminal to the third node under the control of the signal input from the first clock signal line; A pull-up module is electrically connected to the first node, the first level signal line, and the control terminal, respectively. The pull-up module is configured to pull up the voltage of the first node under the control of the control terminal. The output module is electrically connected to the first node, the first level signal line, and the output terminal of the shift register, respectively. Under the control of the voltage of the first node, the output module transmits the signal input from the first level signal line to the output terminal. A reset module is electrically connected to the third node, the second level signal line, and the fourth node, respectively. The reset module is configured to transmit the signal input from the second level signal line to the output terminal under the control of the voltage of the fourth node, so as to reset the output terminal. The adjustment module is electrically connected to the first node, the fourth node, the fifth node, the first level signal line, and the control clock signal line, respectively. The adjustment module is configured to assist the reset module in resetting the output terminal under the control of the voltage of the fifth node.

2. The driving circuit according to claim 1, wherein, Both the first level signal line and the second level signal line transmit signals with constant voltage, and the voltage of the signal transmitted by the first level signal line is greater than the voltage of the signal transmitted by the second level signal line.

3. The driving circuit according to claim 2, wherein, The control terminal includes the trigger signal input terminal; Alternatively, the control terminal may include the third node, and the pull-up module may be electrically connected to the input module through the third node.

4. The driving circuit according to claim 1, wherein, The pull-down module includes a first transistor, a second transistor, a third transistor, and a first capacitor; The gate of the first transistor is electrically connected to the second node, the source of the first transistor is electrically connected to the first clock signal line, and the drain of the first transistor is electrically connected to the first node; the source of the second transistor and the source of the third transistor are respectively electrically connected to the first level signal line, the drain of the second transistor and the drain of the third transistor are respectively electrically connected to the second node, the gate of the second transistor is electrically connected to the trigger signal input terminal, and the gate of the third transistor is electrically connected to the second clock signal line; the first electrode of the first capacitor is electrically connected to the source of the first transistor, and the second electrode of the first capacitor is electrically connected to the second node.

5. The driving circuit according to claim 4, wherein, The input module includes a fourth transistor, the gate of which is electrically connected to the first clock signal line, the source of which is electrically connected to the trigger signal input terminal, and the drain of which is electrically connected to the third node.

6. The driving circuit according to claim 5, wherein, The pull-up module includes a fifth transistor, the source of which is electrically connected to the first node, and the drain of which is electrically connected to the first level signal line. The gate of the fifth transistor is electrically connected to the third node; or the gate of the fifth transistor is electrically connected to the trigger signal input terminal.

7. The driving circuit according to claim 6, wherein, The reset module includes a sixth transistor, a seventh transistor, and a second capacitor. The gate of the sixth transistor is electrically connected to the second level signal line, the source of the sixth transistor is electrically connected to the third node, and the drain of the sixth transistor is electrically connected to the fourth node. The gate of the seventh transistor is electrically connected to the fourth node, the source of the seventh transistor is electrically connected to the output terminal, and the drain of the seventh transistor is electrically connected to the second level signal line. The first electrode of the second capacitor is electrically connected to the fourth node, and the second electrode of the second capacitor is electrically connected to the output terminal.

8. The driving circuit according to claim 7, wherein, The output module includes an eighth transistor and a third capacitor. The gate of the eighth transistor is electrically connected to the first node, the source of the eighth transistor is electrically connected to the first level signal line, and the drain of the eighth transistor is electrically connected to the output terminal. The first electrode of the third capacitor is electrically connected to the first node, and the second electrode of the third capacitor is electrically connected to the first level signal line.

9. The driving circuit according to claim 8, wherein, The adjustment module includes a ninth transistor, a tenth transistor, and a fourth capacitor. The gate of the ninth transistor is electrically connected to the first node, the source of the ninth transistor is electrically connected to the first level signal line, and the drain of the ninth transistor is electrically connected to the fifth node. The gate of the tenth transistor is electrically connected to the fourth node, the source of the tenth transistor is electrically connected to the fifth node, and the drain of the tenth transistor is electrically connected to the control clock signal line.

10. The driving circuit according to claim 9, wherein, The control clock signal line includes a third clock signal line and a fourth clock signal line. The third clock signal line is electrically connected to the drain of the tenth transistor in the odd-numbered shift register, and the fourth clock signal line is electrically connected to the drain of the tenth transistor in the even-numbered shift register. The first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge of the fourth clock signal transmitted by the fourth clock signal line is delayed by the first preset time period relative to the first signal edge of the second clock signal transmitted by the second clock signal line, wherein the first signal edge includes a rising edge or a falling edge.

11. The driving circuit according to claim 9, wherein, The control clock signal line includes a third clock signal line, which is electrically connected to the drain of the tenth transistor in each stage of the shift register; The period and pulse width of the first clock signal transmitted by the first clock signal line are 2N times that of the third clock signal transmitted by the third clock signal line, where N is a positive integer; The first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line. The first signal edge includes a rising edge or a falling edge.

12. The driving circuit according to claim 9, wherein, The control clock signal line includes the first clock signal line.

13. The driving circuit according to claim 10 or 11, wherein, The first preset time period includes 0~2μs.

14. The driving circuit according to claim 9, wherein, All of the transistors mentioned are P-type transistors.

15. A display device, wherein, The device includes the driving circuit as described in any one of claims 1-14, and further includes a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel driving circuit, and a shift register electrically connected to each of the pixel driving circuits in the same row of sub-pixels.

16. A driving method, wherein, Applied to the drive circuit as described in any one of claims 1-14; the method includes: During the input phase, a high-level trigger signal is input to the trigger signal input terminal electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line, a low-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a high-level control clock signal is input to the control clock signal line. During the output phase, a high-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line. During the reset phase, a low-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line.

Images