Pixel circuit, driving method and display device

Abstract

This application provides a pixel circuit, a driving method, and a display device. The pixel circuit is located in the nth row of a display panel. The display panel includes N rows of pixel circuits and a gate driving circuit. The gate driving circuit includes N cascaded shift registers. A first reset control signal receives the output signal of the (n-4)th shift register, thereby increasing the reset time of the pixel circuit. A write control signal receives the output signal of the (n+2)th shift register, and a compensation control signal receives the output signal of the nth shift register, thereby increasing the compensation time of the pixel circuit. By increasing the reset time and compensation time of the pixel circuit, image retention during pixel circuit driving is reduced, and power consumption during pixel circuit driving is also reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit, driving method and display device. Background Technology

[0002] In active-matrix organic light-emitting diode (AMOLED) display products, when driving the pixel circuit (e.g., 7T1C circuit), the reset time of the control electrode of the driving transistor (DTFT, Discrete-time Fourier Transform) and the internal compensation time of the pixel circuit are both short. Furthermore, due to the influence of the capacitor in the pixel circuit, there may be a serious problem of image retention during the driving process of the pixel circuit.

[0003] In related technologies, image retention issues are optimized by adding a light-emitting signal source to the driving pixel circuit. However, the inventors of this application have discovered that adding a light-emitting signal source has a certain impact on the power consumption of the driving pixel circuit. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a pixel circuit, driving method and display device to solve or partially solve the above problems.

[0005] To achieve the above objectives, the first aspect of this application provides a pixel circuit, comprising: a driving circuit, a data writing circuit, a compensation circuit, a light-emitting control circuit, a first reset circuit, a second reset circuit, and a light-emitting element;

[0006] The driving circuit includes a control terminal, a first terminal, and a second terminal, which are electrically connected to the first node, the second node, and the third node, respectively, and are used to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light.

[0007] The data writing circuit is used to write data signals to the first terminal of the driving circuit under the control of the write control signal;

[0008] The compensation circuit is used to electrically connect the control terminal and the second terminal of the drive circuit under the control of the compensation control signal, and to store the voltage of the control terminal of the drive circuit.

[0009] The light-emitting control circuit is used to make the driving current flow through the light-emitting element under the control of the light-emitting control signal;

[0010] The first reset circuit is used to apply a first reset voltage to the control terminal of the drive circuit under the control of a first reset control signal;

[0011] The second reset circuit is used to apply a second reset voltage to the first electrode of the light-emitting element under the control of the write control signal;

[0012] The pixel circuit is located in the nth row of the display panel. The display panel includes N rows of pixel circuits and a gate driving circuit. The gate driving circuit includes N cascaded shift registers. The first reset control signal receives the output signal of the (n-4)th shift register. The write control signal receives the output signal of the (n+2)th shift register. The compensation control signal receives the output signal of the nth shift register.

[0013] Optionally, the first output level of the output signal of the adjacent shift register has a shift of one unit time, and the output signal of the shift register includes at least three of the first output levels with the unit time as the time interval.

[0014] Optionally, the light-emitting control circuit includes:

[0015] The first light-emitting control circuit is used to apply a first power supply voltage to the first terminal of the driving circuit under the control of the light-emitting control signal;

[0016] The second light-emitting control circuit is used to apply the driving current from the second terminal of the driving circuit to the first electrode of the light-emitting element under the control of the light-emitting control signal.

[0017] Optionally, the first light-emitting control circuit includes a fifth transistor, the control electrode of the fifth transistor is used to receive the light-emitting control signal, the first electrode of the fifth transistor is used to receive the first power supply voltage, and the second electrode of the fifth transistor is electrically connected to the second node.

[0018] Optionally, the second light-emitting control circuit includes a sixth transistor, the control electrode of which is used to receive the light-emitting control signal, the first electrode of which is used to receive the driving current from the second terminal of the driving circuit, and the second electrode of which is electrically connected to the second node.

[0019] Optionally, the compensation circuit includes a second transistor and a storage capacitor;

[0020] The control electrode of the second transistor is used to receive the compensation control signal. The first electrode of the second transistor is electrically connected to the third node. The second electrode of the second transistor is electrically connected to the first electrode of the storage capacitor and the first node. The second electrode of the storage capacitor is used to receive the first power supply voltage.

[0021] Optionally, the driving circuit includes a third transistor, wherein the control electrode of the third transistor is electrically connected to the first node as the control terminal of the driving circuit, the first electrode of the third transistor is electrically connected to the second node as the third terminal of the driving circuit, and the second electrode of the third transistor is electrically connected to the third node as the second terminal of the driving circuit.

[0022] Optionally, the first reset control circuit includes a first transistor, the control electrode of the first transistor is used to receive the first reset signal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is used to receive the first reset voltage.

[0023] Optionally, the data writing circuit includes a fourth transistor, the control electrode of which is used to receive the write control signal, the first electrode of which is used to receive the data signal, and the second electrode of the second transistor is electrically connected to the second node.

[0024] Optionally, the second reset control circuit includes a seventh transistor, the control electrode of which is used to receive the write control signal, the first electrode of the second transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the seventh transistor is used to receive the second reset voltage.

[0025] Based on the same inventive concept, a second aspect of this application provides a driving method applied to the pixel circuit described in any one of the first aspects above, the driving method comprising:

[0026] Each display cycle includes a reset phase, a data writing and compensation phase, and a light emission phase.

[0027] During the reset phase, the first reset signal includes at least three first levels, the compensation control signal includes at least three first levels that are continuous with the first reset signal, and the light emission control signal and the write control signal are second levels.

[0028] During the data writing and compensation phase, the compensation control signal includes at least three first levels that are continuous with the first reset control signal, the write control signal includes at least three first levels that are continuous with the compensation control signal, and the first reset control signal and the light emission control signal are second levels.

[0029] During the light emission stage, the light emission control signal includes at least three first levels, and the write control signal, the compensation signal, and the first reset control signal are all second levels.

[0030] Based on the same inventive concept, a third aspect of this application provides a display device including the pixel circuit described in any one of the first aspects above.

[0031] As can be seen from the above description, this application provides a pixel circuit, a driving method, and a display device. The pixel circuit includes a driving circuit for controlling a driving current flowing through a first terminal and a second terminal of the driving circuit to drive a light-emitting element to emit light; a data writing circuit for writing a data signal to the first terminal of the driving circuit under the control of a writing control signal; a compensation circuit for electrically connecting the control terminal and the second terminal of the driving circuit under the control of a compensation control signal and storing the voltage of the control terminal of the driving circuit; a light-emitting control circuit for causing the driving current to flow through the light-emitting element under the control of a light-emitting control signal; a first reset circuit for applying a first reset voltage to the control terminal of the driving circuit under the control of a first reset control signal; and a second reset circuit for... Under the control of the write control signal, a second reset voltage is applied to the first electrode of the light-emitting element; wherein, the pixel circuit is located in the nth row of the display panel, the display panel includes N rows of pixel circuits and a gate driving circuit, the gate driving circuit includes N cascaded shift registers, the first reset control signal receives the output signal of the (n-4)th shift register, thereby increasing the reset time of the pixel circuit; the write control signal receives the output signal of the (n+2)th shift register, the compensation control signal receives the output signal of the nth shift register, thereby increasing the compensation time of the pixel circuit, by increasing the reset time and compensation time of the pixel circuit, the image retention that occurs in the product during the pixel circuit driving process is reduced, and the power consumption generated during the pixel circuit driving process is also reduced. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1A A schematic diagram of an exemplary pixel circuit is shown.

[0034] Figure 1B It shows Figure 1A An exemplary driving timing diagram of the pixel circuit.

[0035] Figure 2A A schematic diagram of the structure of an exemplary pixel circuit provided in this application is shown.

[0036] Figure 2B A schematic diagram of the circuit structure of an exemplary pixel circuit provided in this application is shown.

[0037] Figure 2C An exemplary driving timing diagram of a pixel circuit according to this application is shown.

[0038] Figure 3A A block diagram showing the connection structure of the N-row pixel circuit and the gate driving circuit according to this application is illustrated.

[0039] Figure 3B A schematic diagram of the circuit structure of the N-row pixel circuit according to this application is shown.

[0040] In the attached image:

[0041] 10. Pixel circuit; 11. Gate driving circuit; 101. Driving circuit; 102. Data writing circuit; 103. Compensation circuit; 104. Light emission control circuit; 1041. First light emission control circuit; 1042. Second light emission control circuit; 105. First reset circuit; 106. Second reset circuit; 107. Light emission element; ELVDD, First power supply voltage; EM, Light emission control signal; Reset, First reset control signal; Gate2, Write control signal; Vinit2, Second reset voltage; Gate1, Compensation control signal; Vinit1, First reset voltage; Vdata, Data signal; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; T5, Fifth transistor; T6, Sixth transistor; T7, Seventh transistor; Cst, Storage capacitor. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0043] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] Based on the description of the background technology, refer to Figure 1AThe diagram illustrates a schematic of an exemplary pixel circuit. Exemplarily, this pixel circuit is a 7T1C circuit, meaning it consists of seven transistors and one capacitor. Specifically, T1 is a reset transistor, T2 is a compensation transistor, T3 is a drive transistor, T4 is a data write transistor, T5 and T6 are light-emitting control transistors, and T7 is an anode reset transistor. The 7T1C circuit uses two reference signals and two reset signals to reset the gate of the drive transistor T3, resulting in low reset efficiency. Furthermore, the two light-emitting control signals (EM) have a significant afterimage effect on the display bezel and also increase drive power consumption.

[0045] Figure 1B It shows Figure 1A An exemplary driving timing diagram of the pixel circuit.

[0046] Combination Figure 1A and Figure 1B As shown, at time t1, the control terminal of the driving transistor is reset three times by the first transistor T1. However, after each reset, due to the input of the compensation control signal Gate, the compensation transistor T2 and the write transistor T4 are turned on, and the data signal Vdata is written to the driving transistor T3. Figure 1B It can be seen that although the compensation control signal Gate is passed three times, the first node N1 is pulled to the first reset voltage Vinit1 in the first two times. Therefore, the data written to the driving transistor T3 is only the data at time t2 (that is, the writing time is 1H), which results in a short actual writing time of the compensation control signal Gate, causing a serious problem of image retention in the product.

[0047] Based on the above description, this application provides a pixel circuit 10, which receives the output signal of the (n-4)th shift register through a first reset control signal Reset, thereby increasing the reset time of the pixel circuit 10; the write control signal Gate2 receives the output signal of the (n+2)th shift register, and the compensation control signal Gate1 receives the output signal of the nth shift register, thereby increasing the compensation time of the pixel circuit 10. By increasing the reset time and compensation time of the pixel circuit 10, the image retention that occurs in the product during the driving process of the pixel circuit 10 is reduced, and the power consumption generated during the driving process of the pixel circuit 10 is also reduced.

[0048] Figure 2A A schematic diagram of the structure of the exemplary pixel circuit 10 provided in this application is shown.

[0049] like Figure 2AAs shown, this application embodiment provides a pixel circuit 10, including: a driving circuit 101, a data writing circuit 102, a compensation circuit 103, a light-emitting control circuit 104, a first reset circuit 105, a second reset circuit 106, and a light-emitting element 107.

[0050] The driving circuit 101 includes a control terminal, a first terminal, and a second terminal, which are electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and are used to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element 107 to emit light.

[0051] Specifically, the control terminal of the drive circuit 101 is electrically connected to the first node N1, the first terminal of the drive circuit 101 is electrically connected to the second node N2, and the second terminal of the drive circuit 101 is electrically connected to the third node N3.

[0052] The data writing circuit 102 is used to write the data signal Vdata to the first terminal of the driving circuit 101 under the control of the writing control signal Gate2.

[0053] Specifically, the digital writing circuit includes a control terminal, a first pole, and a second pole. The control terminal of the digital writing circuit is electrically connected to the write control signal Gate2 terminal, the first pole is electrically connected to the digital signal terminal, and the second pole is electrically connected to the second node N2, that is, the circuit is connected to the driving circuit 101 through the second node N2.

[0054] Optionally, the write control signal Gate2 is generated by a gate driving circuit (optionally, a gate-on-array (GOA) circuit). The gate driving circuit includes N cascaded shift registers (also called GOA units), the first output level of the output signals of adjacent shift registers having a shift per unit time, and applied row-by-row to a plurality of pixel circuits 10 on each row to control the pixel circuits 10 to perform data writing.

[0055] Furthermore, for each pixel circuit 10, since the signals controlling the various circuits inside it and the write control signal Gate2 need to satisfy a specific timing relationship, these signals are also shifted row by row.

[0056] The compensation circuit 103 is used to electrically connect the control terminal and the second terminal of the drive circuit 101 under the control of the compensation control signal Gate1, and to store the voltage of the control terminal of the drive circuit 101.

[0057] The light-emitting control circuit 104 is used to make the driving current flow through the light-emitting element 107 under the control of the light-emitting control signal EM.

[0058] Optionally, the light-emitting control circuit 104 may include: a first light-emitting control circuit 1041, used to apply a first power supply voltage ELVDD to the first terminal of the driving circuit 101 under the control of the light-emitting control signal EM;

[0059] The second light-emitting control circuit 1042 is used to apply the driving current from the second terminal of the driving circuit 101 to the first electrode of the light-emitting element 107 under the control of the light-emitting control signal EM. The first light-emitting control circuit 1041 and the second light-emitting control circuit 1042 are generated by a GOA circuit.

[0060] The first reset circuit 105 is used to apply the first reset voltage Vinit1 to the control terminal of the drive circuit 101 under the control of the first reset control signal Reset.

[0061] The second reset circuit 106 is used to apply the second reset voltage Vinit2 to the first electrode of the light-emitting element 107 under the control of the write control signal Gate2.

[0062] Figures 2B to 2C A schematic diagram of the circuit structure of the exemplary pixel circuit provided in this application and an exemplary driving timing diagram of the pixel circuit are shown.

[0063] It should be noted that the various example pixel circuits 10 shown herein are for Figure 2A The circuit configurations of each circuit module are described with examples, but this is not a limitation requiring every circuit module to adopt the same configuration. Figure 2B The structure is exactly the same as described in the text; for example, the drive circuit 101 adopts a structure as described in the text. Figure 2B The circuit configuration shown can be modified so that the data writing circuit 102 can be different from the one used in the circuit diagram. Figure 2B The circuit configuration shown may include, for example, more transistors, as long as the data voltage can be applied to the second node N2 under the control of the scan signal. This understanding also applies to other example circuit structures of this disclosure.

[0064] like Figure 2B As shown, the driving circuit 101 includes a third transistor T3. The control terminal of the third transistor T3 is electrically connected to the first node N1 as the control terminal of the driving circuit 101. The first terminal of the third transistor T3 is electrically connected to the second node N2 as the third terminal of the driving circuit 101. The second terminal of the third transistor T3 is electrically connected to the third node N3 as the second terminal of the driving circuit 101.

[0065] The data writing circuit 102 includes a fourth transistor T4. The control electrode of the fourth transistor T4 is used to receive the write control signal Gate2. The first electrode of the fourth transistor T4 is used to receive the data signal Vdata. The second electrode of the fourth transistor T4 is electrically connected to the second node N2.

[0066] Specifically, the gate driving circuit 11 writes the write control signal Gate2 into the pixel circuit 10, which turns on the fourth transistor T4. The fourth transistor T4 writes the received data signal Vdata to the first terminal of the third transistor T3.

[0067] The compensation circuit 103 includes a second transistor T2 and a storage capacitor Cst; the control terminal of the second transistor T2 is used to receive the compensation control signal Gate1, the first terminal of the second transistor T2 is electrically connected to the third node N3, the second terminal of the second transistor T2 is electrically connected to the first terminal of the storage capacitor Cst and the first node N1, and the second terminal of the storage capacitor Cst is used to receive the first power supply voltage ELVDD.

[0068] Specifically, the gate driving circuit 11 writes the compensation control signal Gate1 into the pixel circuit 10, which turns on the second transistor T2, that is, the control terminal of the driving circuit 101 is connected to the second transistor.

[0069] The first light-emitting control circuit 1041 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is used to receive the light-emitting control signal EM. The first electrode of the fifth transistor T5 is used to receive the first power supply voltage ELVDD. The second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0070] Specifically, the EM circuit writes the light emission control signal EM into the pixel circuit 10, which turns on the fifth transistor T5, thereby applying the first power supply voltage ELVDD to the first terminal of the third transistor T3.

[0071] The second light-emitting control circuit 1042 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is used to receive the light-emitting control signal EM. The first electrode of the sixth transistor T6 is used to receive the driving current from the second terminal of the driving circuit 101. The second electrode of the sixth transistor T6 is electrically connected to the second node N2.

[0072] Specifically, the EM circuit writes the light-emitting control signal EM into the pixel circuit 10, which turns on the sixth transistor T6, thereby applying the voltage of the second electrode of the third transistor T3 to the first electrode of the light-emitting element 107.

[0073] The first reset control circuit includes a first transistor T1, the control electrode of the first transistor T1 is used to receive the first reset signal, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is used to receive the first reset voltage Vinit1.

[0074] Specifically, the gate driving circuit 11 writes a first reset signal into the pixel circuit 10, turns on the first transistor T1, and applies the first reset voltage Vinit1 to the first node N1 to reset the first node N1.

[0075] The second reset control circuit includes a seventh transistor T7. The control electrode of the seventh transistor T7 is used to receive the write control signal Gate2. The first electrode of the second transistor T2 is electrically connected to the first electrode of the light-emitting element 107. The second electrode of the seventh transistor T7 is used to receive the second reset voltage Vinit2.

[0076] Specifically, the gate driving circuit 11 writes the write control signal Gate2 into the pixel circuit 10, which turns on the seventh transistor T7. After the seventh transistor T7 turns on, the second reset voltage Vinit2 is applied to the first electrode of the light-emitting element 107 to reset the first electrode of the light-emitting element 107.

[0077] Furthermore, when the light emission control signal EM is at an invalid level and the write signal is at an effective level, the seventh transistor T7 is reset. When the light emission control signal EM is at an effective level, the driving current flows through the light emission element 107 to emit light.

[0078] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 mentioned above are all LTPS transistors. LTPS transistors have advantages such as fast driving speed, which can ensure the driving speed of the driving circuit 101 and reduce power consumption.

[0079] The following combination Figure 2B and Figure 2C The driving method and working process of the pixel circuit 10 shown are described.

[0080] like Figure 2C As shown, the first output level of the output signal of the adjacent shift register has a shift of one unit time, and the output signal of the shift register includes at least three of the first output levels with the unit time as the time interval.

[0081] Specifically, the shift register outputs at least three first output levels at unit time intervals to increase the reset time and compensation time, thereby further improving the afterimage effect of the product.

[0082] The working process within each display cycle includes a reset phase, a data writing and compensation phase, and a light emission phase.

[0083] During the reset phase, the first reset signal includes at least three first levels, the compensation control signal includes at least three first levels that are continuous with the first reset signal, and the light emission control signal and the write control signal are second levels.

[0084] During the data writing and compensation phase, the compensation control signal includes at least three first levels that are continuous with the first reset control signal, the write control signal includes at least three first levels that are continuous with the compensation control signal, and the first reset control signal and the light emission control signal are second levels.

[0085] During the light emission stage, the light emission control signal includes at least three first levels, and the write control signal, the compensation signal, and the first reset control signal are all second levels.

[0086] Wherein, the first level is an active level and the second level is an inactive level. For example, during the reset phase, the first reset control signal Reset is set to three active levels, the compensation control signal Gate1 is set to one active level, and the light emission control signal EM and the write control signal Gate2 are set to inactive levels.

[0087] Thus, since the first reset control signal Reset has three active levels and the light emission control signal EM has an inactive level, the first transistor T1 is turned on, the second transistor T2 is turned on, and the remaining transistors are turned off, so that the first reset voltage Vinit1 is provided to the first node N1 and the first reset voltage Vinit1 is provided to the third node N3. At this time, the voltage of the first node N1 is Vint1, the voltage of the third node N3 is Vint1, and the second node N2 and the first electrode of the light emission element 107 are floated after the previous stage ends.

[0088] During the data writing and compensation phase, the compensation control signal Gate1 is set to three valid levels, the write control signal Gate2 is set to three valid levels, and the first reset control signal Reset and the light emission control signal EM are set to invalid levels.

[0089] In this way, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned on, while the remaining transistors are turned off. The third transistor T3 forms a diode connection. The data signal Vdata passes through the fourth transistor T4, the third transistor T3, and the second transistor T2 in sequence to charge the first node N1 until the voltage of the first node N1 is Vdata + Vth (that is, the data signal Vdata + threshold voltage), at which point the charging ends. The voltage of the second node N2 is Vdata, and the voltage of the third node N3 is Vdata + Vth, thus completing the extraction of the threshold voltage Vth of the third transistor T3 and the writing of the data voltage Vdata. At this time, the voltage on the storage capacitor Cst is Vdata + Vth - ELVDD, that is, the threshold voltage Vth of the third transistor T3 is stored in the storage capacitor Cst.

[0090] Furthermore, during the data writing and compensation phase, the voltage of the first electrode (fourth node) of the light-emitting element 107 is reset because the seventh transistor T7 is turned on.

[0091] Combination Figure 2B and Figure 2C During times t1-t2, the control terminal of the driving transistor is reset three times by T1, increasing the reset time of the driving transistor control terminal. During the last potential reset (i.e., at time t2), the compensation control signal Gate1 is continuously input for three consecutive times. At time t2, the third node N3 is reset due to the input of the compensation control signal Gate1, eliminating the influence of the capacitor of the third node N3 on the charging of node N1. At time t3, the compensation control signal Gate1 is written to the driving transistor, that is, the write control signal Gate2 is input for three consecutive times after the reset is completed. Since at time t3... The writing of the compensation control signal Gate1 turns on the second transistor T2, connecting its first node N1 and third node N3. Furthermore, the writing of the write control signal Gate2 turns on the fourth transistor T4. The data signal Vdata flows sequentially through the fourth transistor T4, the third transistor T3, and the second transistor T2 to charge the first node N1. This increases the compensation time of the drive circuit 101 and the writing time of the digital signal. Simultaneously, the writing of the control signal Gate2 at time t4 eliminates the influence of the third node N3 capacitor on the charging of node N1, further improving the image retention effect of the product.

[0092] During the light emission stage, the light emission control signal EM is set to an active level, while the write control signal Gate2, the compensation control signal Gate1, and the first reset control signal Reset are all set to an inactive level.

[0093] Thus, transistors T3, T5, and T6 are turned on, while the remaining transistors are turned off. Current flows from ELVDD to ELVSS. At this time, the voltage at the first node N1 is Vdata + Vth due to the storage capacitor Cst, the voltage at the second node N2 is ELVDD, and the voltage at the third node N3 is the voltage at the first terminal of the light-emitting element 107. The voltage difference between the control terminal and the first terminal of the third transistor T3 is: Vgs = N1 voltage - N2 voltage = Vdata + Vth - VDD. The driving current I flowing through the light-emitting element 107 is I = KVgs - Vth2 = KVdata + Vth - VDD - Vth2 = KVdata - VDD2, where K is the eigenfactor of the transistor. Therefore, the driving current I flowing through the light-emitting element 107 is independent of the threshold voltage Vth of the driving transistor T1. This pixel circuit 10 achieves compensation for the threshold voltage Vth of the first transistor T1.

[0094] In the various pixel circuits 10 shown in the embodiments of this disclosure, the light-emitting element 107 can be an organic light-emitting diode (OLED), with its first stage being the anode of the OLED and its second stage being the cathode of the OLED. In this disclosure, the first power supply voltage ELVDD can be, for example, a DC voltage greater than 0, such as 5V or 4.6V.

[0095] Figure 3A A block diagram showing the connection structure of the N-row pixel circuit 10 and the gate driving circuit 11 according to this application is illustrated.

[0096] like Figure 3A As shown, the pixel circuit 10 is located in the nth row of the display panel. The display panel includes N rows of pixel circuits 10 and a gate driving circuit 11. The gate driving circuit 11 includes N cascaded shift registers. The first reset control signal Reset receives the output signal of the (n-4)th shift register. The write control signal Gate2 receives the output signal of the (n+2)th shift register. The compensation control signal Gate1 receives the output signal of the nth shift register.

[0097] The reset control signal Reset receives the output signal of the (n-4)th shift register, thereby increasing the reset time of the pixel circuit 10. The write control signal Gate2 receives the output signal of the (n+2)th shift register, and the compensation control signal Gate1 receives the output signal of the nth shift register, thereby increasing the compensation time of the pixel circuit 10. By increasing the reset time and compensation time of the pixel circuit 10, the image retention that occurs during the driving process of the pixel circuit 10 is reduced, and the power consumption generated during the driving process of the pixel circuit 10 is also reduced.

[0098] Figure 3BA schematic diagram of the circuit structure of the N-row pixel circuit 10 according to this application is shown.

[0099] like Figure 3B As shown, the first reset signal of the pixel circuit 10 in the first four rows receives the first reset voltage Vinit1 generated by the GOA circuit; the first reset signal of the pixel circuit 10 in the fifth row receives the output signal of the first shift register (i.e., the G1 signal); the first reset signal of the pixel circuit 10 in the sixth row receives the output signal of the second shift register (i.e., the G2 signal); and so on. The first reset signal of the pixel circuit 10 in the Nth row receives the output signal of the N-4th shift register (i.e., the GN-4 signal).

[0100] The compensation control signal Gate1 of the first row pixel circuit 10 receives the output signal of the first shift register (i.e., the G1 signal), the compensation control signal Gate1 of the second row pixel circuit 10 receives the output signal of the second shift register (i.e., the G2 signal), and so on. The compensation control signal Gate1 of the Nth row pixel circuit 10 receives the output signal of the Nth shift register (i.e., the GN signal).

[0101] The write signal of the first row pixel circuit 10 receives the output signal of the third shift register (i.e., the G3 signal), the write signal of the second row pixel circuit 10 receives the output signal of the fourth shift register (i.e., the G4 signal), and so on, the write signal of the Nth row pixel circuit 10 receives the output signal of the N+2th shift register (i.e., the GN+2 signal).

[0102] Furthermore, the light emission control signal EM of each row pixel circuit 10 receives the light emission control signal EM of the EM circuit.

[0103] Based on the same inventive concept, this application also provides a driving method, the driving method comprising:

[0104] Each display cycle includes a reset phase, a data writing and compensation phase, and a light emission phase.

[0105] During the reset phase, the first reset signal is set to at least three valid levels, the compensation control signal is set to at least three valid levels consecutive to the first reset signal, and the light emission control signal and the write control signal are set to invalid levels.

[0106] During the data writing and compensation phase, the first reset control signal is set to an active level, the compensation control signal is set to at least three active levels consecutive to the first reset control signal, the write control signal is set to at least three active levels consecutive to the compensation control signal, and the light emission control signal is set to an inactive level.

[0107] During the light emission stage, the light emission control signal is set to at least three valid levels, while the write control signal, the compensation signal, and the first reset control signal are all invalid levels.

[0108] Specifically, this driving method increases the reset time and compensation time of the driving transistor by inputting three first reset control signals Reset, three compensation control signals Gate1 that are continuous with the first reset control signals Reset, and three write control signals Gate2 that are continuous with the compensation control signals Gate1 within a preset time during the reset phase, data writing and compensation phase, and light emission phase, thereby reducing image retention in the product.

[0109] Based on the same inventive concept, this application also provides a display device, including the pixel circuit disclosed above.

[0110] The pixel circuit is located in the nth row of the display panel, which includes N rows of pixel circuits and a gate driving circuit. The gate driving circuit includes N cascaded shift registers. The first reset control signal receives the output signal of the (n-4)th shift register, thereby increasing the reset time of the pixel circuit. The write control signal receives the output signal of the (n+2)th shift register, and the compensation control signal Gate1 receives the output signal of the nth shift register, thereby increasing the compensation time of the pixel circuit. By increasing the reset time and compensation time of the pixel circuit, the image retention that occurs during the pixel circuit driving process is reduced, and the power consumption generated during the pixel circuit driving process is also reduced.

[0111] The display device provided in this embodiment can be applied to any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, and navigator.

[0112] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0113] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0114] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0115] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A pixel circuit, characterized by include: The circuit includes a driving circuit, a data writing circuit, a compensation circuit, a light-emitting control circuit, a first reset circuit, a second reset circuit, and a light-emitting element. The driving circuit includes a control terminal, a first terminal, and a second terminal, which are electrically connected to the first node, the second node, and the third node, respectively, and are used to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light. The data writing circuit is used to write data signals to the first terminal of the driving circuit under the control of the write control signal; The compensation circuit is used to electrically connect the control terminal and the second terminal of the drive circuit under the control of the compensation control signal, and to store the voltage of the control terminal of the drive circuit. The light-emitting control circuit is used to make the driving current flow through the light-emitting element under the control of the light-emitting control signal; The first reset circuit is used to apply a first reset voltage to the control terminal of the drive circuit under the control of a first reset control signal; The second reset circuit is used to apply a second reset voltage to the first electrode of the light-emitting element under the control of the write control signal; The pixel circuit is located in the nth row of the display panel. The display panel includes N rows of pixel circuits and a gate driving circuit. The gate driving circuit includes N cascaded shift registers. The first reset control signal receives the output signal of the (n-4)th shift register. The write control signal receives the output signal of the (n+2)th shift register. The compensation control signal receives the output signal of the nth shift register. The first output level of the output signals of adjacent shift registers has a shift of one unit time.

2. The pixel circuit of claim 1, wherein, The output signal of the shift register includes at least three of the first output levels with a time interval of the unit time.

3. The pixel circuit according to claim 1, characterized in that, The light-emitting control circuit includes: The first light-emitting control circuit is used to apply a first power supply voltage to the first terminal of the driving circuit under the control of the light-emitting control signal; The second light-emitting control circuit is used to apply the driving current from the second terminal of the driving circuit to the first electrode of the light-emitting element under the control of the light-emitting control signal.

4. The pixel circuit according to claim 3, characterized in that, The first light-emitting control circuit includes a fifth transistor, the control electrode of which is used to receive the light-emitting control signal, the first electrode of which is used to receive the first power supply voltage, and the second electrode of which is electrically connected to the second node.

5. The pixel circuit according to claim 3, characterized in that, The second light-emitting control circuit includes a sixth transistor, the control electrode of which is used to receive the light-emitting control signal, the first electrode of which is used to receive the driving current from the second terminal of the driving circuit, and the second electrode of which is electrically connected to the second node.

6. The pixel circuit according to claim 3, characterized in that, The compensation circuit includes a second transistor and a storage capacitor; The control electrode of the second transistor is used to receive the compensation control signal. The first electrode of the second transistor is electrically connected to the third node. The second electrode of the second transistor is electrically connected to the first electrode of the storage capacitor and the first node. The second electrode of the storage capacitor is used to receive the first power supply voltage.

7. The pixel circuit according to claim 1, characterized in that, The driving circuit includes a third transistor. The control electrode of the third transistor is electrically connected to the first node as the control terminal of the driving circuit. The first electrode of the third transistor is electrically connected to the second node as the third terminal of the driving circuit. The second electrode of the third transistor is electrically connected to the third node as the second terminal of the driving circuit.

8. The pixel circuit according to claim 1, characterized in that, The first reset circuit includes a first transistor, the control electrode of the first transistor is used to receive the first reset control signal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is used to receive the first reset voltage.

9. The pixel circuit according to claim 1, characterized in that, The data writing circuit includes a fourth transistor, the control electrode of which is used to receive the write control signal, the first electrode of which is used to receive the data signal, and the second electrode of which is electrically connected to the second node.

10. The pixel circuit according to claim 1, characterized in that, The second reset circuit includes a seventh transistor, the control electrode of which is used to receive the write control signal, the first electrode of which is electrically connected to the first electrode of the light-emitting element, and the second electrode of which is used to receive the second reset voltage.

11. A driving method applied to a pixel circuit as described in any one of claims 1 to 10, characterized in that, The driving method includes: During the reset phase, the first reset control signal includes at least three first levels, the compensation control signal includes at least three first levels that are continuous with the first reset control signal, and the light emission control signal and the write control signal are second levels. During the data writing and compensation phase, the compensation control signal includes at least three first levels that are continuous with the first reset control signal, the write control signal includes at least three first levels that are continuous with the compensation control signal, and the first reset control signal and the light emission control signal are second levels. During the light emission stage, the light emission control signal includes at least three first levels, and the write control signal, the compensation control signal, and the first reset control signal are all second levels.

12. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 10.

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