An Adaptive Decoding Method and System for Aviation Data Bus Rate

Abstract

This disclosure provides an adaptive decoding method and system for aviation data bus, relating to the field of aviation data technology. The method includes receiving 429 aviation bus data to be decoded and converted; performing an AND-OR operation on the 429 aviation bus data and saving the result; calculating the bus bit time of the 429 aviation bus data, dividing the bus bit time by frequency and storing it in the sampling interval; sampling once at the rising edge of each sampling interval and shifting it left in real time to save it in a shift register; using a shift register sequence detection method to adaptively decode and receive the sampled values ​​saved in real time; designing a fault tolerance rate for the interval between two sampled values; when the transmission rate changes, if more than half of the current n data sampled values ​​are 1, and more than half of the subsequent n clock sampled values ​​are 0, then the sampled data is determined to be 1, thus achieving the correct decoding and reception process of the 429 aviation data. This disclosure ensures the accuracy of data decoding and reception.

Description

Technical Field

[0001] This disclosure relates to the field of aviation data technology, specifically to an aviation data bus rate adaptive decoding method and system. Background Technology

[0002] The statements in this section are merely background information relating to this disclosure and do not necessarily constitute prior art.

[0003] The ARINC 429 bus protocol, short for Digital Information Transport System (DITS), was first proposed by the Airlines Electronic Engineering Committee (AEEC). The protocol specification defines the requirements for digital information transmission between avionics equipment and related systems, and serves as the standard for many avionics devices connecting to aircraft data networks.

[0004] The ARINC 429 protocol specification is widely used in modern civil aircraft, including Airbus A310 / A320, A330 / A340, Boeing B727, B737, B747, B757, and B767, covering almost all mainstream civil aircraft. The domestically produced large passenger aircraft C919 also uses the ARINC 429 protocol specification to define data exchange between airborne avionics equipment.

[0005] Currently, traditional ARINC429 bus data reception methods are broadly divided into two types: one uses a dedicated chip for data decoding and reception, and the other uses programmable logic. However, these two existing solutions are only suitable for receiving 429 bus data at a selected fixed clock frequency. In practical applications, two situations can affect data reception. One is that even though a clock frequency has been selected, deviations can occur due to various reasons, such as crystal aging or excessively long transmission lines. If the sender's clock frequency increases, the receiver may miss some data while receiving at the selected frequency; if the sender's clock frequency decreases, the receiver may repeatedly collect some data, both affecting data transmission accuracy. The other is that the sender's clock frequency is non-standard. Non-standard frequencies require manual measurement, increasing complexity and potentially leading to deviations and inaccurate data reception. Furthermore, the HI-844X series chips used in the front-end hardware receiving circuit of the second solution are expensive and difficult to procure. Summary of the Invention

[0006] To address the aforementioned issues, this disclosure proposes an adaptive decoding method and system for aviation data bus rates. In data reception, a shift register sequence detection method is employed to ensure correct data decoding and reception even when bus bit time calculations change, thus achieving adaptive rate decoding.

[0007] According to some embodiments, the present disclosure adopts the following technical solutions:

[0008] An adaptive decoding method for aviation data bus rate includes:

[0009] Receive the 429 aviation bus data to be decoded and converted, perform AND-OR operations on the 429 aviation bus data and save the OR operation result;

[0010] Calculate the bus bit time of the 429 aviation bus data, divide the bus bit time by frequency, and store it in the sampling interval. Sample once at the rising edge of each sampling interval and shift left in real time to save it into the shift register.

[0011] A shift register sequence detection method is used to adaptively decode and receive the sampled values ​​that are saved by left shift in real time. The error tolerance rate of the time interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n data sampled values ​​are 1 and more than half of the next n clock sampled values ​​are 0, then the sampled data is judged to be 1, thus realizing the correct decoding and reception process of 429 aviation data.

[0012] According to some embodiments, the present disclosure adopts the following technical solutions:

[0013] An aviation data bus rate adaptive decoding system includes:

[0014] The data preprocessing module is used to receive 429 aviation bus data to be decoded and converted, perform AND-OR operations on the 429 aviation bus data, and save the OR operation results;

[0015] The timing module is used to calculate the bus bit time of the 429 aviation bus data;

[0016] The frequency divider module is used to divide the bus bit time.

[0017] The shift and window module is used to store the bus bit time after frequency division in the sampling interval. It samples once at the rising edge of each sampling interval and shifts it left in real time to save it into the shift register. The shift register sequence detection method is used to perform adaptive rate decoding and reception of the sampled values ​​saved in real time. The error tolerance rate of the time interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n data sampled values ​​are 1 and more than half of the next n clock sampled values ​​are 0, then the sampled data is judged to be 1.

[0018] The data processing and receiving module is used to output the received data.

[0019] According to some embodiments, the present disclosure adopts the following technical solutions:

[0020] A non-transitory computer-readable storage medium is provided for storing computer instructions, which, when executed by a processor, implement the aforementioned aviation data bus rate adaptive decoding method.

[0021] According to some embodiments, the present disclosure adopts the following technical solutions:

[0022] An electronic device includes a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement the aforementioned aviation data bus rate adaptive decoding method.

[0023] Compared with the prior art, the beneficial effects of this disclosure are as follows:

[0024] This disclosure provides an adaptive decoding method and system for aviation data bus rate. In the data preprocessing module of the system, a front-end hardware receiving circuit is designed, which uses an EL0631(TA) optocoupler to be responsible for level conversion, which can save costs and reduce procurement difficulties.

[0025] In the adaptive rate decoding method, the window module is the core of the method implementation. The shift register sequence detection method is used to ensure that the data is correctly decoded and received even if there is a slight deviation in the calculation of the 429 bus bit time or the 429 bus bit time changes. This achieves adaptive rate decoding and reception of the 429 bus, while ensuring the accuracy of data transmission and reducing the complexity of data transmission and reception. Attached Figure Description

[0026] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure.

[0027] Figure 1 This is a circuit connection diagram of the data preprocessing module of this disclosure;

[0028] Figure 2 This is a schematic diagram of the internal structure of the optocoupler disclosed herein;

[0029] Figure 3 This is a schematic diagram of the data processing circuit connection for the adaptive rate decoding method of this disclosure;

[0030] Figure 4 This is a calculation example diagram of the timing module of this disclosure;

[0031] Figure 5 This is a schematic diagram of the method for setting all 1s in the Ai_ register [5:2] sequence of this disclosure;

[0032] Figure 6 This is a schematic diagram of the Ai_ register in this disclosure;

[0033] Figure 7 This is a schematic diagram of the method for setting all 1s in the Bi_ register [5:2] sequence of this disclosure;

[0034] Figure 8 This is a schematic diagram of the Bi_ register of this disclosure. Detailed Implementation

[0035] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0036] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0037] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0038] Example 1

[0039] One embodiment of this disclosure provides an adaptive decoding method for aviation data bus rates, including:

[0040] Step 1: Receive the 429 aviation bus data to be decoded and converted, perform AND-OR operations on the 429 aviation bus data and save the OR operation result;

[0041] Step 2: Calculate the bus bit time of the 429 aviation bus data, divide the bus bit time by frequency, and store it in the sampling interval. Sample once at the rising edge of each sampling interval and shift left in real time to save it to the shift register.

[0042] Step 3: The shift register sequence detection method is used to adaptively decode and receive the sampled values ​​saved by the real-time left shift. The error tolerance rate of the interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n data sampled values ​​are 1 and more than half of the next n clock sampled values ​​are 0, then the sampled data is judged to be 1, thus realizing the correct decoding and reception process of 429 aviation data.

[0043] As one example, the characteristics of the existing ARINC429 bus include:

[0044] (1) Transmission method

[0045] The ARINC429 bus consists of a pair of grounded twisted-pair shielded wires. The two wires in the twisted pair carry signals 180° out of phase (high and low levels), and the transmission is unidirectional. Information can only be output from the transmitting port of the communication device, transmitted through the twisted-pair shielded wire to the interface of other connected devices that need the information. However, information must never flow back to an interface designated for transmitting information. When bidirectional transmission is required between two communication devices, a separate transmission bus is used for each direction.

[0046] (2) Driving ability

[0047] Only one transmitter is allowed on the bus, but up to 20 receivers can be connected. Due to the limited number of devices, there is ample time guarantee for information transmission.

[0048] (3) Encoding method

[0049] The ARINC429 uses a bipolar return-to-zero tri-state code method. A signal returning from a high level to a zero level indicates a logic state 1, and a signal returning from a low level to a zero level indicates a logic state 0. Furthermore, each bit of the 429 bus is in the first half of the cycle as data and in the second half of the cycle as 0. Therefore, sending data and sending 0 constitute the transmission process of each bit, and the two states alternate continuously.

[0050] (4) Transmission rate

[0051] The system operates in two speeds: a high-speed mode with a bit rate of 100 Kb / s and a low-speed mode with a bit rate of 12.5 Kb / s. The bit rate selected should have an error range within 1%. High-speed and low-speed data cannot be transmitted on the same bus.

[0052] (5) Synchronization method

[0053] The basic unit of transmission is the word, which consists of 32 bits. Bit synchronization information is carried in the bipolar return-to-zero code signal waveform. Word synchronization is based on a zero-level time interval of at least 4 bits during the transmission period. The starting point of the first bit to be sent immediately after this word interval is the starting point of the new word.

[0054] According to the ARINC 429 bus specification, each word format (binary or binary-decimal) consists of 32 bits: bits 1-8 are label bits. These label bits indicate the type of information included in the transmitted word, that is, the meaning of the transmitted code. For example, if VHF information is transmitted, the label is octal number 030; if it is DME data, the label is octal number 201, and so on.

[0055] Bits 9 and 10 are Source Terminal Identifier (SDI). It indicates the source or destination of the information. For example, if a control box's tuning word needs to be sent to three VHF transceivers, the destination of the information needs to be identified, i.e., which VHF receiver the tuning word is sent to.

[0056] Bits 11-28 or 29 are the data field, which can be determined by the word type. It represents specific data. For example, if the label is 030, bits 11-29 are frequency data, using BCD encoding format, i.e., bits 11-29.

[0057] Bits 29 to 30 or 31 are the Symbol Status Matrix (SSM) bits, which are 29 or 30 to 31 depending on the word type number. They indicate the characteristics of the data, such as north, south, positive, negative, etc., or its state. Bits 30 to 31 are used in VHF (BCD encoding).

[0058] Bit 32 is the parity bit (P), used to check if the transmitted data is valid. The check method is as follows: if the sum of the number of high-level bits (i.e., the number of 1s) from bit 1 to bit 31 is even, then bit 32 is set to "1". If it is odd, it is displayed as "0".

[0059] As one embodiment, this disclosure proposes an ARNIC429 aviation data bus rate adaptive decoding method and method, the specific implementation of which is as follows:

[0060] The design consists of two main parts: a front-end hardware receiving circuit, which is a preprocessing module responsible for level conversion, and an adaptive rate decoding back-end processing circuit described in Verilog code, which is the overall data processing and decoding part responsible for decoding and receiving ARINC429 bus data.

[0061] Step 1: Receive the 429 aviation bus data to be decoded and converted, perform AND-OR operations on the 429 aviation bus data and save the OR operation result;

[0062] Before step 1, design the front-end hardware receiving circuit and use an optoelectronic coupler. There are various models of optoelectronic couplers. For example, for 4-pin linear optocouplers, there are PC81A---C, TLP521, etc., and for 6-pin linear optocouplers, there are: TLP632, TLP532, PC614, PC14, PS2031, etc. However, the basic composition and working principle are the same. The optoelectronic coupler mainly consists of three parts: light emission, light reception, and signal amplification. The light emission part is mainly composed of a light-emitting device. Generally, the light-emitting device is a light-emitting diode. When a forward voltage is applied to the light-emitting diode, it can convert electrical energy into light energy and emit light. The light-emitting diode can be driven by DC, AC, pulse, etc. power supplies, but a forward voltage must be applied when using the light-emitting diode. The light reception part is mainly composed of a photosensitive device. Generally, the photosensitive device is a photosensitive transistor. The photosensitive transistor works based on the principle that when a reverse voltage is applied to the PN junction and it is irradiated by light, the reverse resistance changes from large to small.

[0063] The light signal amplification part is mainly composed of an electronic circuit, etc. The pins of the light-emitting device are the input terminals, and the pins of the photosensitive device are the output terminals. During operation, an electrical signal is applied to the input terminal to make the core of the light-emitting device emit light. After the photosensitive device is irradiated by light, a photocurrent is generated and amplified by the electronic circuit and then output, realizing the conversion of electricity → light → electricity, thereby achieving electrical isolation between the input and output circuits.

[0064] As Figure 1 shown, pin 1 and pin 3 of the chip are connected to the A end of the 429 bus data, pin 2 and pin 4 are connected to the B end of the 429 bus data, pin 8 is connected to the 3.3V power supply, and pin 5 is grounded. As Figure 2 known, when there is no data transmission on the 429 bus (A = B = 0), pins 6 and 7 output a high level. When the bit value 1 is transmitted on the 429 bus (A > B), pin 7 outputs a low level and pin 6 outputs a high level. When the bit value 0 is transmitted on the 429 bus (A < B), pin 7 outputs a high level and pin 6 outputs a low level. Therefore, the data after level conversion is opposite to the input data, and an inverter needs to be added after output pins 6 and 7 and then connected to the FPGA.

[0065] Then perform data preprocessing. For the 429 bus data input, perform AND-OR operations and save the a or b values. a or b is the result of the OR operation, a and b are the results of the AND operation, and the a or b register saves the value of a or b in the previous clock. ​​​​​ Figure 4 As shown, when the 429 aviation bus is idle, A_in and B_in are both 0. When transmitting data 1, A_in changes from 1 to 0 at half the bit time, and B_in is 0 for the entire bit time. When transmitting data 0, A_in is 0 for the entire bit time, and B_in changes from 1 to 0 at half the bit time. When both A_in and B_in are 1, a data transmission error occurs. Figure 4 As shown, the detection of the rising edge of a or b marks the start of data transmission. After the rising edge of a or b, T1 starts timing and T2 stops timing. On the falling edge of a or b, T1 stops timing and T2 starts timing. T1 and T2 each store half of the time, so the 429 bus bit time is the sum of T1 and T2. This is because this module uses the time of the first bit of the first word of the 429 bus data as the reception time. However, the sender may change the transmission rate for various reasons, so this module only roughly calculates the 429 bus bit time.

[0068] The bus bit time is divided by frequency, and 1 / 16 of the 429 bus bit time is extracted and stored in the sampling interval (clock / 16).

[0069] Furthermore, a sample is taken once at the rising edge of each sampling interval, and then shifted left in real time and saved to the shift register. This includes: taking a sample once at the rising edge of each sampling interval (clock / 16), and shifting the sampled value (A_in / 16) left in real time and saving it to the Ai_ register and the Bi_ register, as shown below. Figure 6 , Figure 8 As shown.

[0070] Step 3: The shift register sequence detection method is used to adaptively decode and receive the sampled values ​​saved by real-time left shift. The error tolerance rate of the interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n data sampled values ​​are 1 and more than half of the next n clock sampled values ​​are 0, then the sampled data is judged to be 1, thus realizing the correct decoding and reception process of 429 aviation data.

[0071] The principle of shift register sequence detection is as follows: shift the data sequence and compare it with a predefined sequence to detect whether a specific pattern or error exists in the data sequence.

[0072] The process is as follows: extract the bits of Ai_ register [5:2], Ai_ register [13:10], Bi_ register [5:2], and Bi_ register [13:10].

[0073] Logical comparisons are performed on Ai and Bi registers [5:2] and 1111, and on Ai and Bi registers [13:10] and 0000.

[0074] Save the results and output them.

[0075] An adaptive rate decoding reception method is adopted for the sampled values ​​saved by real-time left shift using a shift register sequence detection method. Specifically, the input Ai_ register and Bi_ register are shift registers. The shift registers are used to save 2n sampled values ​​of 429 avionics bus data by real-time left shift. 429 avionics bus encoding is performed. In the 2n sampled values, the first n cycles sample the data value, and the sampled values ​​in the last n cycles are always zero. When the transmission rate changes, if more than half of the current n data sampled values ​​are 1 and more than half of the last n clock sampled values ​​are 0, the sampled data is determined to be 1.

[0076] Specifically, the shift register sequence detection method is used to ensure that the data is correctly decoded and received even if there is a slight deviation in the calculation of the 429 bus bit time or the 429 bus bit time changes, thus truly realizing the adaptive rate decoding and reception of the 429 bus.

[0077] Because when receiving data on a 429 bus, correct data reception can only be guaranteed if the sending and receiving ends have the same data rate. Adaptive rate means that the receiving end's rate changes with the sending end's rate, rather than fixing the rate at a certain value. This ensures that the receiving end can correctly receive data even when the sending end's rate changes. This invention calculates the sending end's rate and ensures that the calculated sending end rate is correct.

[0078] This includes the input Ai_ register and Bi_ register, which are shift registers. They are shifted left in real-time to store 16 sampled values ​​of the 429 bus data. As can be seen from the 429 bus encoding method, the first 8 cycles sample the data value, while the last 8 cycles always sample zero. For the A terminal of the 429 bus, when transmitting data 1, ideally, the first 8 data sampled values ​​should all be 1, and the last 8 sampled values ​​should all be 0. When the transmission rate changes, usually, as long as more than half of the first 8 data sampled values ​​are 1, and more than half of the last 8 clock sampled values ​​are 0, it can be determined that the sampled data is 1. Therefore, when the Ai_ register [5:2] sequence of the shift register is all 1, and the Ai_ register [13:10] sequence is all 0, it is determined that the received data is 1. Figure 5 As shown; for the B end of the 429 bus, similarly, when the Bi_ register [5:2] sequence is all 1 and the Bi_ register [13:10] sequence is all 0, the received data is determined to be 0, as shown. Figure 7As shown. This sampling method has a tolerance for the time interval between two sampling values. Taking the 429 bus standard low-rate 12.5kHz as an example, the time interval between the two sampling values ​​is {(12.5 / 16)*2}1.5625kHz. Therefore, this design can be applied to transmission frequencies from 10.9375kHz to 14.0625kHz. Thus, even if the 429 bus bit time extracted by the timing module has a slight deviation, correct data reception can be guaranteed. When data 1 is received, A_data is 1; when data 0 is received, B_data is 1.

[0079] Then, the rising edges of data A and data B are detected, and the results are transmitted to the data receiving module through the rising edge pins of data A and data B.

[0080] The data receiving module is responsible for saving the received data based on the values ​​of the rising edges of A_data and B_data. If A_data_rising edge = 1 and B_data_rising edge = 0, then bit value 1 is saved to the 32-bit data register. If A_data_rising edge = 0 and B_data_rising edge = 1, then bit value 0 is saved to the 32-bit data register. If A_data_rising edge = 1 and B_data_rising edge = 1, according to the 429 bus protocol, a data reception error has occurred, and reception must be restarted. After saving 32 bits of data, the reception completion flag is set to 1, and the data is output before data reception resumes.

[0081] Example 2

[0082] One embodiment of this disclosure provides an aviation data bus rate adaptive decoding system, comprising:

[0083] The data preprocessing module is used to receive 429 aviation bus data to be decoded and converted, perform AND-OR operations on the 429 aviation bus data, and save the OR operation results;

[0084] The timing module is used to calculate the bus bit time of the 429 aviation bus data;

[0085] The frequency divider module is used to divide the bus bit time.

[0086] The shift and window module is used to store the bus bit time after frequency division in the sampling interval. It samples once at the rising edge of each sampling interval and shifts it left in real time to save it into the shift register. The shift register sequence detection method is used to perform adaptive rate decoding and reception of the sampled values ​​saved in real time. The error tolerance rate of the time interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n data sampled values ​​are 1 and more than half of the next n clock sampled values ​​are 0, then the sampled data is judged to be 1.

[0087] The data processing and receiving module is used to output the received data.

[0088] Example 3

[0089] A non-transitory computer-readable storage medium is provided for storing computer instructions, which, when executed by a processor, implement the aforementioned aviation data bus rate adaptive decoding method.

[0090] Example 4

[0091] An electronic device includes a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement the aforementioned aviation data bus rate adaptive decoding method.

[0092] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0093] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0094] While the specific embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this disclosure are still within the scope of protection of this disclosure.

Claims

1. A method for adaptive decoding of aviation data bus rate, characterized in that, include: Receive the 429 aviation bus data to be decoded and converted, perform AND and OR operations on the A and B end data input of the 429 aviation bus data respectively, a or b is the OR operation result, a and b is the AND operation result, and save the OR operation result; Calculate the bus bit time of the 429 aviation bus data, divide the bus bit time by frequency, and store it in the sampling interval. Sample once at the rising edge of each sampling interval and shift left in real time to save it into the shift register. The shift register sequence detection method is used to adaptively decode and receive the sampled values ​​that are saved by left shift in real time. The error tolerance rate of the time interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n sampled values ​​are 1 and more than half of the next n sampled values ​​are 0, then the sampled data is judged to be 1, thus realizing the correct decoding and reception process of 429 aviation bus data. An adaptive rate decoding reception method is adopted for the sampled values ​​saved by real-time left shift using a shift register sequence detection method. Specifically, the input Ai_ register and Bi_ register are shift registers. The shift registers are shifted left in real time to save 2n sampled values ​​of 429 avionics bus data for 429 avionics bus encoding. In the 2n sampled values, the first n cycles sampled data values, and the sampled values ​​in the last n cycles are always zero. When the transmission rate changes, if more than half of the first n sampled values ​​are 1 and more than half of the last n sampled values ​​are 0, it is determined that the sampled data is 1.

2. The aviation data bus rate adaptive decoding method as described in claim 1, characterized in that, The OR operation result of the 429 avionics bus data is stored in register a or b, and register a or b stores the value of a or b in the previous clock cycle.

3. The aviation data bus rate adaptive decoding method as described in claim 1, characterized in that, The calculation of the 429 avionics bus bit time includes: the output terminals of the 429 avionics bus data include terminal A and terminal B. When the 429 avionics bus is idle, A_in and B_in are both 0. When transmitting data 1, A_in changes from 1 to 0 at half the bit time, and B_in is 0 for the entire bit time. When transmitting data 0, A_in is 0 for the entire bit time, and B_in changes from 1 to 0 at half the bit time. When both A_in and B_in are 1, then the data transmission is incorrect.

4. The aviation data bus rate adaptive decoding method as described in claim 3, characterized in that, The detection of the rising edge of a or b marks the start of data transmission. Timing starts at the rising edge of a or b (T1) and ends at the falling edge of a or b (T2). Timing stops at the falling edge of a or b (T1) and starts at the falling edge of b (T2). T1 and T2 each store half of the time. Therefore, the 429 aerospace bus bit time is the sum of T1 and T2.

5. The aviation data bus rate adaptive decoding method as described in claim 1, characterized in that, The received data is stored based on the values ​​of the rising edges of A_data and B_data. If A_data_rising edge = 1 and B_data_rising edge = 0, then bit values ​​1 to 32 are stored in the data register. If A_data_rising edge = 0 and B_data_rising edge = 1, then bit values ​​0 to 32 are stored in the data register. If A_data_rising edge = 1 and B_data_rising edge = 1, according to the 429 bus protocol, a data reception error has occurred, and reception must be restarted.

6. The aviation data bus rate adaptive decoding method as described in claim 5, characterized in that, After storing the 32-bit data in the register, the receive completion flag is set to 1, and the data is output, completing the decoding and receiving process of the 429 avionics bus data.

7. An adaptive decoding system for aviation data bus rates, characterized in that, include: The data preprocessing module is used to receive the 429 aviation bus data to be decoded and converted, perform AND and OR operations on the A-end and B-end data of the 429 aviation bus data input respectively, where a or b is the OR operation result, a and b is the AND operation result, and saves the OR operation result. The timing module is used to calculate the bus bit time of the 429 aviation bus data; The frequency divider module is used to divide the bus bit time. The shift and window module is used to store the bus bit time after frequency division in the sampling interval. It samples once at the rising edge of each sampling interval and shifts it left in real time to save it into the shift register. The shift register sequence detection method is used to perform adaptive rate decoding and reception of the sampled values ​​saved in real time. The error tolerance rate of the time interval between two sampled values ​​is designed. When the transmission rate changes, if more than half of the current n sampled values ​​are 1 and more than half of the next n sampled values ​​are 0, then the sampled data is judged to be 1. An adaptive rate decoding and reception method is adopted for the sampled values ​​saved by real-time left shift using a shift register sequence detection method. Specifically, the input Ai_ register and Bi_ register are shift registers. The shift registers are shifted left in real time to save 2n sampled values ​​of 429 avionics bus data for 429 avionics bus encoding. In the 2n sampled values, the first n cycles sample the data value, and the sampled values ​​in the last n cycles are always zero. When the transmission rate changes, if more than half of the first n sampled values ​​are 1 and more than half of the last n sampled values ​​are 0, the sampled data is determined to be 1. The data processing and receiving module is used to output the received data.

8. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium is used to store computer instructions, which, when executed by a processor, implement an aviation data bus rate adaptive decoding method as described in any one of claims 1-6.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to perform an adaptive decoding method for aviation data bus rate as described in any one of claims 1-6.

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