Imaging device and camera system

Abstract

This imaging device comprises: a first pixel and a second pixel; a signal line to which a signal from the first pixel is input; a signal line to which a signal from the second pixel is input; a switch element connected between the two signal lines; and a shift register including a plurality of registers connected in series. A signal corresponding to an output of one register among the plurality of registers of the shift register is input to a control terminal of the switch element.

Description

Imaging Device and Camera System

[0001] The present disclosure relates to an imaging device and a camera system.

[0002] Imaging devices using a CCD (Charge Coupled Device) image sensor, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, etc. are widely used in digital cameras and the like.

[0003] In an imaging device, a technique for controlling whether to mix and output signals output from a plurality of pixels is known.

[0004] For example, in Patent Documents 1 and 2, by connecting two or more signal lines to which signals from pixels are input with a switch, it is possible to control whether to mix and output signals output from pixels connected to the two or more signal lines. A technique is disclosed.

[0005] Japanese Unexamined Patent Application Publication No. 2023-106550, Japanese Unexamined Patent Application Publication No. 2010-259027

[0006] In the techniques disclosed in Patent Documents 1 and 2, a control unit that also controls other circuits also controls a switch that connects two or more signal lines to which signals from pixels are input. In such a case, since the number of control lines coming out of the control unit increases, the structure of the device tends to become complicated.

[0007] Therefore, the present disclosure provides an imaging device or the like that can control a switch element for mixing signals from pixels with a simple configuration.

[0008] An imaging device according to an aspect of the present disclosure includes a first pixel and a second pixel, a first wiring to which a signal from the first pixel is input, a second wiring to which a signal from the second pixel is input, and a first wiring and a second wiring. A first switch element connected between the wirings, and a first shift register including a plurality of registers connected in series, and a signal corresponding to the output of a first register among the plurality of registers of the first shift register is input to a control terminal of the first switch element. It is configured as such.

[0009] An imaging device according to one aspect of the present disclosure includes a first pixel, a second pixel, and a third pixel arranged along a first direction; a first wiring to which a signal from the first pixel is input; a second wiring to which a signal from the second pixel is input; a third wiring to which a signal from the third pixel is input; a first switch element connected between the first wiring and the second wiring; a second switch element connected between the second wiring and the third wiring; and a first register and a second register, wherein a signal corresponding to the output of the first register is input to the control terminal of the first switch element, and a signal corresponding to the output of the second register is input to the control terminal of the second switch element, and the first register and the second register are arranged along the first direction.

[0010] A camera system according to one aspect of this disclosure includes the above-mentioned imaging device.

[0011] According to this disclosure, a switching element for mixing signals from pixels can be controlled with a simple configuration.

[0012] Figure 1 is a schematic plan view showing the configuration of an imaging device according to Embodiment 1. Figure 2A is a diagram showing the circuit configuration of an example of a pixel according to Embodiment 1. Figure 2B is a diagram showing the circuit configuration of another example of a pixel according to Embodiment 1. Figure 3A is a diagram showing the configuration of an example of a switch element according to Embodiment 1. Figure 3B is a diagram showing the configuration of another example of a switch element according to Embodiment 1. Figure 3C is a diagram showing the configuration of yet another example of a switch element according to Embodiment 1. Figure 4 is a schematic plan view showing the configuration of an imaging device according to Modification 1 of Embodiment 1. Figure 5 is a schematic plan view showing the configuration of an imaging device according to Modification 2 of Embodiment 1. Figure 6 is a schematic plan view showing the configuration of an imaging device according to Modification 3 of Embodiment 1. Figure 7 is a schematic plan view showing the configuration of an imaging device according to Modification 4 of Embodiment 1. Figure 8 is a schematic perspective view showing the configuration of an imaging device according to Modification 5 of Embodiment 1. Figure 9A is a schematic plan view showing the configuration of the first substrate of an imaging device according to Modification 5 of Embodiment 1. Figure 9B is a schematic plan view showing the configuration of the second substrate of an imaging device according to Modification 5 of Embodiment 1. Figure 10 is a schematic plan view showing the configuration of an imaging device according to Modification 6 of Embodiment 1. Figure 11 is a schematic plan view showing the configuration of an imaging device according to a modification 7 of Embodiment 1. Figure 12 is a schematic plan view showing the configuration of an imaging device according to a modification 8 of Embodiment 1. Figure 13 is a schematic plan view showing the configuration of an imaging device according to a modification 9 of Embodiment 1. Figure 14 is a time chart showing an example of the operation of an imaging device according to a modification 9 of Embodiment 1 when reading signals from pixels. Figure 15 is a schematic plan view showing the configuration of an imaging device according to Embodiment 2. Figure 16 is a schematic plan view showing the configuration of a first example of a mixed control circuit including a plurality of switch control units according to Embodiment 2. Figure 17 is a schematic plan view showing the configuration of a second example of a mixed control circuit including a plurality of switch control units according to Embodiment 2. Figure 18 is a schematic plan view showing the configuration of a third example of a mixed control circuit including a plurality of switch control units according to Embodiment 2. Figure 19 is a diagram showing the relationship between an address signal and a mixed signal in a mixed control circuit. Figure 20 is a time chart showing an example of the operation of a mixed control circuit. Figure 21 is a schematic plan view showing the configuration of a fourth example of a mixed control circuit including a plurality of switch control units according to Embodiment 2.Figure 22 is a schematic plan view showing the configuration of a fifth example of a mixed control circuit including a plurality of switch control units according to Embodiment 2. Figure 23 is a schematic plan view showing the configuration of a sixth example of a mixed control circuit including a plurality of switch control units according to Embodiment 2. Figure 24 is a block diagram showing an example of the configuration of a camera system according to Embodiment 3.

[0013] (Summary of this disclosure) An example of an imaging device and camera system related to this disclosure is shown below as an overview of this disclosure.

[0014] For example, an imaging device according to a first aspect of the present disclosure includes a first pixel and a second pixel, a first wiring to which a signal from the first pixel is input, a second wiring to which a signal from the second pixel is input, a first switch element connected between the first wiring and the second wiring, and a first shift register including a plurality of registers connected in series, wherein a signal corresponding to the output of the first register among the plurality of registers of the first shift register is input to the control terminal of the first switch element.

[0015] This allows the first switch element to mix the signal input from the first pixel to the first wiring and the signal input from the second pixel to the second wiring. Furthermore, a 1-bit memory element, such as a first register, can output a signal for controlling the first switch element. Therefore, the switch element for mixing signals from pixels can be controlled with a simple configuration.

[0016] Furthermore, for example, an imaging device according to a second aspect of the present disclosure is an imaging device according to a first aspect, further comprising a third pixel, a third wiring to which a signal from the third pixel is input, and a second switch element connected between the second wiring and the third wiring, wherein a signal corresponding to the output of the second register among the plurality of registers of the first shift register is input to the control terminal of the second switch element.

[0017] This allows the second switch element to mix the signal input from the second pixel to the second wiring with the signal input from the third pixel to the third wiring. Furthermore, a 1-bit memory element, such as a second register, can output a signal for controlling the second switch element. Therefore, the switch element for mixing signals from the pixels can be controlled with a simple configuration. Additionally, since the first and second registers are included in the first shift register, the settings of the first and second registers are determined by the settings of the first shift register. This allows for easy modification of the signal mixing behavior of the three pixels: the first, second, and third pixels.

[0018] Furthermore, for example, an imaging device according to a third aspect of the present disclosure comprises a first pixel, a second pixel, and a third pixel arranged along a first direction; a first wiring to which a signal from the first pixel is input; a second wiring to which a signal from the second pixel is input; a third wiring to which a signal from the third pixel is input; a first switch element connected between the first wiring and the second wiring; a second switch element connected between the second wiring and the third wiring; and a first register and a second register, wherein a signal corresponding to the output of the first register is input to the control terminal of the first switch element, and a signal corresponding to the output of the second register is input to the control terminal of the second switch element, and the first register and the second register are arranged along the first direction.

[0019] This allows the first switch element to mix the signal input from the first pixel to the first wiring with the signal input from the second pixel to the second wiring, and the second switch element to mix the signal input from the second pixel to the second wiring with the signal input from the third pixel to the third wiring. Furthermore, one-bit memory elements such as the first and second registers can output signals for controlling the first and second switch elements. Thus, the switch elements for mixing signals from pixels can be controlled with a simple configuration.

[0020] Furthermore, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to a first aspect, further comprising a third pixel and a fourth pixel, a third wiring to which a signal from the third pixel is input, a fourth wiring to which a signal from the fourth pixel is input, and a third switch element connected between the third wiring and the fourth wiring, wherein a signal corresponding to the output of the third register among the plurality of registers of the first shift register is input to the control terminal of the third switch element.

[0021] This allows the third switch element to mix the signal input from the third pixel to the third wiring with the signal input from the fourth pixel to the fourth wiring. Furthermore, a 1-bit memory element, such as the third register, can output a signal for controlling the third switch element. Therefore, the switch element for mixing signals from pixels can be controlled with a simple configuration. Moreover, since the first and third registers are included in the first shift register, the settings of the first and second registers are determined by the settings of the first shift register. This allows for easy switching between mixing the signals from the first and second pixels, and between mixing the signals from the third and fourth pixels.

[0022] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to a first aspect, further comprising a third pixel, a third wiring to which a signal from the third pixel is input, a second switch element connected between the second wiring and the third wiring, and a second shift register including a plurality of registers connected in series, wherein a signal corresponding to the output of the second register among the plurality of registers of the second shift register is input to the control terminal of the second switch element.

[0023] This allows the second switch element to mix the signal input from the second pixel to the second wiring with the signal input from the third pixel to the third wiring. Furthermore, a 1-bit memory element, such as a second register, can output a signal for controlling the second switch element. Therefore, the switch element for mixing signals from the pixels can be controlled with a simple configuration. Additionally, since the first register is included in the first shift register and the second register is included in the second shift register, the setting time for the settings of the first and second registers can be shortened.

[0024] Furthermore, for example, an imaging device according to a sixth aspect of the present disclosure is an imaging device according to a first aspect, wherein the first pixel and the second pixel are arranged along a first direction, the imaging device further comprises the first pixel and a third pixel arranged along a second direction intersecting the first direction, a third wiring to which a signal from the third pixel is input, a second switch element connected between the first wiring and the third wiring, and a second shift register including a plurality of registers connected in series, wherein a signal corresponding to the output of the second register among the plurality of registers of the second shift register is input to the control terminal of the second switch element.

[0025] This allows the signals of the first and second pixels, which are arranged along the first direction, to be mixed by the first switch element, and the signals of the first and third pixels, which are arranged along the second direction, to be mixed by the second switch element. Thus, it becomes possible to mix the signals of pixels arranged in different directions.

[0026] Furthermore, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to a sixth aspect, further comprising a second pixel, a fourth pixel arranged along the second direction, a fourth wiring to which a signal from the fourth pixel is input, and a third switch element connected between the second wiring and the fourth wiring, wherein a signal corresponding to the output of the third register among the plurality of registers of the second shift register is input to the control terminal of the third switch element.

[0027] This allows the signals of the second and fourth pixels, which are arranged along the second direction, to be mixed by the third switching element. Thus, it becomes possible to mix the signals of pixels arranged in a two-dimensional array.

[0028] Furthermore, for example, the imaging device according to the eighth aspect of the present disclosure is an imaging device according to any one of the first, second, and fourth to seventh aspects, wherein the first shift register is a series-input parallel-output type shift register.

[0029] This allows serial signals to be used as input.

[0030] Furthermore, for example, an imaging device according to a ninth aspect of the present disclosure is an imaging device according to a first aspect, further comprising a plurality of pixels arranged in row and column directions, including the first pixel and the second pixel, and a fourth switch element, each of the plurality of pixels including a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge, the first pixel and the second pixel are arranged along the row direction, the plurality of pixels include the first pixel and a third pixel arranged along the column direction, and the fourth switch element is connected between the charge storage unit of the first pixel and the charge storage unit of the third pixel.

[0031] As a result, the first switch element can mix the signals of the first and second pixels arranged along the row direction, and the fourth switch element can mix the signals of the first and third pixels arranged along the column direction. Therefore, it becomes possible to mix the pixel signals in both the row and column directions.

[0032] Furthermore, for example, an imaging device according to a tenth aspect of the present disclosure is an imaging device according to a first aspect, further comprising a plurality of pixels arranged in a row direction and a column direction, including the first pixel and the second pixel, each of the plurality of pixels including a photoelectric conversion unit that converts light into a signal charge, a charge storage unit that stores the signal charge, and a transistor whose source and drain are connected to the charge storage unit, the first pixel and the second pixel are arranged along the row direction, the plurality of pixels include the first pixel and a third pixel arranged along the column direction, the other of the source and drain of the transistor of the first pixel is connected via the first wiring to the other of the source and drain of the transistor of the third pixel.

[0033] As a result, the first switch element can mix the signals of the first and second pixels arranged along the row direction, and the transistors of the first and third pixels can mix the signals of the first and third pixels arranged along the column direction. Therefore, it becomes possible to mix the pixel signals in both the row and column directions.

[0034] Furthermore, for example, an imaging device according to the 11th aspect of the present disclosure is an imaging device according to any one of the first to tenth aspects, wherein each of the first pixel and the second pixel includes a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge, and the photoelectric conversion unit includes a first electrode connected to the charge storage unit, a second electrode facing the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode.

[0035] This allows for the control of a switching element for mixing signals from pixels in an imaging device having a stacked photoelectric conversion unit, using a simple configuration.

[0036] Furthermore, for example, an imaging device according to a twelfth aspect of the present disclosure is an imaging device according to any one of the first to tenth aspects, further comprising a semiconductor substrate, wherein each of the first pixel and the second pixel includes a photoelectric conversion unit that converts light into a signal charge, and the photoelectric conversion unit is a photodiode located within the semiconductor substrate.

[0037] As a result, in a photodiode type imaging device, a switch element for mixing signals from pixels can be controlled with a simple configuration.

[0038] Further, for example, the imaging device according to the 13th aspect of the present disclosure is an imaging device according to any one of the 1st aspect, the 2nd aspect, and the 4th aspect to the 10th aspect, and further includes a rewritable memory that holds data input to the 1st shift register.

[0039] As a result, by rewriting the data held in the memory, the control of the 1st switch element can be changed.

[0040] Further, for example, the imaging device according to the 14th aspect of the present disclosure is an imaging device according to any one of the 1st aspect, the 2nd aspect, and the 4th aspect to the 10th aspect, and further includes a non-rewritable memory that holds data input to the 1st shift register.

[0041] As a result, it is not necessary to input the set value to the memory each time.

[0042] Further, for example, the imaging device according to the 15th aspect of the present disclosure is an imaging device according to any one of the 1st aspect to the 14th aspect, and further includes an AD conversion circuit that converts a signal from the 1st pixel into a digital signal, and a signal corresponding to the output of the 1st register is configured to be input to the AD conversion circuit, and the AD conversion circuit switches between an operating state and a standby state according to the signal from the 1st register.

[0043] As a result, the AD conversion circuit can be put into a standby state as needed by the 1st register, so that power consumption can be reduced. In addition, since the state of the AD conversion circuit can be switched by a 1-bit storage element such as the 1st register, the AD conversion circuit can be controlled with a simple configuration.

[0044] Further, for example, the camera system according to the 16th aspect of the present disclosure includes an imaging device according to any one of the 1st aspect to the 15th aspect.

[0045] As a result, since the camera system according to this aspect includes the above imaging device, a switch element for mixing signals from pixels can be controlled with a simple configuration.

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that each of the embodiments described below shows a comprehensive or specific example. The numerical values, shapes, materials, components, arrangements and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in this specification can be combined with each other as long as there is no contradiction. In addition, among the components in the following embodiments, the components not described in the independent claims are described as optional components. In each figure, components having substantially the same function are denoted by common reference numerals, and redundant descriptions may be omitted or simplified.

[0047] In addition, the various elements shown in the drawings are merely schematically shown for the purpose of understanding the present disclosure, and the dimensional ratios and appearances may be different from the actual ones. That is, each figure is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, the scales in each figure do not necessarily match.

[0048] In this specification, terms indicating the relationship between elements such as parallel or coincident, terms indicating the shape of elements such as rectangular, and numerical ranges are not expressions representing only strict meanings, but expressions meaning substantially equivalent ranges, for example, including differences of about several percent.

[0049] In this specification, "connection" means an electrical connection unless otherwise specified. Also, "C is connected between A and B" means that a part of C (for example, one end) is connected to A and another part of C (for example, the other end) is connected to B, and C is arranged in series in the path connecting A and B. The "path connecting A and B" means a path composed of a conductor that electrically connects A and B.

[0050] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0051] Furthermore, in this specification, a register refers to a memory element that holds one bit of information. A specific example of a register is a flip-flop.

[0052] (Embodiment 1) The imaging device according to Embodiment 1 will be described below. Figure 1 is a schematic plan view showing the configuration of the imaging device 100 according to this embodiment.

[0053] As shown in Figure 1, the imaging device 100 includes a pixel array PA composed of a plurality of pixels 24, a plurality of signal lines 27, a plurality of switch elements 50, a shift register 70 including a plurality of registers 60, a plurality of A / D conversion circuits 30, a memory 40, and a vertical scanning circuit 25. In the example shown in Figure 1, the imaging device 100 includes a semiconductor substrate 5, and the pixel array PA, the plurality of signal lines 27, the plurality of switch elements 50, the shift register 70, the plurality of A / D conversion circuits 30, the memory 40, and the vertical scanning circuit 25 are formed on the semiconductor substrate 5. The imaging device 100 may also have a structure in which a plurality of semiconductor substrates are stacked. In this case, the pixel array PA, the plurality of signal lines 27, the plurality of switch elements 50, the shift register 70, the plurality of A / D conversion circuits 30, the memory 40, and the vertical scanning circuit 25 may be formed separately on a plurality of semiconductor substrates. Also, for ease of viewing, Figure 1 shows the configuration of the imaging device 100 necessary for explanation, and the imaging device 100 may include circuits and wiring that are not shown. For example, the imaging device 100 may include a control circuit that outputs signals for various control purposes, which will be described later.

[0054] Multiple pixels 24 are arranged in both row and column directions. In this specification and in each drawing, the X-axis direction is the row direction of the multiple pixels 24, and the Y-axis direction is the column direction of the multiple pixels 24. Furthermore, below, the row direction of the multiple pixels 24 may be simply referred to as the "row direction," and the column direction of the multiple pixels 24 may be simply referred to as the "column direction." Also, the X-axis direction is an example of a first direction, and the Y-axis direction is an example of a second direction.

[0055] Furthermore, Figure 1 shows the configuration of a portion of the imaging device 100, and the multiple pixels 24 are arranged in the row and column directions, as well as in areas not shown. In addition, the same configuration is repeated along the row direction for components other than the pixels 24, such as the multiple switch elements 50 which will be described later. These are also the same in the drawings of the imaging device according to the present disclosure which will be described later. The number of columns of the multiple pixels 24 is, for example, 10 or more, and may be 100 or more.

[0056] In Figure 1, each pixel 24 is represented by a rectangle labeled "R," "B," "Gr," or "Gb." "R," "B," "Gr," and "Gb" indicate the color of the color filter contained within the pixel 24. "R" indicates a red color filter. A pixel 24 labeled "R" is a red (R) pixel. "B" indicates a blue color filter. A pixel 24 labeled "B" is a blue (B) pixel. "Gr" and "Gb" indicate green color filters. A pixel 24 labeled "Gr" is a green (Gr) pixel in the same row as a red pixel. A pixel 24 labeled "Gb" is a green (Gb) pixel in the same row as a blue pixel. In the example shown in Figure 1, the color array of multiple pixels 24 is a Bayer array. However, the color array of multiple pixels 24 is not particularly limited and may be an array other than a Bayer array, such as a quad Bayer array.

[0057] The vertical scanning circuit 25 is connected to each pixel 24 via control lines, which will be described in detail later. A control line is provided for each row of multiple pixels 24 and is electrically connected to one or more pixels 24 belonging to the same row. Each row of pixels 24 may have two or more control lines. The vertical scanning circuit 25 selects pixels 24 row by row by applying a predetermined voltage to the control lines and causes the pixels 24 to output signals and perform reset operations, etc.

[0058] A signal line 27 is provided for each row of pixels 24 and is connected to the corresponding pixel 24 in that row. Each of the signal lines 27 receives the signal output by the corresponding pixel 24 in that row. An AD conversion circuit 30 is also connected to each of the signal lines 27. In Figure 1, an AD conversion circuit 30 connected to a signal line 27 to which Gr pixels and B pixels are connected is shown, but there are also AD conversion circuits 30 (not shown) connected to signal lines 27 to which R pixels and Gb pixels are connected.

[0059] The signal from the pixel 24 input to the signal line 27 is input to the corresponding AD conversion circuit 30 among the multiple AD conversion circuits 30 provided for each row of multiple pixels 24 corresponding to the signal line 27.

[0060] Multiple A / D conversion circuits 30 are connected to signal lines 27 for each row of multiple pixels 24. The A / D conversion circuits 30 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion). The digital signal converted by the A / D conversion circuits 30 is processed as needed and output to the outside of the imaging device 100.

[0061] Here, the circuit configuration of the pixel 24 will be described. Figure 2A shows the circuit configuration of pixel 24A, which is an example of a pixel 24 according to this embodiment. Figure 2B shows the circuit configuration of pixel 24B, which is another example of a pixel 24 according to this embodiment. The circuit configurations of multiple pixels 24 are the same as those of each other. Each pixel 24 is, for example, pixel 24A having the circuit configuration shown in Figure 2A or pixel 24B having the circuit configuration shown in Figure 2B.

[0062] First, the circuit configuration of pixel 24A shown in Figure 2A will be described. Pixel 24A includes a photoelectric conversion unit 10A, a charge detection circuit for detecting the signal charge generated by the photoelectric conversion unit 10A, and a charge storage node 34 electrically connected to the photoelectric conversion unit 10A and the charge detection circuit. The charge storage node 34 stores the signal charge generated by the photoelectric conversion unit 10A. The charge detection circuit of pixel 24A detects the signal charge stored in the charge storage node 34. The charge detection circuit of pixel 24A includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0063] The photoelectric conversion unit 10A includes a photoelectric conversion layer 3, a pixel electrode 2, and a counter electrode 4. The entire photoelectric conversion unit 10A does not need to be an independent element for each pixel 24A; a part of the photoelectric conversion unit 10A may span multiple pixels 24A. The photoelectric conversion layer 3 receives incident light and generates positive and negative charges through photoelectric conversion. Positive and negative charges are typically hole-electron pairs. One of the holes and electrons generated in the photoelectric conversion layer 3 is used as a signal charge. In the photoelectric conversion unit 10A, the signal charge generated by the photoelectric conversion of the photoelectric conversion layer 3 is collected by the pixel electrode 2.

[0064] The pixel electrode 2 is connected to the gate of the amplification transistor 21, and the signal charge collected by the pixel electrode 2 is stored in a charge storage node 34 located between the pixel electrode 2 and the gate of the amplification transistor 21. The signal charge is, for example, a hole. That is, the charge storage node 34 is electrically connected to the pixel electrode 2 and stores the holes generated in the photoelectric conversion layer 3. In the following, unless otherwise specified, the case where the signal charge is a hole will be described. Note that the signal charge may also be an electron.

[0065] A voltage is supplied to the counter electrode 4 via the counter electrode signal line 26 to apply a predetermined bias voltage. When the imaging device 100 is in operation, a predetermined bias voltage is applied to the counter electrode signal line 26. By applying a predetermined bias voltage to the counter electrode 4, one of the positive and negative charges generated by photoelectric conversion can be selectively stored as a signal charge in the charge storage node 34. Specifically, when a bias voltage is applied to the counter electrode 4 such that the potential of the counter electrode 4 is higher than the potential of the pixel electrode 2, the holes, which are signal charges, move to the pixel electrode 2 and are stored in the charge storage node 34.

[0066] The amplification transistor 21, reset transistor 22, and address transistor 23 are, for example, field-effect transistors (FETs). In the example shown in Figure 2A, each of the amplification transistor 21, reset transistor 22, and address transistor 23 is an N-channel MOSFET (Metal Oxide Semiconductor FET). Note that which of the two diffusion regions of the FET corresponds to the source and which corresponds to the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and which is the drain may vary depending on the operating state of the FET.

[0067] As shown in Figure 2A, the gate of the amplification transistor 21 is electrically connected to the pixel electrode 2. The signal charge generated by the photoelectric conversion unit 10A is stored in a charge storage node 34 between the pixel electrode 2 and the gate of the amplification transistor 21. The charge storage node 34 is connected to the pixel electrode 2, the gate of the amplification transistor 21, and one of the source and drain of the reset transistor 22. The charge storage node 34 includes wiring connecting the pixel electrode 2, the amplification transistor 21, and the reset transistor 22. The signal charge stored in the charge storage node 34 is applied to the gate of the amplification transistor 21 as a voltage corresponding to the amount of signal charge. The charge storage node 34 is an example of a charge storage unit.

[0068] One of the sources and drains of the amplification transistor 21 is connected to a power supply wiring 31 that supplies a predetermined power supply voltage to each pixel 24A when the imaging device 100 is operating. The amplification transistor 21 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion unit 10A. The other of the sources and drains of the amplification transistor 21 is connected to one of the sources and drains of the address transistor 23.

[0069] A signal line 27 is connected to the source and the other drain of the address transistor 23. A current source (not shown in Figures 1 and 2A, but shown later in Figure 12 as current source 28) is connected to the signal line 27, for example, to form a source follower circuit together with the amplifying transistor 21.

[0070] The address signal line 36 is connected to the gate of the address transistor 23. The address signal line 36 is one of the control lines connected to the vertical scanning circuit 25. The vertical scanning circuit 25 applies a row selection signal to the address signal line 36 to control the on and off states of the address transistor 23. This causes the row to be read to be scanned in the column direction and the row to be read to be selected. By controlling the on and off states of the address transistor 23 via the address signal line 36, the vertical scanning circuit 25 can input the output of the amplification transistor 21 as the signal of the selected pixel 24A to the corresponding signal line 27.

[0071] A reset signal line 37, which is connected to the vertical scanning circuit 25, is connected to the gate of the reset transistor 22. The reset signal line 37 is one of the control lines connected to the vertical scanning circuit 25. The vertical scanning circuit 25 applies a reset signal to the gate of the reset transistor 22 via the reset signal line 37 to control the on and off states of the reset transistor 22. This allows for the selection of pixels 24A to be reset row by row. When the reset transistor 22 is turned on, the potential of the charge storage node 34 is reset.

[0072] In the example shown in Figure 2A, the source and the other drain of the reset transistor 22 are connected to a reset voltage line 33 that supplies a predetermined reset voltage to the pixel 24A when the pixel 24A is reset. That is, in this example, a reset voltage that initializes the potential of the charge storage node 34 is supplied to the charge storage node 34 via the reset transistor 22. The reset voltage line 33 is provided, for example, for each row of multiple pixels 24 and is connected to the pixel 24 of the corresponding row. Each reset voltage line 33 corresponding to each row of multiple pixels 24 is connected to a voltage source for supplying one reset voltage, but it may also be connected to two or more voltage sources for supplying reset voltages. Note that if a reset voltage is supplied to the other end of the source and drain of the reset transistor 22, the reset voltage line 33 does not need to be provided for each row of multiple pixels 24. Furthermore, the configuration in which the source and the other end of the reset transistor 22 are connected to the reset voltage line 33 is not limited to that which is connected to the reset voltage line 33, but may also be connected to a feedback line connected to the output of a feedback amplifier that feeds back the output from the pixel 24A.

[0073] Next, the circuit configuration of pixel 24B shown in Figure 2B will be described. In the following description of the circuit configuration of pixel 24B, the differences from the description of the circuit configuration of pixel 24A will be the main focus, and the explanation of the common points will be omitted or simplified.

[0074] Pixel 24B includes a photoelectric conversion unit 10B, a charge detection circuit for detecting the signal charge generated by the photoelectric conversion unit 10B, and a charge storage node 34 provided in the charge detection circuit. The charge detection circuit of pixel 24B includes an amplification transistor 21, a reset transistor 22, an address transistor 23, and a transfer transistor 18. In pixel 24B, the charge storage node 34 stores the signal charge generated by the photoelectric conversion unit 10B, and the charge detection circuit of pixel 24B detects the signal charge stored in the charge storage node 34. Pixel 24B has a circuit configuration in which the photoelectric conversion unit 10A of pixel 24A is replaced with the photoelectric conversion unit 10B, and a transfer transistor 18 is added.

[0075] The photoelectric conversion unit 10B is a photodiode located within the semiconductor substrate 5. The photoelectric conversion unit 10B receives incident light and generates a signal charge through photoelectric conversion. The signal charge generated by the photoelectric conversion unit 10B is transferred to the charge storage node 34 by the transfer transistor 18.

[0076] The transfer transistor 18 is, for example, a field-effect transistor. In the example shown in Figure 2B, an N-channel MOSFET is used for the transfer transistor 18.

[0077] As shown in Figure 2B, one of the source and drain of the transfer transistor 18 is connected to the photoelectric conversion unit 10B. The other of the source and drain of the transfer transistor 18 is connected to the charge storage node 34. A transfer signal line 19 is connected to the gate of the transfer transistor 18. The transfer signal line 19 is one of the control lines connected to the vertical scanning circuit 25. The vertical scanning circuit 25 applies a transfer control signal to the gate of the transfer transistor 18 via the transfer signal line 19 to control the on and off states of the transfer transistor 18. When the transfer transistor 18 is turned on, the signal charge generated in the photoelectric conversion unit 10B is transferred to the charge storage node 34.

[0078] The signal charge generated by the photoelectric conversion unit 10B is stored in the charge storage node 34. In the pixel 24B, the charge storage node 34 is connected to the source and drain of the transfer transistor 18, the gate of the amplification transistor 21, and one of the source and drain of the reset transistor 22.

[0079] In pixel 24B, the source and the other drain of the reset transistor 22 are connected to the power supply wiring 31. In addition, in pixel 24B, the source and the other drain of the reset transistor 22 may also be connected to the reset voltage line 33 or the feedback line, similar to pixel 24A.

[0080] Referring again to Figure 1, each of the multiple switch elements 50 is connected between two signal lines 27 that correspond to different columns of multiple pixels 24. Specifically, each of the multiple switch elements 50 is connected between two adjacent signal lines 27 to which pixels 24 arranged in columns in the same color sequence are connected. For example, a switch element 50 is connected between every two adjacent signal lines 27 to which pixels 24 arranged in columns in the same color sequence are connected. In the example shown in Figure 1, the multiple switch elements 50 are arranged along the row direction.

[0081] The multiple switch elements 50 are arranged in the row direction at positions corresponding to the pixel array PA. For example, the multiple switch elements 50 are arranged in the row direction within the range where the pixel array PA is located. In Figure 1, multiple switch elements 50 are shown connected between two signal lines 27 to which Gr pixels and B pixels are connected among the multiple pixels 24, but there are also multiple switch elements 50 (not shown) connected between two signal lines 27 to which R pixels and Gb pixels are connected among the multiple pixels 24. For example, multiple switch elements 50, a shift register 70, a memory 40, and an AD conversion circuit 30 may be arranged on the positive side of the Y-axis direction of the pixel array PA, similar to the negative side of the Y-axis direction of the pixel array PA.

[0082] In this embodiment, the signal line 27 connected to the first pixel 24a1 among the plurality of pixels 24 is an example of a first wiring. The signal line 27 connected to the second pixel 24a2 among the plurality of pixels 24 is an example of a second wiring. The signal line 27 connected to the third pixel 24a3 among the plurality of pixels 24 is an example of a third wiring. The first pixel 24a1, the second pixel 24a2, and the third pixel 24a3 are pixels of the same color and are arranged along the row direction. The first pixel 24a1, the second pixel 24a2, and the third pixel 24a3 are adjacent pixels of the same color. The switch element 50 connected between the first wiring and the second wiring and the register 60 that outputs a signal to the switch element 50 are examples of a first switch element and a first register, respectively. The switch element 50 connected between the second wiring and the third wiring and the register 60 that outputs a signal to the switch element 50 are examples of a second switch element and a second register, respectively.

[0083] Each of the multiple switch elements 50 controls the conduction and non-conductivity of two signal lines 27 corresponding to different rows of multiple pixels 24. By making the two signal lines 27 conduction, the switch elements 50 can mix the signals output by the pixels 24 connected to the two signal lines 27.

[0084] Each switch element 50 has a control terminal that is configured to receive a signal corresponding to the output of the register 60. Each switch element 50 is controlled to be on or off by the setting value ("0" or "1") of the register 60. For example, if the output of the register 60 is a signal indicating "1", the switch element 50 is in the ON state and conducts through the two signal lines 27. On the other hand, if the output of the register 60 is a signal indicating "0", the switch element 50 is in the OFF state and deconducts through the two signal lines 27. A signal indicating "1" is, for example, a high-level voltage, and a signal indicating "0" is, for example, a low-level voltage.

[0085] Here, the specific configuration of the switch element 50 will be described. Figure 3A shows the configuration of switch element 50A, which is an example of the switch element 50 according to this embodiment. Figure 3B shows the configuration of switch element 50B, which is another example of the switch element 50 according to this embodiment. Figure 3C shows the configuration of switch element 50C, which is yet another example of the switch element 50 according to this embodiment. The configurations of the multiple switch elements 50 are the same as each other. Each switch element 50 is, for example, switch element 50A having the configuration shown in Figure 3A, switch element 50B having the configuration shown in Figure 3B, or switch element 50C having the configuration shown in Figure 3C.

[0086] The switch element 50A shown in Figure 3A is a COMMS switch. The switch element 50B shown in Figure 3B is a MOS switch. Because switch element 50B is a MOS switch, miniaturization is possible. Furthermore, the switch element 50C shown in Figure 3C has a configuration in which a level shifter 50d is added to switch element 50B to convert the voltage level input to the gate of the transistor of the MOS switch. In switch element 50C, the output voltage of the register 60 can be reduced by increasing the signal level (voltage) output from the register 60 by the level shifter 50d. Therefore, it is possible to miniaturize the transistor included in the register 60.

[0087] Referring again to Figure 1, the shift register 70 includes a plurality of registers 60 connected in series. In this embodiment, the shift register 70 is an example of a first shift register. The shift register 70 is a series-input, parallel-output type shift register. The plurality of registers 60 are arranged along the row direction. The shift register 70 is positioned in the row direction at a location corresponding to the pixel array PA. For example, the shift register 70 is positioned in the row direction within the range where the pixel array PA is located.

[0088] The settings of each register 60 of the shift register 70 are stored in the memory 40. The settings of each register 60 stored in the memory 40 are set in each register 60 by the shift clock ShiftCLK and the reset signal RST. Each of the multiple registers 60 outputs a signal corresponding to the setting value to one of the control terminals of the multiple switch elements 50. In the example shown in Figure 1, the multiple switch elements 50 and the multiple registers 60 are arranged in a one-to-one correspondence. The pitch in which the multiple registers 60 are arranged is, for example, the same as the pitch in which the multiple switch elements 50 are arranged.

[0089] Memory 40 holds the setting values ​​of each register 60 of the shift register 70, which are data input to the shift register 70. The setting values ​​of each register 60 are stored in memory 40 via the data bus 91 from, for example, an external controller 90 of the imaging device 100. The controller 90 stores the setting values ​​of each register 60 in memory 40 based on input from the user regarding the setting values. The controller 90 may store the setting values ​​of each register 60 in memory 40 according to the imaging mode of the imaging device 100. The controller 90 may be connected to the imaging device 100 at all times, or it may not be connected to the imaging device 100 except when storing the setting values ​​of each register 60 in memory 40. The controller 90 may also be the system controller 603 in the camera system 400 described later. The imaging device 100 may also be equipped with the controller 90.

[0090] Memory 40 is, for example, a rewritable memory. Memory 40 may also be a volatile memory such as SRAM (Static Random Access Memory). For example, if memory 40 is SRAM, it is possible to miniaturize memory 40.

[0091] Furthermore, the memory 40 may be a non-rewritable memory such as OTP (One Time Programmable) memory. In this case, for example, the setting values ​​of each register 60 are stored in the memory 40 when the imaging device 100 is shipped. This eliminates the need to input setting values ​​to the controller 90 each time.

[0092] With the configuration of the imaging device 100 according to this embodiment described above, signals for controlling multiple switch elements 50 are output from each register 60 of the shift register 70. Therefore, signals for controlling the switch elements 50 can be output by a 1-bit memory element such as a register 60. Thus, in the imaging device 100, the switch elements 50 for mixing signals from the pixels 24 can be controlled with a simple configuration.

[0093] Furthermore, when an imaging device is used in devices such as smartphones and digital cameras, depending on the size of the lens mounted on the device, it may or may not use all the pixels of the imaging device to generate an image. In other words, the range of pixels used to generate an image (angle of view) may change depending on the application of the imaging device. Also, the range of pixels used to generate an image may change when the user of the imaging device uses a lens or lens hood of their choice.

[0094] Furthermore, imaging devices may be required to have two modes: one that outputs a signal at maximum resolution without mixing the pixel signals, and another that outputs a signal at lower resolution by mixing the signals of multiple pixels. In this case, these modes can be realized, for example, by using a technique to control whether or not to mix the signals output from multiple pixels before outputting them.

[0095] When an imaging device operates in a mode that outputs a signal at a low resolution, changing the range of pixels used to generate the image will change the number of pixels mixed, even if the signal output is at the same low resolution. For example, to achieve the same resolution for the generated image, using only a portion of the pixels of the imaging device to generate the image will result in fewer pixels being mixed than using all of the pixels of the imaging device to generate the image. Furthermore, even if the range of pixels used to generate the image remains the same, changing the resolution of the generated image will also change the number of pixels being mixed.

[0096] Therefore, when mixing signals output from multiple pixels, a technology is needed that allows the signals from pixels to be mixed at any arbitrary position.

[0097] In contrast, in the technology described in Patent Document 1, the pixels to be mixed are fixed, and it is not possible to mix the signals of pixels at an arbitrary position.

[0098] Furthermore, in the technology described in Patent Document 2, the operation of switches connecting two or more signal lines is individually controlled by the control unit, so it is possible to mix the pixel signals at any position. However, in the technology described in Patent Document 2, all switches are controlled from a single control unit, so as the number of switches increases with the number of pixels, the number of control lines for controlling the switches coming out of the control unit also increases, resulting in a dense arrangement of control lines, which makes implementation difficult from a structural standpoint.

[0099] On the other hand, in the imaging device 100 according to this embodiment, the on and off states of multiple switch elements 50 can be individually switched by the setting values ​​of each register 60 of the shift register 70. Therefore, the combination in which the signal lines 27 are conducted can be arbitrarily changed. Thus, in the imaging device 100, the signals of the pixels 24 can be mixed at any position by the multiple switch elements 50. Furthermore, since signals are output from each of the multiple registers 60 connected in series to the multiple switch elements 50, the control lines are not densely packed, and the structure is easy to implement.

[0100] [Modification 1] Next, Modification 1 of Embodiment 1 will be described. In the following, the differences from Embodiment 1 described above will be the focus of the explanation, and the explanation of the common points will be omitted or simplified.

[0101] Figure 4 is a schematic plan view showing the configuration of the imaging device 101 according to this modified example. In Figure 4, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 101 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91.

[0102] As shown in Figure 4, the imaging device 101 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that it is equipped with shift registers 71 and 72, memory 41 and 42 instead of shift registers 70 and memory 40. While the imaging device 100 was equipped with one system of shift registers 70, the imaging device 101 is equipped with two systems of shift registers 71 and 72.

[0103] Shift register 71 includes a plurality of registers 61 connected in series. The plurality of registers 61 are arranged along the row direction. Shift register 72 includes a plurality of registers 62 connected in series. The plurality of registers 62 are arranged along the row direction. In Figure 4, one register 62 is shown, but there are further registers 62 on the positive side of the illustrated register 62 in the X-axis direction. Shift registers 71 and 72 are series-input, parallel-output type shift registers. Shift registers 71 and 72 are positioned in the row direction at locations corresponding to the pixel array PA. For example, shift registers 71 and 72 are positioned in the row direction within the range where the pixel array PA is located. The control terminals of each switch element 50 are configured to receive signals corresponding to the output of register 61 or register 62.

[0104] In this modified example, shift register 71 is an example of a first shift register. Shift register 72 is an example of a second shift register. A signal line 27 connected to the first pixel 24a1 among the plurality of pixels 24 is an example of a first wiring. A signal line 27 connected to the second pixel 24a2 among the plurality of pixels 24 is an example of a second wiring. A signal line 27 connected to the third pixel 24a3 among the plurality of pixels 24 is an example of a third wiring. A switch element 50 connected between the first wiring and the second wiring, and a register 61 that outputs a signal to the switch element 50, are examples of a first switch element and a first register, respectively. A switch element 50 connected between the second wiring and the third wiring, and a register 62 that outputs a signal to the switch element 50, are examples of a second switch element and a second register, respectively.

[0105] The settings of each register 61 in the shift register 71 are stored in the memory 41. The settings of each register 61 stored in the memory 41 are set in each register 61 by the shift clock ShiftCLK1 and the reset signal RST1. Each of the multiple registers 61 outputs a signal corresponding to the setting value to one of the control terminals of some of the multiple switch elements 50.

[0106] The settings of each register 62 in the shift register 72 are stored in the memory 42. The settings of each register 62 stored in the memory 42 are set in each register 62 by the shift clock ShiftCLK2 and the reset signal RST2. Each of the multiple registers 62 outputs a signal corresponding to the setting value to one of the control terminals of the remaining switch elements 50 that do not receive signals from the multiple registers 61. In the example shown in Figure 4, registers 61 and 62 alternately output signals corresponding to the setting values ​​to the control terminals of the multiple switch elements 50 arranged in the row direction.

[0107] In the example shown in Figure 4, the multiple switch elements 50, multiple registers 61, and multiple registers 62 are arranged such that one register 61 and one register 62 correspond to every two switch elements 50.

[0108] Memory 41 holds the setting values ​​of each register 61 of the shift register 71, which are the data input to the shift register 71. Memory 42 holds the setting values ​​of each register 62 of the shift register 72, which are the data input to the shift register 72. The setting values ​​of each register 61 and each register 62 are stored in memory 41 and memory 42, respectively, from the controller 90 (see Figure 1) via the data bus 91 (see Figure 1). Memory 41 and memory 42 are, for example, rewritable memories. Memory 41 and memory 42 may be volatile memories such as SRAM.

[0109] In the imaging device 101, multiple switch elements 50 are controlled by signals output by registers 61 and 62 of two shift registers 71 and 72. Therefore, the setting time for the set values ​​of each register 61 and 62 for controlling the multiple switch elements 50 can be shortened.

[0110] [Modification 2] Next, Modification 2 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modification 1 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0111] Figure 5 is a schematic plan view showing the configuration of the imaging device 102 according to this modified example. In Figure 5, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 102 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91.

[0112] As shown in Figure 5, the imaging device 102 according to this modified example differs from the imaging device 101 according to Modification 1 of Embodiment 1 mainly in that it further includes a plurality of selectors 80. Furthermore, the imaging device 102 according to this modified example also differs from the imaging device 101 according to Modification 1 of Embodiment 1 in that the outputs of the plurality of registers 61 included in the shift register 71 and the plurality of registers 62 included in the shift register 72 are configured to be input to the control terminals of the plurality of switch elements 50 via the plurality of selectors 80.

[0113] In the imaging device 102, multiple switch elements 50 and multiple registers 61 are arranged in a one-to-one correspondence. Furthermore, multiple switch elements 50 and multiple registers 62 are arranged in a one-to-one correspondence.

[0114] In the imaging device 102, each switch element 50 is configured to receive input to its control terminal, which is selected by a selector 80 from either the signal corresponding to the output of register 61 or the signal corresponding to the output of register 62. Based on the selection signal SEL, the selector 80 selects one of the signals corresponding to the output of register 61 or the signal corresponding to the output of register 62 and outputs it to the control terminal of the switch element 50. Multiple selectors 80 are controlled collectively by the selection signal SEL, and the selection of which signal from the signal corresponding to the output of register 61 or the signal corresponding to the output of register 62 is unified.

[0115] In the imaging device 102, the selection signal SEL allows the user to choose which of the two shift registers 71 and 72 to use to control the multiple switch elements 50. This allows the user to change the setting value of a shift register that was not used to control the multiple switch elements 50 before the switch when switching the pixels 24 to which signals are mixed, eliminating the need to wait for the shift register setting value to be changed. Therefore, for example, even if the blank period between frames is short, the pixels 24 to which signals are mixed can be changed frame by frame.

[0116] [Modification 3] Next, Modification 3 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 and 2 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0117] Figure 6 is a schematic plan view showing the configuration of the imaging device 103 according to this modified example. In Figure 6, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 103 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91.

[0118] As shown in Figure 6, the imaging device 103 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that it has multiple switch elements 51 instead of multiple switch elements 50.

[0119] In this modified example, the signal line 27 connected to the first pixel 24d1 among the multiple pixels 24 is an example of the first wiring. The signal line 27 connected to the second pixel 24d2 among the multiple pixels 24 is an example of the second wiring. The signal line 27 connected to the third pixel 24d3 among the multiple pixels 24 is an example of the third wiring. The signal line 27 connected to the fourth pixel 24d4 among the multiple pixels 24 is an example of the fourth wiring. The first pixel 24d1, second pixel 24d2, third pixel 24d3 and fourth pixel 24d4 are arranged continuously along the row direction. The switch element 51 connected between the first wiring and the second wiring and the register 60 that outputs a signal to the switch element 51 are examples of the first switch element and the first register, respectively. The switch element 51 connected between the second wiring and the third wiring and the register 60 that outputs a signal to the switch element 51 are examples of the second switch element and the second register, respectively. Furthermore, the switch element 51 connected between the third and fourth wiring and the register 60 that outputs a signal to the switch element 51 are examples of the third switch element and the third register, respectively.

[0120] Each of the multiple switch elements 51 is connected to two signal lines 27 to which pixels 24 arranged in columns with different color arrangements are connected. In the example shown in Figure 6, each of the multiple switch elements 51 is connected between two adjacent signal lines 27. For example, a switch element 51 is connected between each pair of adjacent signal lines 27. Each of the multiple switch elements 51 controls the conduction and non-conductivity of the two signal lines 27 to which pixels 24 arranged in columns with different color arrangements are connected. By making the two signal lines 27 conductive, the signals output by the pixels 24 connected to the two signal lines 27 can be mixed.

[0121] In the example shown in Figure 6, the multiple switch elements 51 are arranged along the row direction. The multiple switch elements 51 are positioned in the row direction at locations corresponding to the pixel array PA. For example, the multiple switch elements 51 are arranged in the row direction within the range where the pixel array PA is located.

[0122] Each switch element 51 is configured to receive a signal corresponding to the output of the register 60 at its control terminal. Each switch element 51 is controlled to be on or off by the setting value ("0" or "1") of the register 60.

[0123] The configurations of the multiple switch elements 51 are the same. Each switch element 51 is, for example, a switch element 50A having the configuration shown in Figure 3A, a switch element 50B having the configuration shown in Figure 3B, or a switch element 50C having the configuration shown in Figure 3C.

[0124] Each of the multiple registers 60 outputs a signal corresponding to a set value to one of the control terminals of the multiple switch elements 51. In the example shown in Figure 6, the multiple switch elements 51 and the multiple registers 60 are arranged in a one-to-one correspondence. The pitch at which the multiple registers 60 are arranged is, for example, the same as the pitch at which the multiple switch elements 51 are arranged.

[0125] In the imaging device 103, a switch element 51 connected between two signal lines 27 to which pixels 24 arranged in columns with different color arrangements are connected is controlled by a shift register 70, so that the signals of the pixels 24 can be mixed to generate a grayscale image. In the example shown in Figure 6, each pixel 24 includes a color filter, but each pixel 24 may be a grayscale pixel without a color filter.

[0126] [Modification 4] Next, Modification 4 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 3 of Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0127] Figure 7 is a schematic plan view showing the configuration of the imaging device 104 according to this modified example. In Figure 7, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 104 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91.

[0128] As shown in Figure 7, the imaging device 104 according to this modified example differs from the imaging device 103 according to Modification 3 of Embodiment 1 mainly in that it is equipped with a shift register 72 and memory 42 instead of a shift register 70 and memory 40, and further equipped with a plurality of switch elements 50, a shift register 71 and memory 41.

[0129] In the imaging device 104, the control terminals of each switch element 50 are configured to receive signals corresponding to the output of the register 61. Each switch element 50 is controlled to be on or off by the setting value ("0" or "1") of the register 61. In the example shown in Figure 7, in the imaging device 104, the switch element 50 connected between two signal lines 27 to which Gr pixels and B pixels of the plurality of pixels 24 are connected, and the switch element 50 connected to the signal line 27 to which R pixels and Gb pixels of the plurality of pixels 24 are connected, are controlled by the same shift register 71.

[0130] Furthermore, in the imaging device 104, the control terminals of each switch element 51 are configured to receive signals corresponding to the output of the register 62. Each switch element 51 is controlled to be on or off by the setting value ("0" or "1") of the register 62.

[0131] Each of the multiple registers 61 outputs a signal corresponding to a set value to one of the control terminals of the multiple switch elements 50. In the example shown in Figure 7, the multiple switch elements 50 and the multiple registers 61 are arranged in a one-to-one correspondence. Similarly, each of the multiple registers 62 outputs a signal corresponding to a set value to one of the control terminals of the multiple switch elements 51. In the example shown in Figure 7, the multiple switch elements 51 and the multiple registers 62 are arranged in a one-to-one correspondence.

[0132] In the imaging device 104, a switch element 50 connected between two signal lines 27 to which pixels 24 arranged in columns of the same color are connected, and a switch element 51 connected between two signal lines 27 to which pixels 24 arranged in columns of different colors are connected, are individually controlled by two shift registers 71 and 72. Therefore, it is possible to choose whether to mix the signals of the pixels 24 to generate a black and white image or to mix them while retaining color information.

[0133] [Modification 5] Next, Modification 5 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 4 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0134] Figure 8 is a schematic perspective view showing the configuration of the imaging device 105 according to this modified example. Figure 9A is a schematic plan view showing the configuration of the first substrate 5A of the imaging device 105 according to this modified example. Figure 9B is a schematic plan view showing the configuration of the second substrate 5B of the imaging device 105 according to this modified example. In Figures 8, 9A, and 9B, the vertical scanning circuit 25, the AD conversion circuit 30, the controller 90, and the data bus 91 are not shown, but similar to the imaging device 100, the imaging device 105 may also have components that are not shown, such as the vertical scanning circuit 25, the AD conversion circuit 30, the controller 90, and the data bus 91.

[0135] As shown in Figure 8, the imaging device 105 according to this modified example comprises a first substrate 5A and a second substrate 5B stacked on top of each other. Although not shown, the imaging device 105 may further stack substrates different from the first substrate 5A and the second substrate 5B. As shown in Figure 9A, in the imaging device 105, the pixel array PA is formed on the first substrate 5A. Also, as shown in Figure 9B, the imaging device 105 comprises a plurality of switch elements 53, a plurality of switch elements 54, a plurality of shift registers 71 and a plurality of shift registers 72. The plurality of switch elements 53, a plurality of switch elements 54, a plurality of shift registers 71 and a plurality of shift registers 72 are formed on the second substrate 5B. In Figure 9B, all the white rectangles represent switch elements (switch element 53 or switch element 54).

[0136] In this modified example, the signal line 27a connected to the first pixel 24f1 among the multiple pixels 24 is an example of the first wiring. The signal line 27b connected to the second pixel 24f2 among the multiple pixels 24 is an example of the second wiring. The signal line 27c connected to the third pixel 24f3 among the multiple pixels 24 is an example of the third wiring. The signal line 27d connected to the fourth pixel 24f4 among the multiple pixels 24 is an example of the fourth wiring. The first pixel 24f1 and the second pixel 24f2 are pixels of the same color and are arranged along the row direction. The third pixel 24f3 and the fourth pixel 24f4 are pixels of the same color and are arranged along the row direction. The first pixel 24f1 and the third pixel 24f3 are pixels of the same color and are arranged along the column direction. The second pixel 24f2 and the fourth pixel 24f4 are pixels of the same color and are arranged along the column direction. Furthermore, the switch element 53 connected between signal line 27a and signal line 27b, and the register 61 that outputs a signal to the switch element 53, are examples of a first switch element and a first register, respectively. Also, the switch element 54 connected between signal line 27a and signal line 27c, and the register 62 that outputs a signal to the switch element 54, are examples of a second switch element and a second register, respectively. Furthermore, the switch element 54 connected between signal line 27b and signal line 27d, and the register 62 that outputs a signal to the switch element 54, are examples of a third switch element and a third register, respectively.

[0137] As shown in Figure 9A, in the imaging device 105, signal lines 27 are provided for each of the multiple pixels 24 and are connected to the corresponding pixels 24. In Figure 9A, the signal lines 27 are indicated by white circles or black circles. In Figure 9A, the white circles indicate signal lines 27 connected to Gr pixels, and the black circles indicate signal lines 27 connected to R pixels, B pixels, or Gb pixels. In Figure 9B, the signal lines 27 connected to Gr pixels, indicated by white circles, are shown, and the signal lines 27 connected to R pixels, B pixels, or Gb pixels are not shown. The signal lines 27 are connected between the first substrate 5A and the second substrate 5B by, for example, a Cu-Cu junction or a TSV (Through Silicon Via).

[0138] Each of the multiple switch elements 53 and 54 is connected between two signal lines 27 connected to different pixels 24. Specifically, each of the multiple switch elements 53 is connected between two signal lines 27 connected to adjacent pixels 24 of the same color in the row direction. Each of the multiple switch elements 54 is connected between two signal lines 27 connected to adjacent pixels 24 of the same color in the column direction. For example, a switch element 53 is connected between each pair of signal lines 27 connected to adjacent pixels 24 of the same color in the row direction. Also, for example, a switch element 54 is connected between each pair of signal lines 27 connected to adjacent pixels 24 of the same color in the column direction. Each of the multiple switch elements 53 and 54 controls the conduction and non-conductivity of two signal lines 27 connected to different pixels 24.

[0139] In the example shown in Figure 9B, multiple switch elements 53 are arranged along the row and column directions. Similarly, multiple switch elements 54 are also arranged along the row and column directions.

[0140] Each switch element 53 has a control terminal that receives a signal corresponding to the output of register 61. Each switch element 53 is controlled to be on or off by the setting value of register 61 ("0" or "1"). Each switch element 54 has a control terminal that receives a signal corresponding to the output of register 62. Each switch element 54 is controlled to be on or off by the setting value of register 62 ("0" or "1").

[0141] The configurations of the multiple switch elements 53 and the multiple switch elements 54 are the same as those of each other. Each switch element 53 and each switch element 54 is, for example, a switch element 50A having the configuration shown in Figure 3A, a switch element 50B having the configuration shown in Figure 3B, or a switch element 50C having the configuration shown in Figure 3C.

[0142] In the example shown in Figure 9B, a shift register 71 for controlling multiple switch elements 53 and a shift register 72 for controlling multiple switch elements 54 are arranged alternately along the column direction. In the imaging device 105, each of the multiple registers 61 of each shift register 71 outputs a signal corresponding to a set value to one of the control terminals of the multiple switch elements 53. In the example shown in Figure 9B, the multiple registers 61 of each shift register 71 are arranged along the row direction. In the row direction, there is a one-to-one correspondence between the multiple switch elements 53 and the multiple registers 61. Also, each of the multiple registers 62 of each shift register 72 outputs a signal corresponding to a set value to one of the control terminals of the multiple switch elements 54. In the example shown in Figure 9B, the multiple registers 62 of each shift register 72 are arranged along the row direction. In the row direction, there is a one-to-one correspondence between the multiple switch elements 54 and the multiple registers 62.

[0143] In the imaging device 105, a switch element 53 connected between two signal lines 27 to which pixels 24 arranged in the row direction are connected, and a switch element 54 connected between two signal lines 27 to which pixels 24 arranged in the column direction are connected, are individually controlled by a plurality of shift registers 71 and 72. This makes it possible to mix the signals of the pixels 24 at any position in both the row and column directions.

[0144] [Modification 6] Next, Modification 6 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 5 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0145] Figure 10 is a schematic plan view showing the configuration of the imaging device 106 according to this modified example. In Figure 10, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 106 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91. Also, Figure 10 shows an example of the control result by the shift register 70 in the imaging device 106. In Figure 10, the switch element 50 with a diagonal line pattern is in the ON state, and the switch element 50 without a diagonal line pattern is in the OFF state. Also, in Figure 10, the AD conversion circuit 30 with a diagonal line pattern is operating, and the AD conversion circuit 30 with a diagonal line pattern is in a dormant state.

[0146] As shown in Figure 10, the imaging device 106 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that it further includes a plurality of logic gates 81.

[0147] In the imaging device 106, the signal corresponding to the output of the register 60 is input to the AD conversion circuit 30 via the logic gate 81.

[0148] Each of the multiple logic gates 81 outputs a power-saving signal EN_PSV to the AD conversion circuit 30 according to the setting value of the register 60. In the example shown in Figure 10, except for the logic gate 81 located at the end in the row direction, the logic gates 81 are input with signals corresponding to the outputs of the two registers 60. In the example shown in Figure 10, when the power-saving signal EN_PSV is "1", the AD conversion circuit 30 remains in a dormant state without operating. On the other hand, when the power-saving signal EN_PSV is "0", the AD conversion circuit 30 operates. Therefore, the AD conversion circuit 30 switches between an operating state and a dormant state according to the signals from the register 60 via the logic gates 81.

[0149] Figure 10 shows the control results when the setting values ​​of register 60 of the shift register 70 are "0", "0", "0", "1", "1", and "0", starting from the negative side in the X-axis direction. In this case, at the positions indicated as "columns not to be read" in Figure 10, the switch element 50 is turned off and the AD conversion circuit 30 enters a dormant state. Therefore, the signal of the pixel 24 is not read. In other words, by setting the register 60, it is possible to change the range (field of view) of the pixels 24 used for image generation by putting the AD conversion circuit 30 into a dormant state.

[0150] Furthermore, at the position indicated as "3-row mixing" in Figure 10, the signals output from the three rows of pixels 24 corresponding to the signal lines 27 connected to the two switch elements 50 that are turned ON by the setting value of the register 60 are mixed. Also, depending on the setting value of the register 60, only one of the three AD conversion circuits 30 that receive the signals output from the three rows of pixels 24 is operated. Since the signals output from the three rows of pixels 24 are mixed, an image can be generated by operating only one AD conversion circuit 30, so the remaining two AD conversion circuits 30 can be put into a dormant state, thus reducing power consumption. In this way, the imaging device 106 can switch between the operating state and the dormant state of the AD conversion circuits 30 at the required position by the setting value of each register 60 of the shift register 70. Therefore, the configuration for switching between the operating state and the dormant state of the AD conversion circuits 30 can be simplified. For example, if one attempts to control the AD conversion circuit 30 from another control circuit without using the shift register 70, control lines corresponding to all of the multiple AD conversion circuits 30 will have to be sent from that other control circuit. Therefore, if the number of multiple AD conversion circuits 30 increases, this becomes difficult to implement.

[0151] Note that the circuit configuration shown in Figure 10 is just one example, and a different logic circuit may be formed. The circuit configuration in the imaging device 106 is not particularly limited, as long as the signal corresponding to the output of the register 60 is input to the AD conversion circuit 30, and the AD conversion circuit 30 switches between an operating state and a dormant state in response to the signal from the register 60.

[0152] [Modification 7] Next, Modification 7 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 6 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0153] Figure 11 is a schematic plan view showing the configuration of the imaging device 107 according to this modified example. In Figure 11, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 107 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91. Also, Figure 11 shows an example of the control result by the shift register 70 in the imaging device 107. In Figure 11, the switch elements 50 that do not have a diagonal line pattern are in the off state. In other words, in Figure 11, all switch elements 50 are in the off state. Also, in Figure 11, the AD conversion circuit 30 that has a diagonal line pattern is operating, and the AD conversion circuit 30 that has a diagonal line pattern is in a dormant state.

[0154] As shown in Figure 11, the imaging device 107 according to this modified example differs from the imaging device 106 according to Modification 6 of Embodiment 1 mainly in that it has multiple logic gates 82 instead of multiple logic gates 81, and further includes multiple selectors 83 and multiple logic gates 84.

[0155] In the imaging device 107, the signal corresponding to the output of the register 60 is configured to be input to the AD conversion circuit 30 via the logic gate 82 and the selector 83, or via the selector 83, according to the signal selected by the selector 83. In addition, the signal corresponding to the output of the register 60 is configured to be input to the control terminal of the switch element 50 via the logic gate 84.

[0156] Each of the multiple logic gates 82 outputs a signal to the selector 83 corresponding to the setting value of register 60. In the example shown in Figure 11, except for the logic gate 82 located at the end in the row direction, each logic gate 82 receives a signal corresponding to the output of one register 60 and an inverted signal of the signal corresponding to the output of another register 60.

[0157] Each of the multiple selectors 83 selects one of the two input signals and outputs it to the AD conversion circuit 30 as a power-saving signal EN_PSV. In the example shown in Figure 11, the multiple selectors 83 are controlled collectively by the all-row unmixed signal ROI_FULL. When the all-row unmixed signal ROI_FULL is "1", the selector 83 selects the inverted signal of the signal corresponding to the output of register 60. When the all-row unmixed signal ROI_FULL is "0", the selector 83 selects the signal output by logic gate 82.

[0158] Each of the multiple logic gates 84 outputs a signal corresponding to the setting value of register 60 and the all-row unmixed signal ROI_FULL to the control terminal of the switch element 50. The logic gates 84 receive a signal corresponding to the setting value of register 60 and the all-row unmixed signal ROI_FULL as input. In the example shown in Figure 11, when the all-row unmixed signal ROI_FULL is "1", the logic gate 84 outputs a signal indicating "0" regardless of the setting value of register 60. Also, when the all-row unmixed signal ROI_FULL is "0", the logic gate 84 outputs a signal indicating the setting value of register 60.

[0159] As shown in Figure 11, the settings of register 60 of the shift register 70 are "0", "0", "1", "1", "1", and "0" in order from the negative side in the X-axis direction, and the case where the all-row unmixed signal ROI_FULL is "1". In this case, since the all-row unmixed signal ROI_FULL is "1", all of the multiple switch elements 50 are turned off regardless of the setting of register 60, and the signals output from the pixels 24 of all rows are not mixed. In addition, the AD conversion circuit 30 of the row corresponding to the register 60 with a setting of "0" is put into a dormant state. In other words, even when the signals output from the pixels 24 are not mixed, the AD conversion circuit 30 can be put into a dormant state by the setting of register 60, thereby reducing power consumption and changing the range (field of view) of the pixels 24 used for image generation. Furthermore, if the unmixed signal ROI_FULL for all rows is "0", the multiple switch elements 50 and multiple AD conversion circuits 30 can be controlled in the same way as the imaging device 106, according to the setting value of register 60 of the shift register 70.

[0160] Note that the circuit configuration shown in Figure 11 is just one example, and a different logic circuit may be formed. The circuit configuration in the imaging device 107 is not particularly limited, as long as the signal corresponding to the output of the register 60 is input to the AD conversion circuit 30, and the AD conversion circuit 30 switches between an operating state and a dormant state in response to the signal from the register 60.

[0161] [Modification 8] Next, Modification 8 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 7 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0162] Figure 12 is a schematic plan view showing the configuration of the imaging device 108 according to this modified example. In Figure 12, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 108 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91.

[0163] As shown in Figure 12, the imaging device 108 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that it has multiple switch elements 55 instead of multiple switch elements 50, and further includes multiple switch elements 56. Also, in the example shown in Figure 12, each of the multiple pixels 24 provided by the imaging device 108 is the pixel 24A shown in Figure 2A.

[0164] In this modified example, the reset voltage line 33 connected to the first pixel 24i1 among the multiple pixels 24A is an example of the first wiring. The reset voltage line 33 connected to the second pixel 24i2 among the multiple pixels 24A is an example of the second wiring. The first pixel 24i1 and the second pixel 24i2 are arranged along the row direction. The first pixel 24i1 and the third pixel 24i3 among the multiple pixels 24A are arranged along the column direction. The switch element 55 connected between the first wiring and the second wiring, and the register 60 that outputs a signal to the switch element 55, are examples of the first switch element and the first register, respectively. The reset transistor 22 of each pixel 24A is an example of a transistor.

[0165] In the imaging device 108, a reset voltage line 33 is provided for each row of pixels 24A and is connected to the pixel 24A of the corresponding row. The source and drain of the reset transistors 22 of the pixels 24A arranged along the row direction are connected to each other via the reset voltage line 33 of the corresponding row.

[0166] Each of the multiple switch elements 55 is connected between two reset voltage lines 33 corresponding to different rows of multiple pixels 24A. In Figure 12, one switch element 55 is shown, but there are other switch elements 55 connected between two reset voltage lines 33 corresponding to different rows of multiple pixels 24A that are not shown. Each of the multiple switch elements 55 controls the conduction and non-conductivity of two reset voltage lines 33 corresponding to different rows of multiple pixels 24A. Each of the multiple switch elements 55 may be connected between two reset voltage lines 33 to which pixels 24A arranged in the same color in the column direction are connected, or between two reset voltage lines 33 to which pixels 24A arranged in the different color in the column direction are connected.

[0167] The multiple switch elements 55 are arranged, for example, along the row direction. The multiple switch elements 55 are positioned, for example, in the row direction, at positions corresponding to the pixel array PA. The multiple switch elements 55 are positioned, for example, in the row direction, within the range where the pixel array PA is located.

[0168] Each switch element 55 is configured to receive a signal corresponding to the output of the register 60 at its control terminal. Each switch element 55 is controlled to be on or off by the setting value ("0" or "1") of the register 60.

[0169] The configurations of the multiple switch elements 55 are the same. Each switch element 55 is, for example, a switch element 50A having the configuration shown in Figure 3A, a switch element 50B having the configuration shown in Figure 3B, or a switch element 50C having the configuration shown in Figure 3C.

[0170] Each of the multiple registers 60 (only one is shown in Figure 12) outputs a signal corresponding to a set value to one of the control terminals of the multiple switch elements 55. The multiple switch elements 55 and the multiple registers 60 are arranged in a one-to-one correspondence, for example. The pitch at which the multiple registers 60 are arranged is, for example, the same as the pitch at which the multiple switch elements 55 are arranged.

[0171] Each of the multiple switch elements 56 is provided for each row of multiple pixels 24A, corresponding to the reset voltage line 33. The switch element 56 controls whether or not to supply the reset voltage Vrst to the reset voltage line 33. The driving of the multiple switch elements 56 is controlled, for example, by a control circuit (not shown). The imaging device 108 may have only one switch element 56. In this case, the single switch element 56 controls whether or not to supply the reset voltage Vrst to the multiple reset voltage lines 33 provided for each of the multiple pixels 24A.

[0172] The configurations of the multiple switch elements 56 are the same. Each switch element 56 is, for example, a switch element 50A having the configuration shown in Figure 3A, a switch element 50B having the configuration shown in Figure 3B, or a switch element 50C having the configuration shown in Figure 3C.

[0173] Multiple switch elements 56 are controlled to supply a reset voltage Vrst to the reset voltage line 33 when the pixel 24A is reset.

[0174] Furthermore, the multiple switch elements 56 are controlled, for example, not to supply a reset voltage Vrst to the reset voltage line 33 when reading out a signal based on the signal charge of a pixel 24A. In other words, the multiple switch elements 56 isolate the reset voltage line 33 from the voltage source that supplies the reset voltage Vrst when reading out a signal from a pixel 24A. In this state, the reset transistor 22 is turned on by the vertical scanning circuit 25, and the potential of the charge storage node 34 is not reset, and the signal charge stored in the charge storage node 34 is input to the reset voltage line 33 as a signal from the pixel 24A. Also, when the reset transistors 22 of two or more pixels 24A are turned on, the signals from those two or more pixels 24A are mixed in the reset voltage line 33. Therefore, since the signals of those two or more pixels 24A can be mixed using the reset transistors 22 and the reset voltage line 33, the configuration for signal mixing can be simplified. In addition, in the imaging device 108, the signals of pixels 24A can be mixed at any position in the column direction by changing the pixel 24A to which the reset transistor 22 is turned on.

[0175] Furthermore, in the imaging device 108, the switch element 55 conducts through the two reset voltage lines 33, allowing the signals of pixels 24A connected to the two reset voltage lines 33 and with the reset transistor 22 turned on to be mixed. Also, the on and off states of multiple switch elements 55 can be individually switched by the setting values ​​of each register 60 of the shift register 70. Therefore, the combination of which reset voltage lines 33 are conducted can be arbitrarily changed. Thus, in the imaging device 108, the signals of two or more pixels 24A arranged along the column direction, which have been mixed by the reset voltage lines 33, can be further mixed between any columns in the row direction. The signals mixed in the reset voltage lines 33 are read out from any of the pixels 24A targeted for signal mixing to the signal line 27.

[0176] Furthermore, similar to the imaging devices 106 and 107 described above, the AD conversion circuit 30 may be configured so that a signal corresponding to the output of the register 60 is input to the AD conversion circuit 30, and the AD conversion circuit 30 may be switched between an operating state and a dormant state in response to the signal from the register 60. In this case, the current source 28 provided in the column corresponding to the AD conversion circuit 30 may also be configured so that a signal corresponding to the output of the register 60 is input to the current source 28, and the current source 28 may be switched between an operating state and a dormant state in response to the signal from the register 60. The configuration in which the current source 28 is switched between an operating state and a dormant state may be applied to imaging devices according to this disclosure other than the modified example 8 of Embodiment 1.

[0177] Furthermore, in the example shown in Figure 12, each of the multiple pixels 24 was a pixel 24A, but this is not limited to this. Even if each of the multiple pixels 24 is a pixel 24B, the other of the source and drain of the reset transistor 22 can be connected to the reset voltage line 33, thereby allowing the use of a pixel 24B as the pixel 24 in the imaging device 108.

[0178] [Modification 9] Next, Modification 9 of Embodiment 1 will be described. In the following, the differences between Embodiment 1 and Modifications 1 to 8 of Embodiment 1 will be described in detail, and the explanation of the common points will be omitted or simplified.

[0179] Figure 13 is a schematic plan view showing the configuration of the imaging device 109 according to this modified example. In Figure 13, the semiconductor substrate 5, controller 90, and data bus 91 are not shown, but similar to the imaging device 100, the imaging device 109 may also have components that are not shown, such as the semiconductor substrate 5, controller 90, and data bus 91.

[0180] As shown in Figure 13, the imaging device 109 according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that it further includes a plurality of switch elements 57, a plurality of switch elements 58, a plurality of capacitive elements 38, and a plurality of logic gates 85. Also, in the example shown in Figure 13, each of the plurality of pixels 24 provided in the imaging device 109 is the pixel 24B shown in Figure 2B.

[0181] In this modified example, the signal line 27 connected to the first pixel 24j1 among the multiple pixels 24B is an example of a first wiring. The signal line 27 connected to the second pixel 24j2 among the multiple pixels 24B is an example of a second wiring. The first pixel 24j1 and the second pixel 24j2 are arranged along the row direction. The first pixel 24j1 and the third pixel 24j3 among the multiple pixels 24B are arranged along the column direction. The switch element 50 connected between the first wiring and the second wiring, and the register 60 that outputs a signal to the switch element 50, are examples of a first switch element and a first register, respectively. The switch element 57 connected between the charge storage node 34 of the first pixel 24j1 and the charge storage node 34 of the third pixel 24j3 is an example of a fourth switch element.

[0182] Each of the multiple switch elements 57 is connected between charge storage nodes 34 of two pixels 24B arranged along the column direction. In Figure 13, one switch element 57 is shown corresponding to each column of multiple pixels 24B, but there are also switch elements 57 connected between charge storage nodes 34 of two pixels 24B arranged along the column direction at positions not shown.

[0183] The configurations of the multiple switch elements 57 are the same. Each switch element 57 is, for example, a switch element 50A having the configuration shown in Figure 3A, a switch element 50B having the configuration shown in Figure 3B, or a switch element 50C having the configuration shown in Figure 3C.

[0184] Each of the multiple switch elements 57 controls the conduction and non-conductivity of the charge storage nodes 34 of two pixels 24B arranged along the column direction. Each of the multiple switch elements 57 may be connected between the charge storage nodes 34 of two adjacent pixels 24B of the same color in the column direction, or between the charge storage nodes 34 of two adjacent pixels 24B of different colors in the column direction. The multiple switch elements 57 mix the signal charges of the charge storage nodes 34 of two or more pixels 24B arranged along the column direction as the signal of the pixels 24B, and the mixed signal is read out to the signal line 27 from any of the two or more pixels 24B. The multiple switch elements 57 are controlled, for example, by a control circuit (not shown). The multiple switch elements 57 may also be controlled by the setting values ​​of each register of a shift register (not shown).

[0185] Each of the multiple capacitive elements 38 is provided for each row of multiple pixels 24B, corresponding to the signal line 27. Each of the multiple capacitive elements 38 is connected to the signal line 27 of the corresponding row. Each of the multiple capacitive elements 38 stores the signal from the pixel 24B output to the signal line 27 of the corresponding row. The multiple capacitive elements 38 function as capacitances for averaging the signals from the pixels 24B output to the two signal lines 27 connected by the switch element 50.

[0186] Each of the multiple switch elements 58 is located in the middle of the signal line 27 and is provided for each row of multiple pixels 24B. Each of the multiple switch elements 58 is located on the AD conversion circuit 30 side of the signal line 27, relative to the pixels 24B and current source 28. Each of the multiple switch elements 58 controls the conduction and non-conductivity between the corresponding row of pixels 24B and current source 28 and the capacitive element 38. The control terminal of each of the multiple switch elements 58 is configured to receive the read row signal READ_COL. When the read row signal READ_COL is "1", the switch element 58 makes the pixels 24B and current source 28 and the capacitive element 38 conduct. When the read row signal READ_COL is "0", the switch element 58 makes the pixels 24B and current source 28 and the capacitive element 38 non-conductive.

[0187] In the imaging device 109, each of the multiple switch elements 50 (only one is shown in Figure 13) has a connection to the connection path between the capacitive element 38 and the switch element 58 on the signal line 27. Furthermore, the signal corresponding to the output of the register 60 is configured to be input to the control terminal of the switch element 50 via the logic gate 85.

[0188] Each of the multiple logic gates 85 outputs a signal corresponding to the setting value of register 60 and the mixed signal MIX_ON to the control terminal of the switch element 50. The logic gate 85 receives a signal corresponding to the setting value of register 60 and the mixed signal MIX_ON as input. In the example shown in Figure 13, when the mixed signal MIX_ON is "1", the logic gate 85 outputs a signal indicating the setting value of register 60. Also, when the mixed signal MIX_ON is "0", the logic gate 85 outputs a signal indicating "0" regardless of the setting value of register 60.

[0189] Figure 14 is a time chart showing an example of the operation when reading out a signal from pixel 24B of the imaging device 109 according to this modified example. Figure 14 shows the changes in the voltage levels of the readout column signal READ_COL and the mixed signal MIX_ON.

[0190] In each column of multiple pixels 24B, the address transistor 23 is turned on, and the signal from the pixel 24B is input to the signal line 27. Then, at time t1, the readout column signal READ_COL changes from "0" to "1", and the pixel 24B and the capacitive element 38 become conductive. As a result, in each column of multiple pixels 24B, the signal from the pixel 24B output to the signal line 27 is stored in the capacitive element 38. Also, at time t1, the mixed signal MIX_ON is "0", so the switch element 50 is in the off state. Therefore, the multiple capacitive elements 38 are not connected to each other.

[0191] Next, at time t2, the readout column signal READ_COL changes from "1" to "0", and the capacitive element 38, the pixels 24B, and the current source 28 become non-conductive in each column of the multiple pixels 24B. Then, at time t3, the mixing signal MIX_ON changes from "0" to "1", and the switch element 50, which receives the signal corresponding to the output of the register 60 whose set value is "1", turns ON. As a result, the signals accumulated in the interconnected capacitive elements 38 are averaged by the ON state of the switch element 50. Furthermore, at this time, since the capacitive element 38 is non-conductive with the pixels 24B and the current source 28, the signals accumulated in the capacitive element 38 are not affected by the pixels 24B and the current source 28. This allows for more accurate signal averaging and mixing compared to mixing signals input to the signal line 27 without using the capacitive element 38.

[0192] In the example shown in Figure 14, each of the multiple pixels 24 was a pixel 24B, but this is not limited to this. In the imaging device 109, each of the multiple pixels 24 may be a pixel 24A.

[0193] Furthermore, the configuration of mixing signals input to the signal line 27 using multiple capacitive elements 38 may also be applied to imaging devices according to this disclosure other than the modified example 9 of Embodiment 1.

[0194] (Embodiment 2) Next, Embodiment 2 will be described. In the following, the differences between Embodiment 1 and the modifications 1 to 9 of Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0195] Figure 15 is a schematic plan view showing the configuration of the imaging device 200 according to this embodiment. In Figure 15, the semiconductor substrate 5 is not shown, but similar to the imaging device 100, the imaging device 200 may also have components that are not shown, such as the semiconductor substrate 5.

[0196] As shown in Figure 15, the imaging device 200 according to this embodiment differs from the imaging device 100 according to Embodiment 1 mainly in that it includes a mixed control circuit 220 which includes a plurality of switch control units 210 instead of a shift register 70 which includes a plurality of registers 60.

[0197] In the imaging device 200, the control terminals of each switch element 50 are configured to receive signals corresponding to the output of the switch control unit 210.

[0198] The mixing control circuit 220 includes a plurality of switch control units 210 arranged along the row direction. The mixing control circuit 220 is positioned in the row direction at locations corresponding to the pixel array PA. For example, the mixing control circuit 220 is positioned in the row direction within the range where the pixel array PA is located.

[0199] In the imaging device 200, multiple switch control units 210 arranged along the row direction can output control signals for multiple switch elements 50 that mix the signals of pixels 24 arranged along the row direction, thus simplifying the structure of the imaging device 200. Furthermore, the multiple switch control units 210 can individually switch the on and off states of the multiple switch elements 50. Therefore, the signals of the pixels 24 can be mixed at any desired position.

[0200] The following describes a specific example of a mixed control circuit 220 that includes multiple switch control units 210.

[0201] Figure 16 is a schematic plan view showing the configuration of a mixed control circuit 220A, which is a first example of a mixed control circuit 220 including a plurality of switch control units 210 according to this embodiment, and includes a plurality of switch control units 210A.

[0202] In the mixed control circuit 220A shown in Figure 16, the multiple switch control units 210A are multiple registers arranged along the row direction. The mixed control circuit 220A outputs signals corresponding to the set values ​​of each register to multiple switch elements 50.

[0203] Figure 17 is a schematic plan view showing the configuration of a mixed control circuit 220B, which is a second example of a mixed control circuit 220 including a plurality of switch control units 210B according to this embodiment, and includes a plurality of switch control units 210B.

[0204] In the mixed control circuit 220B shown in Figure 17, the multiple switch control units 210B are multiple registers arranged along the row direction and connected in series. In other words, in this example, the mixed control circuit 220B is a shift register, and the configuration of the imaging device 200 is the same as the configuration of the imaging device 100.

[0205] Figure 18 is a schematic plan view showing the configuration of a mixed control circuit 220C which includes a plurality of switch control units 210C, which is a third example of a mixed control circuit 220 including a plurality of switch control units 210 according to this embodiment.

[0206] In the mixed control circuit 220C shown in Figure 18, each of the multiple switch control units 210C includes an H memory register 211 and a logic gate that is part of the decoder circuit 212. The H memory registers 211 of each of the multiple switch control units 210C are arranged in the row direction. When the H memory register 211 is set to "1" by the clock CLK, it outputs a signal indicating "1" until it is reset. Also, "0" is not set in the H memory register 211 by the clock CLK. In the example shown in Figure 18, the decoder circuit 212 decodes the address signal ADD[1:0] into the mixed signal MIX[3:0]. Figure 19 is a diagram showing the relationship between the address signal ADD[1:0] and the mixed signal MIX[3:0] in the mixed control circuit 220C.

[0207] Here, we will describe an example in which the mixing control circuit 220C decodes the address signal ADD[1:0] into the mixed signal MIX[3:0] and outputs the register signal REG[3:0] to multiple switch elements 50. Figure 20 is a time chart showing an example of the operation of the mixing control circuit 220C. As the mixing control circuit 220C operates as shown in Figure 20, the mixed signals MIX[0] and [2] and the register signals REG[0] and [2] become "1", and the mixed signals MIX[1] and [3] and the register signals REG[1] and [3] become "0".

[0208] Figure 21 is a schematic plan view showing the configuration of a mixed control circuit 220D which includes a plurality of switch control units 210D, which is a fourth example of a mixed control circuit 220 including a plurality of switch control units 210 according to this embodiment.

[0209] In the mixing control circuit 220D shown in Figure 21, the multiple switch control units 210D are multiple pads arranged along the row direction. Each of the multiple pads is a pad terminal that receives input from an external source, and the mixing control circuit 220D outputs signals to the multiple switch elements 50 corresponding to the external input to each pad.

[0210] Figure 22 is a schematic plan view showing the configuration of a mixed control circuit 220E, which is a fifth example of a mixed control circuit 220 including a plurality of switch control units 210 according to this embodiment, and includes a plurality of switch control units 210E.

[0211] In the mixed control circuit 220E shown in Figure 22, the multiple switch control units 210E are multiple SRAM cells arranged along the row direction. In this case, the mixed control circuit 220E is a cell array of SRAM 213. Each SRAM cell is a 1-bit memory element. The mixed control circuit 220E outputs signals corresponding to the setting value of each SRAM cell to multiple switch elements 50. The setting value of each SRAM cell is set by the controller of the SRAM 213.

[0212] Furthermore, Figure 23 is a schematic plan view showing the configuration of a mixed control circuit 220F including a plurality of switch control units 210F, which is a sixth example of a mixed control circuit 220 including a plurality of switch control units 210 according to this embodiment.

[0213] The mixed control circuit 220F shown in Figure 23 has a configuration in which a plurality of logic gates 214 arranged in the row direction are added to the mixed control circuit 220E. In the mixed control circuit 220F, each of the plurality of switch control units 210F includes a logic gate 214 and an SRAM cell 215. The logic gate 214 outputs a signal corresponding to the set value of the SRAM cell 215 and the enable signal EN to the control terminal of the switch element 50. The logic gate 214 receives a signal corresponding to the set value of the SRAM cell 215 and the enable signal EN as input. This allows control whether or not to output a signal corresponding to the set value of the SRAM cell 215 to the switch element 50 using the enable signal EN.

[0214] (Embodiment 3) Next, Embodiment 3 will be described. Embodiment 3 describes a camera system equipped with an imaging device according to the present disclosure.

[0215] Figure 24 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0216] As shown in Figure 24, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0217] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to any of the above-described embodiments 1, each of the modifications of embodiment 1, and embodiment 2 may be used.

[0218] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0219] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data such as differential digital signals from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device including the imaging device 602 as part can be made smaller.

[0220] (Other Embodiments) The imaging apparatus and camera system relating to the present disclosure have been described above based on embodiments, but the present disclosure is not limited to these embodiments. Various modifications to the embodiments that a person skilled in the art can conceive of, as long as they do not depart from the spirit of the present disclosure, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of the present disclosure.

[0221] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents.

[0222] The imaging device relating to this disclosure is useful for, for example, image sensors and digital cameras. The imaging device relating to this disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like.

[0223] 2 Pixel electrodes 3 Photoelectric conversion layer 4 Counter electrodes 5 Semiconductor substrate 5A First substrate 5B Second substrate 10A, 10B Photoelectric conversion section 18 Transfer transistor 19 Transfer signal line 21 Amplifier transistor 22 Reset transistor 23 Address transistor 24, 24A, 24B Pixels 24a1, 24d1, 24f1, 24i1, 24j1 First pixels 24a2, 24d2, 24f2, 24i2, 24j2 Second pixels 24a3, 24d3, 24f3, 24i3, 24j3 Third pixels 24d4, 24f4 Fourth pixels 25 Vertical scanning circuit 26 Counter electrode signal line 27, 27a, 27b, 27c, 27d Signal line 28 Current source 30 AD conversion circuit 31 Power supply wiring 33 Reset voltage line 34 Charge storage node 36 Address signal line 37 Reset signal line 38 Capacitive elements 40, 41, 42 Memory 50, 50A, 50B, 50C, 51, 52, 53, 54, 55, 56, 57, 58 Switch element 50d Level shifter 60, 61, 62 Register 70, 71, 72 Shift register 80, 83 Selector 81, 82, 84, 85, 214 Logic gate 90 Controller 91 Data bus 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 200, 602 Imaging device 210, 210A, 210B, 210C, 210D, 210E, 210F Switch control unit 211 H memory register 212 Decoder circuit 213 SRAM 215 SRAM cells 220, 220A, 220B, 220C, 220D, 220E, 220F Mixing control circuit 400 Camera system 601 Lens optics 603 System controller 604 Camera signal processing circuit

Claims

1. An imaging device comprising: a first pixel and a second pixel; a first wiring to which a signal from the first pixel is input; a second wiring to which a signal from the second pixel is input; a first switch element connected between the first wiring and the second wiring; and a first shift register including a plurality of registers connected in series, wherein a signal corresponding to the output of the first register among the plurality of registers of the first shift register is input to the control terminal of the first switch element.

2. The imaging apparatus according to claim 1, further comprising: a third pixel; a third wiring to which a signal from the third pixel is input; and a second switch element connected between the second wiring and the third wiring, wherein a signal corresponding to the output of the second register among the plurality of registers of the first shift register is input to the control terminal of the second switch element.

3. An imaging device comprising: first pixels, second pixels, and third pixels arranged along a first direction; a first wiring to which a signal from the first pixel is input; a second wiring to which a signal from the second pixel is input; a third wiring to which a signal from the third pixel is input; a first switch element connected between the first wiring and the second wiring; a second switch element connected between the second wiring and the third wiring; and a first register and a second register, wherein a signal corresponding to the output of the first register is input to the control terminal of the first switch element, and a signal corresponding to the output of the second register is input to the control terminal of the second switch element, and the first register and the second register are arranged along the first direction.

4. The imaging apparatus according to claim 1, further comprising: a third pixel and a fourth pixel; a third wiring to which a signal from the third pixel is input; a fourth wiring to which a signal from the fourth pixel is input; and a third switch element connected between the third wiring and the fourth wiring, wherein a signal corresponding to the output of the third register among the plurality of registers of the first shift register is input to the control terminal of the third switch element.

5. The imaging apparatus according to claim 1, further comprising: a third pixel; a third wiring to which a signal from the third pixel is input; a second switch element connected between the second wiring and the third wiring; and a second shift register including a plurality of registers connected in series, wherein a signal corresponding to the output of the second register among the plurality of registers of the second shift register is input to the control terminal of the second switch element.

6. The imaging device according to claim 1, wherein the first pixel and the second pixel are arranged along a first direction, the imaging device further comprises: the first pixel and a third pixel arranged along a second direction intersecting the first direction; a third wiring to which a signal from the third pixel is input; a second switch element connected between the first wiring and the third wiring; and a second shift register including a plurality of registers connected in series, wherein a signal corresponding to the output of the second register among the plurality of registers of the second shift register is input to the control terminal of the second switch element.

7. The imaging apparatus according to claim 6, further comprising: a second pixel and a fourth pixel arranged along the second direction; a fourth wiring to which a signal from the fourth pixel is input; and a third switch element connected between the second wiring and the fourth wiring, wherein a signal corresponding to the output of the third register among the plurality of registers of the second shift register is input to the control terminal of the third switch element.

8. The imaging apparatus according to claim 1, wherein the first shift register is a series-input, parallel-output type shift register.

9. The imaging apparatus according to claim 1, further comprising: a plurality of pixels, including the first pixel and the second pixel, arranged in a row direction and a column direction; and a fourth switch element, wherein each of the plurality of pixels includes a photoelectric conversion unit that converts light into signal charge and a charge storage unit that stores the signal charge; the first pixel and the second pixel are arranged along the row direction; the plurality of pixels include the first pixel and a third pixel arranged along the column direction; and the fourth switch element is connected between the charge storage unit of the first pixel and the charge storage unit of the third pixel.

10. The imaging apparatus according to claim 1, further comprising a plurality of pixels, including the first pixel and the second pixel, arranged in a row direction and a column direction, each of the plurality of pixels comprising a photoelectric conversion unit that converts light into signal charge, a charge storage unit that stores the signal charge, and a transistor whose source and drain are connected to the charge storage unit, the first pixel and the second pixel being arranged along the row direction, the plurality of pixels including the first pixel and a third pixel arranged along the column direction, the other of the source and drain of the transistor of the first pixel being connected via the first wiring to the other of the source and drain of the transistor of the third pixel.

11. The imaging apparatus according to claim 1, wherein each of the first and second pixels includes a photoelectric conversion unit that converts light into signal charges and a charge storage unit that stores the signal charges, and the photoelectric conversion unit includes a first electrode connected to the charge storage unit, a second electrode facing the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode.

12. The imaging apparatus according to claim 1, further comprising a semiconductor substrate, wherein each of the first pixel and the second pixel includes a photoelectric conversion unit that converts light into a signal charge, and the photoelectric conversion unit is a photodiode located within the semiconductor substrate.

13. The imaging apparatus according to claim 1, further comprising a rewritable memory for holding data input to the first shift register.

14. The imaging apparatus according to claim 1, further comprising a non-rewritable memory for holding data input to the first shift register.

15. The imaging apparatus according to claim 1, further comprising an AD conversion circuit that converts the signal from the first pixel into a digital signal, wherein a signal corresponding to the output of the first register is input to the AD conversion circuit, and the AD conversion circuit is switched between an operating state and a dormant state in accordance with the signal from the first register.

16. A camera system comprising an imaging device according to any one of claims 1 to 15.

Images